# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Iacobovici:1988:HFC
author: S. Iacobovici
title: High-performance floating-point coprocessor for the NS32532 CPU
crossref: Wescon:1988:WCR
pages: 1.3/1--6
year: 1988
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: National Semicond. Corp., Santa Clara, CA, USA
thesaurus: Digital arithmetic; Microprocessor chips
rawauthor: S. Iacobovici
rawtitle: High-performance floating-point coprocessor for the {NS32532 CPU}
abstract:
The need to match the integer processing performance of the NS32532 CPU with the floating-point performance teams the NS32580 floating-point controller with Weitek's WTL3164 floating-point data path to achieve a peak performance of 15 MFLOPS for single- or double-precision. Using a pipelined slave protocol this solution is software compatible with existing Series 32000 software base and supports precise exception handling. Together, NS32532-NS32580-WTL3164 provide a high-performance, well-balanced solution for scientific applications, as well as number crunching, graphics and image processing.

keywords:
15 MFLOPS; Double-precision; Exception handling; Floating-point coprocessor; Graphics; Image processing; NS32532 CPU; NS32580 floating-point controller; Pipelined slave protocol; Processing performance; Scientific applications; Series 32000 software; Single precision arithmetic; WTL3164 floating-point data path

rawabstract:
The need to match the integer processing performance of the NS32532 CPU with the floating-point performance teams the NS32580 floating-point controller with Weitek's WTL3164 floating-point data path to achieve a peak performance of 15 MFLOPS for single- or double-precision. Using a pipelined slave protocol this solution is software compatible with existing Series 32000 software base and supports precise exception handling. Together, NS32532-NS32580-WTL3164 provide a high-performance, well-balanced solution for scientific applications, as well as number crunching, graphics and image processing.

entry:
@InProceedings{Iacobovici:1988:HFC,
  author =       "S. Iacobovici",
  title =        "High-performance floating-point coprocessor for the
                 {NS32532 CPU}",
  crossref =     "Wescon:1988:WCR",
  pages =        "1.3/1--6",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The need to match the integer processing performance
                 of the NS32532 CPU with the floating-point performance
                 teams the NS32580 floating-point controller with
                 Weitek's WTL3164 floating-point data path to achieve a
                 peak performance of 15 MFLOPS for single- or
                 double-precision. Using a pipelined slave protocol this
                 solution is software compatible with existing Series
                 32000 software base and supports precise exception
                 handling. Together, NS32532-NS32580-WTL3164 provide a
                 high-performance, well-balanced solution for scientific
                 applications, as well as number crunching, graphics and
                 image processing.",
  acknowledgement = ack-nhfb,
  affiliation =  "National Semicond. Corp., Santa Clara, CA, USA",
  classification = "C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods)",
  keywords =     "15 MFLOPS; Double-precision; Exception handling;
                 Floating-point coprocessor; Graphics; Image processing;
                 NS32532 CPU; NS32580 floating-point controller;
                 Pipelined slave protocol; Processing performance;
                 Scientific applications; Series 32000 software; Single
                 precision arithmetic; WTL3164 floating-point data
                 path",
  numericalindex = "Computer speed 1.5E+07 FLOPS",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Iacobovici:1988:PIH
author: S. Iacobovici
title: A pipelined interface for high floating-point performance with precise exceptions
journal: j-IEEE-MICRO
volume: 8
number: 3
pages: 77--87
month: may
monthnumber: 5
year: 1988
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.542
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: S. Iacobovici
rawtitle: A pipelined interface for high floating-point performance with precise exceptions
entry:
@Article{Iacobovici:1988:PIH,
  author =       "S. Iacobovici",
  title =        "A pipelined interface for high floating-point
                 performance with precise exceptions",
  journal =      j-IEEE-MICRO,
  volume =       "8",
  number =       "3",
  pages =        "77--87",
  month =        may # "\slash " # jun,
  year =         "1988",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.542",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "Two options are presented that were considered for a
                 pipelined interface between a central processing unit
                 (CPU) and a floating-point coprocessor (FPU), along
                 with the CPU recovery mechanisms that provide precise
                 floating-point exceptions for each \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Irwin:1988:SIP
author: M. J. Irwin
title: Special issue on parallelism in computer arithmetic
journal: j-J-PAR-DIST-COMP
volume: 5
number: 3
pages: 205--208
month: jun
monthnumber: 6
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 17:13:17 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 17:13:17 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Pennsylvania State University, University Park, PA, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: G General Review; P Practical
rawauthor: M. J. Irwin
rawtitle: Special issue on parallelism in computer arithmetic
keywords:
computer arithmetic; digital arithmetic; lookahead adders; parallel processing; parallelism; pipelined arithmetic processors; VLSI systems

entry:
@Article{Irwin:1988:SIP,
  author =       "M. J. Irwin",
  title =        "Special issue on parallelism in computer arithmetic",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "3",
  pages =        "205--208",
  month =        jun,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 17:13:17 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5230 (Digital arithmetic methods); C5440
                 (Multiprocessor systems and techniques)",
  corpsource =   "Pennsylvania State University, University Park, PA,
                 USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "computer arithmetic; digital arithmetic; lookahead
                 adders; parallel processing; parallelism; pipelined
                 arithmetic processors; VLSI systems",
  treatment =    "G General Review; P Practical",
}


bibtype: article
filename: fparith.bib
label: Jenkins:1988:SCP
author: W. K. Jenkins and E. J. Altman
title: Self-checking properties of residue number error checkers based on mixed radix conversion
journal: j-IEEE-TRANS-CIRCUITS-SYST
volume: 35
number: 2
pages: 159--167
month: feb
monthnumber: 2
year: 1988
CODEN: ICSYBT
DOI: https://doi.org/10.1109/31.1717
ISSN: 0098-4094 (print), 1558-1276 (electronic) OR 00984094 (print), 15581276 (electronic)
ISSNL: 0098-4094 OR 00984094
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=107
fjournal: IEEE Transactions on Circuits and Systems
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. K. Jenkins and E. J. Altman
rawtitle: Self-checking properties of residue number error checkers based on mixed radix conversion
entry:
@Article{Jenkins:1988:SCP,
  author =       "W. K. Jenkins and E. J. Altman",
  title =        "Self-checking properties of residue number error
                 checkers based on mixed radix conversion",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST,
  volume =       "35",
  number =       "2",
  pages =        "159--167",
  month =        feb,
  year =         "1988",
  CODEN =        "ICSYBT",
  DOI =          "https://doi.org/10.1109/31.1717",
  ISSN =         "0098-4094 (print), 1558-1276 (electronic)",
  ISSN-L =       "0098-4094",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=107",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems",
  keywords =     "residue arithmetic; residue number system",
  summary =      "It has been shown previously that a mixed-radix
                 converter can be modified to perform all the essential
                 functions of an error checker for error detection and
                 correction in residue number system hardware
                 architectures. Since the computations in a \ldots{}",
}


bibtype: phdthesis
filename: fparith.bib
label: Johnstone:1988:DFP
author: Paul Johnstone
title: Decimal floating point representation
type: Thesis (Ph.D.)
school: Tulane University
address: New Orleans, LA 70118, USA
pages: vi + 101
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Binary system (Mathematics); decimal floating-point arithmetic; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Paul Johnstone
rawtitle: Decimal floating point representation
entry:
@PhdThesis{Johnstone:1988:DFP,
  author =       "Paul Johnstone",
  title =        "Decimal floating point representation",
  type =         "Thesis ({Ph.D.})",
  school =       "Tulane University",
  address =      "New Orleans, LA 70118, USA",
  pages =        "vi + 101",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Binary system (Mathematics); decimal floating-point
                 arithmetic; Floating-point arithmetic.",
}


bibtype: techreport
filename: fparith.bib
label: Jouppi:1988:MFA
author: Norman Paul Jouppi and Jeremy Dion and David Reeves Boggs and Michael J. K. Nielsen
title: MultiTitan: four architecture papers
institution: Digital Western Research Laboratory
address: Palo Alto, CA, USA
edition: [Revised]
pages: various
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: WRL research report; 87/8
keywords: Computer architecture.; MultiTitan (Computer)
acknowledgement: ack-nhfb
rawauthor: Norman Paul Jouppi and Jeremy Dion and David Reeves Boggs and Michael J. K. Nielsen
rawtitle: {MultiTitan}: four architecture papers
remark:
``April 10, 1988.'' MultiTitan central processor unit / Norman P. Jouppi --- MultiTitan floating point unit / Norman P. Jouppi --- MultiTitan cache control unit / Jeremy Dion --- MultiTitan intra-processor bus / David Boggs, Jeremy Dion, Michael J. K. Nielsen.

entry:
@TechReport{Jouppi:1988:MFA,
  author =       "Norman Paul Jouppi and Jeremy Dion and David Reeves
                 Boggs and Michael J. K. Nielsen",
  title =        "{MultiTitan}: four architecture papers",
  institution =  "Digital Western Research Laboratory",
  address =      "Palo Alto, CA, USA",
  edition =      "[Revised]",
  pages =        "various",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "WRL research report; 87/8",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture.; MultiTitan (Computer)",
  remark =       "``April 10, 1988.'' MultiTitan central processor unit
                 / Norman P. Jouppi --- MultiTitan floating point unit /
                 Norman P. Jouppi --- MultiTitan cache control unit /
                 Jeremy Dion --- MultiTitan intra-processor bus / David
                 Boggs, Jeremy Dion, Michael J. K. Nielsen.",
}


bibtype: techreport
filename: fparith.bib
label: Jouppi:1988:UVS
author: Norman P. Jouppi and Jonathan Bertoni and David W. Wall
title: A unified vector / scalar floating-point architecture
type: Report
number: WRL TN-3
institution: Digital Western Research Laboratory
address: Palo Alto, CA, USA
pages: 19
year: 1988
bibdate: Thu May 09 08:38:06 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 08:38:06 ???
acknowledgement: ack-nhfb
rawauthor: Norman P. Jouppi and Jonathan Bertoni and David W. Wall
rawtitle: A unified vector\slash scalar floating-point architecture
entry:
@TechReport{Jouppi:1988:UVS,
  author =       "Norman P. Jouppi and Jonathan Bertoni and David W.
                 Wall",
  title =        "A unified vector\slash scalar floating-point
                 architecture",
  type =         "Report",
  number =       "WRL TN-3",
  institution =  "Digital Western Research Laboratory",
  address =      "Palo Alto, CA, USA",
  pages =        "19",
  year =         "1988",
  bibdate =      "Thu May 09 08:38:06 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Joy:1988:OCT
author: Edward Bennett Joy and Paul R. Beaudet and Pankaj K. Das
title: Optical communications techniques / floating point residue number system
institution: School of Electrical Engineering, Georgia Institute of Technology
address: Atlanta, GA, USA
pages: 17
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer network architectures.; Computers --- Optical equipment.
acknowledgement: ack-nhfb
rawauthor: Edward Bennett Joy and Paul R. Beaudet and Pankaj K. Das
rawtitle: Optical communications techniques\slash floating point residue number system
remark:
Issued as R and D status reports [nos. 1--7], Contract funds status reports [nos. 1--8], Final technical report, and Final report, Project E-21-T01. Final technical report has author: Paul R. Beaudet. Final report has author: Pankaj K. Das. Final technical report has title: Floating point residue number system. Final report has title: New techniques in optical communications and signal processing.

entry:
@TechReport{Joy:1988:OCT,
  author =       "Edward Bennett Joy and Paul R. Beaudet and Pankaj K.
                 Das",
  title =        "Optical communications techniques\slash floating point
                 residue number system",
  institution =  "School of Electrical Engineering, Georgia Institute of
                 Technology",
  address =      "Atlanta, GA, USA",
  pages =        "17",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer network architectures.; Computers --- Optical
                 equipment.",
  remark =       "Issued as R and D status reports [nos. 1--7], Contract
                 funds status reports [nos. 1--8], Final technical
                 report, and Final report, Project E-21-T01. Final
                 technical report has author: Paul R. Beaudet. Final
                 report has author: Pankaj K. Das. Final technical
                 report has title: Floating point residue number system.
                 Final report has title: New techniques in optical
                 communications and signal processing.",
}


bibtype: article
filename: fparith.bib
label: Juffa:1988:SAF
author: N. Juffa
title: Schnelle Algorithmen fur Sin und Cos toenglish Fast Algorithms for Sin and Cos endtoenglish
journal: j-MC
volume: 5
pages: 105--107
year: 1988
ISSN: 0720-4442, 0941-777x, 0943-5409 OR 07204442, 0941777x, 09435409
bibdate: Fri Sep 16 16:30:41 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:41 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: N. Juffa
rawtitle:
{Schnelle Algorithmen f{\"u}r Sin und Cos} \toenglish {Fast Algorithms for Sin and Cos} \endtoenglish

entry:
@Article{Juffa:1988:SAF,
  author =       "N. Juffa",
  title =        "{Schnelle Algorithmen f{\"u}r Sin und Cos} \toenglish
                 {Fast Algorithms for Sin and Cos} \endtoenglish",
  journal =      j-MC,
  volume =       "5",
  pages =        "105--107",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x, 0943-5409",
  bibdate =      "Fri Sep 16 16:30:41 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: misc
filename: fparith.bib
label: Kahan:1988:AFP
author: William Kahan
title: Arithmazium: The Floating Point Expose
pages: 105--107
month: may
monthnumber: 5
year: 1988
bibdate: Wed Jun 05 09:50:01 2024
bibtimestamp: 2024.06.05 09:50:01 ???
URL: https://www.arithmazium.org/classroom/wk88_toc.html
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: William Kahan
rawtitle: Arithmazium: The Floating Point Expos{\'e}
note:
This site includes 27 lectures with notes and videos for CS 279 (Computer System Support for Scientific and Engineering Computation). The class handouts amount to more than 2000 pages.

rawnote:
This site includes 27 lectures with notes and videos for CS 279 (Computer System Support for Scientific and Engineering Computation). The class handouts amount to more than 2000 pages.

entry:
@Misc{Kahan:1988:AFP,
  author =       "William Kahan",
  title =        "Arithmazium: The Floating Point Expos{\'e}",
  howpublished = "Web site",
  month =        may # "\slash " # jul,
  year =         "1988",
  bibdate =      "Wed Jun 05 09:50:01 2024",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This site includes 27 lectures with notes and videos
                 for CS 279 (Computer System Support for Scientific and
                 Engineering Computation). The class handouts amount to
                 more than 2000 pages.",
  URL =          "https://www.arithmazium.org/classroom/wk88_toc.html",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Kahan:1988:CSS
author: W. Kahan and David Goldberg
title: Computer System Support for Scientific and Engineering Computation
type: Report
institution: inst-BERKELEY-CS
address: inst-BERKELEY-CS:adr
pages: 105--107
day: 26
month: jul
monthnumber: 7
year: 1988
bibdate: Mon Aug 26 10:39:23 2024
bibtimestamp: 2024.08.26 10:39:23 ???
note: Revised 14 June 1990.
URL: http://www.arithmazium.org/classroom/lib//Lecture_25_notes_slides.pdf
acknowledgement: ack-nhfb
rawauthor: W. Kahan and David Goldberg
rawnote: Revised 14 June 1990.
rawtitle: Computer System Support for Scientific and Engineering Computation
entry:
@TechReport{Kahan:1988:CSS,
  author =       "W. Kahan and David Goldberg",
  title =        "Computer System Support for Scientific and Engineering
                 Computation",
  type =         "Report",
  institution =  inst-BERKELEY-CS,
  address =      inst-BERKELEY-CS:adr,
  day =          "26",
  month =        jul,
  year =         "1988",
  bibdate =      "Mon Aug 26 10:39:23 2024",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Revised 14 June 1990.",
  URL =          "http://www.arithmazium.org/classroom/lib//Lecture_25_notes_slides.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kahaner:1988:BRP
author: D. K. Kahaner
title: Benchmarks for `real' programs
journal: j-SIAM-NEWS
pages: A-61
month: nov
monthnumber: 11
year: 1988
ISSN: 0036-1437 OR 00361437
ISSNL: 0036-1437 OR 00361437
bibdate: Mon Sep 16 16:15:31 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.09.16 16:15:31 ???
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: https://sinews.siam.org/
rawauthor: D. K. Kahaner
rawtitle: Benchmarks for `real' programs
entry:
@Article{Kahaner:1988:BRP,
  author =       "D. K. Kahaner",
  title =        "Benchmarks for `real' programs",
  journal =      j-SIAM-NEWS,
  pages =        "A-61",
  month =        nov,
  year =         "1988",
  ISSN =         "0036-1437",
  ISSN-L =       "0036-1437",
  bibdate =      "Mon Sep 16 16:15:31 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "https://sinews.siam.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Kanada:1988:VMA
author: Yasumasa Kanada
booktitle: Proceedings of Supercomputing 88. Vol. II: Science and Applications
crossref: Martin:1988:SPN
volume: 2
pages: 117--128
year: 1988
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
corpsource: Comput. Centre, Tokyo University, Japan
treatment: P Practical
rawauthor: Yasumasa Kanada
rawbooktitle: Proceedings of Supercomputing 88. Vol. {II}: Science and Applications
title:
Vectorization of multiple-precision arithmetic program and 201,326,000 decimal digits of $ pi $ calculation

bibsource:
https://www.math.utah.edu/pub/tex/bib/agm.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pi.bib

abstract:
More than 200 million decimal places of $ pi $ were calculated using an arithmetic geometric mean formula independently discovered by E. Salamin and R. P. Brent in 1976. Correctness of the calculation was verified through Borwein's quartic convergent formula developed in 1983. The computation took CPU times of 5 hours 57 minutes for the main calculation and 7 hours 30 minutes for the verification calculation on the HITAC S-820 model 80 supercomputer with 256 MB of main memory and 3 GB of high speed semiconductor storage, Extended Storage, to shorten I/O time.par Computation was completed in 27th of January 1988. At that day two programs generated values up to $ 3 times 2^26 $, about 201 million. The two results agreed except for the last 21 digits. These results also agree with the 133,554,000 places of calculation of $ pi $ which was done by the author in January 1987. Compare to the record in 1987, 50% more decimal digits were calculated with about $ 1 / 6 $ of CPU time.par Computation was performed with real arithmetic based vectorized Fast Fourier Transform (FFT) multiplier and newly vectorized multiple-precision add, subtract and (single word) constant multiplication programs. Vectorizations for the later cases were realized through first order linear recurrence vector instruction on the S-820. Details of the computation and statistical tests on the first 200 million digits of $ pi - 3 $ are reported.

keywords:
arithmetic geometric mean formula; Borwein's quartic convergent formula; fast Fourier transform; fast Fourier transforms; first order linear recurrence vector instruction; HITAC S-820 model 80 supercomputer; mathematics computing; multiple-precision arithmetic program; multiplier; parallel processing; pi calculation; S-820; vectorization

rawabstract:
More than 200 million decimal places of {$ \pi $} were calculated using an arithmetic geometric mean formula independently discovered by E. Salamin and R. P. Brent in 1976. Correctness of the calculation was verified through Borwein's quartic convergent formula developed in 1983. The computation took CPU times of 5 hours 57 minutes for the main calculation and 7 hours 30 minutes for the verification calculation on the HITAC S-820 model 80 supercomputer with 256 MB of main memory and 3 GB of high speed semiconductor storage, Extended Storage, to shorten I/O time.\par Computation was completed in 27th of January 1988. At that day two programs generated values up to $ 3 \times 2^{26} $, about 201 million. The two results agreed except for the last 21 digits. These results also agree with the 133,554,000 places of calculation of $ \pi $ which was done by the author in January 1987. Compare to the record in 1987, 50\% more decimal digits were calculated with about $ 1 / 6 $ of CPU time.\par Computation was performed with real arithmetic based vectorized Fast Fourier Transform (FFT) multiplier and newly vectorized multiple-precision add, subtract and (single word) constant multiplication programs. Vectorizations for the later cases were realized through first order linear recurrence vector instruction on the S-820. Details of the computation and statistical tests on the first 200 million digits of $ \pi - 3 $ are reported.

rawtitle:
Vectorization of multiple-precision arithmetic program and 201,326,000 decimal digits of {$ \pi $} calculation

entry:
@InProceedings{Kanada:1988:VMA,
  author =       "Yasumasa Kanada",
  booktitle =    "Proceedings of Supercomputing 88. Vol. {II}: Science
                 and Applications",
  title =        "Vectorization of multiple-precision arithmetic program
                 and 201,326,000 decimal digits of {$ \pi $}
                 calculation",
  crossref =     "Martin:1988:SPN",
  volume =       "2",
  pages =        "117--128",
  year =         "1988",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/agm.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pi.bib",
  abstract =     "More than 200 million decimal places of {$ \pi $} were
                 calculated using an arithmetic geometric mean formula
                 independently discovered by E. Salamin and R. P. Brent
                 in 1976. Correctness of the calculation was verified
                 through Borwein's quartic convergent formula developed
                 in 1983. The computation took CPU times of 5 hours 57
                 minutes for the main calculation and 7 hours 30 minutes
                 for the verification calculation on the HITAC S-820
                 model 80 supercomputer with 256 MB of main memory and 3
                 GB of high speed semiconductor storage, Extended
                 Storage, to shorten I/O time.\par Computation was
                 completed in 27th of January 1988. At that day two
                 programs generated values up to $ 3 \times 2^{26} $,
                 about 201 million. The two results agreed except for
                 the last 21 digits. These results also agree with the
                 133,554,000 places of calculation of $ \pi $ which was
                 done by the author in January 1987. Compare to the
                 record in 1987, 50\% more decimal digits were
                 calculated with about $ 1 / 6 $ of CPU time.\par
                 Computation was performed with real arithmetic based
                 vectorized Fast Fourier Transform (FFT) multiplier and
                 newly vectorized multiple-precision add, subtract and
                 (single word) constant multiplication programs.
                 Vectorizations for the later cases were realized
                 through first order linear recurrence vector
                 instruction on the S-820. Details of the computation
                 and statistical tests on the first 200 million digits
                 of $ \pi - 3 $ are reported.",
  acknowledgement = ack-nhfb,
  classification = "C4190 (Other numerical methods); C7310
                 (Mathematics)",
  corpsource =   "Comput. Centre, Tokyo University, Japan",
  keywords =     "arithmetic geometric mean formula; Borwein's quartic
                 convergent formula; fast Fourier transform; fast
                 Fourier transforms; first order linear recurrence
                 vector instruction; HITAC S-820 model 80 supercomputer;
                 mathematics computing; multiple-precision arithmetic
                 program; multiplier; parallel processing; pi
                 calculation; S-820; vectorization",
  sponsororg =   "IEEE; ACM SIGARCH",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Kanada:1988:VMP
author: Yasumasa Kanada
booktitle: Proceedings of Supercomputing 88. Vol. II: Science and Applications
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 117--128
year: 1988
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
rawauthor: Yasumasa Kanada
rawbooktitle: Proceedings of Supercomputing 88. Vol. {II}: Science and Applications
title:
Vectorization of multiple-precision arithmetic program and 201,326,000 decimal digits of $ pi $ calculation

abstract:
More than 200 million decimal places of pi were calculated using an arithmetic geometric mean formula independently discovered by E. Salamin and R. P. Brent in 1976. Correctness of the calculation was verified through Borwein's quartic convergent formula developed in 1983. The computation took CPU times of 5 hours 57 minutes for the main calculation and 7 hours 30 minutes for the verification calculation on the HITAC S-820 model 80 supercomputer with 256 MB of main memory and 3 GB of high speed semiconductor storage, Extended Storage, to shorten I/O time.par Computation was completed in 27th of January 1988. At that day two programs generated values up to $ 3 times 2^26 $, about 201 million. The two results agreed except for the last 21 digits. These results also agree with the 133,554,000 places of calculation of $ pi $ which was done by the author in January 1987. Compare to the record in 1987, 50% more decimal digits were calculated with about $ 1 / 6 $ of CPU time.par Computation was performed with real arithmetic based vectorized Fast Fourier Transform (FFT) multiplier and newly vectorized multiple-precision add, subtract and (single word) constant multiplication programs. Vectorizations for the later cases were realized through first order linear recurrence vector instruction on the S-820. Dertails of the computation and statistical tests on the first 200 million digits of $ pi - 3 $ are reported.

rawabstract:
More than 200 million decimal places of {\pi} were calculated using an arithmetic geometric mean formula independently discovered by E. Salamin and R. P. Brent in 1976. Correctness of the calculation was verified through Borwein's quartic convergent formula developed in 1983. The computation took CPU times of 5 hours 57 minutes for the main calculation and 7 hours 30 minutes for the verification calculation on the HITAC S-820 model 80 supercomputer with 256 MB of main memory and 3 GB of high speed semiconductor storage, Extended Storage, to shorten I/O time.\par Computation was completed in 27th of January 1988. At that day two programs generated values up to $ 3 \times 2^{26} $, about 201 million. The two results agreed except for the last 21 digits. These results also agree with the 133,554,000 places of calculation of $ \pi $ which was done by the author in January 1987. Compare to the record in 1987, 50\% more decimal digits were calculated with about $ 1 / 6 $ of CPU time.\par Computation was performed with real arithmetic based vectorized Fast Fourier Transform (FFT) multiplier and newly vectorized multiple-precision add, subtract and (single word) constant multiplication programs. Vectorizations for the later cases were realized through first order linear recurrence vector instruction on the S-820. Dertails of the computation and statistical tests on the first 200 million digits of $ \pi - 3 $ are reported.

rawtitle:
Vectorization of multiple-precision arithmetic program and 201,326,000 decimal digits of {$ \pi $} calculation

entry:
@InProceedings{Kanada:1988:VMP,
  author =       "Yasumasa Kanada",
  booktitle =    "Proceedings of Supercomputing 88. Vol. {II}: Science
                 and Applications",
  title =        "Vectorization of multiple-precision arithmetic program
                 and 201,326,000 decimal digits of {$ \pi $}
                 calculation",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "117--128",
  year =         "1988",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "More than 200 million decimal places of {\pi} were
                 calculated using an arithmetic geometric mean formula
                 independently discovered by E. Salamin and R. P. Brent
                 in 1976. Correctness of the calculation was verified
                 through Borwein's quartic convergent formula developed
                 in 1983. The computation took CPU times of 5 hours 57
                 minutes for the main calculation and 7 hours 30 minutes
                 for the verification calculation on the HITAC S-820
                 model 80 supercomputer with 256 MB of main memory and 3
                 GB of high speed semiconductor storage, Extended
                 Storage, to shorten I/O time.\par

                 Computation was completed in 27th of January 1988. At
                 that day two programs generated values up to $ 3 \times
                 2^{26} $, about 201 million. The two results agreed
                 except for the last 21 digits. These results also agree
                 with the 133,554,000 places of calculation of $ \pi $
                 which was done by the author in January 1987. Compare
                 to the record in 1987, 50\% more decimal digits were
                 calculated with about $ 1 / 6 $ of CPU
                 time.\par

                 Computation was performed with real arithmetic based
                 vectorized Fast Fourier Transform (FFT) multiplier and
                 newly vectorized multiple-precision add, subtract and
                 (single word) constant multiplication programs.
                 Vectorizations for the later cases were realized
                 through first order linear recurrence vector
                 instruction on the S-820. Dertails of the computation
                 and statistical tests on the first 200 million digits
                 of $ \pi - 3 $ are reported.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kida:1988:FPP
author: H. Kida and M. Watabe and T. Nakamikawa and S. Morinaga and S. Kawasaki and H. Inayoshi
title: A floating point processing unit for the GMICRO CPU
crossref: Sakamura:1988:TPO
pages: 301--316
year: 1988
DOI: https://doi.org/10.1007/978-4-431-68081-9_21
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Hitachi Ltd., Tokyo, Japan
bookpages: xi + 384
thesaurus: Computer architecture; Microprocessor chips
rawauthor: H. Kida and M. Watabe and T. Nakamikawa and S. Morinaga and S. Kawasaki and H. Inayoshi
rawtitle: A floating point processing unit for the {GMICRO} {CPU}
abstract:
Describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit GMICRO microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic. High performance was achieved by the high speed coprocessor's interface with the GMICRO CPU and the pipeline processing. The coprocessor's interface was designed to minimize CPU-FPU communication overhead caused by transferring commands, operands and coprocessor information. Furthermore, to improve operation speed, the FPU performs pipeline processing named command pipeline. The FPU has three main elements, the bus control unit, format conversion unit, and execution control unit. In order to perform high speed calculations, each element in the chip is designed to operate in parallel. (5 Refs.)

keywords:
32 Bit; Coprocessor; Floating point processing unit; FPU; GMICRO CPU; GMICRO microprocessor; IEEE 754; Standard for Binary Floating-Point Arithmetic

rawabstract:
Describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit GMICRO microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic. High performance was achieved by the high speed coprocessor's interface with the GMICRO CPU and the pipeline processing. The coprocessor's interface was designed to minimize CPU-FPU communication overhead caused by transferring commands, operands and coprocessor information. Furthermore, to improve operation speed, the FPU performs pipeline processing named command pipeline. The FPU has three main elements, the bus control unit, format conversion unit, and execution control unit. In order to perform high speed calculations, each element in the chip is designed to operate in parallel. (5 Refs.)

entry:
@InProceedings{Kida:1988:FPP,
  author =       "H. Kida and M. Watabe and T. Nakamikawa and S.
                 Morinaga and S. Kawasaki and H. Inayoshi",
  title =        "A floating point processing unit for the {GMICRO}
                 {CPU}",
  crossref =     "Sakamura:1988:TPO",
  bookpages =    "xi + 384",
  pages =        "301--316",
  year =         "1988",
  DOI =          "https://doi.org/10.1007/978-4-431-68081-9_21",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Describes the architecture and implementation of a
                 newly developed floating point processing unit (FPU).
                 It was developed as a high performance 32-bit
                 coprocessor of the 32-bit GMICRO microprocessor, which
                 satisfies the IEEE 754 Standard for Binary
                 Floating-Point Arithmetic. High performance was
                 achieved by the high speed coprocessor's interface with
                 the GMICRO CPU and the pipeline processing. The
                 coprocessor's interface was designed to minimize
                 CPU-FPU communication overhead caused by transferring
                 commands, operands and coprocessor information.
                 Furthermore, to improve operation speed, the FPU
                 performs pipeline processing named command pipeline.
                 The FPU has three main elements, the bus control unit,
                 format conversion unit, and execution control unit. In
                 order to perform high speed calculations, each element
                 in the chip is designed to operate in parallel. (5
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Hitachi Ltd., Tokyo, Japan",
  classification = "C5220 (Computer architecture)",
  confdate =     "1988",
  conflocation = "Japan",
  keywords =     "32 Bit; Coprocessor; Floating point processing unit;
                 FPU; GMICRO CPU; GMICRO microprocessor; IEEE 754;
                 Standard for Binary Floating-Point Arithmetic",
  numericalindex = "Word length 3.2E+01 bit",
  pubcountry =   "Japan",
  thesaurus =    "Computer architecture; Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Kirchner:1988:AAV
author: R. Kirchner and U. Kulisch
title: Accurate arithmetic for vector processors
journal: j-J-PAR-DIST-COMP
volume: 5
number: 3
pages: 250--270
month: jun
monthnumber: 6
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Univ Kaiserslautern, West Ger
corpsource: Fachbereich Inf., Kaiserslautern University, West Germany
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical
rawauthor: R. Kirchner and U. Kulisch
rawtitle: Accurate arithmetic for vector processors
keywords:
arithmetic operations; Computational Methods; computer systems, digital --- Parallel Processing; computers; computers, digital; computers, microcomputer; digital arithmetic; dot products; implementation techniques; local memory; microcomputers; parallel; parallel processing; pipelined compound operations; sums; vector processors; VLSI technology

entry:
@Article{Kirchner:1988:AAV,
  author =       "R. Kirchner and U. Kulisch",
  title =        "Accurate arithmetic for vector processors",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "3",
  pages =        "250--270",
  month =        jun,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Univ Kaiserslautern, West Ger",
  classification = "721; 722; 723; C5230 (Digital arithmetic methods);
                 C5440 (Multiprocessor systems and techniques)",
  corpsource =   "Fachbereich Inf., Kaiserslautern University, West
                 Germany",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "arithmetic operations; Computational Methods; computer
                 systems, digital --- Parallel Processing; computers;
                 computers, digital; computers, microcomputer; digital
                 arithmetic; dot products; implementation techniques;
                 local memory; microcomputers; parallel; parallel
                 processing; pipelined compound operations; sums; vector
                 processors; VLSI technology",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Knuth:1988:FM
author: Donald E. Knuth
title: Fibonacci multiplication
journal: j-APPL-MATH-LETT
volume: 1
number: 1
pages: 57--60
year: 1988
CODEN: AMLEEL
ISSN: 0893-9659 (print), 1873-5452 (electronic) OR 08939659 (print), 18735452 (electronic)
ISSNL: 0893-9659 OR 08939659
MRclass: 11B39
MRnumber: 89f:11031
MRreviewer: W. Herget
bibdate: Fri Mar 22 18:03:29 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database
bibtimestamp: 2002.03.22 18:03:29 MST
fjournal: Applied Mathematics Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08939659
rawauthor: Donald E. Knuth
rawtitle: {Fibonacci} multiplication
entry:
@Article{Knuth:1988:FM,
  author =       "Donald E. Knuth",
  title =        "{Fibonacci} multiplication",
  journal =      j-APPL-MATH-LETT,
  volume =       "1",
  number =       "1",
  pages =        "57--60",
  year =         "1988",
  CODEN =        "AMLEEL",
  ISSN =         "0893-9659 (print), 1873-5452 (electronic)",
  ISSN-L =       "0893-9659",
  MRclass =      "11B39",
  MRnumber =     "89f:11031",
  MRreviewer =   "W. Herget",
  bibdate =      "Fri Mar 22 18:03:29 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08939659",
}


bibtype: article
filename: fparith.bib
label: Kornerup:1988:LAU
author: Peter Kornerup and David W. Matula
title: An on-line arithmetic unit for bit-pipelined rational arithmetic
journal: j-J-PAR-DIST-COMP
volume: 5
number: 3
pages: 310--330
month: jun
monthnumber: 6
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Odense Univ, Odense, Den
corpsource: Odense University, Denmark
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical
rawauthor: Peter Kornerup and David W. Matula
rawtitle: An on-line arithmetic unit for bit-pipelined rational arithmetic
keywords:
algorithm of Gosper; Algorithms; binary version; bit-pipelined rational arithmetic; computer metatheory --- Binary Sequences; computer programming; computers, digital --- Computational Methods; difference; digital arithmetic; functions; mathematical techniques --- Algorithms; on-line arithmetic unit; online arithmetic unit; product; quotient; rational; sum

entry:
@Article{Kornerup:1988:LAU,
  author =       "Peter Kornerup and David W. Matula",
  title =        "An on-line arithmetic unit for bit-pipelined rational
                 arithmetic",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "3",
  pages =        "310--330",
  month =        jun,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Odense Univ, Odense, Den",
  classification = "722; 723; 921; C5230 (Digital arithmetic methods)",
  corpsource =   "Odense University, Denmark",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "algorithm of Gosper; Algorithms; binary version;
                 bit-pipelined rational arithmetic; computer metatheory
                 --- Binary Sequences; computer programming; computers,
                 digital --- Computational Methods; difference; digital
                 arithmetic; functions; mathematical techniques ---
                 Algorithms; on-line arithmetic unit; online arithmetic
                 unit; product; quotient; rational; sum",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishnan:1988:IRN
author: R. Krishnan
booktitle: IEEE International Symposium on Circuits and Systems, 7--9 June 1988
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1297--1300
year: 1988
DOI: https://doi.org/10.1109/ISCAS.1988.15166
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Krishnan
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 7--9 June 1988
title:
Implementation of recursive and nonrecursive digital filters using the single multiplexed ROM in the quadratic residue number system

rawtitle:
Implementation of recursive and nonrecursive digital filters using the single multiplexed {ROM} in the quadratic residue number system

entry:
@InProceedings{Krishnan:1988:IRN,
  author =       "R. Krishnan",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 7--9 June 1988",
  title =        "Implementation of recursive and nonrecursive digital
                 filters using the single multiplexed {ROM} in the
                 quadratic residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1297--1300",
  year =         "1988",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1988.15166",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Recursive and nonrecursive digital filters have been
                 implemented using the proposed single-multiplexed
                 dual-clock computational module (SDCM) in the bit-slice
                 architecture. The amount of memory requirements has
                 been reduced to 50\% required for the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishnan:1988:SCR
author: R. Krishnan
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-88, 11--14 April 1988
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1842--1845
year: 1988
DOI: https://doi.org/10.1109/ICASSP.1988.196981
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Krishnan
title:
A single-channel ROM-based complex digital filter implementation in the quadratic residue number systems

rawbooktitle:
International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-88, 11--14} April 1988

rawtitle:
A single-channel {ROM}-based complex digital filter implementation in the quadratic residue number systems

entry:
@InProceedings{Krishnan:1988:SCR,
  author =       "R. Krishnan",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-88, 11--14} April 1988",
  title =        "A single-channel {ROM}-based complex digital filter
                 implementation in the quadratic residue number
                 systems",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1842--1845",
  year =         "1988",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1988.196981",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The implementation of complex digital filters using
                 the quadratic residue number system (QRNs) and modified
                 quadratic residue number system (MQRNS) is considered.
                 These QRNS/MQRNS-based filter architectures are
                 memory-intensive because the lookup- \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Lai:1988:FAI
author: K. Lai and J. Valerio
title: The floating-point architecture of Intel's 80960
crossref: Wescon:1988:WCR
pages: 1.5/1--3
year: 1988
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Intel Corp., Hillsboro, OR, USA
thesaurus: Computer architecture; Digital arithmetic; Microprocessor chips
rawauthor: K. Lai and J. Valerio
rawtitle: The floating-point architecture of {Intel's 80960}
abstract:
The Intel 80960KB is a microprocessor with hardware floating-point support integrated on-chip. In a departure from previous microprocessors, the 80960KB incorporates full floating-point support within the processor instead of relying on a coprocessor. As floating-point speeds increase, the off-chip coprocessor interface becomes a significant performance bottleneck. Additionally, component and system cost, board space, and cleanliness of architecture are other good reasons to have on-chip floating-point support. The implementation delivers accurate results with good performance: 1.1 single-precision Linpack MFLOPS, and 4.1 single-precision mega-Whetstones per second. (0 Refs.)

keywords:
1.1 MFLOPS; Board space; Cleanliness; Component costs; Floating-point architecture; Intel 80960KB; Linpack; Microprocessor; On-chip floating-point support; Performance; System cost

rawabstract:
The Intel 80960KB is a microprocessor with hardware floating-point support integrated on-chip. In a departure from previous microprocessors, the 80960KB incorporates full floating-point support within the processor instead of relying on a coprocessor. As floating-point speeds increase, the off-chip coprocessor interface becomes a significant performance bottleneck. Additionally, component and system cost, board space, and cleanliness of architecture are other good reasons to have on-chip floating-point support. The implementation delivers accurate results with good performance: 1.1 single-precision Linpack MFLOPS, and 4.1 single-precision mega-Whetstones per second. (0 Refs.)

entry:
@InProceedings{Lai:1988:FAI,
  author =       "K. Lai and J. Valerio",
  title =        "The floating-point architecture of {Intel's 80960}",
  crossref =     "Wescon:1988:WCR",
  pages =        "1.5/1--3",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Intel 80960KB is a microprocessor with hardware
                 floating-point support integrated on-chip. In a
                 departure from previous microprocessors, the 80960KB
                 incorporates full floating-point support within the
                 processor instead of relying on a coprocessor. As
                 floating-point speeds increase, the off-chip
                 coprocessor interface becomes a significant performance
                 bottleneck. Additionally, component and system cost,
                 board space, and cleanliness of architecture are other
                 good reasons to have on-chip floating-point support.
                 The implementation delivers accurate results with good
                 performance: 1.1 single-precision Linpack MFLOPS, and
                 4.1 single-precision mega-Whetstones per second. (0
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp., Hillsboro, OR, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods)",
  keywords =     "1.1 MFLOPS; Board space; Cleanliness; Component costs;
                 Floating-point architecture; Intel 80960KB; Linpack;
                 Microprocessor; On-chip floating-point support;
                 Performance; System cost",
  numericalindex = "Computer speed 1.1E+06 FLOPS",
  thesaurus =    "Computer architecture; Digital arithmetic;
                 Microprocessor chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Lai:1988:IFS
author: K. Lai and J. Valerio
title: Integrated floating-point solution for the Intel 80960KB
crossref: Midcon:1988:MCP
pages: 249--251
year: 1988
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Intel Corp., Hillsboro, OR, USA
thesaurus: Digital arithmetic; Microprocessor chips
rawauthor: K. Lai and J. Valerio
rawtitle: Integrated floating-point solution for the {Intel 80960KB}
abstract:
The Intel 80960KB is a microprocessor with hardware floating-point support integrated on-chip. In a departure from previous microprocessors, the 80960KB incorporates full floating-point support within the processor instead of relying on a coprocessor. As floating-point speeds increase, the off-chip coprocessor interface becomes a significant performance bottleneck. Additionally, component and system cost, board space, and cleanliness of architecture are other good reasons to have on-chip floating-point support. The implementation delivers accurate results with good performance: 1.1 single precision Linpack MFLOPS, and 4.1 single precision mega Whetstones per second. (0 Refs.)

keywords:
Floating-point support; Integrated floating point; Intel 80960KB; Microprocessor; Onchip floating point

rawabstract:
The Intel 80960KB is a microprocessor with hardware floating-point support integrated on-chip. In a departure from previous microprocessors, the 80960KB incorporates full floating-point support within the processor instead of relying on a coprocessor. As floating-point speeds increase, the off-chip coprocessor interface becomes a significant performance bottleneck. Additionally, component and system cost, board space, and cleanliness of architecture are other good reasons to have on-chip floating-point support. The implementation delivers accurate results with good performance: 1.1 single precision Linpack MFLOPS, and 4.1 single precision mega Whetstones per second. (0 Refs.)

entry:
@InProceedings{Lai:1988:IFS,
  author =       "K. Lai and J. Valerio",
  title =        "Integrated floating-point solution for the {Intel
                 80960KB}",
  crossref =     "Midcon:1988:MCP",
  pages =        "249--251",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Intel 80960KB is a microprocessor with hardware
                 floating-point support integrated on-chip. In a
                 departure from previous microprocessors, the 80960KB
                 incorporates full floating-point support within the
                 processor instead of relying on a coprocessor. As
                 floating-point speeds increase, the off-chip
                 coprocessor interface becomes a significant performance
                 bottleneck. Additionally, component and system cost,
                 board space, and cleanliness of architecture are other
                 good reasons to have on-chip floating-point support.
                 The implementation delivers accurate results with good
                 performance: 1.1 single precision Linpack MFLOPS, and
                 4.1 single precision mega Whetstones per second. (0
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp., Hillsboro, OR, USA",
  classification = "C5130 (Microprocessor chips)",
  keywords =     "Floating-point support; Integrated floating point;
                 Intel 80960KB; Microprocessor; Onchip floating point",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Lawson:1988:SRR
author: Charles L. Lawson
title: Series reversion as the reversed chain rule
journal: j-SIGNUM
volume: 23
number: 1
pages: 7--9
month: jan
monthnumber: 1
year: 1988
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:16 MDT 2005
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 07:50:16 MDT
fjournal: ACM SIGNUM Newsletter
keywords: design; differentiation arithmetic; implicit functions; languages; theory
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/signum
rawauthor: Charles L. Lawson
rawtitle: Series reversion as the reversed chain rule
abstract:
Lawson gives Fortran subroutines for differentiation arithmetic. A subroutine SWPRO for products corresponds to Chang's ATS [Chang74a]. The chain rule is implemented by repeated calls to SWPRO. Series reversion for implicit functions is implemented by reversing the chain rule. An application is given to Keppler's equation, $ M - E + e sin (E) = 0 $.

subject:
D.3.3 Software, PROGRAMMING LANGUAGES, Language Constructs, Modules, packages G.4 Mathematics of Computing, MATHEMATICAL SOFTWARE D.3.3 Software, PROGRAMMING LANGUAGES, Language Constructs, Procedures, functions, and subroutines

rawabstract:
Lawson gives Fortran subroutines for differentiation arithmetic. A subroutine SWPRO for products corresponds to Chang's ATS [Chang74a]. The chain rule is implemented by repeated calls to SWPRO. Series reversion for implicit functions is implemented by reversing the chain rule. An application is given to Keppler's equation, $ M - E + e \sin (E) = 0 $.

entry:
@Article{Lawson:1988:SRR,
  author =       "Charles L. Lawson",
  title =        "Series reversion as the reversed chain rule",
  journal =      j-SIGNUM,
  volume =       "23",
  number =       "1",
  pages =        "7--9",
  month =        jan,
  year =         "1988",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:16 MDT 2005",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Lawson gives Fortran subroutines for differentiation
                 arithmetic. A subroutine SWPRO for products corresponds
                 to Chang's ATS [Chang74a]. The chain rule is
                 implemented by repeated calls to SWPRO. Series
                 reversion for implicit functions is implemented by
                 reversing the chain rule. An application is given to
                 Keppler's equation, $ M - E + e \sin (E) = 0 $.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "design; differentiation arithmetic; implicit
                 functions; languages; theory",
  subject =      "D.3.3 Software, PROGRAMMING LANGUAGES, Language
                 Constructs, Modules, packages \\ G.4 Mathematics of
                 Computing, MATHEMATICAL SOFTWARE \\ D.3.3 Software,
                 PROGRAMMING LANGUAGES, Language Constructs, Procedures,
                 functions, and subroutines",
}


bibtype: techreport
filename: fparith.bib
label: Liu:1988:BEF
author: Zhi-Shun Alex Liu
title: Berkeley Elementary Function Test Suite
address: Berkeley, CA, USA
pages: ii + 59
day: 30
month: dec
monthnumber: 12
year: 1988
bibdate: Mon Sep 12 23:52:34 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.12 23:52:34 ???
URL: http://www.netlib.org/fp/ucbtest.tgz; http://www.ucbtest.org/zaliu-papers/zaliu-beef-doc.pdf
keywords: BeEF test suite; floating-point testing
acknowledgement: ack-nj
rawauthor: Zhi-Shun Alex Liu
rawtitle: {Berkeley} Elementary Function Test Suite
institution:
Computer Science Division, Department of Electrical Engineering and Computer Science, Univerity of California at Berkeley

abstract:
A suite of programs is presented to test how accurately the elementary transcendental functions exp, log, sin, cos and atan have been implemented in a computer's run-time library. The suite is written in the language C and designed to run on any computer with binary floating-point arithmetic rounded in a reasonable way. The suite makes no appeal to extra-precise arithmetic; the tests use only whatever arithmetic capabilities are present in the environment where the transcendental functions are to be used. Despite this limitation, the tests run fast and deliver indication of accuracy to within a small fraction of an ULP (Unit in the Last Place) of the functions under test. This account includes the proofs of the test suite's claims to accuracy.

rawabstract:
A suite of programs is presented to test how accurately the elementary transcendental functions exp, log, sin, cos and atan have been implemented in a computer's run-time library. The suite is written in the language C and designed to run on any computer with binary floating-point arithmetic rounded in a reasonable way. The suite makes no appeal to extra-precise arithmetic; the tests use only whatever arithmetic capabilities are present in the environment where the transcendental functions are to be used. Despite this limitation, the tests run fast and deliver indication of accuracy to within a small fraction of an ULP (Unit in the Last Place) of the functions under test. This account includes the proofs of the test suite's claims to accuracy.

entry:
@TechReport{Liu:1988:BEF,
  author =       "Zhi-Shun Alex Liu",
  title =        "{Berkeley} Elementary Function Test Suite",
  institution =  "Computer Science Division, Department of Electrical
                 Engineering and Computer Science, Univerity of
                 California at Berkeley",
  address =      "Berkeley, CA, USA",
  pages =        "ii + 59",
  day =          "30",
  month =        dec,
  year =         "1988",
  bibdate =      "Mon Sep 12 23:52:34 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.netlib.org/fp/ucbtest.tgz;
                 http://www.ucbtest.org/zaliu-papers/zaliu-beef-doc.pdf",
  abstract =     "A suite of programs is presented to test how
                 accurately the elementary transcendental functions exp,
                 log, sin, cos and atan have been implemented in a
                 computer's run-time library. The suite is written in
                 the language C and designed to run on any computer with
                 binary floating-point arithmetic rounded in a
                 reasonable way. The suite makes no appeal to
                 extra-precise arithmetic; the tests use only whatever
                 arithmetic capabilities are present in the environment
                 where the transcendental functions are to be used.
                 Despite this limitation, the tests run fast and deliver
                 indication of accuracy to within a small fraction of an
                 ULP (Unit in the Last Place) of the functions under
                 test. This account includes the proofs of the test
                 suite's claims to accuracy.",
  acknowledgement = ack-nj,
  keywords =     "BeEF test suite; floating-point testing",
}


bibtype: inproceedings
filename: fparith.bib
label: Lu:1988:MCF
author: P. Y. Lu and A. Jain and J. Kung and P. H. Ang
title: A 30-MFLOP 32b CMOS Floating-Point Processor
crossref: IEEE:1988:IIS
pages: 28, 29, 285
year: 1988
bibdate: Fri Dec 08 13:04:40 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:04:40 ???
acknowledgement: ack-nj
rawauthor: P. Y. Lu and A. Jain and J. Kung and P. H. Ang
rawtitle: A 30-{MFLOP} 32b {CMOS} Floating-Point Processor
entry:
@InProceedings{Lu:1988:MCF,
  author =       "P. Y. Lu and A. Jain and J. Kung and P. H. Ang",
  title =        "A 30-{MFLOP} 32b {CMOS} Floating-Point Processor",
  crossref =     "IEEE:1988:IIS",
  pages =        "28, 29, 285",
  year =         "1988",
  bibdate =      "Fri Dec 08 13:04:40 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Luk:1988:AAB
author: Franklin T. Luk and Haesun Park
title: An analysis of algorithm-based fault tolerance techniques
journal: j-J-PAR-DIST-COMP
volume: 5
number: 2
pages: 172--184
month: apr
monthnumber: 4
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Cornell Univ, Ithaca, NY, USA
corpsource: Sch. of Electr. Eng., Cornell University, Ithaca, NY, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: T Theoretical or Mathematical
rawauthor: Franklin T. Luk and Haesun Park
rawtitle: An analysis of algorithm-based fault tolerance techniques
keywords:
algorithm-based fault tolerance; analysis; computation; computer programming --- Algorithms; computer systems, digital; decomposition; error analysis; Fault Tolerant Capability; fault tolerant computing; floating point error; Gaussian elimination; Gaussian elimination with pairwise pivoting; LU; lu decomposition; matrix algebra; pairwise pivoting; qr decomposition; QR decomposition; rank-one perturbation; rounding errors; roundoff errors; systolic array; transient error; unified checksum scheme

entry:
@Article{Luk:1988:AAB,
  author =       "Franklin T. Luk and Haesun Park",
  title =        "An analysis of algorithm-based fault tolerance
                 techniques",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "2",
  pages =        "172--184",
  month =        apr,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Cornell Univ, Ithaca, NY, USA",
  classification = "722; 723; C4110 (Error analysis in numerical
                 methods); C4140 (Linear algebra); C5230 (Digital
                 arithmetic methods); C5470 (Performance evaluation and
                 testing)",
  corpsource =   "Sch. of Electr. Eng., Cornell University, Ithaca, NY,
                 USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "algorithm-based fault tolerance; analysis;
                 computation; computer programming --- Algorithms;
                 computer systems, digital; decomposition; error
                 analysis; Fault Tolerant Capability; fault tolerant
                 computing; floating point error; Gaussian elimination;
                 Gaussian elimination with pairwise pivoting; LU; lu
                 decomposition; matrix algebra; pairwise pivoting; qr
                 decomposition; QR decomposition; rank-one perturbation;
                 rounding errors; roundoff errors; systolic array;
                 transient error; unified checksum scheme",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Lyu:1988:PFP
author: Chung-nan Lyu
title: Pipelined floating point divider with built-in testing circuits
type: Thesis (M.S.)
school: Ohio University
address: Athens, OH, USA
pages: 90
month: jun
monthnumber: 6
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: floating-point testing; parallel processing (electronic computers)
acknowledgement: ack-nhfb
rawauthor: Chung-nan Lyu
rawtitle: Pipelined floating point divider with built-in testing circuits
entry:
@MastersThesis{Lyu:1988:PFP,
  author =       "Chung-nan Lyu",
  title =        "Pipelined floating point divider with built-in testing
                 circuits",
  type =         "Thesis ({M.S.})",
  school =       "Ohio University",
  address =      "Athens, OH, USA",
  pages =        "90",
  month =        jun,
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point testing; parallel processing
                 (electronic computers)",
}


bibtype: article
filename: fparith.bib
label: Magenheimer:1988:IMD
author: Daniel J. Magenheimer and Liz Peters and Karl W. Peters and Dan Zuras
title: Integer Multiplication and Division on the HP Precision Architecture
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 8
pages: 980--990
month: aug
monthnumber: 8
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2248
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Aug 04 16:38:15 2001
bibtimestamp: 2001.08.04 16:38:15 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Daniel J. Magenheimer and Liz Peters and Karl W. Peters and Dan Zuras
rawtitle: Integer Multiplication and Division on the {HP Precision Architecture}
entry:
@Article{Magenheimer:1988:IMD,
  author =       "Daniel J. Magenheimer and Liz Peters and Karl W.
                 Peters and Dan Zuras",
  title =        "Integer Multiplication and Division on the {HP
                 Precision Architecture}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "8",
  pages =        "980--990",
  month =        aug,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2248",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Aug 04 16:38:15 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Marchyulaitis:1988:SRN
author: Saulyus Marchyulaui tis
journal: Statist. Problemy Upravleniya
volume: 82
pages: 57--68
year: 1988
MRclass: 65G05 (65C20)
MRnumber: 89k:65056
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
keywords: accurate floating-point summation
language: Russian
acknowledgement: ack-nhfb
rawauthor: Saulyus Marchyula{\u\i}tis
title:
Summation of real numbers in arithmetic with a floating point. A probability approach to determining the variance of absolute round-off error. (Russian)

rawtitle:
Summation of real numbers in arithmetic with a floating point. {A} probability approach to determining the variance of absolute round-off error. ({Russian})

entry:
@Article{Marchyulaitis:1988:SRN,
  author =       "Saulyus Marchyula{\u\i}tis",
  title =        "Summation of real numbers in arithmetic with a
                 floating point. {A} probability approach to determining
                 the variance of absolute round-off error. ({Russian})",
  journal =      "Statist. Problemy Upravleniya",
  volume =       "82",
  pages =        "57--68",
  year =         "1988",
  MRclass =      "65G05 (65C20)",
  MRnumber =     "89k:65056",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
  language =     "Russian",
}


bibtype: article
filename: fparith.bib
label: Maurer:1988:DVW
author: P. M. Maurer
title: Design Verification of the WE 32106 Math Accelerator Unit
journal: j-IEEE-DES-TEST-COMPUT
volume: 5
number: 3
pages: 11--21
month: jun
monthnumber: 6
year: 1988
ISSN: 0740-7475 (print), 1558-1918 (electronic) OR 07407475 (print), 15581918 (electronic)
ISSNL: 0740-7475 OR 07407475
bibdate: Wed Sep 7 22:32:00 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:00 ???
fjournal: IEEE Design & Test of Computers
acknowledgement: ack-nj
rawauthor: P. M. Maurer
rawtitle: Design Verification of the {WE} 32106 Math Accelerator Unit
entry:
@Article{Maurer:1988:DVW,
  author =       "P. M. Maurer",
  title =        "Design Verification of the {WE} 32106 Math Accelerator
                 Unit",
  journal =      j-IEEE-DES-TEST-COMPUT,
  volume =       "5",
  number =       "3",
  pages =        "11--21",
  month =        jun,
  year =         "1988",
  ISSN =         "0740-7475 (print), 1558-1918 (electronic)",
  ISSN-L =       "0740-7475",
  bibdate =      "Wed Sep 7 22:32:00 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "IEEE Design \& Test of Computers",
}


bibtype: article
filename: fparith.bib
label: McLellan:1988:DCF
author: E. J. McLellan and G. M. Wolrich and R. A. J. Yodlowski
title: Development of the CVAX floating-point chip
journal: j-DEC-TECH-J
number: 7
pages: 109--120
month: aug
monthnumber: 8
year: 1988
CODEN: DTJOEL
ISSN: 0898-901X OR 0898901X
bibdate: Wed Sep 7 22:32:00 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:00 ???
fjournal: Digital Technical Journal
acknowledgement: ack-nj
rawauthor: E. J. McLellan and G. M. Wolrich and R. A. J. Yodlowski
rawtitle: Development of the {CVAX} floating-point chip
entry:
@Article{McLellan:1988:DCF,
  author =       "E. J. McLellan and G. M. Wolrich and R. A. J.
                 Yodlowski",
  title =        "Development of the {CVAX} floating-point chip",
  journal =      j-DEC-TECH-J,
  volume =       "??",
  number =       "7",
  pages =        "109--120",
  month =        aug,
  year =         "1988",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Wed Sep 7 22:32:00 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Digital Technical Journal",
}


bibtype: inproceedings
filename: fparith.bib
label: Melear:1988:IFP
author: C. Melear
title: An integrated floating point unit for a RISC architecture
crossref: Wescon:1988:WCR
pages: 1.2/1--8
year: 1988
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Motorola, Austin, TX, USA
thesaurus: Digital arithmetic; Microprocessor chips; Reduced instruction set computing
rawauthor: C. Melear
rawtitle: An integrated floating point unit for a {RISC} architecture
abstract:
RISC architectures require multiple bus structures that allow for instructions, operands, and results to all travel about the processor on each clock cycle. Thus, by putting the floating point unit on these multiple bus structures, it can receive instructions and operands on each clock cycle. Some number of cycles later, as more floating point instructions are issued, floating point results can also be sent out on the destination bus, yielding burst execution rates equal to the clock rate. The present clock rate is 20 MHz and will be increased eventually to the 40 MHz area. At 20 MHz, sustained execution rates of 7 MFLOPS are typical. Performance rates of 10.5 MWhetstones have also been demonstrated (20 MHz clock). The floating point unit is only one part of the RISC processor. By combining all the aspects of software, memory system interfacing and high performance hardware like the 88100 floating point unit, mainframe performance moves one step closer to the desktop computer world.

keywords:
20 MHz; 7 MFLOPS; 88100 Floating point unit; Burst execution rates; Clock cycle; Clock rate; Desktop computer; Execution rates; Memory system interfacing; Multiple bus structures; Performance rates; RISC architecture

rawabstract:
RISC architectures require multiple bus structures that allow for instructions, operands, and results to all travel about the processor on each clock cycle. Thus, by putting the floating point unit on these multiple bus structures, it can receive instructions and operands on each clock cycle. Some number of cycles later, as more floating point instructions are issued, floating point results can also be sent out on the destination bus, yielding burst execution rates equal to the clock rate. The present clock rate is 20 MHz and will be increased eventually to the 40 MHz area. At 20 MHz, sustained execution rates of 7 MFLOPS are typical. Performance rates of 10.5 MWhetstones have also been demonstrated (20 MHz clock). The floating point unit is only one part of the RISC processor. By combining all the aspects of software, memory system interfacing and high performance hardware like the 88100 floating point unit, mainframe performance moves one step closer to the desktop computer world.

entry:
@InProceedings{Melear:1988:IFP,
  author =       "C. Melear",
  title =        "An integrated floating point unit for a {RISC}
                 architecture",
  crossref =     "Wescon:1988:WCR",
  pages =        "1.2/1--8",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "RISC architectures require multiple bus structures
                 that allow for instructions, operands, and results to
                 all travel about the processor on each clock cycle.
                 Thus, by putting the floating point unit on these
                 multiple bus structures, it can receive instructions
                 and operands on each clock cycle. Some number of cycles
                 later, as more floating point instructions are issued,
                 floating point results can also be sent out on the
                 destination bus, yielding burst execution rates equal
                 to the clock rate. The present clock rate is 20 MHz and
                 will be increased eventually to the 40 MHz area. At 20
                 MHz, sustained execution rates of 7 MFLOPS are typical.
                 Performance rates of 10.5 MWhetstones have also been
                 demonstrated (20 MHz clock). The floating point unit is
                 only one part of the RISC processor. By combining all
                 the aspects of software, memory system interfacing and
                 high performance hardware like the 88100 floating point
                 unit, mainframe performance moves one step closer to
                 the desktop computer world.",
  acknowledgement = ack-nhfb,
  affiliation =  "Motorola, Austin, TX, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods)",
  keywords =     "20 MHz; 7 MFLOPS; 88100 Floating point unit; Burst
                 execution rates; Clock cycle; Clock rate; Desktop
                 computer; Execution rates; Memory system interfacing;
                 Multiple bus structures; Performance rates; RISC
                 architecture",
  numericalindex = "Frequency 2.0E+07 Hz; Computer speed 7.0E+06 FLOPS",
  thesaurus =    "Digital arithmetic; Microprocessor chips; Reduced
                 instruction set computing",
}


bibtype: article
filename: fparith.bib
label: Milnikel:1988:SRF
author: R. Milnikel and R. Wollenberg
journal: j-ELECTRONIK
volume: 8
pages: 114--1122
year: 1988
CODEN: EKRKAR
ISSN: 0013-5658 OR 00135658
bibdate: Fri Sep 16 16:30:41 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:41 ???
fjournal: Elektronik
acknowledgement: ack-nj
rawauthor: R. Milnikel and R. Wollenberg
title:
Schnelles Radizierverfahren fur Gleitkommazahlen im IEEE-Format toenglish Fast Square-rooting method for Floating-point Numbers in IEEE Format endtoenglish 

rawtitle:
{Schnelles Radizierverfahren f{\"u}r Gleitkommazahlen im IEEE-Format} \toenglish {Fast Square-rooting method for Floating-point Numbers in IEEE Format} \endtoenglish

entry:
@Article{Milnikel:1988:SRF,
  author =       "R. Milnikel and R. Wollenberg",
  title =        "{Schnelles Radizierverfahren f{\"u}r Gleitkommazahlen
                 im IEEE-Format} \toenglish {Fast Square-rooting method
                 for Floating-point Numbers in IEEE Format}
                 \endtoenglish",
  journal =      j-ELECTRONIK,
  volume =       "8",
  pages =        "114--1122",
  year =         "1988",
  CODEN =        "EKRKAR",
  ISSN =         "0013-5658",
  bibdate =      "Fri Sep 16 16:30:41 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Elektronik",
}


bibtype: article
filename: fparith.bib
label: Monahan:1988:CAG
author: John F. Monahan
title: Corrigendum: ``An Algorithm for Generating Chi Random Variables''
journal: j-TOMS
volume: 14
number: 1
pages: 111--111
month: mar
monthnumber: 3
year: 1988
CODEN: ACMSCU
DOI: https://doi.org/10.1145/42288.356228
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
MRclass: 111. 65C10
MRnumber: 89d:65006, 88d:65013
bibdate: Fri Mar 28 10:45:16 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.03.28 10:45:16 ???
note: See cite Monahan:1987:AGC.
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: John F. Monahan
rawnote: See \cite{Monahan:1987:AGC}.
rawtitle: Corrigendum: ``{An} Algorithm for Generating Chi Random Variables''
entry:
@Article{Monahan:1988:CAG,
  author =       "John F. Monahan",
  title =        "Corrigendum: ``{An} Algorithm for Generating Chi
                 Random Variables''",
  journal =      j-TOMS,
  volume =       "14",
  number =       "1",
  pages =        "111--111",
  month =        mar,
  year =         "1988",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/42288.356228",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  MRclass =      "111. 65C10",
  MRnumber =     "89d:65006, 88d:65013",
  bibdate =      "Fri Mar 28 10:45:16 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Monahan:1987:AGC}.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: manual
filename: fparith.bib
label: Motorola:1988:GPF
title: 96-bit general purpose floating-point digital-signal processor technical summary
organization: Motorola, Inc.
address: Phoenix, AZ, USA
pages: 23
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: Motorola semiconductor technical data
keywords: Integrated circuits.; Signal processing --- Digital techniques.
remark: Caption title. ``BR574/D.''
acknowledgement: ack-nhfb
rawtitle: 96-bit general purpose floating-point digital-signal processor technical summary
entry:
@Manual{Motorola:1988:GPF,
  title =        "96-bit general purpose floating-point digital-signal
                 processor technical summary",
  organization = "Motorola, Inc.",
  address =      "Phoenix, AZ, USA",
  pages =        "23",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Motorola semiconductor technical data",
  acknowledgement = ack-nhfb,
  keywords =     "Integrated circuits.; Signal processing --- Digital
                 techniques.",
  remark =       "Caption title. ``BR574/D.''",
}


bibtype: book
filename: fparith.bib
label: Motorola:1988:MFP
author: Motorola, Inc.
title: MC68881 / MC68882 Floating-Point Coprocessor User's Manual
publisher: pub-PH
address: pub-PH:adr
pages: 23
month: feb
monthnumber: 2
year: 1988
ISBN: 0-13-566936-7 OR 0135669367
ISBN13: 978-0-13-566936-5 OR 9780135669365
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
language: eng
acknowledgement: ack-nhfb
rawauthor: {Motorola, Inc.}
rawtitle: {MC68881\slash MC68882} Floating-Point Coprocessor User's Manual
entry:
@Book{Motorola:1988:MFP,
  author =       "{Motorola, Inc.}",
  title =        "{MC68881\slash MC68882} Floating-Point Coprocessor
                 User's Manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  month =        feb,
  year =         "1988",
  ISBN =         "0-13-566936-7",
  ISBN-13 =      "978-0-13-566936-5",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$22.50",
  acknowledgement = ack-nhfb,
  language =     "eng",
}


bibtype: article
filename: fparith.bib
label: Nakamura:1988:SCP
author: S. Nakamura and K.-Y. Chu
title: A single chip parallel multiplier by MOS technology
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 3
pages: 274--282
month: mar
monthnumber: 3
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2164
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 9 08:33:25 MDT 2011
bibtimestamp: 2011.07.09 08:33:25 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2164
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Nakamura and K.-Y. Chu
rawtitle: A single chip parallel multiplier by {MOS} technology
entry:
@Article{Nakamura:1988:SCP,
  author =       "S. Nakamura and K.-Y. Chu",
  title =        "A single chip parallel multiplier by {MOS}
                 technology",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "3",
  pages =        "274--282",
  month =        mar,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2164",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 9 08:33:25 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2164",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Nikolos:1988:EDT
author: D. Nikolos and A. M. Paschalis and G. Philokyprou
title: Efficient design of totally self-checking checkers for all low-cost arithmetic codes
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 7
pages: 807--814
month: jul
monthnumber: 7
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2226
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 9 08:33:27 MDT 2011
bibtimestamp: 2011.07.09 08:33:27 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2226
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Nikolos and A. M. Paschalis and G. Philokyprou
rawtitle: Efficient design of totally self-checking checkers for all low-cost arithmetic codes
entry:
@Article{Nikolos:1988:EDT,
  author =       "D. Nikolos and A. M. Paschalis and G. Philokyprou",
  title =        "Efficient design of totally self-checking checkers for
                 all low-cost arithmetic codes",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "7",
  pages =        "807--814",
  month =        jul,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2226",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 9 08:33:27 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2226",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Normand:1988:PSP
author: J. M. Normand
title: Percola: a special purpose programmable 64-bit floating-point processor
crossref: ACM:1988:ICS
pages: 55--65
year: 1988
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
URL: http://doi.acm.org/10.1145/55364.55370
acknowledgement: ack-nhfb
affiliation: Centre d'Etudes Nucleaires, Saclay, France
rawauthor: J. M. Normand
rawtitle: {Percola}: a special purpose programmable 64-bit floating-point processor
subject:
G. Mathematics of Computing; G.3 PROBABILITY AND STATISTICS; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; J. Computer Applications; J.2 PHYSICAL SCIENCES AND ENGINEERING; G. Mathematics of Computing; G.3 PROBABILITY AND STATISTICS; B. Hardware; B.6 LOGIC DESIGN

entry:
@InProceedings{Normand:1988:PSP,
  author =       "J. M. Normand",
  title =        "{Percola}: a special purpose programmable 64-bit
                 floating-point processor",
  crossref =     "ACM:1988:ICS",
  pages =        "55--65",
  year =         "1988",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$49.00",
  URL =          "http://doi.acm.org/10.1145/55364.55370",
  acknowledgement = ack-nhfb,
  affiliation =  "Centre d'Etudes Nucl{\'e}aires, Saclay, France",
  bibno =        "55370",
  catcode =      "G.3; C.5.1; C.5.3; J.2; G.3; B.6.3",
  CRclass =      "G.3 Random number generation; C.5.1 Large and Medium
                 (``Mainframe'') Computers; C.5.1 Super (very large)
                 computers; C.5.3 Microcomputers; C.5.3 Motorola 68000;
                 J.2 Physics; G.3 Statistical computing; B.6.3 Design
                 Aids; B.6.3 Optimization",
  descriptor =   "Mathematics of Computing, PROBABILITY AND STATISTICS,
                 Random number generation; Computer Systems
                 Organization, COMPUTER SYSTEM IMPLEMENTATION, Large and
                 Medium (``Mainframe'') Computers, Super (very large)
                 computers; Computer Systems Organization, COMPUTER
                 SYSTEM IMPLEMENTATION, Microcomputers, Motorola 68000;
                 Computer Applications, PHYSICAL SCIENCES AND
                 ENGINEERING, Physics; Mathematics of Computing,
                 PROBABILITY AND STATISTICS, Statistical computing;
                 Hardware, LOGIC DESIGN, Design Aids, Optimization",
  genterm =      "ALGORITHMS; DESIGN",
  guideno =      "1988-15563",
  subject =      "G. Mathematics of Computing; G.3 PROBABILITY AND
                 STATISTICS; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; C. Computer Systems
                 Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; J.
                 Computer Applications; J.2 PHYSICAL SCIENCES AND
                 ENGINEERING; G. Mathematics of Computing; G.3
                 PROBABILITY AND STATISTICS; B. Hardware; B.6 LOGIC
                 DESIGN",
  waffil =       "Rennes",
  wauthedit =    "Lenfant, J.",
  wsub =         "Conference Proceedings",
}


bibtype: article
filename: fparith.bib
label: Oklobdzija:1988:IAV
author: Vojin G. Oklobdzija and Earl R. Barnes
title: On implementing addition in VLSI technology
journal: j-J-PAR-DIST-COMP
volume: 5
number: 6
pages: 716--728
month: dec
monthnumber: 12
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Yorktown Heights, NY, USA
corpsource: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical
rawauthor: Vojin G. Oklobdzija and Earl R. Barnes
rawtitle: On implementing addition in {VLSI} technology
keywords:
addition; Arithmetic Algorithms; arithmetic algorithms; carry-lookahead; CMOS integrated circuits; CMOS technology; Computer Aided Design; Computer Programming--Algorithms; digital arithmetic; estimates; integrated; Integrated Circuits, VLSI; logic circuits; logic design; Logic Levels; logic levels; quick; recurrence solver schemes; Semiconductor Devices, MOS; Single-chip VLSI Processor; VLSI; VLSI Implementation; VLSI technology; VLSI-; VLSI-cmos Technology

entry:
@Article{Oklobdzija:1988:IAV,
  author =       "Vojin G. Oklobdzija and Earl R. Barnes",
  title =        "On implementing addition in {VLSI} technology",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "6",
  pages =        "716--728",
  month =        dec,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Yorktown Heights, NY, USA",
  classification = "713; 714; 723; B1265B (Logic circuits); B2570D (CMOS
                 integrated circuits); C5210 (Logic design methods);
                 C5230 (Digital arithmetic methods)",
  corpsource =   "IBM Thomas J. Watson Res. Center, Yorktown Heights,
                 NY, USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "addition; Arithmetic Algorithms; arithmetic
                 algorithms; carry-lookahead; CMOS integrated circuits;
                 CMOS technology; Computer Aided Design; Computer
                 Programming--Algorithms; digital arithmetic; estimates;
                 integrated; Integrated Circuits, VLSI; logic circuits;
                 logic design; Logic Levels; logic levels; quick;
                 recurrence solver schemes; Semiconductor Devices, MOS;
                 Single-chip VLSI Processor; VLSI; VLSI Implementation;
                 VLSI technology; VLSI-; VLSI-cmos Technology",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Papadourakis:1988:VDP
author: G. M. Papadourakis and J. Condorodis
title: A VLSI design of processing element for reconfigurable systolic architectures based on LNS
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2080--2083
year: 1988
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:14:38 MDT
acknowledgement: ack-nhfb
rawauthor: G. M. Papadourakis and J. Condorodis
rawtitle: A {VLSI} design of processing element for reconfigurable systolic architectures based on {LNS}
booktitle:
1988 International Conference on Acoustics, Speech, and Signal Processing: ICASSP-88, 11--14 April 1988

rawbooktitle:
1988 International Conference on Acoustics, Speech, and Signal Processing: {ICASSP-88, 11--14} April 1988

entry:
@InProceedings{Papadourakis:1988:VDP,
  author =       "G. M. Papadourakis and J. Condorodis",
  booktitle =    "1988 International Conference on Acoustics, Speech,
                 and Signal Processing: {ICASSP-88, 11--14} April 1988",
  title =        "A {VLSI} design of processing element for
                 reconfigurable systolic architectures based on {LNS}",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2080--2083",
  year =         "1988",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The design and development of a processing element
                 (PE) in an orthogonal systolic architecture, using the
                 state of the art in VLSI technology, is presented. The
                 goal was to create a high-speed, high-precision PE
                 which would be adaptive to a highly \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Papamichalis:1988:TFP
author: P. Papamichalis and R. Simar, Jr.
title: The TMS320C30 Floating-Point Digital Signal Processor
journal: j-IEEE-MICRO
volume: 8
number: 6
pages: 13--29
month: nov
monthnumber: 11
year: 1988
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.16778
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: P. Papamichalis and R. {Simar, Jr.}
rawtitle: The {TMS320C30} Floating-Point Digital Signal Processor
entry:
@Article{Papamichalis:1988:TFP,
  author =       "P. Papamichalis and R. {Simar, Jr.}",
  title =        "The {TMS320C30} Floating-Point Digital Signal
                 Processor",
  journal =      j-IEEE-MICRO,
  volume =       "8",
  number =       "6",
  pages =        "13--29",
  month =        nov # "\slash " # dec,
  year =         "1988",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.16778",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "The 320C30 is a fast processor with a large memory
                 space and floating-point-arithmetic capabilities. The
                 authors describe the 320C30 architecture in detail,
                 discussing both the internal organization of the device
                 and the external interfaces. They also \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Perlman:1988:AFP
author: R. M. Perlman
title: The Am29027 --- a floating-point accelerator for the Am29000 streamlined instruction processor
crossref: Wescon:1988:WCR
pages: 1.4/1--7
year: 1988
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Adv. Micro Devices, Sunnyale, CA, USA
thesaurus: Digital arithmetic; Microprocessor chips; Pipeline processing; Reduced instruction set computing
rawauthor: R. M. Perlman
rawtitle: The {Am29027} --- a floating-point accelerator for the {Am29000} streamlined instruction processor
abstract:
The Am29000, a 32-bit RISC processor, sets new standards of performance for integer processing. A 25 MHz Am29000 with cache can achieve in excess of 35600 Dhrystones. Even with simple video DRAM memory, the Am29000 has a performance of 24300 Dhrystones. Although the Am29000 contains no hardware dedicated to floating-point computation, it can emulate floating-point operations in software at speeds that were heretofore achieved only by dedicated floating-point coprocessors. For numerically-intensive applications, the Am29000 can be augmented with the Am29027 arithmetic accelerator. The Am29027 is a single-chip floating-point unit that performs single-, double-, and mixed-precision operations, and completely implements IEEE standard 754 for those operations supported. The Am29027 offers two operating modes: a low-latency mode, for scalar operations, and a pipeline mode, for vector and matrix calculations. When configured in pipeline mode, the AM29027 can achieve a peak throughput of 16 MFLOPS.

keywords:
16 MFLOPS; 32 Bit; Am29000 streamlined instruction processor; Am29027 arithmetic accelerator; Cache; Floating-point operations; IEEE standard 754; Low-latency mode; Matrix calculations; Mixed-precision operations; Pipeline mode; RISC processor; Scalar operations; Vector calculations; Video DRAM memory

rawabstract:
The Am29000, a 32-bit RISC processor, sets new standards of performance for integer processing. A 25 MHz Am29000 with cache can achieve in excess of 35600 Dhrystones. Even with simple video DRAM memory, the Am29000 has a performance of 24300 Dhrystones. Although the Am29000 contains no hardware dedicated to floating-point computation, it can emulate floating-point operations in software at speeds that were heretofore achieved only by dedicated floating-point coprocessors. For numerically-intensive applications, the Am29000 can be augmented with the Am29027 arithmetic accelerator. The Am29027 is a single-chip floating-point unit that performs single-, double-, and mixed-precision operations, and completely implements IEEE standard 754 for those operations supported. The Am29027 offers two operating modes: a low-latency mode, for scalar operations, and a pipeline mode, for vector and matrix calculations. When configured in pipeline mode, the AM29027 can achieve a peak throughput of 16 MFLOPS.

entry:
@InProceedings{Perlman:1988:AFP,
  author =       "R. M. Perlman",
  title =        "The {Am29027} --- a floating-point accelerator for the
                 {Am29000} streamlined instruction processor",
  crossref =     "Wescon:1988:WCR",
  pages =        "1.4/1--7",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Am29000, a 32-bit RISC processor, sets new
                 standards of performance for integer processing. A 25
                 MHz Am29000 with cache can achieve in excess of 35600
                 Dhrystones. Even with simple video DRAM memory, the
                 Am29000 has a performance of 24300 Dhrystones. Although
                 the Am29000 contains no hardware dedicated to
                 floating-point computation, it can emulate
                 floating-point operations in software at speeds that
                 were heretofore achieved only by dedicated
                 floating-point coprocessors. For numerically-intensive
                 applications, the Am29000 can be augmented with the
                 Am29027 arithmetic accelerator. The Am29027 is a
                 single-chip floating-point unit that performs single-,
                 double-, and mixed-precision operations, and completely
                 implements IEEE standard 754 for those operations
                 supported. The Am29027 offers two operating modes: a
                 low-latency mode, for scalar operations, and a pipeline
                 mode, for vector and matrix calculations. When
                 configured in pipeline mode, the AM29027 can achieve a
                 peak throughput of 16 MFLOPS.",
  acknowledgement = ack-nhfb,
  affiliation =  "Adv. Micro Devices, Sunnyale, CA, USA",
  classification = "C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods)",
  keywords =     "16 MFLOPS; 32 Bit; Am29000 streamlined instruction
                 processor; Am29027 arithmetic accelerator; Cache;
                 Floating-point operations; IEEE standard 754;
                 Low-latency mode; Matrix calculations; Mixed-precision
                 operations; Pipeline mode; RISC processor; Scalar
                 operations; Vector calculations; Video DRAM memory",
  numericalindex = "Word length 3.2E+01 bit; Computer speed 1.6E+07
                 FLOPS",
  thesaurus =    "Digital arithmetic; Microprocessor chips; Pipeline
                 processing; Reduced instruction set computing",
}


bibtype: article
filename: fparith.bib
label: Pichat:1988:APC
author: M. A. Pichat
journal: j-MATH-COMPUT-SIMUL
volume: 30
number: 6
pages: 541--552
year: 1988
CODEN: MCSIDR
ISSN: 0378-4754 (print), 1872-7166 (electronic) OR 03784754 (print), 18727166 (electronic)
ISSNL: 0378-4754 OR 03784754
MRclass: 65G05
MRnumber: 90d:65090
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
fjournal: Mathematics and Computers in Simulation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03784754
reviewer: Luciano Biasini
rawauthor: M. A. Pichat
title:
All possible computed results in correct floating-point summation. Stochastic methods in round-off error analysis

rawtitle:
All possible computed results in correct floating-point summation. Stochastic methods in round-off error analysis

entry:
@Article{Pichat:1988:APC,
  author =       "M. A. Pichat",
  title =        "All possible computed results in correct
                 floating-point summation. Stochastic methods in
                 round-off error analysis",
  journal =      j-MATH-COMPUT-SIMUL,
  volume =       "30",
  number =       "6",
  pages =        "541--552",
  year =         "1988",
  CODEN =        "MCSIDR",
  ISSN =         "0378-4754 (print), 1872-7166 (electronic)",
  ISSN-L =       "0378-4754",
  MRclass =      "65G05",
  MRnumber =     "90d:65090",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematics and Computers in Simulation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03784754",
  reviewer =     "Luciano Biasini",
}


bibtype: mastersthesis
filename: fparith.bib
label: Pier:1988:IPA
author: Richard Michael Pier
title: An IBM PC / AT-based floating point imaging workstation architecture
type: Thesis (M.S.E.E.)
school: University of Washington
address: Seattle, WA, USA
pages: vi + 35
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Richard Michael Pier
rawtitle: An {IBM PC\slash AT}-based floating point imaging workstation architecture
keywords:
Computer architecture.; IBM Personal Computer AT.; Image processing --- Equipment and supplies.; Microcomputer workstations.

entry:
@MastersThesis{Pier:1988:IPA,
  author =       "Richard Michael Pier",
  title =        "An {IBM PC\slash AT}-based floating point imaging
                 workstation architecture",
  type =         "Thesis ({M.S.E.E.})",
  school =       "University of Washington",
  address =      "Seattle, WA, USA",
  pages =        "vi + 35",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture.; IBM Personal Computer AT.;
                 Image processing --- Equipment and supplies.;
                 Microcomputer workstations.",
}


bibtype: article
filename: fparith.bib
label: Pitas:1988:FPE
author: I. Pitas and M. G. Strintzis
title: Floating point error analysis of two-dimensional, fast Fourier transform algorithms
journal: j-IEEE-TRANS-CIRCUITS-SYST
volume: 35
number: 1
pages: 112--115
month: jan
monthnumber: 1
year: 1988
CODEN: ICSYBT
ISSN: 0098-4094 (print), 1558-1276 (electronic) OR 00984094 (print), 15581276 (electronic)
ISSNL: 0098-4094 OR 00984094
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems
acknowledgement: ack-nhfb
rawauthor: I. Pitas and M. G. Strintzis
rawtitle: Floating point error analysis of two-dimensional, fast {Fourier} transform algorithms
entry:
@Article{Pitas:1988:FPE,
  author =       "I. Pitas and M. G. Strintzis",
  title =        "Floating point error analysis of two-dimensional, fast
                 {Fourier} transform algorithms",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST,
  volume =       "35",
  number =       "1",
  pages =        "112--115",
  month =        jan,
  year =         "1988",
  CODEN =        "ICSYBT",
  ISSN =         "0098-4094 (print), 1558-1276 (electronic)",
  ISSN-L =       "0098-4094",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems",
  summary =      "Floating-point error is conducted for three algorithms
                 commonly used for the calculation of two-dimensional
                 fast Fourier transforms (FFTs), namely, the
                 conventional row-column FFT, the vector-radix FFT, and
                 the polynomial-transform FFT. The respective \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Plauger:1988:PFP
author: P. J. Plauger
title: Properties of floating-point arithmetic
journal: j-COMP-LANG-MAG
volume: 5
number: 3
pages: 17--22
month: mar
monthnumber: 3
year: 1988
CODEN: COMLEF
ISSN: 0749-2839 OR 07492839
bibdate: Thu Sep 1 10:14:15 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:14:15 ???
fjournal: Computer Language Magazine
acknowledgement: ack-nj
rawauthor: P. J. Plauger
rawtitle: Properties of floating-point arithmetic
entry:
@Article{Plauger:1988:PFP,
  author =       "P. J. Plauger",
  title =        "Properties of floating-point arithmetic",
  journal =      j-COMP-LANG-MAG,
  volume =       "5",
  number =       "3",
  pages =        "17--22",
  month =        mar,
  year =         "1988",
  CODEN =        "COMLEF",
  ISSN =         "0749-2839",
  bibdate =      "Thu Sep 1 10:14:15 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Computer Language Magazine",
}


bibtype: inproceedings
filename: fparith.bib
label: Prandolini:1988:VIB
author: R. Prandolini and S. Sridharan
crossref: IREE:1988:AMC
pages: 33--40
year: 1988
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Sch. of Electr. and Electron. Syst. Eng., Queensland Inst. of Technol., Brisbane, Qld., Australia
thesaurus: Digital filters; Digital signal processing chips; VLSI
rawauthor: R. Prandolini and S. Sridharan
title:
VLSI implementation of a block floating point coprocessor for the TMS320 fixed point digital signal processor

abstract:
The design of a co-processor which can be interfaced to the TMS32020 fixed-point digital signal processor is described. The co-processor enables efficient implementation of block floating-point arithmetic for digital filtering using the TMS32020.

keywords:
Block floating point coprocessor; Block floating-point arithmetic; Digital filtering; TMS320 fixed point digital signal processor; VLSI implementation

rawabstract:
The design of a co-processor which can be interfaced to the TMS32020 fixed-point digital signal processor is described. The co-processor enables efficient implementation of block floating-point arithmetic for digital filtering using the TMS32020.

rawtitle:
{VLSI} implementation of a block floating point coprocessor for the {TMS320} fixed point digital signal processor

entry:
@InProceedings{Prandolini:1988:VIB,
  author =       "R. Prandolini and S. Sridharan",
  title =        "{VLSI} implementation of a block floating point
                 coprocessor for the {TMS320} fixed point digital signal
                 processor",
  crossref =     "IREE:1988:AMC",
  pages =        "33--40",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The design of a co-processor which can be interfaced
                 to the TMS32020 fixed-point digital signal processor is
                 described. The co-processor enables efficient
                 implementation of block floating-point arithmetic for
                 digital filtering using the TMS32020.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sch. of Electr. and Electron. Syst. Eng., Queensland
                 Inst. of Technol., Brisbane, Qld., Australia",
  classification = "B1265F (Microprocessors and microcomputers); B1270F
                 (Digital filters); B2570 (Semiconductor integrated
                 circuits); C5130 (Microprocessor chips); C5240 (Digital
                 filters); C5260 (Digital signal processing)",
  keywords =     "Block floating point coprocessor; Block floating-point
                 arithmetic; Digital filtering; TMS320 fixed point
                 digital signal processor; VLSI implementation",
  thesaurus =    "Digital filters; Digital signal processing chips;
                 VLSI",
}


bibtype: article
filename: fparith.bib
label: Prather:1988:CET
author: R. E. Prather
title: Comparison and Extension of Theories of Zipf and Halstead
journal: j-COMP-J
volume: 31
number: 3
pages: 248--252
month: jun
monthnumber: 6
year: 1988
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Tue Mar 25 13:51:56 MST 1997
bibtimestamp: 1997.03.25 13:51:56 MST
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Trinity Univ, San Antonio, TX, USA
affiliationaddress: Trinity Univ, San Antonio, TX, USA
classcodes: C6110B (Software engineering techniques)
corpsource: Comput. and Inf. Sci., Trinity University, San Antonio, TX, USA
journalURL: http://comjnl.oxfordjournals.org/
treatment: T Theoretical or Mathematical
rawauthor: R. E. Prather
rawtitle: Comparison and Extension of Theories of {Zipf} and {Halstead}
bibsource:
Compendex database; http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/248.tif; http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/249.tif; http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/250.tif; http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/251.tif; http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/252.tif

keywords:
behavioural psychology; computer programming; computer software; empirical law; Halstead metrics; Halstead's hypothesis; length estimates; Measurements; probabilistic hypothesis; process; programming; software engineering; software metrication; software science; Zipf metrics; Zipf's law

entry:
@Article{Prather:1988:CET,
  author =       "R. E. Prather",
  title =        "Comparison and Extension of Theories of {Zipf} and
                 {Halstead}",
  journal =      j-COMP-J,
  volume =       "31",
  number =       "3",
  pages =        "248--252",
  month =        jun,
  year =         "1988",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Tue Mar 25 13:51:56 MST 1997",
  bibsource =    "Compendex database;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/248.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/249.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/250.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/251.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_31/Issue_03/tiff/252.tif",
  acknowledgement = ack-nhfb,
  affiliation =  "Trinity Univ, San Antonio, TX, USA",
  affiliationaddress = "Trinity Univ, San Antonio, TX, USA",
  classcodes =   "C6110B (Software engineering techniques)",
  classification = "723",
  corpsource =   "Comput. and Inf. Sci., Trinity University, San
                 Antonio, TX, USA",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "behavioural psychology; computer programming; computer
                 software; empirical law; Halstead metrics; Halstead's
                 hypothesis; length estimates; Measurements;
                 probabilistic hypothesis; process; programming;
                 software engineering; software metrication; software
                 science; Zipf metrics; Zipf's law",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: book
filename: fparith.bib
label: Press:1988:NRC
author: W. H. Press and B. P. Flannery and S. A. Teukolsky and W. T. Vetterling
title: Numerical Recipes in C: The Art of Scientific Computing
publisher: pub-CAMBRIDGE
address: pub-CAMBRIDGE:adr
pages: xxii + 735
year: 1988
ISBN: 0-521-43724-5 OR 0521437245
ISBN13: 978-0-521-43724-0 OR 9780521437240
LCCN: QA76.73.C15 N865 1988
bibdate: Thu Sep 01 10:34:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:34:42 ???
acknowledgement: ack-nj
rawauthor: W. H. Press and B. P. Flannery and S. A. Teukolsky and W. T. Vetterling
rawtitle: Numerical Recipes in {C}: The Art of Scientific Computing
entry:
@Book{Press:1988:NRC,
  author =       "W. H. Press and B. P. Flannery and S. A. Teukolsky and
                 W. T. Vetterling",
  title =        "Numerical Recipes in {C}: The Art of Scientific
                 Computing",
  publisher =    pub-CAMBRIDGE,
  address =      pub-CAMBRIDGE:adr,
  pages =        "xxii + 735",
  year =         "1988",
  ISBN =         "0-521-43724-5",
  ISBN-13 =      "978-0-521-43724-0",
  LCCN =         "QA76.73.C15 N865 1988",
  bibdate =      "Thu Sep 01 10:34:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: mastersthesis
filename: fparith.bib
label: Rajanala:1988:ISP
author: Arunkumar V. Rajanala
type: Thesis (M.S.)
school: Oregon State University
address: Corvallis, OR, USA
pages: 77
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.; Microprocessors.
acknowledgement: ack-nhfb
rawauthor: Arunkumar V. Rajanala
title:
IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology

rawtitle:
{IEEE 754} single precision standard compatible floating point processor implemented using silicon compiler technology

entry:
@MastersThesis{Rajanala:1988:ISP,
  author =       "Arunkumar V. Rajanala",
  title =        "{IEEE 754} single precision standard compatible
                 floating point processor implemented using silicon
                 compiler technology",
  type =         "Thesis ({M.S.})",
  school =       "Oregon State University",
  address =      "Corvallis, OR, USA",
  pages =        "77",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.; Microprocessors.",
}


bibtype: inproceedings
filename: fparith.bib
label: Randal:1988:FPC
author: V. T. Randal and J. L. Schmalzel and A. P. Shepherd
title: Floating-Point Computation Using a Microcontroller
crossref: Harris:1988:PAI
pages: 1243--1244
year: 1988
bibdate: Wed Sep 07 22:02:38 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:02:38 ???
acknowledgement: ack-nj
rawauthor: V. T. Randal and J. L. Schmalzel and A. P. Shepherd
rawtitle: Floating-Point Computation Using a Microcontroller
entry:
@InProceedings{Randal:1988:FPC,
  author =       "V. T. Randal and J. L. Schmalzel and A. P. Shepherd",
  title =        "Floating-Point Computation Using a Microcontroller",
  crossref =     "Harris:1988:PAI",
  pages =        "1243--1244",
  year =         "1988",
  bibdate =      "Wed Sep 07 22:02:38 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Razaz:1988:TPM
author: M. Razaz and J. L. Schonfelder
title: Test Procedures for Measurement of Floating-Point Characteristics of Computing Environments
journal: j-COMP-J
volume: 31
number: 1
pages: 12--16
month: feb
monthnumber: 2
year: 1988
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Tue Mar 25 13:51:56 MST 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.03.25 13:51:56 MST
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Univ of Birmingham, Birmingham, Engl
affiliationaddress: Univ of Birmingham, Birmingham, Engl
classcodes: C5470 (Performance evaluation and testing)
corpsource: Department of Electron. and Electr. Eng., Birmingham University, UK
journalURL: http://comjnl.oxfordjournals.org/
treatment: P Practical
rawauthor: M. Razaz and J. L. Schonfelder
rawtitle: Test Procedures for Measurement of Floating-Point Characteristics of Computing Environments
keywords:
arithmetic; arithmetic processors; CDC; computer testing; computers, digital; computing environments; conversion test; DEC; digital arithmetic; floating-point arithmetic; floating-point characteristics; floating-point testing; IBM; ICL; mantissa; minimum representable number; nominal decimal; normalisation base; number representation; operations; parameters; performance evaluation; precision; precision-dependent; procedures; representation test; test; Testing

entry:
@Article{Razaz:1988:TPM,
  author =       "M. Razaz and J. L. Schonfelder",
  title =        "Test Procedures for Measurement of Floating-Point
                 Characteristics of Computing Environments",
  journal =      j-COMP-J,
  volume =       "31",
  number =       "1",
  pages =        "12--16",
  month =        feb,
  year =         "1988",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Tue Mar 25 13:51:56 MST 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Univ of Birmingham, Birmingham, Engl",
  affiliationaddress = "Univ of Birmingham, Birmingham, Engl",
  classcodes =   "C5470 (Performance evaluation and testing)",
  classification = "723",
  corpsource =   "Department of Electron. and Electr. Eng., Birmingham
                 University, UK",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "arithmetic; arithmetic processors; CDC; computer
                 testing; computers, digital; computing environments;
                 conversion test; DEC; digital arithmetic;
                 floating-point arithmetic; floating-point
                 characteristics; floating-point testing; IBM; ICL;
                 mantissa; minimum representable number; nominal
                 decimal; normalisation base; number representation;
                 operations; parameters; performance evaluation;
                 precision; precision-dependent; procedures;
                 representation test; test; Testing",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Ries:1988:MFP
author: P. S. Ries
title: An 8 MFLOP Floating-Point Coprocessor for a RISC Microprocessor
crossref: Electro:1988:ECR
pages: 48/1/1--8
year: 1988
bibdate: Wed Sep 7 22:32:00 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:00 ???
acknowledgement: ack-nj
rawauthor: P. S. Ries
rawtitle: An 8 {MFLOP} Floating-Point Coprocessor for a {RISC} Microprocessor
entry:
@InProceedings{Ries:1988:MFP,
  author =       "P. S. Ries",
  title =        "An 8 {MFLOP} Floating-Point Coprocessor for a {RISC}
                 Microprocessor",
  crossref =     "Electro:1988:ECR",
  pages =        "48/1/1--8",
  year =         "1988",
  bibdate =      "Wed Sep 7 22:32:00 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Robertazzi:1988:BOF
author: T. G. Robertazzi and S. C. Schwartz
title: Best ``Ordering'' for Floating-Point Addition
journal: j-TOMS
volume: 14
number: 1
pages: 101--110
month: mar
monthnumber: 3
year: 1988
CODEN: ACMSCU
DOI: https://doi.org/10.1145/42288.42343
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
MRclass: 65G99 (65V05)
MRnumber: 89b:65117
bibdate: Sat Nov 19 13:08:22 1994
bibtimestamp: 1994.11.19 13:08:22 ???
URL: http://www.acm.org/pubs/citations/journals/toms/1988-14-1/p101-robertazzi/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: accurate floating-point summation; algorithms; performance
acknowledgement: ack-nhfb
affiliation: State University of New York at Stony Brook, Stony Brook; Princeton University, Princeton, NJ
journalURL: https://dl.acm.org/loi/toms
reviewer: Jesse L. Barlow
rawauthor: T. G. Robertazzi and S. C. Schwartz
rawtitle: Best {``Ordering''} for Floating-Point Addition
bibsource:
ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

subject:
G. Mathematics of Computing; G.1 NUMERICAL ANALYSIS; G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic

entry:
@Article{Robertazzi:1988:BOF,
  author =       "T. G. Robertazzi and S. C. Schwartz",
  title =        "Best {``Ordering''} for Floating-Point Addition",
  journal =      j-TOMS,
  volume =       "14",
  number =       "1",
  pages =        "101--110",
  month =        mar,
  year =         "1988",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/42288.42343",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  MRclass =      "65G99 (65V05)",
  MRnumber =     "89b:65117",
  bibdate =      "Sat Nov 19 13:08:22 1994",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "http://www.acm.org/pubs/citations/journals/toms/1988-14-1/p101-robertazzi/",
  acknowledgement = ack-nhfb,
  affiliation =  "State University of New York at Stony Brook, Stony
                 Brook; Princeton University, Princeton, NJ",
  bibno =        "42343",
  catcode =      "G.1.0",
  content =      "This paper compares a variety of methods for
                 accumulating a floating-point sum. Wilkinson pointed
                 out that if we compute the $\sum^n_{i = 1} x_i$ in
                 strictly increasing order in magnitude of the $x_i$,
                 then we obtain a better bound on the rounding error
                 than if the sum is computed in random order
                 [1].\par

                 The authors discuss five different accumulation
                 strategies. They compare these accumulation strategies
                 for when the $x_i$ are uniformly distributed and for
                 when they are exponentially distributed. First they
                 compare a random order for summing the $x_i$, summing
                 in decreasing order of magnitude, and summing in
                 increasing order of magnitude. Not surprisingly,
                 summing in increasing order of magnitude is the best
                 and summing in decreasing order of magnitude is the
                 worst. In fact, it is not difficult to show this for
                 any class of distributions where the mean and variance
                 exist.\par

                 The interesting results in the paper concern two other
                 accumulation strategies. Both of these are shown to be
                 better than summing in increasing order of magnitude
                 for both the uniform and exponential distribution.
                 Fortunately, one of these strategies is the tree sum
                 (or fan-in sum) that is often used in parallel
                 computation. The paper calls this strategy the
                 ``adjacency'' ordering.",
  CRclass =      "G.1.0 General; G.1.0 Computer arithmetic",
  CRnumber =     "8810-0794",
  descriptor =   "Mathematics of Computing, NUMERICAL ANALYSIS, General,
                 Computer arithmetic",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  genterm =      "ALGORITHMS; PERFORMANCE",
  journal-URL =  "https://dl.acm.org/loi/toms",
  journalabbrev = "ACM Trans. Math. Softw.",
  keywords =     "accurate floating-point summation; algorithms;
                 performance",
  review =       "ACM CR 8810-0794",
  reviewer =     "Jesse L. Barlow",
  subject =      "G. Mathematics of Computing; G.1 NUMERICAL ANALYSIS;
                 G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS,
                 General, Computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Rowen:1988:MRF
author: Chris Rowen and Mark Johnson and Paul Ries
title: The MIPS R3010 Floating-Point Coprocessor
journal: j-IEEE-MICRO
volume: 8
number: 3
pages: 53--62
month: may
monthnumber: 5
year: 1988
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.540
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
affiliationaddress: MIPS Computer Systems, Sunnyvale, CA, USA
corpsource: MIPS Comput. Syst., Sunnyvale, CA, USA
journalURL: http://www.computer.org/csdl/mags/mi/index.html
treatment: P Practical
rawauthor: Chris Rowen and Mark Johnson and Paul Ries
rawtitle: The {MIPS R3010} Floating-Point Coprocessor
bibsource:
Compendex database; garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt; https://www.math.utah.edu/pub/tex/bib/fparith.bib; Science Citation Index database (1980--2000)

keywords:
32-bit R31010 floating-point coprocessor; accelerator chip; computer architecture; computer systems, digital --- Parallel Processing; computers, microcomputer; Design; design techniques; digital arithmetic; floating-point; instruction set computing; integrated circuits, VLSI; microprocessor chips; million instruction per second (MIPS) processor; MIPS R3010 floating-point coprocessor; reduced; reduced-instruction-set-computer; reduced-instruction-set-computer (RISC); VLSI

classcodes:
B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); C5130 (Microprocessor chips); C5220 (Computer architecture); C5230 (Digital arithmetic methods)

entry:
@Article{Rowen:1988:MRF,
  author =       "Chris Rowen and Mark Johnson and Paul Ries",
  title =        "The {MIPS R3010} Floating-Point Coprocessor",
  journal =      j-IEEE-MICRO,
  volume =       "8",
  number =       "3",
  pages =        "53--62",
  month =        may # "\slash " # jun,
  year =         "1988",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.540",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "Compendex database;
                 garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  affiliationaddress = "MIPS Computer Systems, Sunnyvale, CA, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5230 (Digital arithmetic methods)",
  classification = "714; 722; 723",
  corpsource =   "MIPS Comput. Syst., Sunnyvale, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "32-bit R31010 floating-point coprocessor; accelerator
                 chip; computer architecture; computer systems, digital
                 --- Parallel Processing; computers, microcomputer;
                 Design; design techniques; digital arithmetic;
                 floating-point; instruction set computing; integrated
                 circuits, VLSI; microprocessor chips; million
                 instruction per second (MIPS) processor; MIPS R3010
                 floating-point coprocessor; reduced;
                 reduced-instruction-set-computer;
                 reduced-instruction-set-computer (RISC); VLSI",
  summary =      "A description is given of the R3010 floating-point
                 accelerator chip, a coprocessor that is based on
                 advanced reduced-instruction-set-computer (RISC)
                 architecture and VLSI design techniques and provides
                 high-speed floating-point operation. The 75000-
                 \ldots{}",
  treatment =    "P Practical",
  xxauthor =     "C. Rowen and P. Ries and M. Johnson",
}


bibtype: inproceedings
filename: fparith.bib
label: Roylance:1988:EMS
author: G. Roylance
title: Expressing Mathematical Subroutines Constructively
crossref: ACM:1988:PAC
pages: 8--13
year: 1988
bibdate: Thu Sep 01 11:52:13 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 11:52:13 ???
acknowledgement: ack-nj
rawauthor: G. Roylance
rawtitle: Expressing Mathematical Subroutines Constructively
entry:
@InProceedings{Roylance:1988:EMS,
  author =       "G. Roylance",
  title =        "Expressing Mathematical Subroutines Constructively",
  crossref =     "ACM:1988:PAC",
  pages =        "8--13",
  year =         "1988",
  bibdate =      "Thu Sep 01 11:52:13 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Santoro:1988:PIA
author: M. Santoro and M. Horowitz
booktitle: Digest of Technical Papers, IEEE International Solid-State Circuits Conference
title: A pipelined $ 64 times 64 $ b iterative array multiplier
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 35--36
month: feb
monthnumber: 2
year: 1988
bibdate: Mon Dec 24 10:19:42 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.12.24 10:19:42 ???
acknowledgement: ack-nhfb
rawauthor: M. Santoro and M. Horowitz
rawbooktitle: Digest of Technical Papers, {IEEE} International Solid-State Circuits Conference
rawtitle: A pipelined $ 64 \times 64 $ b iterative array multiplier
entry:
@InProceedings{Santoro:1988:PIA,
  author =       "M. Santoro and M. Horowitz",
  booktitle =    "Digest of Technical Papers, {IEEE} International
                 Solid-State Circuits Conference",
  title =        "A pipelined $ 64 \times 64 $ b iterative array
                 multiplier",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "35--36",
  month =        feb,
  year =         "1988",
  bibdate =      "Mon Dec 24 10:19:42 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Schatte:1988:ASC
author: Peter Schatte
title: On the almost sure convergence of floating-point mantissas and Benford's law
journal: j-MATH-NACHR
volume: 135
pages: 79--83
year: 1988
CODEN: MTMNAQ
ISSN: 0025-584X OR 0025584X
MRclass: 60F15 (11K31)
MRnumber: 89g:60114
bibdate: Fri Dec 08 12:49:25 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 12:49:25 ???
fjournal: Mathematische Nachrichten
keywords: Benford's Law; Law of Anomalous Numbers; Zipf's Law
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1522-2616
reviewer: S. A. Book
rawauthor: Peter Schatte
rawtitle: On the almost sure convergence of floating-point mantissas and {Benford}'s law
entry:
@Article{Schatte:1988:ASC,
  author =       "Peter Schatte",
  title =        "On the almost sure convergence of floating-point
                 mantissas and {Benford}'s law",
  journal =      j-MATH-NACHR,
  volume =       "135",
  pages =        "79--83",
  year =         "1988",
  CODEN =        "MTMNAQ",
  ISSN =         "0025-584X",
  MRclass =      "60F15 (11K31)",
  MRnumber =     "89g:60114",
  bibdate =      "Fri Dec 08 12:49:25 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematische Nachrichten",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1522-2616",
  keywords =     "Benford's Law; Law of Anomalous Numbers; Zipf's Law",
  reviewer =     "S. A. Book",
}


bibtype: article
filename: fparith.bib
label: Schatte:1988:MDC
author: P. Schatte
title: On Mantissa Distribution in Computing and Benford's Law
journal: j-J-INFO-PROC-CYBERNETICS-EIK
volume: 24
number: 9
pages: 443--455
year: 1988
CODEN: JICYE5
ISSN: 0863-0593 OR 08630593
bibdate: Thu Sep 1 10:14:16 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:14:16 ???
fjournal: Journal of Information Processing and Cybernetics: EIK
keywords: Benford's Law; Law of Anomalous Numbers; Zipf's Law
acknowledgement: ack-nj
rawauthor: P. Schatte
rawtitle: On Mantissa Distribution in Computing and {Benford}'s Law
entry:
@Article{Schatte:1988:MDC,
  author =       "P. Schatte",
  title =        "On Mantissa Distribution in Computing and {Benford}'s
                 Law",
  journal =      j-J-INFO-PROC-CYBERNETICS-EIK,
  volume =       "24",
  number =       "9",
  pages =        "443--455",
  month =        "????",
  year =         "1988",
  CODEN =        "JICYE5",
  ISSN =         "0863-0593",
  bibdate =      "Thu Sep 1 10:14:16 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Journal of Information Processing and Cybernetics:
                 EIK",
  keywords =     "Benford's Law; Law of Anomalous Numbers; Zipf's Law",
}


bibtype: article
filename: fparith.bib
label: Scherson:1988:MOA
author: Isaac D. Scherson and Smil Ruhman
title: Multi-operand arithmetic in a partitioned associative architecture
journal: j-J-PAR-DIST-COMP
volume: 5
number: 6
pages: 655--668
month: dec
monthnumber: 12
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Princeton, NJ, USA
corpsource: Department of Electr. Eng., Princeton University, NJ, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical
rawauthor: Isaac D. Scherson and Smil Ruhman
rawtitle: Multi-operand arithmetic in a partitioned associative architecture
keywords:
16-bit precision; Analysis; Associative Multiplication; associative multiplication; common filter vector; Computer Architecture; Computer Metatheory; concurrency; Convolution; convolution; Data Storage, Digital--Associative; digital arithmetic; Disjoint Data Sets; disjoint data sets; Filter Vectors; Mathematical Techniques; Multi-operand Arithmetic; multioperand arithmetic; multiplier bits; parallel architectures; parallel processing; Partitioned Associative Architecture; partitioned associative architecture

entry:
@Article{Scherson:1988:MOA,
  author =       "Isaac D. Scherson and Smil Ruhman",
  title =        "Multi-operand arithmetic in a partitioned associative
                 architecture",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "6",
  pages =        "655--668",
  month =        dec,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Princeton, NJ, USA",
  classification = "722; 723; 921; C5220 (Computer architecture); C5230
                 (Digital arithmetic methods)",
  corpsource =   "Department of Electr. Eng., Princeton University, NJ,
                 USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "16-bit precision; Analysis; Associative
                 Multiplication; associative multiplication; common
                 filter vector; Computer Architecture; Computer
                 Metatheory; concurrency; Convolution; convolution; Data
                 Storage, Digital--Associative; digital arithmetic;
                 Disjoint Data Sets; disjoint data sets; Filter Vectors;
                 Mathematical Techniques; Multi-operand Arithmetic;
                 multioperand arithmetic; multiplier bits; parallel
                 architectures; parallel processing; Partitioned
                 Associative Architecture; partitioned associative
                 architecture",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Schwarz:1988:CLI
author: Jerry Schwarz
title: A C++ Library for Infinite Precision Floating Point
crossref: USENIX:1988:UPC
pages: 271--281
year: 1988
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: ftp://ftp.uu.net/library/bibliography; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: AT&T Bell Laboratories, Murray Hill
bookpages: 362
thesaurus: C language; Digital arithmetic; Object-oriented programming; Subroutines
rawauthor: Jerry Schwarz
rawtitle: A {C++} Library for Infinite Precision Floating Point
abstract:
The Real library supports infinite precision floating point computation in C++. Arbitrary precision rational arithmetic and transcendental functions are supported.

keywords:
C++ library; Infinite precision floating point; Rational arithmetic; Real library; Transcendental functions

rawabstract:
The Real library supports infinite precision floating point computation in C++. Arbitrary precision rational arithmetic and transcendental functions are supported.

entry:
@InProceedings{Schwarz:1988:CLI,
  author =       "Jerry Schwarz",
  title =        "A {C++} Library for Infinite Precision Floating
                 Point",
  crossref =     "USENIX:1988:UPC",
  bookpages =    "362",
  pages =        "271--281",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "ftp://ftp.uu.net/library/bibliography;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Real library supports infinite precision floating
                 point computation in C++. Arbitrary precision rational
                 arithmetic and transcendental functions are
                 supported.",
  acknowledgement = ack-nhfb,
  affiliation =  "AT\&T Bell Laboratories, Murray Hill",
  classification = "C5230 (Digital arithmetic methods); C6130 (Data
                 handling techniques)",
  confdate =     "17--21 Oct. 1988",
  conflocation = "Denver, CO, USA",
  keywords =     "C++ library; Infinite precision floating point;
                 Rational arithmetic; Real library; Transcendental
                 functions",
  thesaurus =    "C language; Digital arithmetic; Object-oriented
                 programming; Subroutines",
}


bibtype: article
filename: fparith.bib
label: Scott:1988:CMM
author: Michael Scott
title: CUG247 --- M.I.R.A.C.L. --- a Multi-Precision Arithmetic Library
journal: j-CUJ
volume: 6
type: CUG New Release
number: 5
pages: 76--??
month: may
monthnumber: 5
year: 1988
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: Michael Scott
rawtitle: {CUG247} --- {M.I.R.A.C.L.} --- a Multi-Pre\-ci\-sion Arithmetic Library
entry:
@Article{Scott:1988:CMM,
  author =       "Michael Scott",
  title =        "{CUG247} --- {M.I.R.A.C.L.} --- a Multi-Pre\-ci\-sion
                 Arithmetic Library",
  journal =      j-CUJ,
  volume =       "6",
  type =         "{CUG} New Release",
  number =       "5",
  pages =        "76--??",
  month =        may,
  year =         "1988",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: article
filename: fparith.bib
label: Shepherd:1988:LEC
author: Roger Shepherd and Charles Farnum
title: Letter to the Editor: Compiler support for floating-point computation
journal: j-SPE
volume: 18
number: 12
pages: 1193--1194
month: dec
monthnumber: 12
year: 1988
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.4380181208
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Wed Sep 10 12:36:39 MDT 2014
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib
bibtimestamp: 2014.09.10 12:36:39 MDT
fjournal: Software --- Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 30 Oct 2006
rawauthor: Roger Shepherd and Charles Farnum
rawtitle: Letter to the {Editor}: Compiler support for floating-point computation
entry:
@Article{Shepherd:1988:LEC,
  author =       "Roger Shepherd and Charles Farnum",
  title =        "Letter to the {Editor}: Compiler support for
                 floating-point computation",
  journal =      j-SPE,
  volume =       "18",
  number =       "12",
  pages =        "1193--1194",
  month =        dec,
  year =         "1988",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.4380181208",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Wed Sep 10 12:36:39 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  onlinedate =   "30 Oct 2006",
}


bibtype: article
filename: fparith.bib
label: Simon:1988:SP
author: Barry Simon and Richard M. Wilson
title: Supercalculators on the PC
journal: j-NAMS
volume: 35
number: 7
pages: 978--1001
month: sep
monthnumber: 9
year: 1988
CODEN: AMNOAN
ISSN: 0002-9920 (print), 1088-9477 (electronic) OR 00029920 (print), 10889477 (electronic)
ISSNL: 0002-9920 OR 00029920
bibdate: Wed Jun 12 16:56:18 2024
bibtimestamp: 2024.06.12 16:56:18 ???
fjournal: Notices of the American Mathematical Society
acknowledgement: ack-nhfb
ajournal: Notices Amer. Math. Soc.
journalURL: http://www.ams.org/notices/
rawauthor: Barry Simon and Richard M. Wilson
rawtitle: Supercalculators on the {PC}
bibsource:
https://www.math.utah.edu/pub/bibnet/subjects/acc-stab-num-alg.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Simon:1988:SP,
  author =       "Barry Simon and Richard M. Wilson",
  title =        "Supercalculators on the {PC}",
  journal =      j-NAMS,
  volume =       "35",
  number =       "7",
  pages =        "978--1001",
  month =        sep,
  year =         "1988",
  CODEN =        "AMNOAN",
  ISSN =         "0002-9920 (print), 1088-9477 (electronic)",
  ISSN-L =       "0002-9920",
  bibdate =      "Wed Jun 12 16:56:18 2024",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/subjects/acc-stab-num-alg.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Notices Amer. Math. Soc.",
  fjournal =     "Notices of the American Mathematical Society",
  journal-URL =  "http://www.ams.org/notices/",
  mynote =       "September",
}


bibtype: article
filename: fparith.bib
label: Smith:1988:ASD
author: S. G. Smith and P. B. Denyer
title: Advanced serial-data computation
journal: j-J-PAR-DIST-COMP
volume: 5
number: 3
pages: 228--249
month: jun
monthnumber: 6
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Univ of Edinburgh, Edinburgh, Scotl
corpsource: Department of Electr. Eng., Edinburgh University, UK
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical
rawauthor: S. G. Smith and P. B. Denyer
rawtitle: Advanced serial-data computation
keywords:
arithmetic operations; bit-parallel architectures; Computational Methods; computational modules; computer architecture; computers, digital; digital arithmetic; dynamic range; high-; multiwire; multiwire techniques; performance computer arithmetic; serial data architectures; serial data computation; serial-data architectures; signal processing --- Digital Techniques; symmetric-coded distributed arithmetic; techniques

entry:
@Article{Smith:1988:ASD,
  author =       "S. G. Smith and P. B. Denyer",
  title =        "Advanced serial-data computation",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "3",
  pages =        "228--249",
  month =        jun,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Univ of Edinburgh, Edinburgh, Scotl",
  classification = "716; 718; 721; 722; 723; C5230 (Digital arithmetic
                 methods)",
  corpsource =   "Department of Electr. Eng., Edinburgh University, UK",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "arithmetic operations; bit-parallel architectures;
                 Computational Methods; computational modules; computer
                 architecture; computers, digital; digital arithmetic;
                 dynamic range; high-; multiwire; multiwire techniques;
                 performance computer arithmetic; serial data
                 architectures; serial data computation; serial-data
                 architectures; signal processing --- Digital
                 Techniques; symmetric-coded distributed arithmetic;
                 techniques",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Sohie:1988:DSP
author: G. R. L. Sohie and K. L. Kloker
title: A Digital Signal Processor with IEEE Floating-Point Arithmetic
journal: j-IEEE-MICRO
volume: 8
number: 6
pages: 49--67
month: nov
monthnumber: 11
year: 1988
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.16780
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: G. R. L. Sohie and K. L. Kloker
rawtitle: A Digital Signal Processor with {IEEE} Floating-Point Arithmetic
entry:
@Article{Sohie:1988:DSP,
  author =       "G. R. L. Sohie and K. L. Kloker",
  title =        "A Digital Signal Processor with {IEEE} Floating-Point
                 Arithmetic",
  journal =      j-IEEE-MICRO,
  volume =       "8",
  number =       "6",
  pages =        "49--67",
  month =        nov # "\slash " # dec,
  year =         "1988",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.16780",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "A overview is given of Motorola's DSP96002, a digital
                 signal processor that implements IEEE-standard
                 floating-point arithmetic. It is designed for graphics,
                 image processing, spectral analysis and scientific
                 computing applications. Performance peaks \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Sridharan:1988:BFP
author: S. Sridharan and G. Dickman
title: Block floating-point implementation of digital filters using the DSP56000
journal: j-MICROPROC-MICROSYS
volume: 12
number: 6
pages: 299--308
month: aug
monthnumber: 8
year: 1988
CODEN: MIMID5
ISSN: 0141-9331 (print), 1872-9436 (electronic) OR 01419331 (print), 18729436 (electronic)
ISSNL: 0141-9331 OR 01419331
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Microprocessors and Microsystems
acknowledgement: ack-nhfb
rawauthor: S. Sridharan and G. Dickman
rawtitle: Block floating-point implementation of digital filters using the {DSP56000}
subject:
G. Mathematics of Computing; G.m MISCELLANEOUS; I. Computing Methodologies; I.5 PATTERN RECOGNITION; C. Computer Systems Organization; C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION

affiliation:
Queensland Institute of Technology, Queensland, Australia; Queensland Institute of Technology, Queensland, Australia

entry:
@Article{Sridharan:1988:BFP,
  author =       "S. Sridharan and G. Dickman",
  title =        "Block floating-point implementation of digital filters
                 using the {DSP56000}",
  journal =      j-MICROPROC-MICROSYS,
  volume =       "12",
  number =       "6",
  pages =        "299--308",
  month =        aug,
  year =         "1988",
  CODEN =        "MIMID5",
  ISSN =         "0141-9331 (print), 1872-9436 (electronic)",
  ISSN-L =       "0141-9331",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Queensland Institute of Technology, Queensland,
                 Australia; Queensland Institute of Technology,
                 Queensland, Australia",
  bibno =        "49397",
  catcode =      "G.m; I.5.4; C.3; C.5.3",
  CRclass =      "I.5.4 Applications; I.5.4 Signal processing; C.3
                 Signal processing systems; C.5.3 Microcomputers; C.5.3
                 Microprocessors",
  descriptor =   "Mathematics of Computing, MISCELLANEOUS; Computing
                 Methodologies, PATTERN RECOGNITION, Applications,
                 Signal processing; Computer Systems Organization,
                 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, Signal
                 processing systems; Computer Systems Organization,
                 COMPUTER SYSTEM IMPLEMENTATION, Microcomputers,
                 Microprocessors",
  fjournal =     "Microprocessors and Microsystems",
  genterm =      "ALGORITHMS; DESIGN",
  guideno =      "1988-12500",
  journalabbrev = "Microprocess. Microsyst.",
  subject =      "G. Mathematics of Computing; G.m MISCELLANEOUS; I.
                 Computing Methodologies; I.5 PATTERN RECOGNITION; C.
                 Computer Systems Organization; C.3 SPECIAL-PURPOSE AND
                 APPLICATION-BASED SYSTEMS; C. Computer Systems
                 Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION",
}


bibtype: book
filename: fparith.bib
label: Startz:1988:IPC
author: Richard Startz
publisher: pub-BRADY
address: pub-BRADY:adr
edition: Third
pages: xviii + 296
year: 1988
ISBN: 0-13-246604-X OR 013246604X
ISBN13: 978-0-13-246604-2 OR 9780132466042
LCCN: QA76.8.I2923 S79 1988
bibdate: Wed Sep 14 20:23:49 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 20:23:49 ???
acknowledgement: ack-nj
rawauthor: Richard Startz
title:
8087 / 80287 / 80387 for the IBM PC and Compatibles: Applications and Programming with Intel's Math Coprocessors

rawtitle:
8087\slash 80287\slash 80387 for the {IBM PC} and Compatibles: Applications and Programming with {Intel}'s Math Coprocessors

entry:
@Book{Startz:1988:IPC,
  author =       "Richard Startz",
  title =        "8087\slash 80287\slash 80387 for the {IBM PC} and
                 Compatibles: Applications and Programming with
                 {Intel}'s Math Coprocessors",
  publisher =    pub-BRADY,
  address =      pub-BRADY:adr,
  edition =      "Third",
  pages =        "xviii + 296",
  year =         "1988",
  ISBN =         "0-13-246604-X",
  ISBN-13 =      "978-0-13-246604-2",
  LCCN =         "QA76.8.I2923 S79 1988",
  bibdate =      "Wed Sep 14 20:23:49 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Stasinski:1988:MRE
author: R. Stasinski and E. Lukasik
title: Minimization of rounding errors in WFTA programs
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1423--1426
year: 1988
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
acknowledgement: ack-nhfb
rawauthor: R. Stasinski and E. Lukasik
rawtitle: Minimization of rounding errors in {WFTA} programs
booktitle:
Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on. 11--14 April 1988

rawbooktitle:
Acoustics, Speech, and Signal Processing, 1988. {ICASSP-88., 1988} International Conference on. 11--14 April 1988

entry:
@InProceedings{Stasinski:1988:MRE,
  author =       "R. Stasinski and E. Lukasik",
  booktitle =    "Acoustics, Speech, and Signal Processing, 1988.
                 {ICASSP-88., 1988} International Conference on. 11--14
                 April 1988",
  title =        "Minimization of rounding errors in {WFTA} programs",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1423--1426",
  year =         "1988",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Two ideas linked with high-precision computation of
                 WFTAs (Winograd-Fourier transform algorithm) using
                 fixed-point arithmetic are analyzed. Use of the best,
                 optimized small-N DFT (discrete Fourier transform)
                 modules is considered. The sizes \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Stouraitis:1988:FPL
author: Thanos Stouraitis and Fred J. Taylor
title: Floating-point to logarithmic encoder error analysis
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 7
pages: 858--863
month: jul
monthnumber: 7
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2232
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Ohio State University of University, Columbus; University of Florida, Gainesville
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Thanos Stouraitis and Fred J. Taylor
rawtitle: Floating-point to logarithmic encoder error analysis
bibsource:
ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib

subject:
F. Theory of Computation; F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY; G. Mathematics of Computing; G.m MISCELLANEOUS; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES

entry:
@Article{Stouraitis:1988:FPL,
  author =       "Thanos Stouraitis and Fred J. Taylor",
  title =        "Floating-point to logarithmic encoder error analysis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "7",
  pages =        "858--863",
  month =        jul,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2232",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Ohio State University of University, Columbus;
                 University of Florida, Gainesville",
  ajournal =     "IEEE Trans. Comput.",
  bibno =        "48698",
  catcode =      "F.2.1; G.m; C.1.m",
  CRclass =      "F.2.1 Numerical Algorithms and Problems; F.2.1
                 Number-theoretic computations; C.1.m Miscellaneous",
  descriptor =   "Theory of Computation, ANALYSIS OF ALGORITHMS AND
                 PROBLEM COMPLEXITY, Numerical Algorithms and Problems,
                 Number-theoretic computations; Mathematics of
                 Computing, MISCELLANEOUS; Computer Systems
                 Organization, PROCESSOR ARCHITECTURES, Miscellaneous",
  fjournal =     "IEEE Transactions on Computers",
  genterm =      "DESIGN; THEORY; VERIFICATION",
  guideno =      "1988-08687",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  journalabbrev = "IEEE Trans. Comput.",
  subject =      "F. Theory of Computation; F.2 ANALYSIS OF ALGORITHMS
                 AND PROBLEM COMPLEXITY; G. Mathematics of Computing;
                 G.m MISCELLANEOUS; C. Computer Systems Organization;
                 C.1 PROCESSOR ARCHITECTURES",
  summary =      "The logarithmic number (LNS), which supports
                 high-speed, high-precision arithmetic, is envisioned as
                 a possible arithmetic coprocessor attachment to a
                 floating-point (FLP) processor. An error analysis of an
                 FLP-to-LNS encoder is presented. Analytic \ldots{}",
}


bibtype: manual
filename: fparith.bib
label: Sun:1988:PG
title: Programmer's guides
publisher: Sun Microsystems
address: Mountain View, CA, USA
pages: 858--863
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
note: 12 volumes in 1 case.
keywords: Operating systems (Computers); Sun computers --- Programming.; SunOS (Computer operating system)
acknowledgement: ack-nhfb
rawnote: 12 volumes in 1 case.
rawtitle: Programmer's guides
remark:
Title from container. Contents sheet has title: 4.0 programmer's guides minibox. ``Revision A, of 9 May 1988.''--Contents. ``825-1050-10.''--Contents. C programmer's guide --- Assembly language reference for the Sun-2 and Sun-3 --- Programming utilities and libraries --- Debugging tools --- Network programming --- Writing device drivers --- Floating point programmer's guide --- SunView 1 programmer's guide --- SunView 1 system programmer's guide --- Pixrect reference manual --- SunCGI reference manual --- SunCore reference manual.

entry:
@Manual{Sun:1988:PG,
  title =        "Programmer's guides",
  publisher =    "Sun Microsystems",
  address =      "Mountain View, CA, USA",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "12 volumes in 1 case.",
  acknowledgement = ack-nhfb,
  keywords =     "Operating systems (Computers); Sun computers ---
                 Programming.; SunOS (Computer operating system)",
  remark =       "Title from container. Contents sheet has title: 4.0
                 programmer's guides minibox. ``Revision A, of 9 May
                 1988.''--Contents. ``825-1050-10.''--Contents. C
                 programmer's guide --- Assembly language reference for
                 the Sun-2 and Sun-3 --- Programming utilities and
                 libraries --- Debugging tools --- Network programming
                 --- Writing device drivers --- Floating point
                 programmer's guide --- SunView 1 programmer's guide ---
                 SunView 1 system programmer's guide --- Pixrect
                 reference manual --- SunCGI reference manual ---
                 SunCore reference manual.",
}


bibtype: techreport
filename: fparith.bib
label: Takagi:1988:SHA
author: Naofumi Takagi
title: Studies on Hardware Algorithms for Arithmetic Operations with a Redundant Binary Representation
type: Report
institution: Department of Information Sciences, Faculty of Engineering, Kyoto University
address: Kyoto, Japan
pages: vii + 150
day: 23
month: jan
monthnumber: 1
year: 1988
bibdate: Thu Nov 13 06:14:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 06:14:34 ???
remark: Wrapper around cite Takagi:1987:SHA.
acknowledgement: ack-nhfb
rawauthor: Naofumi Takagi
rawtitle: Studies on Hardware Algorithms for Arithmetic Operations with a Redundant Binary Representation
URL:
http://hdl.handle.net/2433/154053; https://repository.kulib.kyoto-u.ac.jp/server/api/core/bitstreams/b38960be-ee22-458e-9899-ed77db01155e/content;

entry:
@TechReport{Takagi:1988:SHA,
  author =       "Naofumi Takagi",
  title =        "Studies on Hardware Algorithms for Arithmetic
                 Operations with a Redundant Binary Representation",
  type =         "Report",
  institution =  "Department of Information Sciences, Faculty of
                 Engineering, Kyoto University",
  address =      "Kyoto, Japan",
  pages =        "vii + 150",
  day =          "23",
  month =        jan,
  year =         "1988",
  bibdate =      "Thu Nov 13 06:14:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://hdl.handle.net/2433/154053;
                 https://repository.kulib.kyoto-u.ac.jp/server/api/core/bitstreams/b38960be-ee22-458e-9899-ed77db01155e/content;",
  acknowledgement = ack-nhfb,
  remark =       "Wrapper around \cite{Takagi:1987:SHA}.",
}


bibtype: article
filename: fparith.bib
label: Taylor:1988:BLN
author: F. J. Taylor and R. Gill and J. Joseph and J. Radke
title: A 20 Bit Logarithmic Number System Processor
journal: j-IEEE-TRANS-COMPUT
volume: C-37
number: 2
pages: 190--199
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2148
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 19:49:19 2005
bibtimestamp: 2005.06.24 19:49:19 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: F. J. Taylor and R. Gill and J. Joseph and J. Radke
rawtitle: A 20 Bit Logarithmic Number System Processor
abstract:
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1.

rawabstract:
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1.

entry:
@Article{Taylor:1988:BLN,
  author =       "F. J. Taylor and R. Gill and J. Joseph and J. Radke",
  title =        "A 20 Bit Logarithmic Number System Processor",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "C-37",
  number =       "2",
  pages =        "190--199",
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2148",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 19:49:19 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  abstract =     "The architecture and performance of a 20-bit
                 arithmetic processor based on the logarithmic number
                 system (LNS) is described. The processor performed LNS
                 multiplication and division rapidly and with a low
                 hardware complexity. Addition and subtraction in the
                 LNS require the support of a table lookup unit. A
                 scheme is proposed to minimize this complexity using a
                 partitioned memory (ROM) and a PLA (programmable logic
                 array). For performance evaluation, the target
                 technology is integrated Schottky logic. The processor
                 is shown to compare well with, if not to outperform,
                 existing floating point (FLP) processors of equivalent
                 range and precision. The speed-power-product ratio of
                 an equivalent FLP processor, compared with that of the
                 LNS processor, is reported to be 20 to 1 in the case of
                 the square and square-root operation and 1 to 1 in the
                 case of addition and subtraction. For multiplication
                 and division, this ratio is about 5 to 1.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Taylor:1988:HFP
author: Fred J. Taylor
title: Hybrid floating point / logarithmic number system arithmetic processor
pages: 190--199
day: 19
month: jan
monthnumber: 1
year: 1988
bibdate: Tue Jan 08 21:48:35 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.01.08 21:48:35 ???
URL: http://www.freepatentsonline.com/4720809.html
acknowledgement: ack-nhfb
howpublished: United States Patent 4,720,809
rawauthor: Fred J. Taylor
rawtitle: Hybrid floating point\slash logarithmic number system arithmetic processor
abstract:
A hybrid arithmetic processor which combines attributes of conventional floating point (F.P.) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.

rawabstract:
A hybrid arithmetic processor which combines attributes of conventional floating point (F.P.) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.

entry:
@Misc{Taylor:1988:HFP,
  author =       "Fred J. Taylor",
  title =        "Hybrid floating point\slash logarithmic number system
                 arithmetic processor",
  howpublished = "United States Patent 4,720,809",
  day =          "19",
  month =        jan,
  year =         "1988",
  bibdate =      "Tue Jan 08 21:48:35 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.freepatentsonline.com/4720809.html",
  abstract =     "A hybrid arithmetic processor which combines
                 attributes of conventional floating point (F.P.)
                 arithmetic with logarithmic number system (LNS)
                 arithmetic. The arithmetic processor includes an input
                 section (forward code converter) for converting input
                 operands in F.P. format to intermediate operands in LNS
                 format, an LNS arithmetic section for performing an
                 arithmetic operation on the LNS intermediate operands
                 and providing an intermediate output in LNS format, and
                 an output section (inverse code converter) for
                 converting the LNS intermediate output to an output in
                 F.P. format. Significantly, output is provided in
                 normalized floating point format but without the need
                 for a time-consuming exponent alignment operation.
                 Arithmetic operations, including addition and
                 multiplication, are accomplished at a high speed, which
                 speed moreover is constant and independent of the data.
                 An efficient accumulator structure and the structure of
                 an ultra-fast numeric processor are disclosed.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Thistle:1988:PAH
author: M. R. Thistle and B. J. Smith
title: A processor architecture for Horizon
crossref: IEEE:1988:PSN
volume: 1
pages: 35--41
year: 1988
bibdate: Thu Apr 16 07:55:03 MDT 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.16 07:55:03 MDT
acknowledgement: ack-nhfb
corpsource: Supercomput. Res. Center, Lanham, MD, USA
treatment: P Practical
rawauthor: M. R. Thistle and B. J. Smith
rawtitle: A processor architecture for {Horizon}
keywords:
floating-point operations; Horizon; horizontal instruction set; parallel architectures; parallel machines; processor architecture; scalable shared-memory MIMD computer; scalable shared-memory multiple-instruction-stream-multiple-data-stream computer; scalar processors; three-dimensional nearest-neighbor network

entry:
@InProceedings{Thistle:1988:PAH,
  author =       "M. R. Thistle and B. J. Smith",
  title =        "A processor architecture for {Horizon}",
  crossref =     "IEEE:1988:PSN",
  volume =       "1",
  pages =        "35--41",
  year =         "1988",
  bibdate =      "Thu Apr 16 07:55:03 MDT 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5220 (Computer architecture); C5440 (Multiprocessor
                 systems and techniques)",
  corpsource =   "Supercomput. Res. Center, Lanham, MD, USA",
  keywords =     "floating-point operations; Horizon; horizontal
                 instruction set; parallel architectures; parallel
                 machines; processor architecture; scalable
                 shared-memory MIMD computer; scalable shared-memory
                 multiple-instruction-stream-multiple-data-stream
                 computer; scalar processors; three-dimensional
                 nearest-neighbor network",
  sponsororg =   "IEEE; ACM",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Ton-That:1988:NAC
author: Long Ton-That
title: Numerical accuracy control in fixed-point arithmetic
journal: j-MATH-COMPUT-SIMUL
volume: 30
number: 6
pages: 553--561
month: dec
monthnumber: 12
year: 1988
CODEN: MCSIDR
DOI: https://doi.org/10.1016/0378-4754(88)90076-6
ISSN: 0378-4754 (print), 1872-7166 (electronic) OR 03784754 (print), 18727166 (electronic)
ISSNL: 0378-4754 OR 03784754
bibdate: Mon Aug 18 16:03:57 MDT 2025
bibtimestamp: 2025.08.18 16:03:57 MDT
URL: https://www.sciencedirect.com/science/article/pii/0378475488900766
fjournal: Mathematics and Computers in Simulation
acknowledgement: ack-nhfb
ajournal: Math. Comput. Simul.
journalURL: https://www.sciencedirect.com/science/journal/03784754
rawauthor: Long Ton-That
rawtitle: Numerical accuracy control in fixed-point arithmetic
entry:
@Article{Ton-That:1988:NAC,
  author =       "Long Ton-That",
  title =        "Numerical accuracy control in fixed-point arithmetic",
  journal =      j-MATH-COMPUT-SIMUL,
  volume =       "30",
  number =       "6",
  pages =        "553--561",
  month =        dec,
  year =         "1988",
  CODEN =        "MCSIDR",
  DOI =          "https://doi.org/10.1016/0378-4754(88)90076-6",
  ISSN =         "0378-4754 (print), 1872-7166 (electronic)",
  ISSN-L =       "0378-4754",
  bibdate =      "Mon Aug 18 16:03:57 MDT 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomputsimul1980.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/0378475488900766",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput. Simul.",
  fjournal =     "Mathematics and Computers in Simulation",
  journal-URL =  "https://www.sciencedirect.com/science/journal/03784754",
}


bibtype: techreport
filename: fparith.bib
label: Tsao:1988:AST
author: Nai-kuan Tsao
title: On the accuracy of solving triangular systems in parallel
address: Washington, DC, USA
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: NASA technical memorandum; 101384 ICOMP; 88-19
keywords: Algorithms.; Error analysis.; Errors.; Floating point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Nai-kuan Tsao
rawtitle: On the accuracy of solving triangular systems in parallel
institution:
National Aeronautics and Space Administration; For sale by the National Technical Information Service

remark:
Distributed to depository libraries in microfiche. Microfiche. [Washington, D.C.: National Aeronautics and Space Administration, 1989] 1 microfiche.

entry:
@TechReport{Tsao:1988:AST,
  author =       "Nai-kuan Tsao",
  title =        "On the accuracy of solving triangular systems in
                 parallel",
  institution =  "National Aeronautics and Space Administration; For
                 sale by the National Technical Information Service",
  address =      "Washington, DC, USA",
  pages =        "????",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "NASA technical memorandum; 101384 ICOMP; 88-19",
  acknowledgement = ack-nhfb,
  govtdocnumber = "NAS 1.15:101384 0830-D (MF)",
  keywords =     "Algorithms.; Error analysis.; Errors.; Floating point
                 arithmetic.",
  remark =       "Distributed to depository libraries in microfiche.
                 Microfiche. [Washington, D.C.: National Aeronautics and
                 Space Administration, 1989] 1 microfiche.",
}


bibtype: article
filename: fparith.bib
label: Venkaiah:1988:CMS
author: V. Ch Venkaiah and S. K. Sen
title: Computing a matrix symmetrizer exactly using modified multiple modulus residue arithmetic
journal: j-J-COMPUT-APPL-MATH
volume: 21
number: 1
pages: 27--40
month: jan
monthnumber: 1
year: 1988
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 12:20:37 MST 2017
bibtimestamp: 2017.02.25 12:20:37 MST
URL: http://www.sciencedirect.com/science/article/pii/0377042788903858
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: V. Ch Venkaiah and S. K. Sen
rawtitle: Computing a matrix symmetrizer exactly using modified multiple modulus residue arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1980.bib

entry:
@Article{Venkaiah:1988:CMS,
  author =       "V. Ch Venkaiah and S. K. Sen",
  title =        "Computing a matrix symmetrizer exactly using modified
                 multiple modulus residue arithmetic",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "21",
  number =       "1",
  pages =        "27--40",
  month =        jan,
  year =         "1988",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 12:20:37 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1980.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0377042788903858",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1988:FSAa
author: H. Volzke
journal: j-MC
volume: 10
pages: 123--129
year: 1988
ISSN: 0720-4442, 0941-777x, 0943-5409 OR 07204442, 0941777x, 09435409
bibdate: Fri Sep 16 16:30:39 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:39 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 1: Standards und Strukturen toenglish Floating-point Arithmetic and its IEEE Specification. Part 1: Standards and Structures endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 1: Standards und Strukturen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 1: Standards and Structures} \endtoenglish

entry:
@Article{Voelzke:1988:FSAa,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 1: Standards und
                 Strukturen} \toenglish {Floating-point Arithmetic and
                 its IEEE Specification. Part 1: Standards and
                 Structures} \endtoenglish",
  journal =      j-MC,
  volume =       "10",
  pages =        "123--129",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x, 0943-5409",
  bibdate =      "Fri Sep 16 16:30:39 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1988:FSAb
author: H. Volzke
journal: j-MC
volume: 11
pages: 78--95
year: 1988
ISSN: 0720-4442, 0941-777x, 0943-5409 OR 07204442, 0941777x, 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 2: Entwurf eines Fliess kommapakets toenglish Floating-point Arithmetic and its IEEE Specification. Part 2: Design of a Floating-Point Package endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 2: Entwurf eines Flie{\ss}kommapakets} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 2: Design of a Floating-Point Package} \endtoenglish

entry:
@Article{Voelzke:1988:FSAb,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 2: Entwurf eines
                 Flie{\ss}kommapakets} \toenglish {Floating-point
                 Arithmetic and its IEEE Specification. Part 2: Design
                 of a Floating-Point Package} \endtoenglish",
  journal =      j-MC,
  volume =       "11",
  pages =        "78--95",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x, 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1988:FSAc
author: H. Volzke
journal: j-MC
volume: 12
pages: 95--108
year: 1988
ISSN: 0720-4442, 0941-777x, 0943-5409 OR 07204442, 0941777x, 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 3: Die verwendeten Algorithmen toenglish Floating-point Arithmetic and its IEEE Specification. Part 3: The Algorithms Used endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 3: Die verwendeten Algorithmen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 3: The Algorithms Used} \endtoenglish

entry:
@Article{Voelzke:1988:FSAc,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 3: Die verwendeten
                 Algorithmen} \toenglish {Floating-point Arithmetic and
                 its IEEE Specification. Part 3: The Algorithms Used}
                 \endtoenglish",
  journal =      j-MC,
  volume =       "12",
  pages =        "95--108",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x, 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Weyland:1988:LCS
author: Nicholas J. Weyland and Edward A. Puckett
title: Lossless coding for sources of floating-point and fixed-precision numbers
journal: j-IEEE-TRANS-INF-THEORY
volume: 34
number: 4
pages: 882--888
month: jul
monthnumber: 7
year: 1988
CODEN: IETTAW
DOI: https://doi.org/10.1109/18.9791
ISSN: 0018-9448 (print), 1557-9654 (electronic) OR 00189448 (print), 15579654 (electronic)
ISSNL: 0018-9448 OR 00189448
MRclass: 94A29
MRnumber: 89i:94023
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Information Theory
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=18
rawauthor: Nicholas J. Weyland and Edward A. Puckett
rawtitle: Lossless coding for sources of floating-point and fixed-precision numbers
entry:
@Article{Weyland:1988:LCS,
  author =       "Nicholas J. Weyland and Edward A. Puckett",
  title =        "Lossless coding for sources of floating-point and
                 fixed-precision numbers",
  journal =      j-IEEE-TRANS-INF-THEORY,
  volume =       "34",
  number =       "4",
  pages =        "882--888",
  month =        jul,
  year =         "1988",
  CODEN =        "IETTAW",
  DOI =          "https://doi.org/10.1109/18.9791",
  ISSN =         "0018-9448 (print), 1557-9654 (electronic)",
  ISSN-L =       "0018-9448",
  MRclass =      "94A29",
  MRnumber =     "89i:94023",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Information Theory",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=18",
  summary =      "A procedure for constructing binary models for sources
                 of floating-point and fixed-precision numbers is given
                 and used together with the minimum description length
                 principle to find optimal models. These models are used
                 to design noiseless source code \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Wilson:1988:FPS
author: Pete Wilson
title: Floating-Point Survival Kit
journal: j-BYTE
volume: 13
number: 3
pages: 217--217
month: mar
monthnumber: 3
year: 1988
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Oct 31 18:51:38 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.31 18:51:38 ???
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
rawauthor: Pete Wilson
rawtitle: Floating-Point Survival Kit
entry:
@Article{Wilson:1988:FPS,
  author =       "Pete Wilson",
  title =        "Floating-Point Survival Kit",
  journal =      j-BYTE,
  volume =       "13",
  number =       "3",
  pages =        "217--217",
  month =        mar,
  year =         "1988",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Oct 31 18:51:38 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "BYTE Magazine",
}


bibtype: article
filename: fparith.bib
label: Wilson:1988:NDP
author: Fred Wilson
title: A Note on Division of Positive Integers
journal: j-SIGMICRO
volume: 19
number: 1--2
pages: 4--4
month: jun
monthnumber: 6
year: 1988
CODEN: SIGMDJ
DOI: https://doi.org/10.1145/62197.1096672
ISSN: 0163-5751, 1050-916X OR 01635751, 1050916X
ISSNL: 0163-5751 OR 01635751
bibdate: Fri Apr 16 10:27:39 MDT 2021
bibtimestamp: 2021.04.16 10:27:39 MDT
URL: https://dl.acm.org/doi/10.1145/62197.1096672
fjournal: ACM SIGMICRO Newsletter
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/sigmicro
rawauthor: Fred Wilson
rawtitle: A Note on Division of Positive Integers
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigmicro.bib

abstract:
At the risk of flaunting a marginal grasp of the obvious I would like to make a few observations on the division of fixed point numbers.

rawabstract:
At the risk of flaunting a marginal grasp of the obvious I would like to make a few observations on the division of fixed point numbers.

entry:
@Article{Wilson:1988:NDP,
  author =       "Fred Wilson",
  title =        "A Note on Division of Positive Integers",
  journal =      j-SIGMICRO,
  volume =       "19",
  number =       "1--2",
  pages =        "4--4",
  month =        jun,
  year =         "1988",
  CODEN =        "SIGMDJ",
  DOI =          "https://doi.org/10.1145/62197.1096672",
  ISSN =         "0163-5751, 1050-916X",
  ISSN-L =       "0163-5751",
  bibdate =      "Fri Apr 16 10:27:39 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigmicro.bib",
  URL =          "https://dl.acm.org/doi/10.1145/62197.1096672",
  abstract =     "At the risk of flaunting a marginal grasp of the
                 obvious I would like to make a few observations on the
                 division of fixed point numbers.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGMICRO Newsletter",
  journal-URL =  "https://dl.acm.org/loi/sigmicro",
}


bibtype: article
filename: fparith.bib
label: Wilson:1988:NFP
author: R. Wilson
title: Newest floating-point processors blur architectural distinctions
journal: j-COMP-DESIGN
volume: 27
number: 8
pages: 32--43
day: 15
month: apr
monthnumber: 4
year: 1988
CODEN: CMPDAM
ISSN: 0010-4566 OR 00104566
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Computer Design
acknowledgement: ack-nhfb
rawauthor: R. Wilson
rawtitle: Newest floating-point processors blur architectural distinctions
subject:
B. Hardware; B.7 INTEGRATED CIRCUITS; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES

entry:
@Article{Wilson:1988:NFP,
  author =       "R. Wilson",
  title =        "Newest floating-point processors blur architectural
                 distinctions",
  journal =      j-COMP-DESIGN,
  volume =       "27",
  number =       "8",
  pages =        "32--43",
  day =          "15",
  month =        apr,
  year =         "1988",
  CODEN =        "CMPDAM",
  ISSN =         "0010-4566",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  bibno =        "44373",
  catcode =      "B.7.1; C.1.1; C.1.1",
  CRclass =      "B.7.1 Types and Design Styles; B.7.1 Memory
                 technologies; C.1.1 Single Data Stream Architectures;
                 C.1.1 RISC; C.1.1 Single Data Stream Architectures;
                 C.1.1 CISC",
  descriptor =   "Hardware, INTEGRATED CIRCUITS, Types and Design
                 Styles, Memory technologies; Computer Systems
                 Organization, PROCESSOR ARCHITECTURES, Single Data
                 Stream Architectures, RISC; Computer Systems
                 Organization, PROCESSOR ARCHITECTURES, Single Data
                 Stream Architectures, CISC",
  fjournal =     "Computer Design",
  genterm =      "PERFORMANCE; DESIGN",
  guideno =      "1988-05955",
  journalabbrev = "Comput. Des.",
  subject =      "B. Hardware; B.7 INTEGRATED CIRCUITS; C. Computer
                 Systems Organization; C.1 PROCESSOR ARCHITECTURES; C.
                 Computer Systems Organization; C.1 PROCESSOR
                 ARCHITECTURES",
}


bibtype: article
filename: fparith.bib
label: Wollard:1988:TSS
author: K. Wollard
title: Technology '88: Solid state
journal: j-IEEE-SPECTRUM
volume: 25
number: 1
pages: 44--46
month: jan
monthnumber: 1
year: 1988
CODEN: IEESAM
DOI: https://doi.org/10.1109/6.4483
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Mon Jan 20 06:41:24 2020
bibtimestamp: 2020.01.20 06:41:24 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: K. Wollard
rawtitle: Technology '88: Solid state
keywords:
16 Mbit; 4 Mbit; application-specific ICs; Consumer electronics; digital integrated circuits; Electronics industry; EPROM; floating-point digital signal processors; GaAs-Si; Government; high-density packaging; integrated circuit technology; Japan; Manufacturing industries; Microprocessors; Production; Semiconductor device manufacture; solid state; Solid state circuits; Trade agreements; US

entry:
@Article{Wollard:1988:TSS,
  author =       "K. Wollard",
  title =        "Technology '88: Solid state",
  journal =      j-IEEE-SPECTRUM,
  volume =       "25",
  number =       "1",
  pages =        "44--46",
  month =        jan,
  year =         "1988",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/6.4483",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Mon Jan 20 06:41:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum1980.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "16 Mbit; 4 Mbit; application-specific ICs; Consumer
                 electronics; digital integrated circuits; Electronics
                 industry; EPROM; floating-point digital signal
                 processors; GaAs-Si; Government; high-density
                 packaging; integrated circuit technology; Japan;
                 Manufacturing industries; Microprocessors; Production;
                 Semiconductor device manufacture; solid state; Solid
                 state circuits; Trade agreements; US",
}


bibtype: book
filename: fparith.bib
label: Young:1988:SNMa
author: David M. Young and Robert Todd Gregory
title: A Survey of Numerical Mathematics
volume: I
publisher: pub-DOVER
address: pub-DOVER:adr
pages: x + 492 + A22 + B16 + I18
year: 1988
ISBN: 0-486-65691-8 OR 0486656918
ISBN13: 978-0-486-65691-5 OR 9780486656915
LCCN: QA297.Y63 1972
MRclass: 65-02
MRnumber: 92b:65005b
bibdate: Wed Jan 17 10:30:33 1996
bibtimestamp: 1996.01.17 10:30:33 ???
note: Corrected reprint of the 1973 original.
URL: http://www.zentralblatt-math.org/zmath/en/search/?an=0732.65002
ZMnumber: 0732.65002
acknowledgement: ack-nhfb
rawauthor: David M. Young and Robert Todd Gregory
rawnote: Corrected reprint of the 1973 original.
rawtitle: A Survey of Numerical Mathematics
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/y/young-david-m.bib; https://www.math.utah.edu/pub/bibnet/subjects/matrix-analysis-2ed.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

TOC:
1: Numerical Analysis as a Subject Area 1.1 Introduction 1.2 Some pitfalls in computation 1.3 Mathematical and computer aspects of an algorithm 1.4 Numerical instability of algorithms and ill-conditioned problems 1.5 Typical problems of interest to the numerical analyst 1.6 Iterative methods 2: Elementary Operations with Automatic Digital Computers 2.1 Introduction 2.2 Binary arithmetic 2.3 Conversion from base $D$ to base $B$ representation 2.4 Representation of integers on a binary computer 2.5 Floating-point representations 2.6 Computer-representable numbers 2.7 Floating-point arithmetic operations 2.8 Fortran analysis of a floating-point number 2.9 Calculation of elementary functions 3: Surveillance of Number Ranges 3.1 Introduction 3.2 Allowable number ranges 3.3 Basic real arithmetic operations 3.4 The quadratic equation 3.5 Complex arithmetic operations 4: Solution of Equations 4.1 Introduction 4.2 Attainable accuracy 4.3 Graphical methods 4.4 The method of bisection 4.5 The method of false position 4.6 The secant method 4.7 General properties of iterative methods 4.8 Generation of iterative methods 4.9 The Newton method 4.10 Muller's method 4.11 Orders of convergence of iterative methods 4.12 Acceleration of the convergence 4.13 Systems of nonlinear equations 5: Roots of Polynomial Equations 5.1 Introduction 5.2 General properties of polynomials 5.3 The Newton method and related methods 5.4 Muller's method and Cauchy's method 5.5 Location of the roots 5.6 Root acceptance and refinement 5.7 Matrix related methods: the modified Bernoulli method 5.8 Matrix related methods: the IP method 5.9 Polyalgorithms 5.10 Other methods 6: Interpolation and Approximation 6.1 Introduction 6.2 Linear interpolation 6.3 Convergence and accuracy of linear interpolation 6.4 Lagrangian interpolation 6.5 Convergence and accuracy of Lagrangian interpolation 6.6 Interpolation with equal intervals 6.7 Hermite interpolation 6.8 Limitations on polynomial interpolation: smooth interpolation 6.9 Inverse interpolation 6.10 Approximation by polynomials 6.11 Least squares approximation by polynomials 6.12 Rational approximation 6.13 Trigonometric interpolation and approximation 6.14 Interpolation in two variables 7: Numerical Differentiation and Quadrature 7.1 Introduction 7.2 The method of undetermined weights 7.3 Numerical differentiation 7.4 Numerical quadrature --- equal intervals 7.5 The Euler--MacLaurin formula 7.6 Romberg integration 7.7 Error determination 7.8 Numerical quadrature --- unequal intervals 8: Ordinary Differential Equations 8.1 Introduction 8.2 Existence and uniqueness 8.3 Analytic methods 8.4 Integral equation formulation --- the Picard method of successive approximations 8.5 The Euler method 8.6 Methods based on numerical quadrature 8.7 Error estimation for predictor-corrector methods 8.8 A numerical example 8.9 Runge--Kutta methods 8.10 Methods based on numerical differentiation 8.11 Higher-order equations and systems of first-order equations 8.12 The use of high-speed computers Appendix A Appendix B Appendix C Bibliography Index

rawTOC:
1: Numerical Analysis as a Subject Area \\ 1.1 Introduction \\ 1.2 Some pitfalls in computation \\ 1.3 Mathematical and computer aspects of an algorithm \\ 1.4 Numerical instability of algorithms and ill-conditioned problems \\ 1.5 Typical problems of interest to the numerical analyst \\ 1.6 Iterative methods \\ 2: Elementary Operations with Automatic Digital Computers \\ 2.1 Introduction \\ 2.2 Binary arithmetic \\ 2.3 Conversion from base $D$ to base $B$ representation \\ 2.4 Representation of integers on a binary computer \\ 2.5 Floating-point representations \\ 2.6 Computer-representable numbers \\ 2.7 Floating-point arithmetic operations \\ 2.8 Fortran analysis of a floating-point number \\ 2.9 Calculation of elementary functions \\ 3: Surveillance of Number Ranges \\ 3.1 Introduction \\ 3.2 Allowable number ranges \\ 3.3 Basic real arithmetic operations \\ 3.4 The quadratic equation \\ 3.5 Complex arithmetic operations \\ 4: Solution of Equations \\ 4.1 Introduction \\ 4.2 Attainable accuracy \\ 4.3 Graphical methods \\ 4.4 The method of bisection \\ 4.5 The method of false position \\ 4.6 The secant method \\ 4.7 General properties of iterative methods \\ 4.8 Generation of iterative methods \\ 4.9 The Newton method \\ 4.10 Muller's method \\ 4.11 Orders of convergence of iterative methods \\ 4.12 Acceleration of the convergence \\ 4.13 Systems of nonlinear equations \\ 5: Roots of Polynomial Equations \\ 5.1 Introduction \\ 5.2 General properties of polynomials \\ 5.3 The Newton method and related methods \\ 5.4 Muller's method and Cauchy's method \\ 5.5 Location of the roots \\ 5.6 Root acceptance and refinement \\ 5.7 Matrix related methods: the modified Bernoulli method \\ 5.8 Matrix related methods: the IP method \\ 5.9 Polyalgorithms \\ 5.10 Other methods \\ 6: Interpolation and Approximation \\ 6.1 Introduction \\ 6.2 Linear interpolation \\ 6.3 Convergence and accuracy of linear interpolation \\ 6.4 Lagrangian interpolation \\ 6.5 Convergence and accuracy of Lagrangian interpolation \\ 6.6 Interpolation with equal intervals \\ 6.7 Hermite interpolation \\ 6.8 Limitations on polynomial interpolation: smooth interpolation \\ 6.9 Inverse interpolation \\ 6.10 Approximation by polynomials \\ 6.11 Least squares approximation by polynomials \\ 6.12 Rational approximation \\ 6.13 Trigonometric interpolation and approximation \\ 6.14 Interpolation in two variables \\ 7: Numerical Differentiation and Quadrature \\ 7.1 Introduction \\ 7.2 The method of undetermined weights \\ 7.3 Numerical differentiation \\ 7.4 Numerical quadrature --- equal intervals \\ 7.5 The Euler--MacLaurin formula \\ 7.6 Romberg integration \\ 7.7 Error determination \\ 7.8 Numerical quadrature --- unequal intervals \\ 8: Ordinary Differential Equations \\ 8.1 Introduction \\ 8.2 Existence and uniqueness \\ 8.3 Analytic methods \\ 8.4 Integral equation formulation --- the Picard method of successive approximations \\ 8.5 The Euler method \\ 8.6 Methods based on numerical quadrature \\ 8.7 Error estimation for predictor-corrector methods \\ 8.8 A numerical example \\ 8.9 Runge--Kutta methods \\ 8.10 Methods based on numerical differentiation \\ 8.11 Higher-order equations and systems of first-order equations \\ 8.12 The use of high-speed computers \\ Appendix A \\ Appendix B \\ Appendix C \\ Bibliography \\ Index

entry:
@Book{Young:1988:SNMa,
  author =       "David M. Young and Robert Todd Gregory",
  title =        "A Survey of Numerical Mathematics",
  volume =       "I",
  publisher =    pub-DOVER,
  address =      pub-DOVER:adr,
  pages =        "x + 492 + A22 + B16 + I18",
  year =         "1988",
  ISBN =         "0-486-65691-8",
  ISBN-13 =      "978-0-486-65691-5",
  LCCN =         "QA297.Y63 1972",
  MRclass =      "65-02",
  MRnumber =     "92b:65005b",
  bibdate =      "Wed Jan 17 10:30:33 1996",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/y/young-david-m.bib;
                 https://www.math.utah.edu/pub/bibnet/subjects/matrix-analysis-2ed.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Corrected reprint of the 1973 original.",
  URL =          "http://www.zentralblatt-math.org/zmath/en/search/?an=0732.65002",
  ZMnumber =     "0732.65002",
  acknowledgement = ack-nhfb,
  tableofcontents = "1: Numerical Analysis as a Subject Area \\
                 1.1 Introduction \\
                 1.2 Some pitfalls in computation \\
                 1.3 Mathematical and computer aspects of an algorithm
                 \\
                 1.4 Numerical instability of algorithms and
                 ill-conditioned problems \\
                 1.5 Typical problems of interest to the numerical
                 analyst \\
                 1.6 Iterative methods \\
                 2: Elementary Operations with Automatic Digital
                 Computers \\
                 2.1 Introduction \\
                 2.2 Binary arithmetic \\
                 2.3 Conversion from base $D$ to base $B$ representation
                 \\
                 2.4 Representation of integers on a binary computer \\
                 2.5 Floating-point representations \\
                 2.6 Computer-representable numbers \\
                 2.7 Floating-point arithmetic operations \\
                 2.8 Fortran analysis of a floating-point number \\
                 2.9 Calculation of elementary functions \\
                 3: Surveillance of Number Ranges \\
                 3.1 Introduction \\
                 3.2 Allowable number ranges \\
                 3.3 Basic real arithmetic operations \\
                 3.4 The quadratic equation \\
                 3.5 Complex arithmetic operations \\
                 4: Solution of Equations \\
                 4.1 Introduction \\
                 4.2 Attainable accuracy \\
                 4.3 Graphical methods \\
                 4.4 The method of bisection \\
                 4.5 The method of false position \\
                 4.6 The secant method \\
                 4.7 General properties of iterative methods \\
                 4.8 Generation of iterative methods \\
                 4.9 The Newton method \\
                 4.10 Muller's method \\
                 4.11 Orders of convergence of iterative methods \\
                 4.12 Acceleration of the convergence \\
                 4.13 Systems of nonlinear equations \\
                 5: Roots of Polynomial Equations \\
                 5.1 Introduction \\
                 5.2 General properties of polynomials \\
                 5.3 The Newton method and related methods \\
                 5.4 Muller's method and Cauchy's method \\
                 5.5 Location of the roots \\
                 5.6 Root acceptance and refinement \\
                 5.7 Matrix related methods: the modified Bernoulli
                 method \\
                 5.8 Matrix related methods: the IP method \\
                 5.9 Polyalgorithms \\
                 5.10 Other methods \\
                 6: Interpolation and Approximation \\
                 6.1 Introduction \\
                 6.2 Linear interpolation \\
                 6.3 Convergence and accuracy of linear interpolation
                 \\
                 6.4 Lagrangian interpolation \\
                 6.5 Convergence and accuracy of Lagrangian
                 interpolation \\
                 6.6 Interpolation with equal intervals \\
                 6.7 Hermite interpolation \\
                 6.8 Limitations on polynomial interpolation: smooth
                 interpolation \\
                 6.9 Inverse interpolation \\
                 6.10 Approximation by polynomials \\
                 6.11 Least squares approximation by polynomials \\
                 6.12 Rational approximation \\
                 6.13 Trigonometric interpolation and approximation \\
                 6.14 Interpolation in two variables \\
                 7: Numerical Differentiation and Quadrature \\
                 7.1 Introduction \\
                 7.2 The method of undetermined weights \\
                 7.3 Numerical differentiation \\
                 7.4 Numerical quadrature --- equal intervals \\
                 7.5 The Euler--MacLaurin formula \\
                 7.6 Romberg integration \\
                 7.7 Error determination \\
                 7.8 Numerical quadrature --- unequal intervals \\
                 8: Ordinary Differential Equations \\
                 8.1 Introduction \\
                 8.2 Existence and uniqueness \\
                 8.3 Analytic methods \\
                 8.4 Integral equation formulation --- the Picard method
                 of successive approximations \\
                 8.5 The Euler method \\
                 8.6 Methods based on numerical quadrature \\
                 8.7 Error estimation for predictor-corrector methods
                 \\
                 8.8 A numerical example \\
                 8.9 Runge--Kutta methods \\
                 8.10 Methods based on numerical differentiation \\
                 8.11 Higher-order equations and systems of first-order
                 equations \\
                 8.12 The use of high-speed computers \\
                 Appendix A \\
                 Appendix B \\
                 Appendix C \\
                 Bibliography \\
                 Index",
}


bibtype: inproceedings
filename: fparith.bib
label: Yuen:1988:IFP
author: A. K. Yuen
title: Intel's floating-point processors
crossref: Electro:1988:ECR
pages: 48/5/1--7
year: 1988
bibdate: Wed Sep 7 22:32:00 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:00 ???
acknowledgement: ack-nj
rawauthor: A. K. Yuen
rawtitle: {Intel}'s floating-point processors
entry:
@InProceedings{Yuen:1988:IFP,
  author =       "A. K. Yuen",
  title =        "{Intel}'s floating-point processors",
  crossref =     "Electro:1988:ECR",
  pages =        "48/5/1--7",
  year =         "1988",
  bibdate =      "Wed Sep 7 22:32:00 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Zhou:1988:NBS
author: B. B. Zhou
title: A new bit-serial systolic multiplier over $ mathrm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 6
pages: 749--751
month: jun
monthnumber: 6
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2216
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 9 08:33:27 MDT 2011
bibtimestamp: 2011.07.09 08:33:27 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2216
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. B. Zhou
rawtitle: A new bit-serial systolic multiplier over {$ \mathrm {GF}(2^m) $}
entry:
@Article{Zhou:1988:NBS,
  author =       "B. B. Zhou",
  title =        "A new bit-serial systolic multiplier over {$ \mathrm
                 {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "6",
  pages =        "749--751",
  month =        jun,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2216",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 9 08:33:27 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2216",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Zoicas:1988:PBG
author: A. Zoicas and K. Grohe and C. Kellerhoff
crossref: Lacoume:1988:SPI
pages: 1233--1236 vol.3
year: 1988
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
note: 3 vol.
acknowledgement: ack-nhfb
affiliation: NEC Electron. GmbH, Dusseldorf, West Germany
rawauthor: A. Zoicas and K. Grohe and C. Kellerhoff
rawnote: 3 vol.
title:
PC based general-purpose floating-point DSP $ mu $PD77230 board with various analog front end options and application software packages

abstract:
The EBIBM-77230 FFT is a software and hardware DSP engineering environment incorporated in a PC in the form of a plug-in board. It offers no downgrade from the ideal in terms of its processing power, which amounts of 27 MFLOPs, its open architecture, standard cross-software support and interfaces to popular commercial DSP packages. A variety of analog front-end options and supervisor modules (for stand-alone operation) can be hooked onto the board itself thereby opening its application to most DSP areas. A math library, which features interfaces to most high level languages (C, Fortran, Pascal, Basic), brings workstation computational power to the PC. The EBIBM-77230 FFT bridges the gap between fast high precision number crunching and an accessible user-friendly environment. The turn-around time from an idea to its real-time execution is thus minimised and cost-wise it is an economic solution in relation to most DSP working environments.

keywords:
27 MFLOPS; Analog front end; Application software packages; Basic; C; DSP engineering environment; EBIBM-77230 FFT; Fortran; General purpose floating point DSP; High level languages; Interfaces; Math library; Microprocessor D77230 board; Open architecture; Pascal; PC; Personal computer; Plug-in board; Supervisor modules

thesaurus:
Add-on boards; Computerised signal processing; Microcomputer applications; Microprocessor chips; Software packages

rawabstract:
The EBIBM-77230 FFT is a software and hardware DSP engineering environment incorporated in a PC in the form of a plug-in board. It offers no downgrade from the ideal in terms of its processing power, which amounts of 27 MFLOPs, its open architecture, standard cross-software support and interfaces to popular commercial DSP packages. A variety of analog front-end options and supervisor modules (for stand-alone operation) can be hooked onto the board itself thereby opening its application to most DSP areas. A math library, which features interfaces to most high level languages (C, Fortran, Pascal, Basic), brings workstation computational power to the PC. The EBIBM-77230 FFT bridges the gap between fast high precision number crunching and an accessible user-friendly environment. The turn-around time from an idea to its real-time execution is thus minimised and cost-wise it is an economic solution in relation to most DSP working environments.

rawtitle:
{PC} based general-purpose floating-point {DSP $ \mu $PD77230} board with various analog front end options and application software packages

entry:
@InProceedings{Zoicas:1988:PBG,
  author =       "A. Zoicas and K. Grohe and C. Kellerhoff",
  title =        "{PC} based general-purpose floating-point {DSP $ \mu
                 $PD77230} board with various analog front end options
                 and application software packages",
  crossref =     "Lacoume:1988:SPI",
  pages =        "1233--1236 vol.3",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "3 vol.",
  abstract =     "The EBIBM-77230 FFT is a software and hardware DSP
                 engineering environment incorporated in a PC in the
                 form of a plug-in board. It offers no downgrade from
                 the ideal in terms of its processing power, which
                 amounts of 27 MFLOPs, its open architecture, standard
                 cross-software support and interfaces to popular
                 commercial DSP packages. A variety of analog front-end
                 options and supervisor modules (for stand-alone
                 operation) can be hooked onto the board itself thereby
                 opening its application to most DSP areas. A math
                 library, which features interfaces to most high level
                 languages (C, Fortran, Pascal, Basic), brings
                 workstation computational power to the PC. The
                 EBIBM-77230 FFT bridges the gap between fast high
                 precision number crunching and an accessible
                 user-friendly environment. The turn-around time from an
                 idea to its real-time execution is thus minimised and
                 cost-wise it is an economic solution in relation to
                 most DSP working environments.",
  acknowledgement = ack-nhfb,
  affiliation =  "NEC Electron. GmbH, Dusseldorf, West Germany",
  classification = "B1265F (Microprocessors and microcomputers); B6140
                 (Signal processing and detection); C5130
                 (Microprocessor chips); C5150 (Other circuits for
                 digital computers); C7410F (Communications)",
  keywords =     "27 MFLOPS; Analog front end; Application software
                 packages; Basic; C; DSP engineering environment;
                 EBIBM-77230 FFT; Fortran; General purpose floating
                 point DSP; High level languages; Interfaces; Math
                 library; Microprocessor D77230 board; Open
                 architecture; Pascal; PC; Personal computer; Plug-in
                 board; Supervisor modules",
  numericalindex = "Computer speed 2.7E+07 FLOPS",
  thesaurus =    "Add-on boards; Computerised signal processing;
                 Microcomputer applications; Microprocessor chips;
                 Software packages",
}


bibtype: inproceedings
filename: fparith.bib
label: Ahmed:1989:EEF
author: Hassan M. Ahmed
title: Efficient Elementary Function Generation with Multipliers
crossref: Ercegovac:1989:PSC
pages: 52--59
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ahmed.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Hassan M. Ahmed
rawtitle: Efficient Elementary Function Generation with Multipliers
entry:
@InProceedings{Ahmed:1989:EEF,
  author =       "Hassan M. Ahmed",
  title =        "Efficient Elementary Function Generation with
                 Multipliers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "52--59",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ahmed.pdf",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Amit:1989:MRE
author: G. Amit and U. Shaked
title: Minimization of roundoff errors in digital realizations of Kalman filters
journal: j-IEEE-TRANS-ACOUST-SPEECH
volume: 37
number: 12
pages: 1980--1982
month: dec
monthnumber: 12
year: 1989
CODEN: IETABA
ISSN: 0096-3518 OR 00963518
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Acoustics, Speech, and Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29
rawauthor: G. Amit and U. Shaked
rawtitle: Minimization of roundoff errors in digital realizations of {Kalman} filters
entry:
@Article{Amit:1989:MRE,
  author =       "G. Amit and U. Shaked",
  title =        "Minimization of roundoff errors in digital
                 realizations of {Kalman} filters",
  journal =      j-IEEE-TRANS-ACOUST-SPEECH,
  volume =       "37",
  number =       "12",
  pages =        "1980--1982",
  month =        dec,
  year =         "1989",
  CODEN =        "IETABA",
  ISSN =         "0096-3518",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Acoustics, Speech, and Signal
                 Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29",
  summary =      "A comparison between D. Williamson's method (IEEE
                 Trans. Autom. Contr., vol.AC-30, p.930-9, 1985) and the
                 0-1 method for the design of the digital Kalman filter
                 is made. The 0-1 method is shown to be much better than
                 Williamson's method and the \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Anonymous:1989:FAR
author: Anonymous
title: FasMath Accuracy Report
type: Report
institution: Cyrix Corporation
address: Richardson, TX, USA
month: aug
monthnumber: 8
year: 1989
bibdate: Thu Nov 13 05:50:51 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 05:50:51 ???
keywords: Cyrix FasMath 83D87 (floating-point coprocessor chip pin-compatible with) Intel 80387
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {FasMath} Accuracy Report
entry:
@TechReport{Anonymous:1989:FAR,
  author =       "Anonymous",
  title =        "{FasMath} Accuracy Report",
  type =         "Report",
  institution =  "Cyrix Corporation",
  address =      "Richardson, TX, USA",
  pages =        "????",
  month =        aug,
  year =         "1989",
  bibdate =      "Thu Nov 13 05:50:51 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Cyrix FasMath 83D87 (floating-point coprocessor chip
                 pin-compatible with) Intel 80387",
}


bibtype: inproceedings
filename: fparith.bib
label: Arison:1989:SAN
author: D. Arison and A. Genusov and L. Gerzberg
title: System applications of a new 32-bit floating-point DSP processor
crossref: Chen:1989:TSA
pages: 890--897 vol.2
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Zoran Corp., Santa Clara, CA, USA
thesaurus: Computerised signal processing; Digital signal processing chips; Parallel processing
rawauthor: D. Arison and A. Genusov and L. Gerzberg
rawtitle: System applications of a new 32-bit floating-point {DSP} processor
abstract:
The authors present the ZR34325, a novel floating-point vector signal processor in the context of system applications. The ZR34325 represents the first full IEEE floating-point integrated array processor on silicon, supplemented with the pertinent scalar and control flow capabilities. The ZR34325 directly executes embedded DSP (digital signal processing) and array processing primitives on multidimensional arrays. Furthermore, an integrated development environment which includes a system software simulation, vectorized and parametric DSP, arithmetic and matrix library, C-based assembler/linker, and hardware development tools facilities top-down complete application development. The ZR34325 enables very efficient multiprocessor multitasking schemes for tasks where execution time is either data independent or data dependent. The authors show the top-down integrated design methodology via sample signal/image processing application examples such as Kalman filtering, spectral analysis, and constant false alarm rate processing for radar applications as well as two-dimensional image filtering.

keywords:
32 Bit; Arithmetic library; C-based assembler/linker; Digital signal processing; False alarm rate processing; Floating-point DSP processor; Image filtering; Kalman filtering; Matrix library; Multidimensional arrays; Radar; Spectral analysis; Vector signal processor; ZR34325

rawabstract:
The authors present the ZR34325, a novel floating-point vector signal processor in the context of system applications. The ZR34325 represents the first full IEEE floating-point integrated array processor on silicon, supplemented with the pertinent scalar and control flow capabilities. The ZR34325 directly executes embedded DSP (digital signal processing) and array processing primitives on multidimensional arrays. Furthermore, an integrated development environment which includes a system software simulation, vectorized and parametric DSP, arithmetic and matrix library, C-based assembler/linker, and hardware development tools facilities top-down complete application development. The ZR34325 enables very efficient multiprocessor multitasking schemes for tasks where execution time is either data independent or data dependent. The authors show the top-down integrated design methodology via sample signal/image processing application examples such as Kalman filtering, spectral analysis, and constant false alarm rate processing for radar applications as well as two-dimensional image filtering.

entry:
@InProceedings{Arison:1989:SAN,
  author =       "D. Arison and A. Genusov and L. Gerzberg",
  title =        "System applications of a new 32-bit floating-point
                 {DSP} processor",
  crossref =     "Chen:1989:TSA",
  pages =        "890--897 vol.2",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors present the ZR34325, a novel
                 floating-point vector signal processor in the context
                 of system applications. The ZR34325 represents the
                 first full IEEE floating-point integrated array
                 processor on silicon, supplemented with the pertinent
                 scalar and control flow capabilities. The ZR34325
                 directly executes embedded DSP (digital signal
                 processing) and array processing primitives on
                 multidimensional arrays. Furthermore, an integrated
                 development environment which includes a system
                 software simulation, vectorized and parametric DSP,
                 arithmetic and matrix library, C-based
                 assembler/linker, and hardware development tools
                 facilities top-down complete application development.
                 The ZR34325 enables very efficient multiprocessor
                 multitasking schemes for tasks where execution time is
                 either data independent or data dependent. The authors
                 show the top-down integrated design methodology via
                 sample signal/image processing application examples
                 such as Kalman filtering, spectral analysis, and
                 constant false alarm rate processing for radar
                 applications as well as two-dimensional image
                 filtering.",
  acknowledgement = ack-nhfb,
  affiliation =  "Zoran Corp., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5260 (Digital signal
                 processing)",
  keywords =     "32 Bit; Arithmetic library; C-based assembler/linker;
                 Digital signal processing; False alarm rate processing;
                 Floating-point DSP processor; Image filtering; Kalman
                 filtering; Matrix library; Multidimensional arrays;
                 Radar; Spectral analysis; Vector signal processor;
                 ZR34325",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Computerised signal processing; Digital signal
                 processing chips; Parallel processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:1989:RLN
author: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
title: Redundant logarithmic number systems
crossref: Ercegovac:1989:PSC
pages: 144--151
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Arnold.pdf
acknowledgement: ack-nhfb
affiliation: Wyoming University, Laramie, WY, USA
thesaurus: Digital arithmetic; Table lookup
rawauthor: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
rawtitle: Redundant logarithmic number systems
abstract:
A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times. (25 Refs.)

keywords:
Add; ARITH-9; Floating-point; Multiply; Number system; Redundant logarithmic arithmetic; Sign/logarithm number systems; Subtract; Table lookups

rawabstract:
A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times. (25 Refs.)

entry:
@InProceedings{Arnold:1989:RLN,
  author =       "M. G. Arnold and T. A. Bailey and J. R. Cowles and J.
                 J. Cupal",
  title =        "Redundant logarithmic number systems",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "144--151",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Arnold.pdf",
  abstract =     "A new number system that offers advantages over
                 conventional floating-point and sign/logarithm number
                 systems is described. Called redundant logarithmic
                 arithmetic, it relies, like conventional logarithmic
                 arithmetic, on table lookups to make the arithmetic
                 unit simpler than an equivalent floating-point unit.
                 The cost of 32-b subtraction in a redundant logarithmic
                 number system is lower than that of previously
                 published logarithmic subtraction methods. Another
                 advantage of a redundant logarithmic number system is
                 that a single arithmetic unit can use the same hardware
                 to add, subtract, or multiply in similar times. (25
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Wyoming University, Laramie, WY, USA",
  classification = "C5230 (Digital arithmetic methods)",
  keywords =     "Add; ARITH-9; Floating-point; Multiply; Number system;
                 Redundant logarithmic arithmetic; Sign/logarithm number
                 systems; Subtract; Table lookups",
  thesaurus =    "Digital arithmetic; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Ashton:1989:AFP
author: C. Ashton
title: The Am29C327 floating point processor
journal: Electronic Product Design
volume: 10
number: 3
pages: 51--59
month: mar
monthnumber: 3
year: 1989
bibdate: Wed Sep 7 22:32:01 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:01 ???
acknowledgement: ack-nj
rawauthor: C. Ashton
rawtitle: The {Am29C327} floating point processor
entry:
@Article{Ashton:1989:AFP,
  author =       "C. Ashton",
  title =        "The {Am29C327} floating point processor",
  journal =      "Electronic Product Design",
  volume =       "10",
  number =       "3",
  pages =        "51--59",
  month =        mar,
  year =         "1989",
  bibdate =      "Wed Sep 7 22:32:01 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Azmi:1989:TFP
author: A. M. Azmi and F. Lombardi
title: On a tapered floating point system
crossref: Ercegovac:1989:PSC
pages: 2--9
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Azmi.pdf
keywords: ARITH-9; Error analysis; Exponents; Tapered floating point system
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Colorado University, Boulder, CO, USA
thesaurus: Digital arithmetic
rawauthor: A. M. Azmi and F. Lombardi
rawtitle: On a tapered floating point system
abstract:
R. Morris (see IEEE Trans. Comput., vol. TC-20, p. 1578--1579, 1971), suggested adding an extra field to the fixed floating point system, so that exponents can be stored more efficiently. The exponents are stored in the smallest possible space, passing the extra bits to the mantissa. The extra field is used to monitor the current length of the exponent. The gain in precision and/or exponent range outweighs the overhead of the extra field and the processing speed. The authors provide implementation details, error analysis, and some future research ideas. Simulation results are provided for comparison purposes.

rawabstract:
R. Morris (see IEEE Trans. Comput., vol. TC-20, p. 1578--1579, 1971), suggested adding an extra field to the fixed floating point system, so that exponents can be stored more efficiently. The exponents are stored in the smallest possible space, passing the extra bits to the mantissa. The extra field is used to monitor the current length of the exponent. The gain in precision and/or exponent range outweighs the overhead of the extra field and the processing speed. The authors provide implementation details, error analysis, and some future research ideas. Simulation results are provided for comparison purposes.

entry:
@InProceedings{Azmi:1989:TFP,
  author =       "A. M. Azmi and F. Lombardi",
  title =        "On a tapered floating point system",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "2--9",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Azmi.pdf",
  abstract =     "R. Morris (see IEEE Trans. Comput., vol. TC-20, p.
                 1578--1579, 1971), suggested adding an extra field to
                 the fixed floating point system, so that exponents can
                 be stored more efficiently. The exponents are stored in
                 the smallest possible space, passing the extra bits to
                 the mantissa. The extra field is used to monitor the
                 current length of the exponent. The gain in precision
                 and/or exponent range outweighs the overhead of the
                 extra field and the processing speed. The authors
                 provide implementation details, error analysis, and
                 some future research ideas. Simulation results are
                 provided for comparison purposes.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Colorado
                 University, Boulder, CO, USA",
  classification = "C5230 (Digital arithmetic methods)",
  keywords =     "ARITH-9; Error analysis; Exponents; Tapered floating
                 point system",
  thesaurus =    "Digital arithmetic",
}


bibtype: article
filename: fparith.bib
label: Bailey:1989:FPA
author: D. H. Bailey and H. D. Simon and J. T. Barton
title: Floating Point Arithmetic in Future Supercomputers
journal: j-IJSA
volume: 3
number: 3
pages: 86--90
month: Fall
year: 1989
CODEN: IJSAE9
ISSN: 0890-2720 OR 08902720
bibdate: Thu Aug 22 17:56:36 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; UnCover library database
bibtimestamp: 1996.08.22 17:56:36 MDT
fjournal: International Journal of Supercomputer Applications
acknowledgement: ack-nhfb
journalURL: http://hpc.sagepub.com/content/by/year
rawauthor: D. H. Bailey and H. D. Simon and J. T. Barton
rawtitle: Floating Point Arithmetic in Future Supercomputers
entry:
@Article{Bailey:1989:FPA,
  author =       "D. H. Bailey and H. D. Simon and J. T. Barton",
  title =        "Floating Point Arithmetic in Future Supercomputers",
  journal =      j-IJSA,
  volume =       "3",
  number =       "3",
  pages =        "86--90",
  month =        "Fall",
  year =         "1989",
  CODEN =        "IJSAE9",
  ISSN =         "0890-2720",
  bibdate =      "Thu Aug 22 17:56:36 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover library database",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Supercomputer Applications",
  journal-URL =  "http://hpc.sagepub.com/content/by/year",
}


bibtype: article
filename: fparith.bib
label: Baran:1989:MST
author: N. Baran
title: The Mac SE takes off
journal: j-BYTE
volume: 14
number: 2
pages: 113--116
month: feb
monthnumber: 2
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:54:09 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:54:09 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
thesaurus: Apple computers; Microcomputers
rawauthor: N. Baran
rawtitle: The {Mac SE} takes off
keywords:
16 MHz; 2 MBytes; 4 MBytes; 68030 CPU; 68882 Floating-point unit; Apple Macintosh SE/30; Built-in memory management unit; FPU; Logic board; Mac SE/30; MMU; Motorola 68030 processor; SIMM-mounted ROMs; Single in-line memory module RAM chips

entry:
@Article{Baran:1989:MST,
  author =       "N. Baran",
  title =        "The {Mac SE} takes off",
  journal =      j-BYTE,
  volume =       "14",
  number =       "2",
  pages =        "113--116",
  month =        feb,
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:54:09 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5430 (Microcomputers)",
  fjournal =     "BYTE Magazine",
  keywords =     "16 MHz; 2 MBytes; 4 MBytes; 68030 CPU; 68882
                 Floating-point unit; Apple Macintosh SE/30; Built-in
                 memory management unit; FPU; Logic board; Mac SE/30;
                 MMU; Motorola 68030 processor; SIMM-mounted ROMs;
                 Single in-line memory module RAM chips",
  numericalindex = "Frequency 1.6E+07 Hz; Memory size 2.1E+06 Byte;
                 Memory size 4.2E+06 Byte",
  thesaurus =    "Apple computers; Microcomputers",
}


bibtype: article
filename: fparith.bib
label: Bardin:1989:IUI
author: B. Bardin and C. Colket and D. Smith
title: Implementation of unsigned integers in Ada
journal: j-SIGADA-LETTERS
volume: 9
number: 1
pages: 47--70
month: jan
monthnumber: 1
year: 1989
CODEN: AALEE5
ISSN: 1094-3641 (print), 1557-9476 (electronic) OR 10943641 (print), 15579476 (electronic)
ISSNL: 1094-3641 OR 10943641
bibdate: Thu Mar 20 07:41:09 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigada.bib
bibtimestamp: 1997.03.20 07:41:09 MST
fjournal: ACM SIGAda Ada Letters
acknowledgement: ack-nhfb
classcodes: C6140D (High level languages); C6130 (Data handling techniques)
journalURL: http://portal.acm.org/citation.cfm?id=J32
treatment: P Practical
rawauthor: B. Bardin and C. Colket and D. Smith
rawtitle: Implementation of unsigned integers in {Ada}
keywords:
Ada; address arithmetic; digital arithmetic; full range; logical operations; modular arithmetic; numeric literals; symbol manipulation; unsigned integers

entry:
@Article{Bardin:1989:IUI,
  author =       "B. Bardin and C. Colket and D. Smith",
  title =        "Implementation of unsigned integers in {Ada}",
  journal =      j-SIGADA-LETTERS,
  volume =       "9",
  number =       "1",
  pages =        "47--70",
  month =        jan # "\slash " # feb,
  year =         "1989",
  CODEN =        "AALEE5",
  ISSN =         "1094-3641 (print), 1557-9476 (electronic)",
  ISSN-L =       "1094-3641",
  bibdate =      "Thu Mar 20 07:41:09 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigada.bib",
  acknowledgement = ack-nhfb,
  classcodes =   "C6140D (High level languages); C6130 (Data handling
                 techniques)",
  fjournal =     "ACM SIGAda Ada Letters",
  journal-URL =  "http://portal.acm.org/citation.cfm?id=J32",
  keywords =     "Ada; address arithmetic; digital arithmetic; full
                 range; logical operations; modular arithmetic; numeric
                 literals; symbol manipulation; unsigned integers",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Barrett:1989:FMA
author: Geoff Barrett
title: Formal methods applied to a floating-point number system
journal: j-IEEE-TRANS-SOFTW-ENG
volume: 15
number: 5
pages: 611--621
month: may
monthnumber: 5
year: 1989
CODEN: IESEDJ
DOI: https://doi.org/10.1109/32.24710
ISSN: 0098-5589 (print), 1939-3520 (electronic) OR 00985589 (print), 19393520 (electronic)
ISSNL: 0098-5589 OR 00985589
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Software Engineering
acknowledgement: ack-nhfb
affiliation: Oxford University, Oxford, UK
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=32
reviewer: Simon Thompson
rawauthor: Geoff Barrett
rawtitle: Formal methods applied to a floating-point number system
abstract:
A formalization of the IEEE standard for binary floating-point arithmetic (ANSI/IEEE Std. 754-1985) is presented in the set-theoretic specification language Z. The formal specification is refined into four sequential components, which unpack the operands, perform the arithmetic, and pack and round the result. This refinement follows proven rules and so demonstrates a mathematically rigorous method of program development. In the course of the proofs, useful internal representations of floating-point numbers are specified. The procedures presented form the basis for the floating-point unit of the Inmos IMS T800 transputer.

subject:
F. Theory of Computation; F.3 LOGICS AND MEANINGS OF PROGRAMS; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; D. Software; D.2 SOFTWARE ENGINEERING; D. Software; D.2 SOFTWARE ENGINEERING; B. Hardware; B.2 ARITHMETIC AND LOGIC STRUCTURES; B. Hardware; B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

rawabstract:
A formalization of the IEEE standard for binary floating-point arithmetic (ANSI/IEEE Std. 754-1985) is presented in the set-theoretic specification language Z. The formal specification is refined into four sequential components, which unpack the operands, perform the arithmetic, and pack and round the result. This refinement follows proven rules and so demonstrates a mathematically rigorous method of program development. In the course of the proofs, useful internal representations of floating-point numbers are specified. The procedures presented form the basis for the floating-point unit of the Inmos IMS T800 transputer.

entry:
@Article{Barrett:1989:FMA,
  author =       "Geoff Barrett",
  title =        "Formal methods applied to a floating-point number
                 system",
  journal =      j-IEEE-TRANS-SOFTW-ENG,
  volume =       "15",
  number =       "5",
  pages =        "611--621",
  month =        may,
  year =         "1989",
  CODEN =        "IESEDJ",
  DOI =          "https://doi.org/10.1109/32.24710",
  ISSN =         "0098-5589 (print), 1939-3520 (electronic)",
  ISSN-L =       "0098-5589",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A formalization of the IEEE standard for binary
                 floating-point arithmetic (ANSI/IEEE Std. 754-1985) is
                 presented in the set-theoretic specification language
                 Z. The formal specification is refined into four
                 sequential components, which unpack the operands,
                 perform the arithmetic, and pack and round the result.
                 This refinement follows proven rules and so
                 demonstrates a mathematically rigorous method of
                 program development. In the course of the proofs,
                 useful internal representations of floating-point
                 numbers are specified. The procedures presented form
                 the basis for the floating-point unit of the Inmos IMS
                 T800 transputer.",
  acknowledgement = ack-nhfb,
  affiliation =  "Oxford University, Oxford, UK",
  bibno =        "65476",
  catcode =      "F.3.1; C.5.3; D.2.1; D.2.0; B.2.0; B.5.1",
  content =      "It is paradoxical that no programming language can be
                 completely defined unless it has a formally defined
                 syntax, yet at the same time, languages have informal
                 semantic descriptions. This is most evident in
                 arithmetic, in which the closest thing to a formal
                 description lies in the IEEE standard for binary
                 floating point arithmetic adopted by ANSI in 1985. The
                 standard is written in natural language, with the
                 attendant possibility of ambiguity and inconsistency.
                 The author of this paper has given a formal version of
                 the standard in the Z specification language, which can
                 be thought of as a structured version of predicate
                 logic. After giving a cogent argument for the use of
                 formal methods in standardization, the author presents
                 a stage-by-stage development of the formal description
                 of the standard; while doing this, he stresses the
                 modularity of the description, as exemplified by the
                 separation of normal and exceptional conditions.\par

                 As he introduces the concepts of Z, the author gives
                 brief explanations of the notation, but for a beginner
                 in the field, the paper is best read in conjunction
                 with the original standard and a description of
                 Z.\par

                 A very powerful argument for the formal approach lies
                 in the specification's use. The INMOS T800 floating
                 point unit was developed by means of a series of
                 refinements of the formal specification; the",
  CRclass =      "F.3.1 Specifying and Verifying and Reasoning about
                 Programs; F.3.1 Specification techniques; C.5.3
                 Microcomputers; C.5.3 INMOS Transputer; D.2.1
                 Requirements/Specifications; D.2.1 Z; D.2.0 General;
                 D.2.0 Standards; B.2.0 General; B.5.1 Design; B.5.1
                 Arithmetic and logic units",
  CRnumber =     "9004-0316",
  descriptor =   "Theory of Computation, LOGICS AND MEANINGS OF
                 PROGRAMS, Specifying and Verifying and Reasoning about
                 Programs, Specification techniques; Computer Systems
                 Organization, COMPUTER SYSTEM IMPLEMENTATION,
                 Microcomputers, INMOS Transputer; Software, SOFTWARE
                 ENGINEERING, Requirements/Specifications, Z; Software,
                 SOFTWARE ENGINEERING, General, Standards; Hardware,
                 ARITHMETIC AND LOGIC STRUCTURES, General; Hardware,
                 REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Design,
                 Arithmetic and logic units",
  fjournal =     "IEEE Transactions on Software Engineering",
  genterm =      "ALGORITHMS; DOCUMENTATION; LANGUAGES; STANDARDIZATION;
                 THEORY",
  guideno =      "1989-06803",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=32",
  journalabbrev = "IEEE Trans. Softw. Eng.",
  reviewer =     "Simon Thompson",
  subject =      "F. Theory of Computation; F.3 LOGICS AND MEANINGS OF
                 PROGRAMS; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; D. Software; D.2
                 SOFTWARE ENGINEERING; D. Software; D.2 SOFTWARE
                 ENGINEERING; B. Hardware; B.2 ARITHMETIC AND LOGIC
                 STRUCTURES; B. Hardware; B.5 REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION",
}


bibtype: inproceedings
filename: fparith.bib
label: Bedard:1989:WFD
author: N. Bedard and M. Birman and G. Chu and L. Hu and C. M. Lim and J. McLeod and L. Torban and F. Ware
title: The Weitek 64-bit floating-point datapath unit
crossref: Chen:1989:TSA
pages: 898--902 (vol. 2)
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Weitek Corp., Sunnyvale, CA, USA
rawauthor: N. Bedard and M. Birman and G. Chu and L. Hu and C. M. Lim and J. McLeod and L. Torban and F. Ware
rawtitle: The {Weitek} 64-bit floating-point datapath unit
abstract:
The authors describe the WTL 3165 and WTL 3364, jointly referred to as the WTL 3X64, which are each 64-bit floating-point data path units designed for high-speed operation in pipelined environment while making possible full compliance with the IEEE standard for binary floating-point arithmetic. It also provides full interruptibility, even in a pipelined environment. The architecture and performance of the 3X64 are described, and a detailed block diagram is presented.

keywords:
64 Bit; Architecture; Binary floating-point arithmetic; Computerised signal processing; DSP chip; Floating-point data path units; Interruptibility; Pipelined environment; Weitek; WTL 3165; WTL 3364; WTL 3X64

thesaurus:
CMOS integrated circuits; Computerised signal processing; Digital arithmetic; Digital signal processing chips; Parallel architectures; Pipeline processing

rawabstract:
The authors describe the WTL 3165 and WTL 3364, jointly referred to as the WTL 3X64, which are each 64-bit floating-point data path units designed for high-speed operation in pipelined environment while making possible full compliance with the IEEE standard for binary floating-point arithmetic. It also provides full interruptibility, even in a pipelined environment. The architecture and performance of the 3X64 are described, and a detailed block diagram is presented.

entry:
@InProceedings{Bedard:1989:WFD,
  author =       "N. Bedard and M. Birman and G. Chu and L. Hu and C. M.
                 Lim and J. McLeod and L. Torban and F. Ware",
  title =        "The {Weitek} 64-bit floating-point datapath unit",
  crossref =     "Chen:1989:TSA",
  pages =        "898--902 (vol. 2)",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors describe the WTL 3165 and WTL 3364,
                 jointly referred to as the WTL 3X64, which are each
                 64-bit floating-point data path units designed for
                 high-speed operation in pipelined environment while
                 making possible full compliance with the IEEE standard
                 for binary floating-point arithmetic. It also provides
                 full interruptibility, even in a pipelined environment.
                 The architecture and performance of the 3X64 are
                 described, and a detailed block diagram is presented.",
  acknowledgement = ack-nhfb,
  affiliation =  "Weitek Corp., Sunnyvale, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods); C5260 (Digital signal
                 processing)",
  keywords =     "64 Bit; Architecture; Binary floating-point
                 arithmetic; Computerised signal processing; DSP chip;
                 Floating-point data path units; Interruptibility;
                 Pipelined environment; Weitek; WTL 3165; WTL 3364; WTL
                 3X64",
  numericalindex = "Word length 6.4E+01 bit",
  thesaurus =    "CMOS integrated circuits; Computerised signal
                 processing; Digital arithmetic; Digital signal
                 processing chips; Parallel architectures; Pipeline
                 processing",
}


bibtype: book
filename: fparith.bib
label: Beliankov:1989:NPO
author: A. Ia Beliankov
title: Nekotorye primeneniia otsenochnoi (``gruboi'') arifmetiki
publisher: VTS AN SSSR
address: Moskva, Russia
pages: 35
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: Soobshcheniia po vychislitelnoi matematike
keywords: Algebras, Linear.; Computer arithmetic.; Floating-point arithmetic.
remark: At head of title: Akademiia nauk SSSR. Vychislitelnyi tsentr.
acknowledgement: ack-nhfb
rawauthor: A. Ia Beliankov
rawtitle: Nekotorye primeneniia otsenochnoi (``gruboi'') arifmetiki
entry:
@Book{Beliankov:1989:NPO,
  author =       "A. Ia Beliankov",
  title =        "Nekotorye primeneniia otsenochnoi (``gruboi'')
                 arifmetiki",
  publisher =    "VTS AN SSSR",
  address =      "Moskva, Russia",
  pages =        "35",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Soobshcheniia po vychislitelnoi matematike",
  acknowledgement = ack-nhfb,
  keywords =     "Algebras, Linear.; Computer arithmetic.;
                 Floating-point arithmetic.",
  remark =       "At head of title: Akademiia nauk SSSR. Vychislitelnyi
                 tsentr.",
}


bibtype: inproceedings
filename: fparith.bib
label: Benschneider:1989:MUP
title: A 50 MHz Uniformly Pipelined 64b Floating-Point Arithmetic Processor
crossref: Wuorinen:1989:DTP
pages: 50--51, 288
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Digital Equipment Corp., Hudson, MA, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A 50 {MHz} Uniformly Pipelined 64b Floating-Point Arithmetic Processor
author:
B. J. Benschneider and W. J. Bowhill and E. M. Cooper and M. N. Gavrielov and P. E. Gronowski and V. K. Maheshwari and V. Peng and J. D. Pickholtz and S. Samudrala

abstract:
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.

keywords:
1.5 Micron; 50 MHz; 64 Bit; CMOS technology; Divider; Double-precision floating-point operations; Five-segment execution core; Floating-point arithmetic processor; Fully pipelined stages; Integer multiplication; Interface section; Single-precision floating point; Superminicomputer architecture standard

rawabstract:
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.

rawauthor:
B. J. Benschneider and W. J. Bowhill and E. M. Cooper and M. N. Gavrielov and P. E. Gronowski and V. K. Maheshwari and V. Peng and J. D. Pickholtz and S. Samudrala

entry:
@InProceedings{Benschneider:1989:MUP,
  author =       "B. J. Benschneider and W. J. Bowhill and E. M. Cooper
                 and M. N. Gavrielov and P. E. Gronowski and V. K.
                 Maheshwari and V. Peng and J. D. Pickholtz and S.
                 Samudrala",
  title =        "A 50 {MHz} Uniformly Pipelined 64b Floating-Point
                 Arithmetic Processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "50--51, 288",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A description is given of a uniformly pipelined,
                 50-MHz, 64-b floating-point arithmetic processor
                 implemented in a 1.5- mu m (drawn) CMOS technology
                 which performs single- and double-precision
                 floating-point operations and integer multiplication as
                 defined by a superminicomputer architecture standard.
                 The chip is composed of an interface section and a
                 five-segment execution core. The core insists of a
                 divider, bypassed in all instruction except division,
                 and four fully pipelined stages that are uniformly
                 utilized in the execution of all instructions. The
                 performance is summarized. First pass silicon has been
                 functionally verified at 50 MHz with a set of over one
                 million vectors.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Digital Equipment Corp., Hudson, MA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods)",
  confdate =     "15-17 Feb. 1989",
  conflocation = "New York, NY, USA",
  confsponsor =  "IEEE; University of Pennsylvania",
  keywords =     "1.5 Micron; 50 MHz; 64 Bit; CMOS technology; Divider;
                 Double-precision floating-point operations;
                 Five-segment execution core; Floating-point arithmetic
                 processor; Fully pipelined stages; Integer
                 multiplication; Interface section; Single-precision
                 floating point; Superminicomputer architecture
                 standard",
  numericalindex = "Frequency 5.0E+07 Hz; Word length 6.4E+01 bit; Size
                 1.5E-06 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: article
filename: fparith.bib
label: Benschneider:1989:PMC
title: A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1317--1323
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: Digital Equipment Corp., Hudson, MA, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A pipelined {50-MHz} {CMOS} 64-bit floating-point arithmetic processor
author:
Bradley J. Benschneider and William J. Bowhill and Elizabeth M. Cooper and Moshe N. Gavrielov and Paul E. Gronowski and Vijay K. Maheshwari and Victor Peng and Jeffrey D. Pickholtz and Sridhar Samudrala

abstract:
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.

keywords:
20 Ns; 40 Ns; 50 MHz; 64 Bit; Addition; CMOS; Divider; Execution unit; Exponent difference prediction scheme; Floating-point arithmetic processor; Hardware multiplier; Microprocessor; Processor chip; Radix-2 SRT algorithm; Radix-8 modified Booth algorithm; Sticky-bit computation logic; Subtraction; Unified leading-one; Uniformly pipelined

rawabstract:
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.

rawauthor:
Bradley J. Benschneider and William J. Bowhill and Elizabeth M. Cooper and Moshe N. Gavrielov and Paul E. Gronowski and Vijay K. Maheshwari and Victor Peng and Jeffrey D. Pickholtz and Sridhar Samudrala

entry:
@Article{Benschneider:1989:PMC,
  author =       "Bradley J. Benschneider and William J. Bowhill and
                 Elizabeth M. Cooper and Moshe N. Gavrielov and Paul E.
                 Gronowski and Vijay K. Maheshwari and Victor Peng and
                 Jeffrey D. Pickholtz and Sridhar Samudrala",
  title =        "A pipelined {50-MHz} {CMOS} 64-bit floating-point
                 arithmetic processor",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1317--1323",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 135K transistor, uniformly pipelined 50-MHz CMOS
                 64-bit floating-point arithmetic processor chip is
                 described. The execution unit is capable of sustaining
                 pipelined performance of one 32-bit or 64-bit result
                 every 20 ns for all operations except double-precision
                 multiply (40 ns) and divide. The chip employs an
                 exponent difference prediction scheme and a unified
                 leading-one and sticky-bit computation logic for the
                 addition and subtraction operations. A hardware
                 multiplier using a radix-8 modified Booth algorithm and
                 a divider using a radix-2 SRT algorithm are employed.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Digital Equipment Corp., Hudson, MA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "20 Ns; 40 Ns; 50 MHz; 64 Bit; Addition; CMOS; Divider;
                 Execution unit; Exponent difference prediction scheme;
                 Floating-point arithmetic processor; Hardware
                 multiplier; Microprocessor; Processor chip; Radix-2 SRT
                 algorithm; Radix-8 modified Booth algorithm; Sticky-bit
                 computation logic; Subtraction; Unified leading-one;
                 Uniformly pipelined",
  numericalindex = "Word length 6.4E+01 bit; Frequency 5.0E+07 Hz; Time
                 2.0E-08 s; Time 4.0E-08 s",
  summary =      "A 135K transistor, uniformly pipelined 50-MHz CMOS
                 64-bit floating-point arithmetic processor chip is
                 described. The execution unit is capable of sustaining
                 pipelined performance of one 32-bit or 64-bit result
                 every 20 ns for all operations except \ldots{}",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: misc
filename: fparith.bib
label: Bleher:1989:MCA
author: J. Hartmut Bleher and Axel T. Gerlicher and Siegfried M. Rump and Dieter K. Unkauf
title: Method and circuit arrangement for adding floating point numbers
pages: 1317--1323
day: 12
month: sep
monthnumber: 9
year: 1989
bibdate: Mon Dec 29 16:18:28 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.29 16:18:28 ???
URL: http://www.patentstorm.us/patents/4866651/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 4866651
rawauthor: J. Hartmut Bleher and Axel T. Gerlicher and Siegfried M. Rump and Dieter K. Unkauf
rawtitle: Method and circuit arrangement for adding floating point numbers
abstract:
For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.

rawabstract:
For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.

entry:
@Misc{Bleher:1989:MCA,
  author =       "J. Hartmut Bleher and Axel T. Gerlicher and Siegfried
                 M. Rump and Dieter K. Unkauf",
  title =        "Method and circuit arrangement for adding floating
                 point numbers",
  howpublished = "US Patent 4866651",
  day =          "12",
  month =        sep,
  year =         "1989",
  bibdate =      "Mon Dec 29 16:18:28 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/4866651/fulltext.html",
  abstract =     "For successively adding a series of floating point
                 numbers, a floating point adder stage (FIG. 2) is used
                 which, in addition to the sum of two floating point
                 operands, emits the remainder, truncated from the
                 smaller operand, as a floating point number. For
                 obtaining an exact sum of the operands, these
                 remainders are summed in the form of intermediate sums.
                 A circuit arrangement for parallel operation comprises
                 series-connected floating point adder stages (FIG. 6),
                 the intermediate sum occurring at the output of each
                 stage and the intermediate remainder being buffered.
                 Remainders are in each case passed on to the next
                 stage, their value decreasing until they are zero. A
                 serially operating arrangement (FIG. 8) comprises a
                 single adder stage (30) and a register stack (34) for
                 buffering the intermediate sums and the final result. A
                 remainder occurring is stored in a remainder register
                 (32) at the output of the adder stage and added to the
                 intermediate sums until the remainder is zero.
                 Subsequently, a fresh operand is applied to the input
                 of the adder stage.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Boddie:1989:FDC
author: J. R. Boddie and R. N. Gadenz and C. J. Garen and J. M. Huser and B. Ng and S. P. Pekarich
title: A 32-bit floating-point DSP with C compiler
crossref: Chen:1989:TSA
pages: 880--884 vol.2
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: AT&T Bell Lab., Holmdel, NJ, USA
rawauthor: J. R. Boddie and R. N. Gadenz and C. J. Garen and J. M. Huser and B. Ng and S. P. Pekarich
rawtitle: A 32-bit floating-point {DSP} with {C} compiler
abstract:
A novel digital signal processor (the DSP32C) has been developed which performs 32-bit floating point operations at a rate of 25 MFLOPS (million floating-point operations per second) and can be programmed using a standard C compiler. The authors present an overview of the architecture and instruction set with emphasis on the enhancements over its predecessor, the DSP32. The performance is expressed with common signal processor benchmarks. The application development environment is described which highlights the C compiler and hardware development system. Finally, an application example illustrates the power and ease of this DSP.

keywords:
25 MFLOPS; 32 Bit; Architecture; C compiler; Computerised signal processing; DSP32C; Floating point digital signal processor; Instruction set

thesaurus:
CMOS integrated circuits; Computerised signal processing; Digital signal processing chips; Program compilers

rawabstract:
A novel digital signal processor (the DSP32C) has been developed which performs 32-bit floating point operations at a rate of 25 MFLOPS (million floating-point operations per second) and can be programmed using a standard C compiler. The authors present an overview of the architecture and instruction set with emphasis on the enhancements over its predecessor, the DSP32. The performance is expressed with common signal processor benchmarks. The application development environment is described which highlights the C compiler and hardware development system. Finally, an application example illustrates the power and ease of this DSP.

entry:
@InProceedings{Boddie:1989:FDC,
  author =       "J. R. Boddie and R. N. Gadenz and C. J. Garen and J.
                 M. Huser and B. Ng and S. P. Pekarich",
  title =        "A 32-bit floating-point {DSP} with {C} compiler",
  crossref =     "Chen:1989:TSA",
  pages =        "880--884 vol.2",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A novel digital signal processor (the DSP32C) has been
                 developed which performs 32-bit floating point
                 operations at a rate of 25 MFLOPS (million
                 floating-point operations per second) and can be
                 programmed using a standard C compiler. The authors
                 present an overview of the architecture and instruction
                 set with emphasis on the enhancements over its
                 predecessor, the DSP32. The performance is expressed
                 with common signal processor benchmarks. The
                 application development environment is described which
                 highlights the C compiler and hardware development
                 system. Finally, an application example illustrates the
                 power and ease of this DSP.",
  acknowledgement = ack-nhfb,
  affiliation =  "AT\&T Bell Lab., Holmdel, NJ, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5260 (Digital signal processing); C6150C
                 (Compilers, interpreters and other processors)",
  keywords =     "25 MFLOPS; 32 Bit; Architecture; C compiler;
                 Computerised signal processing; DSP32C; Floating point
                 digital signal processor; Instruction set",
  numericalindex = "Word length 3.2E+01 bit; Computer speed 2.5E+07
                 FLOPS",
  thesaurus =    "CMOS integrated circuits; Computerised signal
                 processing; Digital signal processing chips; Program
                 compilers",
}


bibtype: techreport
filename: fparith.bib
label: Bohlender:1989:FST
author: Gerd Bohlender and Gudenberg, J. Wolff von (Jurgen Wolff) and Willard L. Miranker
title: Floating-point systems for theorem proving
type: Research report
number: RC 15101 (\#67356)
institution: IBM T.J. Watson Research Center
address: Yorktown Heights, NY, USA
pages: 14
day: 2
month: nov
monthnumber: 11
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Electronic digital computers --- Programming.; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Gerd Bohlender and Gudenberg, J. Wolff von (Jurgen Wolff) and Willard L. Miranker
rawtitle: Floating-point systems for theorem proving
abstract:
There are a number of existing floating-point systems (programming languages and libraries) which allow the computer user to produce computation with guarantees. These systems may be conveniently used as a component in theorem proving. Following a brief description of the methodology which underlies these systems, we tabulate them, indicating some properties and noting where they may be obtained for use. A brief appendix supplies an introduction to the formalism of the methodology.

rawabstract:
There are a number of existing floating-point systems (programming languages and libraries) which allow the computer user to produce computation with guarantees. These systems may be conveniently used as a component in theorem proving. Following a brief description of the methodology which underlies these systems, we tabulate them, indicating some properties and noting where they may be obtained for use. A brief appendix supplies an introduction to the formalism of the methodology.

entry:
@TechReport{Bohlender:1989:FST,
  author =       "Gerd Bohlender and Gudenberg, J. Wolff von (Jurgen
                 Wolff) and Willard L. Miranker",
  title =        "Floating-point systems for theorem proving",
  type =         "Research report",
  number =       "RC 15101 (\#67356)",
  institution =  "IBM T.J. Watson Research Center",
  address =      "Yorktown Heights, NY, USA",
  pages =        "14",
  day =          "2",
  month =        nov,
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "There are a number of existing floating-point systems
                 (programming languages and libraries) which allow the
                 computer user to produce computation with guarantees.
                 These systems may be conveniently used as a component
                 in theorem proving. Following a brief description of
                 the methodology which underlies these systems, we
                 tabulate them, indicating some properties and noting
                 where they may be obtained for use. A brief appendix
                 supplies an introduction to the formalism of the
                 methodology.",
  acknowledgement = ack-nhfb,
  keywords =     "Electronic digital computers --- Programming.;
                 Floating-point arithmetic.",
}


bibtype: inproceedings
filename: fparith.bib
label: Brackert:1989:DLM
author: R. H. Brackert, Jr. and M. D. Ercegovac and A. N. Willson, Jr.
title: Design of an on-line multiply-add module for recursive digital filters
crossref: Ercegovac:1989:PSC
pages: 34--41
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Brackert.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: R. H. {Brackert, Jr.} and M. D. Ercegovac and A. N. {Willson, Jr.}
rawtitle: Design of an on-line multiply-add module for recursive digital filters
entry:
@InProceedings{Brackert:1989:DLM,
  author =       "R. H. {Brackert, Jr.} and M. D. Ercegovac and A. N.
                 {Willson, Jr.}",
  title =        "Design of an on-line multiply-add module for recursive
                 digital filters",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "34--41",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Brackert.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Brightman:1989:ASF
author: T. Brightman
title: Advancing the Standard in Floating-Point Performance
journal: j-HIGH-PERFORM-SYST
volume: 10
number: 11
pages: 59, 62--64
month: nov
monthnumber: 11
year: 1989
CODEN: HPSYEA
ISSN: 0279-2834 OR 02792834
bibdate: Wed Dec 13 18:25:43 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.13 18:25:43 ???
fjournal: High performance systems
acknowledgement: ack-nhfb
affiliation: Cyrix Corp., Richardson, TX, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Satellite computers; VLSI
rawauthor: T. Brightman
rawtitle: Advancing the Standard in Floating-Point Performance
abstract:
The Cyrix FasMath 83D87 is a floating-point coprocessor chip that combines Intel 80387 socket and software compatibility with the high performance of Weitek's industry-leading coprocessor. The chip is a VLSI CMOS integrated circuit built initially using 1.2-micron double-layer-metal, single-layer-polysilicon process technology. It was designed to minimize complications in the design of high-performance desktop and laptop computer systems.

keywords:
Cyrix FasMath 83D87; Desktop computer systems; Double-layer-metal; Floating-point coprocessor chip; Intel 80387; Laptop computer systems; Math coprocessor; Si; Single-layer-polysilicon process technology; Socket compatibility; Software compatibility; VLSI CMOS integrated circuit

rawabstract:
The Cyrix FasMath 83D87 is a floating-point coprocessor chip that combines Intel 80387 socket and software compatibility with the high performance of Weitek's industry-leading coprocessor. The chip is a VLSI CMOS integrated circuit built initially using 1.2-micron double-layer-metal, single-layer-polysilicon process technology. It was designed to minimize complications in the design of high-performance desktop and laptop computer systems.

entry:
@Article{Brightman:1989:ASF,
  author =       "T. Brightman",
  title =        "Advancing the Standard in Floating-Point Performance",
  journal =      j-HIGH-PERFORM-SYST,
  volume =       "10",
  number =       "11",
  pages =        "59, 62--64",
  month =        nov,
  year =         "1989",
  CODEN =        "HPSYEA",
  ISSN =         "0279-2834",
  bibdate =      "Wed Dec 13 18:25:43 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Cyrix FasMath 83D87 is a floating-point
                 coprocessor chip that combines Intel 80387 socket and
                 software compatibility with the high performance of
                 Weitek's industry-leading coprocessor. The chip is a
                 VLSI CMOS integrated circuit built initially using
                 1.2-micron double-layer-metal, single-layer-polysilicon
                 process technology. It was designed to minimize
                 complications in the design of high-performance desktop
                 and laptop computer systems.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Cyrix Corp., Richardson, TX, USA",
  chemicalindex = "Si/int Si/el",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips)",
  fjournal =     "High performance systems",
  keywords =     "Cyrix FasMath 83D87; Desktop computer systems;
                 Double-layer-metal; Floating-point coprocessor chip;
                 Intel 80387; Laptop computer systems; Math coprocessor;
                 Si; Single-layer-polysilicon process technology; Socket
                 compatibility; Software compatibility; VLSI CMOS
                 integrated circuit",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Satellite computers; VLSI",
}


bibtype: article
filename: fparith.bib
label: Buell:1989:MIA
author: D. Buell and R. Ward
title: A Multiprecise Integer Arithmetic Package
journal: j-J-SUPERCOMPUTING
volume: 3
pages: 89--107
year: 1989
CODEN: JOSUED
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Sun Sep 11 21:56:51 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.11 21:56:51 ???
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: D. Buell and R. Ward
rawtitle: A Multiprecise Integer Arithmetic Package
entry:
@Article{Buell:1989:MIA,
  author =       "D. Buell and R. Ward",
  title =        "A Multiprecise Integer Arithmetic Package",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "3",
  number =       "??",
  pages =        "89--107",
  month =        "????",
  year =         "1989",
  CODEN =        "JOSUED",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Sun Sep 11 21:56:51 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: inproceedings
filename: fparith.bib
label: Carter:1989:CHH
author: T. M. Carter
title: Cascade: hardware for high / variable precision arithmetic
crossref: Ercegovac:1989:PSC
pages: 184--191
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Carter.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: T. M. Carter
rawtitle: {Cascade}: hardware for high\slash variable precision arithmetic
entry:
@InProceedings{Carter:1989:CHH,
  author =       "T. M. Carter",
  title =        "{Cascade}: hardware for high\slash variable precision
                 arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "184--191",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Carter.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Chan:1989:ADC
author: P. K. Chan and M. D. F. Schlag
title: Analysis and design of CMOS Manchester adders with variable carry-skip
crossref: Ercegovac:1989:PSC
pages: 86--95
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Chan.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: P. K. Chan and M. D. F. Schlag
rawtitle: Analysis and design of {CMOS Manchester} adders with variable carry-skip
entry:
@InProceedings{Chan:1989:ADC,
  author =       "P. K. Chan and M. D. F. Schlag",
  title =        "Analysis and design of {CMOS Manchester} adders with
                 variable carry-skip",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "86--95",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Chan.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1989:DRN
author: J. T. Chen and W. K. Jenkins
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 208--211
year: 1989
DOI: https://doi.org/10.1109/ISCAS.1989.100328
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. T. Chen and W. K. Jenkins
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
title:
Design of a residue number system digital correlator for real-time processing in ultrasonic blood flow measurements

rawtitle:
Design of a residue number system digital correlator for real-time processing in ultrasonic blood flow measurements

entry:
@InProceedings{Chen:1989:DRN,
  author =       "J. T. Chen and W. K. Jenkins",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Design of a residue number system digital correlator
                 for real-time processing in ultrasonic blood flow
                 measurements",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "208--211",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1989.100328",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The design of a high-speed digital correlator for
                 implementing the real-time correlation function
                 required in an ultrasonic blood flowmeter is presented.
                 In order to achieve the necessary real-time processing
                 rates, a residue number system (RNS) \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chen:1989:FCN
author: S. G. Chen and P. Y. Hsieh
title: Fast Computation of the $N$ th Root
journal: j-COMPUT-MATH-APPL
volume: 17
number: 10
pages: 1423--1427
year: 1989
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Thu Sep 15 18:41:31 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.15 18:41:31 ???
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nj
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: S. G. Chen and P. Y. Hsieh
rawtitle: Fast Computation of the {$N$ th} Root
entry:
@Article{Chen:1989:FCN,
  author =       "S. G. Chen and P. Y. Hsieh",
  title =        "Fast Computation of the {$N$ th} Root",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "17",
  number =       "10",
  pages =        "1423--1427",
  year =         "1989",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Thu Sep 15 18:41:31 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
  xxmonth =      "(none)",
}


bibtype: article
filename: fparith.bib
label: Chen:1989:FCTa
author: S.-G. Chen and P. Y. Hsieh
title: Fast computation of the $N$-th root
journal: j-COMPUT-MATH-APPL
volume: 17
number: 10
pages: 1423--1427
year: 1989
CODEN: CMAPDK
DOI: https://doi.org/10.1016/0898-1221(89)90024-2
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 19:01:11 MST 2017
bibtimestamp: 2017.03.01 19:01:11 MST
URL: http://www.sciencedirect.com/science/article/pii/0898122189900242
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nj
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: S.-G. Chen and P. Y. Hsieh
rawtitle: Fast computation of the {$N$}-th root
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/computmathappl1980.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
From the abstract: ``A new class of iterative methods for computing a differentiable function is proposed, which is based on Pade approximation to Taylor's series of the function. It leads to a faster algorithm than Newton's method for $ x^1 / N $ and a different interpretation of Newton's method.''

entry:
@Article{Chen:1989:FCTa,
  author =       "S.-G. Chen and P. Y. Hsieh",
  title =        "Fast computation of the {$N$}-th root",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "17",
  number =       "10",
  pages =        "1423--1427",
  month =        "????",
  year =         "1989",
  CODEN =        "CMAPDK",
  DOI =          "https://doi.org/10.1016/0898-1221(89)90024-2",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 19:01:11 MST 2017",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/computmathappl1980.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0898122189900242",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
  remark =       "From the abstract: ``A new class of iterative methods
                 for computing a differentiable function is proposed,
                 which is based on Pad{\'e} approximation to Taylor's
                 series of the function. It leads to a faster algorithm
                 than Newton's method for $ x^{1 / N} $ and a different
                 interpretation of Newton's method.''",
}


bibtype: mastersthesis
filename: fparith.bib
label: Chinn:1989:DIA
author: Patty Chinn
type: Thesis (M.S.E.E.)
school: University of Washingto
address: Seattle, WA, USA
pages: vi + 45 + 1
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Image processing --- Digital techniques.
acknowledgement: ack-nhfb
rawauthor: Patty Chinn
title:
The design, implementation, and applications of an ACT8837 floating point processor in an image processing hardware subsystem

rawtitle:
The design, implementation, and applications of an {ACT8837} floating point processor in an image processing hardware subsystem

entry:
@MastersThesis{Chinn:1989:DIA,
  author =       "Patty Chinn",
  title =        "The design, implementation, and applications of an
                 {ACT8837} floating point processor in an image
                 processing hardware subsystem",
  type =         "Thesis ({M.S.E.E.})",
  school =       "University of Washingto",
  address =      "Seattle, WA, USA",
  pages =        "vi + 45 + 1",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Image processing --- Digital techniques.",
}


bibtype: book
filename: fparith.bib
label: Chow:1989:MXR
editor: Paul Chow
title: The MIPS-X RISC Microprocessor
publisher: pub-KLUWER
address: pub-KLUWER:adr
pages: xxiv + 231
year: 1989
ISBN: 0-7923-9045-8 OR 0792390458
ISBN13: 978-0-7923-9045-9 OR 9780792390459
LCCN: QA76.8.M524 M57 1989
bibdate: Tue Dec 14 23:27:43 1993
bibtimestamp: 1993.12.14 23:27:43 ???
series: The Kluwer international series in engineering and computer science
keywords: MIPS-X (microprocessor); VLSI, computer architecture, and digital signal processing SECS 81
ZMnumber: 0706.68010
acknowledgement: ack-nhfb
raweditor: Paul Chow
rawtitle: The {MIPS-X RISC} Microprocessor
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib; https://www.math.utah.edu/pub/tex/bib/microchip.bib

entry:
@Book{Chow:1989:MXR,
  editor =       "Paul Chow",
  title =        "The {MIPS-X RISC} Microprocessor",
  publisher =    pub-KLUWER,
  address =      pub-KLUWER:adr,
  pages =        "xxiv + 231",
  year =         "1989",
  ISBN =         "0-7923-9045-8",
  ISBN-13 =      "978-0-7923-9045-9",
  LCCN =         "QA76.8.M524 M57 1989",
  bibdate =      "Tue Dec 14 23:27:43 1993",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  series =       "The Kluwer international series in engineering and
                 computer science",
  ZMnumber =     "0706.68010",
  acknowledgement = ack-nhfb,
  keywords =     "MIPS-X (microprocessor); VLSI, computer architecture,
                 and digital signal processing SECS 81",
}


bibtype: inproceedings
filename: fparith.bib
label: Clenshaw:1989:LIA
author: C. W. Clenshaw and F. W. J. Olver and Peter R. Turner
title: Level-index arithmetic: an introductory survey
crossref: Turner:1989:NAP
pages: 95--168
year: 1989
DOI: https://doi.org/10.1007/BFb0085718
MRclass: 65Q05
MRnumber: 1022263
bibdate: Tue Oct 09 09:58:20 2007
bibtimestamp: 2007.10.09 09:58:20 ???
acknowledgement: ack-nhfb
rawauthor: C. W. Clenshaw and F. W. J. Olver and Peter R. Turner
rawtitle: Level-index arithmetic: an introductory survey
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/o/olver-frank-w-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

authordates:
Charles William Clenshaw (15 March 1926--23 September 2004); Frank William John Olver (15 December 1924--23 April 2013)

entry:
@InProceedings{Clenshaw:1989:LIA,
  author =       "C. W. Clenshaw and F. W. J. Olver and Peter R.
                 Turner",
  title =        "Level-index arithmetic: an introductory survey",
  crossref =     "Turner:1989:NAP",
  pages =        "95--168",
  year =         "1989",
  DOI =          "https://doi.org/10.1007/BFb0085718",
  MRclass =      "65Q05",
  MRnumber =     "1022263",
  bibdate =      "Tue Oct 09 09:58:20 2007",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/o/olver-frank-w-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  author-dates = "Charles William Clenshaw (15 March 1926--23 September
                 2004); Frank William John Olver (15 December 1924--23
                 April 2013)",
}


bibtype: article
filename: fparith.bib
label: Clenshaw:1989:RSU
author: C. W. Clenshaw and Peter R. Turner
title: Root squaring using level-index arithmetic
journal: j-COMPUTING
volume: 43
number: 2
pages: 171--185
month: jun
monthnumber: 6
year: 1989
CODEN: CMPTA2
DOI: https://doi.org/10.1007/BF02241860
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 65G99 (65H05)
MRnumber: 1 034 362
bibdate: Sun Nov 12 06:18:24 2023
bibtimestamp: 2023.11.12 06:18:24 ???
fjournal: Computing. Archives for Scientific Computing
acknowledgement: ack-nhfb
authordates: Charles William Clenshaw (15 March 1926--23 September 2004)
journalURL: http://link.springer.com/journal/607
subjectdates: Frank William John Olver (15 December 1924--23 April 2013)
rawauthor: C. W. Clenshaw and Peter R. Turner
rawtitle: Root squaring using level-index arithmetic
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0010-485X; https://www.math.utah.edu/pub/bibnet/authors/c/clenshaw-charles-w.bib; https://www.math.utah.edu/pub/bibnet/authors/o/olver-frank-w-j.bib; https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database

entry:
@Article{Clenshaw:1989:RSU,
  author =       "C. W. Clenshaw and Peter R. Turner",
  title =        "Root squaring using level-index arithmetic",
  journal =      j-COMPUTING,
  volume =       "43",
  number =       "2",
  pages =        "171--185",
  month =        jun,
  year =         "1989",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/BF02241860",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "65G99 (65H05)",
  MRnumber =     "1 034 362",
  bibdate =      "Sun Nov 12 06:18:24 2023",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0010-485X;
                 https://www.math.utah.edu/pub/bibnet/authors/c/clenshaw-charles-w.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/o/olver-frank-w-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database",
  acknowledgement = ack-nhfb,
  author-dates = "Charles William Clenshaw (15 March 1926--23 September
                 2004)",
  fjournal =     "Computing. Archives for Scientific Computing",
  journal-URL =  "http://link.springer.com/journal/607",
  subject-dates = "Frank William John Olver (15 December 1924--23 April
                 2013)",
  xxtitle =      "{Das Graeffe-Verfahren mit H{\"o}henindexarithmetik}",
}


bibtype: techreport
filename: fparith.bib
label: Cody:1989:AXF
author: W. J. Cody
title: Algorithm XXX: Functions to Support the IEEE Standard for Binary Floating-Point Arithmetic
number: MCS-P90-0789
institution: Mathematics and Computer Science Division, Argonne National Laboratory
address: Argonne, IL, USA
month: jul
monthnumber: 7
year: 1989
bibdate: Thu Sep 01 10:38:08 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:38:08 ???
acknowledgement: ack-nj
rawauthor: W. J. Cody
rawtitle: Algorithm {XXX}: Functions to Support the {IEEE} Standard for Binary Floating-Point Arithmetic
entry:
@TechReport{Cody:1989:AXF,
  author =       "W. J. Cody",
  title =        "Algorithm {XXX}: Functions to Support the {IEEE}
                 Standard for Binary Floating-Point Arithmetic",
  number =       "MCS-P90-0789",
  institution =  "Mathematics and Computer Science Division, Argonne
                 National Laboratory",
  address =      "Argonne, IL, USA",
  pages =        "??",
  month =        jul,
  year =         "1989",
  bibdate =      "Thu Sep 01 10:38:08 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Dadda:1989:PC
author: Luigi Dadda
title: Polyphase convolvers
crossref: Ercegovac:1989:PSC
pages: 78--85
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Dadda.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
authordates: 29 April 1923--26 October 2012
rawauthor: Luigi Dadda
rawtitle: Polyphase convolvers
entry:
@InProceedings{Dadda:1989:PC,
  author =       "Luigi Dadda",
  title =        "Polyphase convolvers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "78--85",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Dadda.pdf",
  acknowledgement = ack-nhfb,
  author-dates = "29 April 1923--26 October 2012",
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Dadda:1989:SIM
author: Luigi Dadda
title: On serial-input multipliers for two's complement numbers
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 9
pages: 1341--1345
month: sep
monthnumber: 9
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.29478
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:41 MDT 2011
bibtimestamp: 2011.07.08 19:00:41 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29478
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
authordates: 29 April 1923--26 October 2012
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Luigi Dadda
rawtitle: On serial-input multipliers for two's complement numbers
entry:
@Article{Dadda:1989:SIM,
  author =       "Luigi Dadda",
  title =        "On serial-input multipliers for two's complement
                 numbers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "9",
  pages =        "1341--1345",
  month =        sep,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.29478",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29478",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  author-dates = "29 April 1923--26 October 2012",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Dally:1989:MOF
author: W. J. Dally
title: Micro-optimization of floating-point operations
journal: j-COMP-ARCH-NEWS
volume: 17
number: 2
pages: 283--289
month: apr
monthnumber: 4
year: 1989
CODEN: CANED2
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Fri May 12 09:40:39 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.12 09:40:39 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/sigarch
rawauthor: W. J. Dally
rawtitle: Micro-optimization of floating-point operations
entry:
@Article{Dally:1989:MOF,
  author =       "W. J. Dally",
  title =        "Micro-optimization of floating-point operations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "283--289",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}


bibtype: article
filename: fparith.bib
label: DAngelo:1989:DEA
author: S. D'Angelo and G. R. Sechi
title: Definition of elementary arithmetic operations by using ACM
journal: j-SIGMICRO
volume: 20
number: 3
pages: 160--162
month: aug
monthnumber: 8
year: 1989
CODEN: SIGMDJ
DOI: https://doi.org/10.1145/75395.75414
ISSN: 0163-5751, 1050-916X OR 01635751, 1050916X
ISSNL: 0163-5751 OR 01635751
bibdate: Fri Apr 16 10:27:41 MDT 2021
bibtimestamp: 2021.04.16 10:27:41 MDT
URL: https://dl.acm.org/doi/10.1145/75395.75414
fjournal: ACM SIGMICRO Newsletter
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/sigmicro
rawauthor: S. D'Angelo and G. R. Sechi
rawtitle: Definition of elementary arithmetic operations by using {ACM}
entry:
@Article{DAngelo:1989:DEA,
  author =       "S. D'Angelo and G. R. Sechi",
  title =        "Definition of elementary arithmetic operations by
                 using {ACM}",
  journal =      j-SIGMICRO,
  volume =       "20",
  number =       "3",
  pages =        "160--162",
  month =        aug,
  year =         "1989",
  CODEN =        "SIGMDJ",
  DOI =          "https://doi.org/10.1145/75395.75414",
  ISSN =         "0163-5751, 1050-916X",
  ISSN-L =       "0163-5751",
  bibdate =      "Fri Apr 16 10:27:41 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigmicro.bib",
  URL =          "https://dl.acm.org/doi/10.1145/75395.75414",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGMICRO Newsletter",
  journal-URL =  "https://dl.acm.org/loi/sigmicro",
}


bibtype: misc
filename: fparith.bib
label: Darley:1989:FPI
title: Floating Point / Integer Processor with Divide and Square Root Functions
pages: 160--162
day: 31
month: oct
monthnumber: 10
year: 1989
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
note: U.S. Patent No. 4,878,190 held by Texas Instruments. Expired 2008-01-29.
URL: https://patentimages.storage.googleapis.com/bb/ca/c5/ed5ce0fc874200/US4878190.pdf
acknowledgement: ack-sfo
rawnote: U.S. Patent No. 4,878,190 held by Texas Instruments. Expired 2008-01-29.
rawtitle: Floating Point\slash Integer Processor with Divide and Square Root Functions
author:
Henry M. Darley and Michael C. Gill and Dale C. Earl and Dinh T. Ngo and Paul C. Wang and Maria B. L. Hipona and Jim Dodrill

rawauthor:
Henry M. Darley and Michael C. Gill and Dale C. Earl and Dinh T. Ngo and Paul C. Wang and Maria B. L. Hipona and Jim Dodrill

entry:
@Misc{Darley:1989:FPI,
  author =       "Henry M. Darley and Michael C. Gill and Dale C. Earl
                 and Dinh T. Ngo and Paul C. Wang and Maria B. L. Hipona
                 and Jim Dodrill",
  title =        "Floating Point\slash Integer Processor with Divide and
                 Square Root Functions",
  day =          "31",
  month =        oct,
  year =         "1989",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 4,878,190 held by Texas Instruments.
                 Expired 2008-01-29.",
  URL =          "https://patentimages.storage.googleapis.com/bb/ca/c5/ed5ce0fc874200/US4878190.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: deLange:1989:DMA
author: A. A. J. de Lange and A. J. van der Hoeven and E. F. Deprettere and P. Dewilde and J. Bu
crossref: IEE:1989:EEC
pages: 410--414
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Delft University of Technol., Netherlands
rawauthor: A. A. J. de Lange and A. J. van der Hoeven and E. F. Deprettere and P. Dewilde and J. Bu
title:
The design of a 50 Mflop arithmetic chip for massively parallel pipelined DSP algorithms: the floating point pipeline CORDIC processor

abstract:
The paper describes a high performance VLSI CORDIC arithmetic chip. It performs 15 10/sup 6/ rotations/sec (50 Mflops) and can be applied as a processing element in parallel/pipelined processor structures (systolic and wavefront arrays) for real time/high speed signal processing algorithms and matrix computation applications. The authors present a novel optimized (floating point) CORDIC algorithm, and architecture, its performance and layout. Algorithm, architecture, performance and layout are parametrized which allows automatic generation of the chip layout for any required chip performance, accuracy and dynamic range of arithmetic operations.

keywords:
50 MFLOPS; Chip layout automatic generation; Dynamic range; Floating point pipeline CORDIC processor; High speed signal processing algorithm; Matrix computation applications; Parallel structure; Pipelined processor structure; Real time signal processing; Systolic arrays; VLSI CORDIC arithmetic chip; Wavefront arrays

thesaurus:
Digital arithmetic; Digital signal processing chips; Parallel architectures; Pipeline processing; VLSI

rawabstract:
The paper describes a high performance VLSI CORDIC arithmetic chip. It performs 15 10/sup 6/ rotations/sec (50 Mflops) and can be applied as a processing element in parallel/pipelined processor structures (systolic and wavefront arrays) for real time/high speed signal processing algorithms and matrix computation applications. The authors present a novel optimized (floating point) CORDIC algorithm, and architecture, its performance and layout. Algorithm, architecture, performance and layout are parametrized which allows automatic generation of the chip layout for any required chip performance, accuracy and dynamic range of arithmetic operations.

rawtitle:
The design of a 50 Mflop arithmetic chip for massively parallel pipelined {DSP} algorithms: the floating point pipeline {CORDIC} processor

entry:
@InProceedings{deLange:1989:DMA,
  author =       "A. A. J. de Lange and A. J. van der Hoeven and E. F.
                 Deprettere and P. Dewilde and J. Bu",
  title =        "The design of a 50 Mflop arithmetic chip for massively
                 parallel pipelined {DSP} algorithms: the floating point
                 pipeline {CORDIC} processor",
  crossref =     "IEE:1989:EEC",
  pages =        "410--414",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper describes a high performance VLSI CORDIC
                 arithmetic chip. It performs 15 10/sup 6/ rotations/sec
                 (50 Mflops) and can be applied as a processing element
                 in parallel/pipelined processor structures (systolic
                 and wavefront arrays) for real time/high speed signal
                 processing algorithms and matrix computation
                 applications. The authors present a novel optimized
                 (floating point) CORDIC algorithm, and architecture,
                 its performance and layout. Algorithm, architecture,
                 performance and layout are parametrized which allows
                 automatic generation of the chip layout for any
                 required chip performance, accuracy and dynamic range
                 of arithmetic operations.",
  acknowledgement = ack-nhfb,
  affiliation =  "Delft University of Technol., Netherlands",
  classification = "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods);
                 C5260 (Digital signal processing)",
  keywords =     "50 MFLOPS; Chip layout automatic generation; Dynamic
                 range; Floating point pipeline CORDIC processor; High
                 speed signal processing algorithm; Matrix computation
                 applications; Parallel structure; Pipelined processor
                 structure; Real time signal processing; Systolic
                 arrays; VLSI CORDIC arithmetic chip; Wavefront arrays",
  numericalindex = "Computer speed 5.0E+07 FLOPS",
  thesaurus =    "Digital arithmetic; Digital signal processing chips;
                 Parallel architectures; Pipeline processing; VLSI",
}


bibtype: techreport
filename: fparith.bib
label: Demmel:1989:FPE
author: J. Demmel
title: On Floating Point Errors in Cholesky
type: LAPACK Working Note
number: 14
institution: inst-UT-CS
address: inst-UT-CS:adr
pages: 410--414
month: oct
monthnumber: 10
year: 1989
bibdate: Fri Apr 22 17:06:37 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.22 17:06:37 ???
note: UT-CS-89-87, October 1989.
URL: http://www.netlib.org/lapack/lawns/lawn14.ps; http://www.netlib.org/lapack/lawnspdf/lawn14.pdf
acknowledgement: ack-nhfb
rawauthor: J. Demmel
rawnote: UT-CS-89-87, October 1989.
rawtitle: On Floating Point Errors in {Cholesky}
entry:
@TechReport{Demmel:1989:FPE,
  author =       "J. Demmel",
  title =        "On Floating Point Errors in {Cholesky}",
  type =         "{LAPACK} Working Note",
  number =       "14",
  institution =  inst-UT-CS,
  address =      inst-UT-CS:adr,
  month =        oct,
  year =         "1989",
  bibdate =      "Fri Apr 22 17:06:37 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "UT-CS-89-87, October 1989.",
  URL =          "http://www.netlib.org/lapack/lawns/lawn14.ps;
                 http://www.netlib.org/lapack/lawnspdf/lawn14.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Dennis:1989:AAD
author: A. M. Dennis and C. B. Marshall and I. A. Burgess
booktitle: IEE Colloquium on Signal Processing Applications of Finite Field Mathematics, 1 June 1989
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1/1--1/5
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266615
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. M. Dennis and C. B. Marshall and I. A. Burgess
rawbooktitle: {IEE} Colloquium on Signal Processing Applications of Finite Field Mathematics, 1 June 1989
title:
Algorithm and architecture design for the implementation of high order FIR filters using the residue number system

rawtitle:
Algorithm and architecture design for the implementation of high order {FIR} filters using the residue number system

entry:
@InProceedings{Dennis:1989:AAD,
  author =       "A. M. Dennis and C. B. Marshall and I. A. Burgess",
  booktitle =    "{IEE} Colloquium on Signal Processing Applications of
                 Finite Field Mathematics, 1 June 1989",
  title =        "Algorithm and architecture design for the
                 implementation of high order {FIR} filters using the
                 residue number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1/1--1/5",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266615",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The computational speed requirements of future signal
                 processing algorithms necessitate the use of special
                 purpose multiprocessor systems implemented using VLSI
                 technology. Finite field arithmetic and algorithms
                 offer an extra degree of freedom in \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Dowling:1989:MVF
author: E. Dowling and M. Griffin and M. Lynch and F. Taylor
title: A multi-purpose VLSI floating-point array processor
crossref: Chen:1989:TSA
pages: 730--734 vol.2
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., Florida University, Gainesville, FL, USA
rawauthor: E. Dowling and M. Griffin and M. Lynch and F. Taylor
rawtitle: A multi-purpose {VLSI} floating-point array processor
abstract:
A 3*3 single-instruction multiple-data (SIMD) array processor for the IBM PC/AT is described. This array processor is a modified bus-connected architecture (MBCA) using TI's SN74ACT8847 64-bit VLSI floating-point units for processing elements. The array processor can operate four different modes of operation: scalar, vector processor, full utilization, and simulated systolic. In full utilization mode, this array processor can sustain a 90-MFLOP computational rate. System software is also discussed, and attention is given to how it will be used with the SIGLAB programming environment.

keywords:
64 Bit; 90 MFLOPS; Full utilization mode; IBM PC/AT; Modes of operation; Modified bus-connected architecture; SIGLAB programming environment; SIMD; Single-instruction multiple-data; SN74ACT8847; VLSI floating-point array processor

thesaurus:
CMOS integrated circuits; IBM computers; Microcomputers; Microprocessor chips; Parallel architectures; Parallel processing; VLSI

rawabstract:
A 3*3 single-instruction multiple-data (SIMD) array processor for the IBM PC/AT is described. This array processor is a modified bus-connected architecture (MBCA) using TI's SN74ACT8847 64-bit VLSI floating-point units for processing elements. The array processor can operate four different modes of operation: scalar, vector processor, full utilization, and simulated systolic. In full utilization mode, this array processor can sustain a 90-MFLOP computational rate. System software is also discussed, and attention is given to how it will be used with the SIGLAB programming environment.

entry:
@InProceedings{Dowling:1989:MVF,
  author =       "E. Dowling and M. Griffin and M. Lynch and F. Taylor",
  title =        "A multi-purpose {VLSI} floating-point array
                 processor",
  crossref =     "Chen:1989:TSA",
  pages =        "730--734 vol.2",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 3*3 single-instruction multiple-data (SIMD) array
                 processor for the IBM PC/AT is described. This array
                 processor is a modified bus-connected architecture
                 (MBCA) using TI's SN74ACT8847 64-bit VLSI
                 floating-point units for processing elements. The array
                 processor can operate four different modes of
                 operation: scalar, vector processor, full utilization,
                 and simulated systolic. In full utilization mode, this
                 array processor can sustain a 90-MFLOP computational
                 rate. System software is also discussed, and attention
                 is given to how it will be used with the SIGLAB
                 programming environment.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng., Florida University,
                 Gainesville, FL, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5430
                 (Microcomputers); C5440 (Multiprocessor systems and
                 techniques)",
  keywords =     "64 Bit; 90 MFLOPS; Full utilization mode; IBM PC/AT;
                 Modes of operation; Modified bus-connected
                 architecture; SIGLAB programming environment; SIMD;
                 Single-instruction multiple-data; SN74ACT8847; VLSI
                 floating-point array processor",
  numericalindex = "Word length 6.4E+01 bit; Computer speed 9.0E+07
                 FLOPS",
  thesaurus =    "CMOS integrated circuits; IBM computers;
                 Microcomputers; Microprocessor chips; Parallel
                 architectures; Parallel processing; VLSI",
}


bibtype: techreport
filename: fparith.bib
label: Dritz:1989:RPS
author: K. W. Dritz
title: Rationale for the Proposed Standard for a Generic Package of Elementary Functions for Ada
type: Report
number: ANL-89/2 Rev. 1
institution: Argonne National Laboratory, Mathematics and Computer Science Division
address: Argonne, IL, USA
month: oct
monthnumber: 10
year: 1989
bibdate: Thu Sep 01 12:08:24 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 12:08:24 ???
acknowledgement: ack-nj
rawauthor: K. W. Dritz
rawtitle: Rationale for the Proposed Standard for a Generic Package of Elementary Functions for {Ada}
entry:
@TechReport{Dritz:1989:RPS,
  author =       "K. W. Dritz",
  title =        "Rationale for the Proposed Standard for a Generic
                 Package of Elementary Functions for {Ada}",
  type =         "Report",
  number =       "ANL-89/2 Rev. 1",
  institution =  "Argonne National Laboratory, Mathematics and Computer
                 Science Division",
  address =      "Argonne, IL, USA",
  pages =        "??",
  month =        oct,
  year =         "1989",
  bibdate =      "Thu Sep 01 12:08:24 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Dunham:1989:ICA
author: C. B. Dunham
title: Improvement of complex arithmetic by use of double elements
journal: j-SIGNUM
volume: 24
number: 4
pages: 3--7
month: oct
monthnumber: 10
year: 1989
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:18 MDT 2005
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 07:50:18 MDT
fjournal: ACM SIGNUM Newsletter
keywords: algorithms; theory
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/signum
rawauthor: C. B. Dunham
rawtitle: Improvement of complex arithmetic by use of double elements
subject:
G.1.3 Mathematics of Computing, NUMERICAL ANALYSIS, Numerical Linear Algebra, Matrix inversion G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic

entry:
@Article{Dunham:1989:ICA,
  author =       "C. B. Dunham",
  title =        "Improvement of complex arithmetic by use of double
                 elements",
  journal =      j-SIGNUM,
  volume =       "24",
  number =       "4",
  pages =        "3--7",
  month =        oct,
  year =         "1989",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:18 MDT 2005",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "algorithms; theory",
  subject =      "G.1.3 Mathematics of Computing, NUMERICAL ANALYSIS,
                 Numerical Linear Algebra, Matrix inversion \\ G.1.0
                 Mathematics of Computing, NUMERICAL ANALYSIS, General,
                 Computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Dunham:1989:PAH
author: C. B. Dunham
title: Perturbation Analysis of Horner's Method for Nice Cases
journal: j-SIGNUM
volume: 24
number: 2 and 3
pages: 8--9
month: apr
monthnumber: 4
year: 1989
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Thu Sep 1 10:15:41 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:41 ???
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nj
journalURL: https://dl.acm.org/loi/signum
rawauthor: C. B. Dunham
rawtitle: Perturbation Analysis of {Horner}'s Method for Nice Cases
entry:
@Article{Dunham:1989:PAH,
  author =       "C. B. Dunham",
  title =        "Perturbation Analysis of {Horner}'s Method for Nice
                 Cases",
  journal =      j-SIGNUM,
  volume =       "24",
  number =       "2 and 3",
  pages =        "8--9",
  month =        apr # "/" # jul,
  year =         "1989",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Thu Sep 1 10:15:41 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
}


bibtype: article
filename: fparith.bib
label: Dunham:1989:S
author: C. B. Dunham
title: Summation
journal: j-SIGNUM
volume: 24
number: 1
pages: 14--15
month: jan
monthnumber: 1
year: 1989
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Sep 13 08:58:48 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.13 08:58:48 ???
fjournal: ACM SIGNUM Newsletter
keywords: accurate floating-point summation
acknowledgement: ack-nj
journalURL: https://dl.acm.org/loi/signum
rawauthor: C. B. Dunham
rawtitle: Summation
entry:
@Article{Dunham:1989:S,
  author =       "C. B. Dunham",
  title =        "Summation",
  journal =      j-SIGNUM,
  volume =       "24",
  number =       "1",
  pages =        "14--15",
  month =        jan,
  year =         "1989",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Sep 13 08:58:48 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Duprat:1989:SRA
author: Jean Duprat and Yves Herreros and Jean-Michel Muller
title: Some results about on-line computation of functions
crossref: Ercegovac:1989:PSC
pages: 112--118
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Duprat.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Jean Duprat and Yves Herreros and Jean-Michel Muller
rawtitle: Some results about on-line computation of functions
entry:
@InProceedings{Duprat:1989:SRA,
  author =       "Jean Duprat and Yves Herreros and Jean-Michel Muller",
  title =        "Some results about on-line computation of functions",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "112--118",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Duprat.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Elleithy:1989:ARA
author: K. M. Elleithy and M. A. Bayoumi and K. P. Lee
title: $ theta (log N) $ architectures for RNS arithmetic decoding
crossref: Ercegovac:1989:PSC
pages: 202--209
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Elleithy.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: K. M. Elleithy and M. A. Bayoumi and K. P. Lee
rawtitle: {$ \theta (\log N) $} architectures for {RNS} arithmetic decoding
entry:
@InProceedings{Elleithy:1989:ARA,
  author =       "K. M. Elleithy and M. A. Bayoumi and K. P. Lee",
  title =        "{$ \theta (\log N) $} architectures for {RNS}
                 arithmetic decoding",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "202--209",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Elleithy.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:FRD
author: M. D. Ercegovac and T. Lang
title: On-the-fly rounding for division and square root
crossref: Ercegovac:1989:PSC
pages: 169--173
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_rounding.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: M. D. Ercegovac and T. Lang
rawtitle: On-the-fly rounding for division and square root
entry:
@InProceedings{Ercegovac:1989:FRD,
  author =       "M. D. Ercegovac and T. Lang",
  title =        "On-the-fly rounding for division and square root",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "169--173",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_rounding.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "In division and square root implementation based on
                 digit-recurrence algorithms, the result is obtained in
                 digit-serial form, from most significant digit to least
                 significant. To reduce the complexity of the
                 result-digit selection and to allow the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:FSC
author: Milos D. Ercegovac and Algirdas Avizienis and Earl Swartzlander
title: Foreword: 9th Symposium on Computer Arithmetic (ARITH9)
crossref: Ercegovac:1989:PSC
pages: v--v
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. Ercegovac and Algirdas Avi{\v{z}}ienis and Earl Swartzlander
rawtitle: Foreword: {9th Symposium on Computer Arithmetic (ARITH9)}
URL:
http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_contents.pdf; http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_foreword.pdf; http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_preface.pdf

entry:
@InProceedings{Ercegovac:1989:FSC,
  author =       "Milo{\v{s}} D. Ercegovac and Algirdas Avi{\v{z}}ienis
                 and Earl Swartzlander",
  title =        "Foreword: {9th Symposium on Computer Arithmetic
                 (ARITH9)}",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "v--v",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_contents.pdf;
                 http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_foreword.pdf;
                 http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_preface.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:IMC
author: M. D. Ercegovac and T. Lang
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
title: Implementation of module combining multiplication, division, and square root
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 150--153
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: M. D. Ercegovac and T. Lang
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
rawtitle: Implementation of module combining multiplication, division, and square root
entry:
@InProceedings{Ercegovac:1989:IMC,
  author =       "M. D. Ercegovac and T. Lang",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Implementation of module combining multiplication,
                 division, and square root",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "150--153",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The implementation of a module that performs radix-$2$
                 multiplication, division, and square root is presented.
                 The module is compact because most of the components
                 are shared by all three operations, the complexity
                 being similar to that of a radix-$2$ \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:RSR
author: Milos D. Ercegovac and Tomas Lang
title: Radix-4 square root without initial PLA
crossref: Ercegovac:1989:PSC
pages: 162--168
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_radix4.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. Ercegovac and Tomas Lang
rawtitle: Radix-4 square root without initial {PLA}
entry:
@InProceedings{Ercegovac:1989:RSR,
  author =       "Milo{\v{s}} D. Ercegovac and Tomas Lang",
  title =        "Radix-4 square root without initial {PLA}",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "162--168",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_radix4.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "A systematic derivation of a radix-$4$ square root
                 algorithm using redundance in the partial residuals and
                 the result is presented. Unlike other similar schemes,
                 the algorithm does not use a table-lookup or
                 programmable logic array (PLA) for the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Fandrianto:1989:AHS
author: Jan Fandrianto
title: Algorithms for high-speed shared radix 8 division and radix 8 square root
crossref: Ercegovac:1989:PSC
pages: 68--75
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fandrianto.pdf
keywords: ARITH-9
acknowledgement: ack-sfo
rawauthor: Jan Fandrianto
rawtitle: Algorithms for high-speed shared radix 8 division and radix 8 square root
entry:
@InProceedings{Fandrianto:1989:AHS,
  author =       "Jan Fandrianto",
  title =        "Algorithms for high-speed shared radix 8 division and
                 radix 8 square root",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "68--75",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fandrianto.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "An algorithm for performing radix-$8$ division and
                 square root in a shared hardware is described. To
                 achieve short iteration cycle time, it utilizes an
                 optimized `next quotient/root prediction PLA' generally
                 used in a radix-$4$ SRT division with minimal
                 \ldots{}",
}


bibtype: inbook
filename: fparith.bib
label: Feldstein:1989:NAP
author: Alan Feldstein and Richard H. Goodman
title: Some aspects of floating point computation
crossref: Turner:1989:NAP
pages: 169--181
year: 1989
DOI: https://doi.org/10.1007/BFb0085718
MRclass: 65G05
MRnumber: 022 264
bibdate: Fri Dec 8 08:24:14 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:14 ???
acknowledgement: ack-nhfb
rawauthor: Alan Feldstein and Richard H. Goodman
rawtitle: Some aspects of floating point computation
abstract:
The floating point format is widely used in computing because it allows for the representation of numbers with greatly varying magnitude. This paper introduces some general aspects of floating point representation and includes a discussion of the implications of balanced and unbalanced exponent ranges. A statistical approach is presented in order to analyze the error in floating point computations. The shortening of computer words is discussed and is applied to study aspects of the fraction error and the relative error.

rawabstract:
The floating point format is widely used in computing because it allows for the representation of numbers with greatly varying magnitude. This paper introduces some general aspects of floating point representation and includes a discussion of the implications of balanced and unbalanced exponent ranges. A statistical approach is presented in order to analyze the error in floating point computations. The shortening of computer words is discussed and is applied to study aspects of the fraction error and the relative error.

entry:
@InBook{Feldstein:1989:NAP,
  author =       "Alan Feldstein and Richard H. Goodman",
  title =        "Some aspects of floating point computation",
  crossref =     "Turner:1989:NAP",
  pages =        "169--181",
  year =         "1989",
  DOI =          "https://doi.org/10.1007/BFb0085718",
  MRclass =      "65G05",
  MRnumber =     "022 264",
  bibdate =      "Fri Dec 8 08:24:14 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The floating point format is widely used in computing
                 because it allows for the representation of numbers
                 with greatly varying magnitude. This paper introduces
                 some general aspects of floating point representation
                 and includes a discussion of the implications of
                 balanced and unbalanced exponent ranges. A statistical
                 approach is presented in order to analyze the error in
                 floating point computations. The shortening of computer
                 words is discussed and is applied to study aspects of
                 the fraction error and the relative error.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Fowler:1989:AHS
author: D. L. Fowler and J. E. Smith
title: An accurate, high speed implementation of division by reciprocal approximation
crossref: Ercegovac:1989:PSC
pages: 60--67
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fowler.pdf
acknowledgement: ack-nhfb
affiliation: Astronaut. Corp. of America, Madison, WI, USA
bookpages: xv + 247
thesaurus: Digital arithmetic; Interpolation; Table lookup
rawauthor: D. L. Fowler and J. E. Smith
rawtitle: An accurate, high speed implementation of division by reciprocal approximation
abstract:
While unlimited accuracy is theoretically possible, it is very important to minimize the number of iteration steps to improve performance and/or to reduce hardware requirements. Consequently, there is an important accuracy/speed/cost tradeoff in reciprocal approximation implementations. A reciprocal approximation implementation is discussed, with special attention given to these tradeoffs. An interpolation method is used to ensure that an initial approximation, held in a ROM table, is as accurate as possible. A method for implementing the iteration steps is given. Special instructions are used so that maximum accuracy can be carried between iteration operations. For 64-b floating-point operands (53-b mantissa), a table lookup and only two iterations are required, and high accuracy is maintained. The rounded reciprocal rarely differs from a true round-to-nearest value based on an infinite precision result. When the results do differ (less than once every 1000 calculations), the difference in accuracy is shown to be less than 0.025 of a least significant bit (LSB).

keywords:
ARITH-9; Division; Hardware requirements; High speed implementation; Interpolation; Reciprocal approximation; ROM table; Rounded reciprocal; Table lookup

rawabstract:
While unlimited accuracy is theoretically possible, it is very important to minimize the number of iteration steps to improve performance and/or to reduce hardware requirements. Consequently, there is an important accuracy/speed/cost tradeoff in reciprocal approximation implementations. A reciprocal approximation implementation is discussed, with special attention given to these tradeoffs. An interpolation method is used to ensure that an initial approximation, held in a ROM table, is as accurate as possible. A method for implementing the iteration steps is given. Special instructions are used so that maximum accuracy can be carried between iteration operations. For 64-b floating-point operands (53-b mantissa), a table lookup and only two iterations are required, and high accuracy is maintained. The rounded reciprocal rarely differs from a true round-to-nearest value based on an infinite precision result. When the results do differ (less than once every 1000 calculations), the difference in accuracy is shown to be less than 0.025 of a least significant bit (LSB).

entry:
@InProceedings{Fowler:1989:AHS,
  author =       "D. L. Fowler and J. E. Smith",
  title =        "An accurate, high speed implementation of division by
                 reciprocal approximation",
  crossref =     "Ercegovac:1989:PSC",
  bookpages =    "xv + 247",
  pages =        "60--67",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fowler.pdf",
  abstract =     "While unlimited accuracy is theoretically possible, it
                 is very important to minimize the number of iteration
                 steps to improve performance and/or to reduce hardware
                 requirements. Consequently, there is an important
                 accuracy/speed/cost tradeoff in reciprocal
                 approximation implementations. A reciprocal
                 approximation implementation is discussed, with special
                 attention given to these tradeoffs. An interpolation
                 method is used to ensure that an initial approximation,
                 held in a ROM table, is as accurate as possible. A
                 method for implementing the iteration steps is given.
                 Special instructions are used so that maximum accuracy
                 can be carried between iteration operations. For 64-b
                 floating-point operands (53-b mantissa), a table lookup
                 and only two iterations are required, and high accuracy
                 is maintained. The rounded reciprocal rarely differs
                 from a true round-to-nearest value based on an infinite
                 precision result. When the results do differ (less than
                 once every 1000 calculations), the difference in
                 accuracy is shown to be less than 0.025 of a least
                 significant bit (LSB).",
  acknowledgement = ack-nhfb,
  affiliation =  "Astronaut. Corp. of America, Madison, WI, USA",
  classification = "C4130 (Interpolation and function approximation);
                 C5230 (Digital arithmetic methods); C6130 (Data
                 handling techniques)",
  confdate =     "6-8 Sept. 1989",
  conflocation = "Santa Monica, CA, USA",
  confsponsor =  "IEEE; IFIP; University of California",
  keywords =     "ARITH-9; Division; Hardware requirements; High speed
                 implementation; Interpolation; Reciprocal
                 approximation; ROM table; Rounded reciprocal; Table
                 lookup",
  thesaurus =    "Digital arithmetic; Interpolation; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Fried:1989:ONC
author: S. Fried
title: Optimizing numeric coprocessing
journal: j-BYTE
volume: 14
number: 11
pages: 221--224
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:47:21 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:47:21 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
thesaurus: Computer testing; Digital arithmetic; Performance evaluation; Satellite computers
rawauthor: S. Fried
rawtitle: Optimizing numeric coprocessing
keywords:
Addition; Compiler optimizations; CPU code; Floating-point operations; Multiplication; Numeric coprocessing; Optimisation; Weitek 3167

entry:
@Article{Fried:1989:ONC,
  author =       "S. Fried",
  title =        "Optimizing numeric coprocessing",
  journal =      j-BYTE,
  volume =       "14",
  number =       "11",
  pages =        "221--224",
  month =        "????",
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:47:21 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5230 (Digital arithmetic methods); C5470
                 (Performance evaluation and testing)",
  fjournal =     "BYTE Magazine",
  keywords =     "Addition; Compiler optimizations; CPU code;
                 Floating-point operations; Multiplication; Numeric
                 coprocessing; Optimisation; Weitek 3167",
  thesaurus =    "Computer testing; Digital arithmetic; Performance
                 evaluation; Satellite computers",
}


bibtype: inproceedings
filename: fparith.bib
label: Fu:1989:PMI
author: B. Fu and A. Saini and P. P. Gelsinger
title: Performance and Microarchitecture of the i486TM Processor
crossref: IEEE:1989:PII
pages: 182--187
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Intel Corp., Santa Clara, CA, USA
thesaurus: Microprocessor chips
rawauthor: B. Fu and A. Saini and P. P. Gelsinger
rawtitle: Performance and Microarchitecture of the i486{\TM} Processor
abstract:
The i486 microprocessor includes a carefully tuned, five-stage pipeline with an integrated 8-kB cache. A variety of techniques previously associated only with RISC (reduced-instruction-set computer) processors are used to execute the average instruction in 1.8 clocks. This represents a 2.5* reduction from its predecessor, the 386 microprocessor. The pipeline and clock count comparisons are described in detail. In addition, an onchip floating-point unit is included which yields a 4* clock count reduction from the 387 numeric coprocessor. The microarchitecture enhancements and optimizations used to achieve this goal, most of which are non-silicon-intensive, are discussed. All instructions of the 386 microprocessor and the 387 numeric coprocessor are implemented in a completely compatible fashion.

keywords:
386 Microprocessor; 387 Numeric coprocessor; Clock count; Five-stage pipeline; I486 processor; Intel; Microarchitecture; Onchip floating-point unit; Performance

rawabstract:
The i486 microprocessor includes a carefully tuned, five-stage pipeline with an integrated 8-kB cache. A variety of techniques previously associated only with RISC (reduced-instruction-set computer) processors are used to execute the average instruction in 1.8 clocks. This represents a 2.5* reduction from its predecessor, the 386 microprocessor. The pipeline and clock count comparisons are described in detail. In addition, an onchip floating-point unit is included which yields a 4* clock count reduction from the 387 numeric coprocessor. The microarchitecture enhancements and optimizations used to achieve this goal, most of which are non-silicon-intensive, are discussed. All instructions of the 386 microprocessor and the 387 numeric coprocessor are implemented in a completely compatible fashion.

entry:
@InProceedings{Fu:1989:PMI,
  author =       "B. Fu and A. Saini and P. P. Gelsinger",
  title =        "Performance and Microarchitecture of the i486{\TM}
                 Processor",
  crossref =     "IEEE:1989:PII",
  pages =        "182--187",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The i486 microprocessor includes a carefully tuned,
                 five-stage pipeline with an integrated 8-kB cache. A
                 variety of techniques previously associated only with
                 RISC (reduced-instruction-set computer) processors are
                 used to execute the average instruction in 1.8 clocks.
                 This represents a 2.5* reduction from its predecessor,
                 the 386 microprocessor. The pipeline and clock count
                 comparisons are described in detail. In addition, an
                 onchip floating-point unit is included which yields a
                 4* clock count reduction from the 387 numeric
                 coprocessor. The microarchitecture enhancements and
                 optimizations used to achieve this goal, most of which
                 are non-silicon-intensive, are discussed. All
                 instructions of the 386 microprocessor and the 387
                 numeric coprocessor are implemented in a completely
                 compatible fashion.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Intel Corp., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips)",
  confdate =     "2-4 Oct. 1989",
  conflocation = "Cambridge, MA, USA",
  confsponsor =  "IEEE",
  keywords =     "386 Microprocessor; 387 Numeric coprocessor; Clock
                 count; Five-stage pipeline; I486 processor; Intel;
                 Microarchitecture; Onchip floating-point unit;
                 Performance",
  thesaurus =    "Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Fujiyama:1989:FD
author: T. Fujiyama and Y. Shimazu and T. Tokuda and S. Tsujimichi
title: A 24-bit floating-point DSP
journal: Mitsubishi Denki Giho
volume: 63
number: 12
pages: 59--62
year: 1989
ISSN: 0369-2302 OR 03692302
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
language: Japanese
acknowledgement: ack-nhfb
affiliation: Mitsubishi Electr. Corp., Tokyo, Japan
thesaurus: Computerised signal processing; Digital signal processing chips
rawauthor: T. Fujiyama and Y. Shimazu and T. Tokuda and S. Tsujimichi
rawtitle: A 24-bit floating-point {DSP}
abstract:
The authors report on a new high-speed 24-bit floating point DSP (digital signal processor) and its development tools. The DSP features a short 75 ns instruction cycle and low 750 mW power dissipation. Other features include a large memory space, internal RAM that can be configured as a cache, and speed control via an internal clock prescaler that is accessed by a special instruction. The DSP is suitable for application in audio and image processing, communications and numerical control.

keywords:
24 Bit; 24-Bit floating-point DSP; 75 Ns; 750 MW; Audio processing; Communications; Development; Digital signal processor; DSP chips; Image processing; Instruction cycle; Internal clock prescaler; Memory; Numerical control; Power dissipation; RAM; Speed control

rawabstract:
The authors report on a new high-speed 24-bit floating point DSP (digital signal processor) and its development tools. The DSP features a short 75 ns instruction cycle and low 750 mW power dissipation. Other features include a large memory space, internal RAM that can be configured as a cache, and speed control via an internal clock prescaler that is accessed by a special instruction. The DSP is suitable for application in audio and image processing, communications and numerical control.

entry:
@Article{Fujiyama:1989:FD,
  author =       "T. Fujiyama and Y. Shimazu and T. Tokuda and S.
                 Tsujimichi",
  title =        "A 24-bit floating-point {DSP}",
  journal =      "Mitsubishi Denki Giho",
  volume =       "63",
  number =       "12",
  pages =        "59--62",
  month =        "????",
  year =         "1989",
  ISSN =         "0369-2302",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors report on a new high-speed 24-bit floating
                 point DSP (digital signal processor) and its
                 development tools. The DSP features a short 75 ns
                 instruction cycle and low 750 mW power dissipation.
                 Other features include a large memory space, internal
                 RAM that can be configured as a cache, and speed
                 control via an internal clock prescaler that is
                 accessed by a special instruction. The DSP is suitable
                 for application in audio and image processing,
                 communications and numerical control.",
  acknowledgement = ack-nhfb,
  affiliation =  "Mitsubishi Electr. Corp., Tokyo, Japan",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5260 (Digital signal
                 processing)",
  keywords =     "24 Bit; 24-Bit floating-point DSP; 75 Ns; 750 MW;
                 Audio processing; Communications; Development; Digital
                 signal processor; DSP chips; Image processing;
                 Instruction cycle; Internal clock prescaler; Memory;
                 Numerical control; Power dissipation; RAM; Speed
                 control",
  language =     "Japanese",
  numericalindex = "Power 7.5E-01 W; Time 7.5E-08 s; Word length 2.4E+01
                 bit",
  pubcountry =   "Japan",
  thesaurus =    "Computerised signal processing; Digital signal
                 processing chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Gamberger:1989:ISN
author: D. Gamberger
title: Incompletely specified numbers in the residue number system-definition and applications
crossref: Ercegovac:1989:PSC
pages: 210--215
year: 1989
DOI: https://doi.org/10.1109/ARITH.1989.72828
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Gamberger.pdf
keywords: ARITH-9; residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: D. Gamberger
rawtitle: Incompletely specified numbers in the residue number system-definition and applications
entry:
@InProceedings{Gamberger:1989:ISN,
  author =       "D. Gamberger",
  title =        "Incompletely specified numbers in the residue number
                 system-definition and applications",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "210--215",
  year =         "1989",
  DOI =          "https://doi.org/10.1109/ARITH.1989.72828",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Gamberger.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9; residue arithmetic; residue number system",
  summary =      "Incompletely specified numbers in the residue number
                 system (RNS) are defined in order to make
                 multiplicative inverse computation of a number
                 regardless of its magnitude possible. Incompletely
                 specified RNS is the general RNS model in which
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Games:1989:AIQ
author: R. A. Games and D. Moulin and S. D. O'Neil and J. J. Rushanan
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: Algebraic-integer quantization an residue number system processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 948--951
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. A. Games and D. Moulin and S. D. O'Neil and J. J. Rushanan
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: Algebraic-integer quantization an residue number system processing
entry:
@InProceedings{Games:1989:AIQ,
  author =       "R. A. Games and D. Moulin and S. D. O'Neil and J. J.
                 Rushanan",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "Algebraic-integer quantization an residue number
                 system processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "948--951",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The algebraic-integer number representation, in which
                 the signal sample is represented by a set of (typically
                 four to eight) small integers, combines with residue
                 number system (RNS) processing to produce processors
                 composed of simple parallel \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Goel:1989:RTA
author: B. D. Goel and M. M. Jamali and S. C. Kwatra
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
title: Real time architecture for vector quantization in residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 204--207
year: 1989
DOI: https://doi.org/10.1109/ISCAS.1989.100327
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: B. D. Goel and M. M. Jamali and S. C. Kwatra
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
rawtitle: Real time architecture for vector quantization in residue number system
entry:
@InProceedings{Goel:1989:RTA,
  author =       "B. D. Goel and M. M. Jamali and S. C. Kwatra",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Real time architecture for vector quantization in
                 residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "204--207",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1989.100327",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A fast and simplified systolic array architecture for
                 real-time implementation of vector quantization is
                 proposed. The proposed architecture uses the residue
                 number system (RNS) for arithmetic operations. The
                 arithmetic operations can be precomputed \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Goldberg:1989:FCS
author: David Goldberg
title: Floating-point and computer systems
type: Technical report
number: CSL-89-9
institution: Xerox Corp., Palo Alto Research Center
address: Palo Alto, CA, USA
pages: 58
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.
remark: ``August 1989.'' ``A version of this paper will appear in Computing Surveys.''
acknowledgement: ack-nhfb
rawauthor: David Goldberg
rawtitle: Floating-point and computer systems
entry:
@TechReport{Goldberg:1989:FCS,
  author =       "David Goldberg",
  title =        "Floating-point and computer systems",
  type =         "Technical report",
  number =       "CSL-89-9",
  institution =  "Xerox Corp., Palo Alto Research Center",
  address =      "Palo Alto, CA, USA",
  pages =        "58",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.",
  remark =       "``August 1989.'' ``A version of this paper will appear
                 in Computing Surveys.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Gonnella:1989:ACF
author: J. Gonnella and J. Periard
title: The application of core functions to residue number system signal processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 604--608
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.103996
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. Gonnella and J. Periard
rawtitle: The application of core functions to residue number system signal processing
booktitle:
IEEE Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

rawbooktitle:
{IEEE} Military Communications Conference, 1989. {MILCOM '89}. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

entry:
@InProceedings{Gonnella:1989:ACF,
  author =       "J. Gonnella and J. Periard",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "The application of core functions to residue number
                 system signal processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "604--608",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.103996",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors briefly outline core-based residue number
                 system (RNS) processing. An RNS adaptive array
                 processor using Choleski decomposition and forward
                 elimination/back substitution is described as an
                 example. The RNS adaptive processor was \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Gordon:1989:RDF
author: Stephen E. Gordon
type: Thesis (M.S.E.C.E.)
school: University of Massachusetts at Amherst
address: Amherst, MA, USA
pages: xi + 123
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital filters (Mathematics)
acknowledgement: ack-nhfb
rawauthor: Stephen E. Gordon
title:
Recursive digital filtering with digital differential analyzers and floating point incremental coders

rawtitle:
Recursive digital filtering with digital differential analyzers and floating point incremental coders

entry:
@MastersThesis{Gordon:1989:RDF,
  author =       "Stephen E. Gordon",
  title =        "Recursive digital filtering with digital differential
                 analyzers and floating point incremental coders",
  type =         "Thesis ({M.S.E.C.E.})",
  school =       "University of Massachusetts at Amherst",
  address =      "Amherst, MA, USA",
  pages =        "xi + 123",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics)",
}


bibtype: article
filename: fparith.bib
label: Grassmann:1989:PAR
author: Winfried K. Grassmann
journal: j-CONG-NUM
volume: 68
pages: 171--182
year: 1989
ISSN: 0384-9864 OR 03849864
MRclass: 65G05
MRnumber: 90d:65089
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
fjournal: Congressus Numerantium
acknowledgement: ack-nhfb
rawauthor: Winfried K. Grassmann
title:
A probabilistic analysis of rounding errors of floating point numbers. Eighteenth Manitoba Conference on Numerical Mathematics and Computing (Winnipeg, MB, 1988)

rawtitle:
A probabilistic analysis of rounding errors of floating point numbers. {Eighteenth Manitoba Conference on Numerical Mathematics and Computing (Winnipeg, MB, 1988)}

entry:
@Article{Grassmann:1989:PAR,
  author =       "Winfried K. Grassmann",
  title =        "A probabilistic analysis of rounding errors of
                 floating point numbers. {Eighteenth Manitoba Conference
                 on Numerical Mathematics and Computing (Winnipeg, MB,
                 1988)}",
  journal =      j-CONG-NUM,
  volume =       "68",
  pages =        "171--182",
  year =         "1989",
  ISSN =         "0384-9864",
  MRclass =      "65G05",
  MRnumber =     "90d:65089",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Congressus Numerantium",
}


bibtype: article
filename: fparith.bib
label: Grehan:1989:FPR
author: R. Grehan
title: Floating-Point Revisited
journal: j-BYTE
volume: 14
number: 4
pages: 311--318
month: apr
monthnumber: 4
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 1 10:15:05 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:05 ???
fjournal: BYTE Magazine
acknowledgement: ack-nj
rawauthor: R. Grehan
rawtitle: Floating-Point Revisited
entry:
@Article{Grehan:1989:FPR,
  author =       "R. Grehan",
  title =        "Floating-Point Revisited",
  journal =      j-BYTE,
  volume =       "14",
  number =       "4",
  pages =        "311--318",
  month =        apr,
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 1 10:15:05 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "BYTE Magazine",
}


bibtype: inproceedings
filename: fparith.bib
label: Griffin:1989:ESR
author: M. Griffin and M. Sousa and F. Taylor
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: Efficient scaling in the residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1075--1078
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266618
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Griffin and M. Sousa and F. Taylor
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: Efficient scaling in the residue number system
entry:
@InProceedings{Griffin:1989:ESR,
  author =       "M. Griffin and M. Sousa and F. Taylor",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "Efficient scaling in the residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1075--1078",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266618",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A unified residue number system scaling technique that
                 allows the designer a great deal of flexibility in
                 choosing the scale factor is presented. The technique
                 is based on the L({\&}epsi;+{\delta})-CRT (Chinese
                 remainder theorem). By embedding \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Griffin:1989:RNS
author: M. F. Griffin and F. J. Taylor
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: A residue number system reduced instruction set computer (RISC) concept
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2581--2584
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266995
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. F. Griffin and F. J. Taylor
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: A residue number system reduced instruction set computer ({RISC}) concept
entry:
@InProceedings{Griffin:1989:RNS,
  author =       "M. F. Griffin and F. J. Taylor",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "A residue number system reduced instruction set
                 computer ({RISC}) concept",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2581--2584",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266995",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A reduced-instruction-set RNS (residue number system)
                 processor is proposed for digital signal processing
                 algorithms. Issues leading toward a RNS RISC are
                 examined, namely suitable RNS algorithms. It is argued
                 that this is a reasonable next step in \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Groeger:1989:DRG
author: Detlef Groger
journal: j-MATH-SEMESTERBER
volume: 36
number: 1
pages: 106--111
year: 1989
ISSN: 0720-728x (print), 1432-1815 (electronic) OR 0720728x (print), 14321815 (electronic)
ISSNL: 0720-728X OR 0720728X
MRclass: 65G99 (11Y16)
MRnumber: 90g:65070
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
fjournal: Mathematische Semesterberichte
language: German
acknowledgement: ack-nhfb
rawauthor: Detlef Gr{\"o}ger
title:
Zur Division mit Rest auf Gleitkommarechnern. (German) [On division with remainder on floating point computers]

rawtitle:
{Zur Division mit Rest auf Gleitkommarechnern. (German)} [{On} division with remainder on floating point computers]

entry:
@Article{Groeger:1989:DRG,
  author =       "Detlef Gr{\"o}ger",
  title =        "{Zur Division mit Rest auf Gleitkommarechnern.
                 (German)} [{On} division with remainder on floating
                 point computers]",
  journal =      j-MATH-SEMESTERBER,
  volume =       "36",
  number =       "1",
  pages =        "106--111",
  year =         "1989",
  ISSN =         "0720-728x (print), 1432-1815 (electronic)",
  ISSN-L =       "0720-728X",
  MRclass =      "65G99 (11Y16)",
  MRnumber =     "90g:65070",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematische Semesterberichte",
  language =     "German",
}


bibtype: inproceedings
filename: fparith.bib
label: Guyot:1989:JLM
author: Alain Guyot and Bertrand Hochet and Jean-Michel Muller
title: JANUS, an on-line multiplier / divider for manipulating large numbers
crossref: Ercegovac:1989:PSC
pages: 106--111
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Guyot.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Alain Guyot and Bertrand Hochet and Jean-Michel Muller
rawtitle: {JANUS}, an on-line multiplier\slash divider for manipulating large numbers
entry:
@InProceedings{Guyot:1989:JLM,
  author =       "Alain Guyot and Bertrand Hochet and Jean-Michel
                 Muller",
  title =        "{JANUS}, an on-line multiplier\slash divider for
                 manipulating large numbers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "106--111",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Guyot.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Hoffmann:1989:PAR
author: C. M. Hoffmann
title: The Problems of Accuracy and Robustness in Geometric Computation
journal: j-COMPUTER
volume: 22
number: 3
institution: Purdue U
pages: 31--39, 41
month: mar
monthnumber: 3
year: 1989
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Sat Sep 14 07:29:35 MDT 1996
bibsource: Graphics/rosenfeld/1989.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; Misc/IMMD_IV.bib
bibtimestamp: 1996.09.14 07:29:35 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Computer Science Dept., Purdue University, West Lafayette, IN, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
thesaurus: Computational geometry
rawauthor: C. M. Hoffmann
rawtitle: The Problems of Accuracy and Robustness in Geometric Computation
keywords:
Accuracy; Degeneracies avoidance; Degenerate positions; Floating-point computation; Geometric computation; Geometric operations; Interacting numeric data; Interacting symbolic data; Limited-precision rational arithmetic; Linear elements; Model, IMAGE PART MEASUREMENT; Numerical precision; Perturbation-free methods; Purely symbolic representations; Representation; Robustness; Symbolic data alteration

entry:
@Article{Hoffmann:1989:PAR,
  author =       "C. M. Hoffmann",
  title =        "The Problems of Accuracy and Robustness in Geometric
                 Computation",
  journal =      j-COMPUTER,
  volume =       "22",
  number =       "3",
  institution =  "Purdue U",
  pages =        "31--39, 41",
  month =        mar,
  year =         "1989",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Sep 14 07:29:35 MDT 1996",
  bibsource =    "Graphics/rosenfeld/1989.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Misc/IMMD_IV.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Computer Science Dept., Purdue University, West
                 Lafayette, IN, USA",
  classification = "C1160 (Combinatorial mathematics); C4190 (Other
                 numerical methods); C4290 (Other computer theory)",
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Accuracy; Degeneracies avoidance; Degenerate
                 positions; Floating-point computation; Geometric
                 computation; Geometric operations; Interacting numeric
                 data; Interacting symbolic data; Limited-precision
                 rational arithmetic; Linear elements; Model, IMAGE PART
                 MEASUREMENT; Numerical precision; Perturbation-free
                 methods; Purely symbolic representations;
                 Representation; Robustness; Symbolic data alteration",
  thesaurus =    "Computational geometry",
}


bibtype: inproceedings
filename: fparith.bib
label: Hohne:1989:PHP
author: R. A. Hohne and R. Siferd
title: A programmable high performance processor using the residue number system and CMOS VLSI technology
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 41--43
year: 1989
DOI: https://doi.org/10.1109/NAECON.1989.40188
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. A. Hohne and R. Siferd
booktitle:
Proceedings of the IEEE 1989 National Aerospace and Electronics Conference, NAECON 1989, 22--26 May 1989

rawbooktitle:
Proceedings of the {IEEE 1989} National Aerospace and Electronics Conference, {NAECON 1989}, 22--26 May 1989

rawtitle:
A programmable high performance processor using the residue number system and {CMOS} {VLSI} technology

entry:
@InProceedings{Hohne:1989:PHP,
  author =       "R. A. Hohne and R. Siferd",
  booktitle =    "Proceedings of the {IEEE 1989} National Aerospace and
                 Electronics Conference, {NAECON 1989}, 22--26 May
                 1989",
  title =        "A programmable high performance processor using the
                 residue number system and {CMOS} {VLSI} technology",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "41--43",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/NAECON.1989.40188",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors describe the general architecture of RNS
                 (residue number system) processors, the VLSI
                 implementation of the associated hardware, and finally,
                 an RNS processor designed by the authors. The 2-{\mu}m
                 CMOS implementation of the processor \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hollingsworth:1989:CPI
author: Walter Hollingsworth and Howard Sachs and Alan Jay Smith
title: The ClipperTM Processor: Instruction Set Architecture and Implementation
journal: j-CACM
volume: 32
number: 2
pages: 200--219
month: feb
monthnumber: 2
year: 1989
CODEN: CACMA2
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Mon Sep 26 13:49:15 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.26 13:49:15 ???
fjournal: Communications of the ACM
keywords: design; measurement; performance
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawauthor: Walter Hollingsworth and Howard Sachs and Alan Jay Smith
rawtitle: The {Clipper\TM} Processor: Instruction Set Architecture and Implementation
subject:
C.5.3 Computer Systems Organization, COMPUTER SYSTEM IMPLEMENTATION, Microcomputers, CLIPPER C.1.1 Computer Systems Organization, PROCESSOR ARCHITECTURES, Single Data Stream Architectures, Single-instruction-stream, single-data-stream processors (SISD) C.4 Computer Systems Organization, PERFORMANCE OF SYSTEMS C.0 Computer Systems Organization, GENERAL, Instruction set design

entry:
@Article{Hollingsworth:1989:CPI,
  author =       "Walter Hollingsworth and Howard Sachs and Alan Jay
                 Smith",
  title =        "The {Clipper\TM} Processor: Instruction Set
                 Architecture and Implementation",
  journal =      j-CACM,
  volume =       "32",
  number =       "2",
  pages =        "200--219",
  month =        feb,
  year =         "1989",
  CODEN =        "CACMA2",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Mon Sep 26 13:49:15 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
  keywords =     "design; measurement; performance",
  review =       "ACM CR 9002-0119",
  subject =      "C.5.3 Computer Systems Organization, COMPUTER SYSTEM
                 IMPLEMENTATION, Microcomputers, CLIPPER \\ C.1.1
                 Computer Systems Organization, PROCESSOR ARCHITECTURES,
                 Single Data Stream Architectures,
                 Single-instruction-stream, single-data-stream
                 processors (SISD) \\ C.4 Computer Systems Organization,
                 PERFORMANCE OF SYSTEMS \\ C.0 Computer Systems
                 Organization, GENERAL, Instruction set design",
}


bibtype: article
filename: fparith.bib
label: Hoshi:1989:RPV
title: RISC processor V/sub R/3000
journal: j-NEC-TECH-J
volume: 42
number: 11
pages: 34--38
month: dec
monthnumber: 12
year: 1989
CODEN: NECGEZ
ISSN: 0285-4139 OR 02854139
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: NEC Technical Journal = NEC giho
keywords: Floating point processor; NEC; RISC type microprocessor; V/sub R/3000; V/sub R/3010
language: Japanese
acknowledgement: ack-nhfb
thesaurus: Microprocessor chips; Reduced instruction set computing
rawtitle: {RISC} processor {V}/sub {R}/3000
author:
T. Hoshi and K. Koya and A. Kuwata and T. Uno and M. Kashimura and T. Kuwata and T. Nishigouri and K. Obuchi and N. Morikawa

abstract:
Outlines NEC's first RISC type microprocessor, the V/sub R/3000 and its developmental environment. V/sub R/3000 is fully compatible with the R3000 developed by MIPS Computer Systems, USA. It offers one of the fastest microprocessor systems in the world, together with a floating point processor V/sub R/3010 that is fully compatible with the R3010.

rawabstract:
Outlines NEC's first RISC type microprocessor, the V/sub R/3000 and its developmental environment. V/sub R/3000 is fully compatible with the R3000 developed by MIPS Computer Systems, USA. It offers one of the fastest microprocessor systems in the world, together with a floating point processor V/sub R/3010 that is fully compatible with the R3010.

rawauthor:
T. Hoshi and K. Koya and A. Kuwata and T. Uno and M. Kashimura and T. Kuwata and T. Nishigouri and K. Obuchi and N. Morikawa

entry:
@Article{Hoshi:1989:RPV,
  author =       "T. Hoshi and K. Koya and A. Kuwata and T. Uno and M.
                 Kashimura and T. Kuwata and T. Nishigouri and K. Obuchi
                 and N. Morikawa",
  title =        "{RISC} processor {V}/sub {R}/3000",
  journal =      j-NEC-TECH-J,
  volume =       "42",
  number =       "11",
  pages =        "34--38",
  month =        dec,
  year =         "1989",
  CODEN =        "NECGEZ",
  ISSN =         "0285-4139",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Outlines NEC's first RISC type microprocessor, the
                 V/sub R/3000 and its developmental environment. V/sub
                 R/3000 is fully compatible with the R3000 developed by
                 MIPS Computer Systems, USA. It offers one of the
                 fastest microprocessor systems in the world, together
                 with a floating point processor V/sub R/3010 that is
                 fully compatible with the R3010.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  fjournal =     "NEC Technical Journal = NEC giho",
  keywords =     "Floating point processor; NEC; RISC type
                 microprocessor; V/sub R/3000; V/sub R/3010",
  language =     "Japanese",
  pubcountry =   "Japan",
  thesaurus =    "Microprocessor chips; Reduced instruction set
                 computing",
}


