# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Hu:1989:ARM
author: Y. H. Hu and S. Naganathan
title: Angle Recoding Method for Efficient Implementation of the CORDIC Algorithm
crossref: IEEE:1989:IISa
pages: 175--178 (Vol. 1)
year: 1989
bibdate: Thu Sep 01 11:41:20 1994
bibtimestamp: 1994.09.01 11:41:20 ???
acknowledgement: ack-nj
rawauthor: Y. H. Hu and S. Naganathan
rawtitle: Angle Recoding Method for Efficient Implementation of the {CORDIC} Algorithm
entry:
@InProceedings{Hu:1989:ARM,
  author =       "Y. H. Hu and S. Naganathan",
  title =        "Angle Recoding Method for Efficient Implementation of
                 the {CORDIC} Algorithm",
  crossref =     "IEEE:1989:IISa",
  pages =        "175--178 (Vol. 1)",
  year =         "1989",
  bibdate =      "Thu Sep 01 11:41:20 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: phdthesis
filename: fparith.bib
label: Hu:1989:SCD
author: Xiaobo Hu
title: A silicon compiler for dedicated mathematical systems based on CORDIC arithmetic processors
type: Ph.D. thesis
school: Purdue University
address: West Lafayette, IN, USA
pages: 184
year: 1989
ISBN13: 979-82-07-65496-6 OR 9798207654966
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
advisor: Steven C. Bass
rawauthor: Xiaobo Hu
rawtitle: A silicon compiler for dedicated mathematical systems based on {CORDIC} arithmetic processors
URL:
https://login.ezproxy.lib.utah.edu/login?url=https://www.proquest.com/dissertations-theses/silicon-compiler-dedicated-mathematical-systems/docview/303729399/se-2

keywords:
0544:Electrical engineering; 0984:Computer science; Applied sciences; Compiler; Computer science; Electrical engineering; Mathematical systems

entry:
@PhdThesis{Hu:1989:SCD,
  author =       "Xiaobo Hu",
  title =        "A silicon compiler for dedicated mathematical systems
                 based on {CORDIC} arithmetic processors",
  type =         "{Ph.D.} thesis",
  school =       "Purdue University",
  address =      "West Lafayette, IN, USA",
  pages =        "184",
  year =         "1989",
  ISBN-13 =      "979-82-07-65496-6",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://login.ezproxy.lib.utah.edu/login?url=https://www.proquest.com/dissertations-theses/silicon-compiler-dedicated-mathematical-systems/docview/303729399/se-2",
  acknowledgement = ack-nhfb,
  advisor =      "Steven C. Bass",
  keywords =     "0544:Electrical engineering; 0984:Computer science;
                 Applied sciences; Compiler; Computer science;
                 Electrical engineering; Mathematical systems",
  ris-m1 =       "9018840",
}


bibtype: book
filename: fparith.bib
label: Huck:1989:ACA
author: Jerome C. Huck and Michael J. Flynn
title: Analyzing Computer Architectures
publisher: pub-IEEE
address: pub-IEEE:adr
pages: xiii + 188
year: 1989
LCCN: QA76.9.A73 H83 1989
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
note: IEEE Computer Society order number 857. IEEE catalog number EH0285-7. SAN 264-620X.
acknowledgement: ack-sfo
rawauthor: Jerome C. Huck and Michael J. Flynn
rawnote: IEEE Computer Society order number 857. IEEE catalog number EH0285-7. SAN 264-620X.
rawtitle: Analyzing Computer Architectures
ISBN:
0-8186-8857-2, 0-8186-4857-0 (microfiche), 0-8186-8857-2 (casebound) OR 0818688572, 0818648570 (microfiche), 0818688572 (casebound)

ISBN13:
978-0-8186-8857-7, 978-0-8186-4857-1 (microfiche), 978-0-8186-8857-7 (casebound) OR 9780818688577, 9780818648571 (microfiche), 9780818688577 (casebound)

entry:
@Book{Huck:1989:ACA,
  author =       "Jerome C. Huck and Michael J. Flynn",
  title =        "Analyzing Computer Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xiii + 188",
  year =         "1989",
  ISBN =         "0-8186-8857-2, 0-8186-4857-0 (microfiche),
                 0-8186-8857-2 (casebound)",
  ISBN-13 =      "978-0-8186-8857-7, 978-0-8186-4857-1 (microfiche),
                 978-0-8186-8857-7 (casebound)",
  LCCN =         "QA76.9.A73 H83 1989",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IEEE Computer Society order number 857. IEEE catalog
                 number EH0285-7. SAN 264-620X.",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Husby:1989:FPE
title: A floating point engine for lattice gauge calculations
journal: j-IEEE-TRANS-NUCL-SCI
volume: 36
number: 1
pages: 734--737
month: feb
monthnumber: 2
year: 1989
CODEN: IRNSAM
ISSN: 0018-9499 (print), 1558-1578 (electronic) OR 00189499 (print), 15581578 (electronic)
ISSNL: 0018-9499 OR 00189499
LCCN: TK6540 .I573 Jan-June 1988
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
URL: http://weblib.cern.ch/format/showfull?uid=1451323_18194&base=CERCER&sysnb=0105825
fjournal: IEEE Transactions on Nuclear Science
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23
rawtitle: A floating point engine for lattice gauge calculations
author:
D. Husby and R. Atac and A. Cook and J. Deppe and M. Fischler and I. Gaines and T. Nash and T. Pham and T. Zmuda and E. Eichten and G. M. Hockney and P. B. Mackenzie and H. B. Thacker and D. Toussaint

rawauthor:
D. Husby and R. Atac and A. Cook and J. Deppe and M. Fischler and I. Gaines and T. Nash and T. Pham and T. Zmuda and E. Eichten and G. M. Hockney and P. B. Mackenzie and H. B. Thacker and D. Toussaint

entry:
@Article{Husby:1989:FPE,
  author =       "D. Husby and R. Atac and A. Cook and J. Deppe and M.
                 Fischler and I. Gaines and T. Nash and T. Pham and T.
                 Zmuda and E. Eichten and G. M. Hockney and P. B.
                 Mackenzie and H. B. Thacker and D. Toussaint",
  title =        "A floating point engine for lattice gauge
                 calculations",
  journal =      j-IEEE-TRANS-NUCL-SCI,
  volume =       "36",
  number =       "1",
  pages =        "734--737",
  month =        feb,
  year =         "1989",
  CODEN =        "IRNSAM",
  ISSN =         "0018-9499 (print), 1558-1578 (electronic)",
  ISSN-L =       "0018-9499",
  LCCN =         "TK6540 .I573 Jan-June 1988",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://weblib.cern.ch/format/showfull?uid=1451323_18194&base=CERCER&sysnb=0105825",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Nuclear Science",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23",
  summary =      "The Fermilab Advanced Computer Program Multiple Array
                 Processor System, which dedicated to solving problems
                 in the field of quantum chromodynamics, is discussed. A
                 typical system with 256 processors, 2.5 Gb of memory,
                 and 64 Gb of online tape storage \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Hwang:1989:OAU
author: Kai Hwang and D. K. Panda
title: Optical arithmetic using high-radix symbolic substitution rules
crossref: Ercegovac:1989:PSC
pages: 226--232
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Hwang.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Kai Hwang and D. K. Panda
rawtitle: Optical arithmetic using high-radix symbolic substitution rules
entry:
@InProceedings{Hwang:1989:OAU,
  author =       "Kai Hwang and D. K. Panda",
  title =        "Optical arithmetic using high-radix symbolic
                 substitution rules",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "226--232",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Hwang.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: book
filename: fparith.bib
label: IEC:1989:IBF
author: IEC
title: IEC 60559 (1989-01): Binary floating-point arithmetic for microprocessor systems
publisher: pub-IEC
address: pub-IEC:adr
pages: 45
year: 1989
bibdate: Mon Apr 24 06:17:57 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.04.24 06:17:57 ???
note: This Standard was formerly known as IEEE 754.
URL: http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019113
acknowledgement: ack-nhfb
rawauthor: {IEC}
rawnote: This Standard was formerly known as IEEE 754.
rawtitle: {IEC 60559 (1989-01)}: Binary floating-point arithmetic for microprocessor systems
remark:
Working Draft, 1997-11-21, WG14/N794 J11/97-158 of the ISO C9X Standard references ``Binary floating-point arithmetic for microprocessor systems, second edition (IEC 559:1993)''. However, I cannot locate that edition at the IEC Web site. The 1997 renumbering of IEC Standards by the addition of 60000 indicates that this document should now be IED 60559:1993, but only the 1989 version is listed in the IEC catalog.

entry:
@Book{IEC:1989:IBF,
  author =       "{IEC}",
  title =        "{IEC 60559 (1989-01)}: Binary floating-point
                 arithmetic for microprocessor systems",
  publisher =    pub-IEC,
  address =      pub-IEC:adr,
  pages =        "45",
  year =         "1989",
  bibdate =      "Mon Apr 24 06:17:57 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This Standard was formerly known as IEEE 754.",
  price =        "US\$86.00",
  URL =          "http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019113",
  acknowledgement = ack-nhfb,
  remark =       "Working Draft, 1997-11-21, WG14/N794 J11/97-158 of the
                 ISO C9X Standard references ``Binary floating-point
                 arithmetic for microprocessor systems, second edition
                 (IEC 559:1993)''. However, I cannot locate that edition
                 at the IEC Web site. The 1997 renumbering of IEC
                 Standards by the addition of 60000 indicates that this
                 document should now be IED 60559:1993, but only the
                 1989 version is listed in the IEC catalog.",
}


bibtype: mastersthesis
filename: fparith.bib
label: Intwala:1989:BFP
author: Jaiprakash D. Intwala
title: 8085A based floating point arithmetic system
type: Thesis (M.S.)
school: California State University, Northridge
address: Northridge, CA, USA
pages: viii + 81
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Jaiprakash D. Intwala
rawtitle: {8085A} based floating point arithmetic system
entry:
@MastersThesis{Intwala:1989:BFP,
  author =       "Jaiprakash D. Intwala",
  title =        "{8085A} based floating point arithmetic system",
  type =         "Thesis ({M.S.})",
  school =       "California State University, Northridge",
  address =      "Northridge, CA, USA",
  pages =        "viii + 81",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jain:1989:SLU
author: V. K. Jain and D. L. Landia and C. E. Alvarez
title: Systolic L-U Decomposition Array With a New Reciprocal Cell
crossref: IEEE:1989:PII
pages: 460--465
year: 1989
bibdate: Sun Sep 11 20:59:19 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.11 20:59:19 ???
acknowledgement: ack-nj
rawauthor: V. K. Jain and D. L. Landia and C. E. Alvarez
rawtitle: Systolic {L-U} Decomposition Array With a New Reciprocal Cell
entry:
@InProceedings{Jain:1989:SLU,
  author =       "V. K. Jain and D. L. Landia and C. E. Alvarez",
  title =        "Systolic {L-U} Decomposition Array With a New
                 Reciprocal Cell",
  crossref =     "IEEE:1989:PII",
  pages =        "460--465",
  year =         "1989",
  bibdate =      "Sun Sep 11 20:59:19 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Jamieson:1989:SNR
author: M. J. Jamieson
journal: j-COMP-J
volume: 32
number: 1
pages: 93--94
month: feb
monthnumber: 2
year: 1989
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/32.1.93
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
MRclass: 65H05
MRnumber: 89k:65063
bibdate: Tue Dec 4 14:48:26 MST 2012
bibtimestamp: 2012.12.04 14:48:26 MST
note: This work generalizes the Pythagorean sums in cite Dubrulle:1983:CNM,Moler:1983:RSR.
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Glasgow University, UK
affiliationaddress: Glasgow, Scotl
classcodes: B0290F (Interpolation and function approximation); C4130 (Interpolation and function approximation)
corpsource: Department of Computer Science, Glasgow University, UK
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Convergence of numerical methods; Function approximation; Iterative methods
treatment: P Practical
rawauthor: M. J. Jamieson
rawnote: This work generalizes the Pythagorean sums in \cite{Dubrulle:1983:CNM,Moler:1983:RSR}.
title:
Short Notes: Rapidly Converging Iterative Formulae for Finding Square Roots and their Computational Efficiencies

bibsource:
Compendex database; http://comjnl.oxfordjournals.org/content/32/1.toc; http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/; https://www.math.utah.edu/pub/tex/bib/compj1980.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/content/32/1/93.full.pdf+html; http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/93.tif; http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/94.tif

abstract:
A derivation is given of rapidly converging iterative formulae for finding square roots which include, as special cases, some recently published examples. Their computational efficiencies are investigated for sequential and parallel implementation. It is concluded that the most efficient method is equivalent to sequential application of the Newton Raphson formula; a simple modification is suggested which brings the advantage of root bracketing at little extra computational cost.

keywords:
computational; Computational efficiencies; Computational Efficiency; Computer Metatheory; Convergence; convergence of numerical methods; Converging iterative formulae; converging iterative formulae; efficiencies; formula; function approximation; Iterative Methods; iterative methods; Newton Raphson; Newton Raphson formula, Mathematical Techniques; Parallel implementation; parallel implementation; Square Roots; Square roots; square roots

rawabstract:
A derivation is given of rapidly converging iterative formulae for finding square roots which include, as special cases, some recently published examples. Their computational efficiencies are investigated for sequential and parallel implementation. It is concluded that the most efficient method is equivalent to sequential application of the Newton Raphson formula; a simple modification is suggested which brings the advantage of root bracketing at little extra computational cost.

rawtitle:
Short Notes: Rapidly Converging Iterative Formulae for Finding Square Roots and their Computational Efficiencies

entry:
@Article{Jamieson:1989:SNR,
  author =       "M. J. Jamieson",
  title =        "Short Notes: Rapidly Converging Iterative Formulae for
                 Finding Square Roots and their Computational
                 Efficiencies",
  journal =      j-COMP-J,
  volume =       "32",
  number =       "1",
  pages =        "93--94",
  month =        feb,
  year =         "1989",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/32.1.93",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  MRclass =      "65H05",
  MRnumber =     "89k:65063",
  bibdate =      "Tue Dec 4 14:48:26 MST 2012",
  bibsource =    "Compendex database;
                 http://comjnl.oxfordjournals.org/content/32/1.toc;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/;
                 https://www.math.utah.edu/pub/tex/bib/compj1980.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This work generalizes the Pythagorean sums in
                 \cite{Dubrulle:1983:CNM,Moler:1983:RSR}.",
  URL =          "http://comjnl.oxfordjournals.org/content/32/1/93.full.pdf+html;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/93.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/94.tif",
  abstract =     "A derivation is given of rapidly converging iterative
                 formulae for finding square roots which include, as
                 special cases, some recently published examples. Their
                 computational efficiencies are investigated for
                 sequential and parallel implementation. It is concluded
                 that the most efficient method is equivalent to
                 sequential application of the Newton Raphson formula; a
                 simple modification is suggested which brings the
                 advantage of root bracketing at little extra
                 computational cost.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Glasgow University,
                 UK",
  affiliationaddress = "Glasgow, Scotl",
  classcodes =   "B0290F (Interpolation and function approximation);
                 C4130 (Interpolation and function approximation)",
  classification = "723; 921; B0290F (Interpolation and function
                 approximation); C4130 (Interpolation and function
                 approximation)",
  corpsource =   "Department of Computer Science, Glasgow University,
                 UK",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "computational; Computational efficiencies;
                 Computational Efficiency; Computer Metatheory;
                 Convergence; convergence of numerical methods;
                 Converging iterative formulae; converging iterative
                 formulae; efficiencies; formula; function
                 approximation; Iterative Methods; iterative methods;
                 Newton Raphson; Newton Raphson formula, Mathematical
                 Techniques; Parallel implementation; parallel
                 implementation; Square Roots; Square roots; square
                 roots",
  thesaurus =    "Convergence of numerical methods; Function
                 approximation; Iterative methods",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Jenkins:1989:AFP
author: W. K. Jenkins and J. K. Yun
booktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
title: Analysis of fixed point roundoff effects in transform domain LMS adaptive filters
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 228--232
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: W. K. Jenkins and J. K. Yun
rawbooktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
rawtitle: Analysis of fixed point roundoff effects in transform domain {LMS} adaptive filters
entry:
@InProceedings{Jenkins:1989:AFP,
  author =       "W. K. Jenkins and J. K. Yun",
  booktitle =    "European Conference on Circuit Theory and Design, 5--8
                 Sep 1989",
  title =        "Analysis of fixed point roundoff effects in transform
                 domain {LMS} adaptive filters",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "228--232",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "One of the disadvantages of the well known LMS FIR
                 adaptive digital filter is that, for a colored noise
                 input signals, the filter tends to converge slowly. One
                 way to improve the convergence rate is to prefilter the
                 input signal with an \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Johnson:1989:IMA
author: K. R. Johnson
title: An Iterative Method for Approximating Square Roots
journal: j-MATH-MAG
volume: 62
number: 4
pages: 253--259
month: oct
monthnumber: 10
year: 1989
CODEN: MAMGA8
ISSN: 0025-570X OR 0025570X
bibdate: Thu Sep 1 10:15:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:42 ???
fjournal: Mathematics Magazine
acknowledgement: ack-nj
journalURL: http://www.maa.org/pubs/mathmag.html
rawauthor: K. R. Johnson
rawtitle: An Iterative Method for Approximating Square Roots
entry:
@Article{Johnson:1989:IMA,
  author =       "K. R. Johnson",
  title =        "An Iterative Method for Approximating Square Roots",
  journal =      j-MATH-MAG,
  volume =       "62",
  number =       "4",
  pages =        "253--259",
  month =        oct,
  year =         "1989",
  CODEN =        "MAMGA8",
  ISSN =         "0025-570X",
  bibdate =      "Thu Sep 1 10:15:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Mathematics Magazine",
  journal-URL =  "http://www.maa.org/pubs/mathmag.html",
}


bibtype: inproceedings
filename: fparith.bib
label: Johnstone:1989:HRF
author: Paul Johnstone and Frederick E. Petry
title: Higher Radix Floating Point Representations
crossref: Ercegovac:1989:PSC
pages: 128--135
year: 1989
DOI: https://doi.org/10.1109/ARITH.1989.72818
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Johnstone.pdf
acknowledgement: ack-nhfb
affiliation: Telerate Syst. Inc., New Orleans, LA, USA
thesaurus: Digital arithmetic
rawauthor: Paul Johnstone and Frederick E. Petry
rawtitle: Higher Radix Floating Point Representations
abstract:
An examination is made of the feasibility of higher-radix floating-point representations and, in particular, decimal-based representations. Traditional analyses of such representations have assumed the format of a floating-point datum to be roughly identical to that of traditional binary floating-point encodings such as the IEEE P754 task group standard representations. The authors relax this restriction and propose a method of encoding higher-radix floating-point data with range, precision, and storage requirements comparable to those exhibited by traditional binary representations. The results of other authors are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed, and the behavior of such a system is contrasted with that of a comparable binary system.

keywords:
ARITH-9; Binary representations; decimal floating-point arithmetic; Decimal-based representations; encodings; higher radix floating point representation; IEEE P754 task group standard representations

rawabstract:
An examination is made of the feasibility of higher-radix floating-point representations and, in particular, decimal-based representations. Traditional analyses of such representations have assumed the format of a floating-point datum to be roughly identical to that of traditional binary floating-point encodings such as the IEEE P754 task group standard representations. The authors relax this restriction and propose a method of encoding higher-radix floating-point data with range, precision, and storage requirements comparable to those exhibited by traditional binary representations. The results of other authors are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed, and the behavior of such a system is contrasted with that of a comparable binary system.

entry:
@InProceedings{Johnstone:1989:HRF,
  author =       "Paul Johnstone and Frederick E. Petry",
  title =        "Higher Radix Floating Point Representations",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "128--135",
  year =         "1989",
  DOI =          "https://doi.org/10.1109/ARITH.1989.72818",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Johnstone.pdf",
  abstract =     "An examination is made of the feasibility of
                 higher-radix floating-point representations and, in
                 particular, decimal-based representations. Traditional
                 analyses of such representations have assumed the
                 format of a floating-point datum to be roughly
                 identical to that of traditional binary floating-point
                 encodings such as the IEEE P754 task group standard
                 representations. The authors relax this restriction and
                 propose a method of encoding higher-radix
                 floating-point data with range, precision, and storage
                 requirements comparable to those exhibited by
                 traditional binary representations. The results of
                 other authors are extended to accommodate the proposed
                 representation. A decimal alternative to traditional
                 binary representations is proposed, and the behavior of
                 such a system is contrasted with that of a comparable
                 binary system.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Telerate Syst. Inc., New Orleans, LA, USA",
  classification = "C5230 (Digital arithmetic methods)",
  confdate =     "6-8 Sept. 1989",
  conflocation = "Santa Monica, CA, USA",
  confsponsor =  "IEEE; IFIP; University of California",
  keywords =     "ARITH-9; Binary representations; decimal
                 floating-point arithmetic; Decimal-based
                 representations; encodings; higher radix floating point
                 representation; IEEE P754 task group standard
                 representations",
  thesaurus =    "Digital arithmetic",
}


bibtype: article
filename: fparith.bib
label: Jones:1989:EDC
author: Tom Jones
title: Engineering design of the Convex C2
journal: j-COMPUTER
volume: 22
number: 1
pages: 36--44
month: jan
monthnumber: 1
year: 1989
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Convex Computer Corp., Richardson, TX
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
key: C.5.1 Convex C2
reviewer: P. C. Patton
rawauthor: Tom Jones
rawtitle: Engineering design of the {Convex C2}
subject:
C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS; B. Hardware; B.7 INTEGRATED CIRCUITS; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES

entry:
@Article{Jones:1989:EDC,
  author =       "Tom Jones",
  key =          "C.5.1 Convex C2",
  title =        "Engineering design of the {Convex C2}",
  journal =      j-COMPUTER,
  volume =       "22",
  number =       "1",
  pages =        "36--44",
  month =        jan,
  year =         "1989",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Convex Computer Corp., Richardson, TX",
  bibno =        "58556",
  catcode =      "C.5.1; C.5.1; B.4.3; B.7.1; C.1.2",
  content =      "The Convex C220 and C240 supercomputers are 64-bit
                 multiprocessors that are tightly coupled through a
                 shared main memory. Each processor contains an
                 integrated vector processor. A microcoded instruction
                 set controls all processor features, including the
                 vector processor. The system is implemented in 100K
                 emitter-coupled logic with a cycle time of 40
                 nanoseconds. The C220 contains two processors, an I/O
                 system, and memory. The C240 contains four processors,
                 a larger I/O system, and memory. This paper describes
                 the design process of this computer family and tries to
                 illuminate the methods and rationale behind
                 project-related decisions.\par

                 The original C1 system was designed in early 1983 using
                 transistor-transistor logic and complementary
                 metal-oxide semiconductor (CMOS) technologies. The bulk
                 of the machine consisted of medium- and
                 small-scale-integration logic, and the vector
                 functional units were built with 8,000-gate CMOS
                 arrays. The original C1 (later dubbed the C1-XL) had no
                 scalar floating-point hardware but sent the operands to
                 the vector processor. In 1984, floating-point
                 add-and-multiply functional units were designed in
                 20,000-gate CMOS arrays, and the C1 was upgraded to the
                 C1-XP. That machine, with minor changes, became the
                 C120 when the C2 was announced.\par

                 This paper is unusually frank for a retrospective
                 design trade-off study. The author describes",
  CRclass =      "C.5.1 Large and Medium (``Mainframe'') Computers;
                 C.5.1 Super (very large) computers; C.5.1 Large and
                 Medium (``Mainframe'') Computers; C.5.1 Convex C2;
                 B.4.3 Interconnections (subsystems); B.7.1 Types and
                 Design Styles; B.7.1 Gate arrays; C.1.2 Multiple Data
                 Stream Architectures (Multiprocessors); C.1.2
                 Interconnection architectures",
  CRnumber =     "8909-0654",
  descriptor =   "Computer Systems Organization, COMPUTER SYSTEM
                 IMPLEMENTATION, Large and Medium (``Mainframe'')
                 Computers, Super (very large) computers; Computer
                 Systems Organization, COMPUTER SYSTEM IMPLEMENTATION,
                 Large and Medium (``Mainframe'') Computers, Convex C2;
                 Hardware, INPUT/OUTPUT AND DATA COMMUNICATIONS,
                 Interconnections (subsystems); Hardware, INTEGRATED
                 CIRCUITS, Types and Design Styles, Gate arrays;
                 Computer Systems Organization, PROCESSOR ARCHITECTURES,
                 Multiple Data Stream Architectures (Multiprocessors),
                 Interconnection architectures",
  fjournal =     "Computer",
  genterm =      "DESIGN; MANAGEMENT; PERFORMANCE; ECONOMICS",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  journalabbrev = "Computer",
  reviewer =     "P. C. Patton",
  subject =      "C. Computer Systems Organization; C.5 COMPUTER SYSTEM
                 IMPLEMENTATION; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.4
                 INPUT/OUTPUT AND DATA COMMUNICATIONS; B. Hardware; B.7
                 INTEGRATED CIRCUITS; C. Computer Systems Organization;
                 C.1 PROCESSOR ARCHITECTURES",
}


bibtype: book
filename: fparith.bib
label: Jorke:1989:AAM
author: Gunter Jorke and Bernhard Lampe and Norbert Wengel
publisher: pub-VEB-VERLAG-TECHNIK
address: pub-VEB-VERLAG-TECHNIK:adr
pages: 323
year: 1989
ISBN: 3-341-00515-3 OR 3341005153
ISBN13: 978-3-341-00515-6 OR 9783341005156
bibdate: Fri Sep 16 16:30:36 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:36 ???
acknowledgement: ack-nj
rawauthor: G{\"u}nter Jorke and Bernhard Lampe and Norbert Wengel
title:
Arithmetische Algorithmen der Mikrorechentechnik toenglish Arithmetic Algorithms of Microcomputing endtoenglish 

rawtitle:
{Arithmetische Algorithmen der Mikrorechentechnik} \toenglish {Arithmetic Algorithms of Microcomputing} \endtoenglish

entry:
@Book{Jorke:1989:AAM,
  author =       "G{\"u}nter Jorke and Bernhard Lampe and Norbert
                 Wengel",
  title =        "{Arithmetische Algorithmen der Mikrorechentechnik}
                 \toenglish {Arithmetic Algorithms of Microcomputing}
                 \endtoenglish",
  publisher =    pub-VEB-VERLAG-TECHNIK,
  address =      pub-VEB-VERLAG-TECHNIK:adr,
  pages =        "323",
  year =         "1989",
  ISBN =         "3-341-00515-3",
  ISBN-13 =      "978-3-341-00515-6",
  LCCN =         "????",
  bibdate =      "Fri Sep 16 16:30:36 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  xxnote =       "fpbiblio.txt 1.8 has order Lampe, Jorke, Wengel, but
                 RLIN catalog has Jorke, Lampe, Wengel.",
}


bibtype: article
filename: fparith.bib
label: Joslin:1989:EPN
author: David A. Joslin
title: Extended Pascal --- numerical features
journal: j-SIGPLAN
volume: 24
number: 6
pages: 77--80
month: jun
monthnumber: 6
year: 1989
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:40 MST 2003
bibsource: Compendex database; http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:15:40 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliationaddress: Middlesbrough, Engl
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
rawauthor: David A. Joslin
rawtitle: Extended {Pascal} --- numerical features
abstract:
The Extended Pascal standard, drafted by the Joint X3J9 / IEEE-770 Pascal Standards Committee (JPC) in conjunction with the ISO Pascal working group (ISO / IEC JTC1 / SC22 / WG2), completed its second public comment period at the end of 1988. The comments received have been considered by JPC and the ISO group, and the standard is now almost certainly in its final form. Earlier papers by this author described the main features of the standard by means of illustrative examples. This is now the first in an occasional series of articles, by this author and other JPC & WG2 members, describing in more detail various extensions which have been made to the Pascal language; rationale is given where appropriate. This paper describes the predefined type COMPLEX, the range and precision of type REAL, and the EXPONENTIATION operators.

keywords:
Complex Arithmetic; Computer Operating Systems--Program Compilers; Computer Programming Languages; design; Extended Pascal; languages; pascal; standardization; Standards

subject:
D.2.1 Software, SOFTWARE ENGINEERING, Requirements/Specifications D.3.2 Software, PROGRAMMING LANGUAGES, Language Classifications, Pascal

rawabstract:
The Extended Pascal standard, drafted by the Joint X3J9\slash IEEE-770 Pascal Standards Committee (JPC) in conjunction with the ISO Pascal working group (ISO\slash IEC JTC1\slash SC22\slash WG2), completed its second public comment period at the end of 1988. The comments received have been considered by JPC and the ISO group, and the standard is now almost certainly in its final form. Earlier papers by this author described the main features of the standard by means of illustrative examples. This is now the first in an occasional series of articles, by this author and other JPC \& WG2 members, describing in more detail various extensions which have been made to the Pascal language; rationale is given where appropriate. This paper describes the predefined type COMPLEX, the range and precision of type REAL, and the EXPONENTIATION operators.

entry:
@Article{Joslin:1989:EPN,
  author =       "David A. Joslin",
  title =        "Extended {Pascal} --- numerical features",
  journal =      j-SIGPLAN,
  volume =       "24",
  number =       "6",
  pages =        "77--80",
  month =        jun,
  year =         "1989",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:40 MST 2003",
  bibsource =    "Compendex database; http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Extended Pascal standard, drafted by the Joint
                 X3J9\slash IEEE-770 Pascal Standards Committee (JPC) in
                 conjunction with the ISO Pascal working group
                 (ISO\slash IEC JTC1\slash SC22\slash WG2), completed
                 its second public comment period at the end of 1988.
                 The comments received have been considered by JPC and
                 the ISO group, and the standard is now almost certainly
                 in its final form. Earlier papers by this author
                 described the main features of the standard by means of
                 illustrative examples. This is now the first in an
                 occasional series of articles, by this author and other
                 JPC \& WG2 members, describing in more detail various
                 extensions which have been made to the Pascal language;
                 rationale is given where appropriate. This paper
                 describes the predefined type COMPLEX, the range and
                 precision of type REAL, and the EXPONENTIATION
                 operators.",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Middlesbrough, Engl",
  classification = "723; 902",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "Complex Arithmetic; Computer Operating
                 Systems--Program Compilers; Computer Programming
                 Languages; design; Extended Pascal; languages; pascal;
                 standardization; Standards",
  subject =      "D.2.1 Software, SOFTWARE ENGINEERING,
                 Requirements/Specifications \\ D.3.2 Software,
                 PROGRAMMING LANGUAGES, Language Classifications,
                 Pascal",
}


bibtype: techreport
filename: fparith.bib
label: Jouppi:1989:UVSa
author: Norman Paul Jouppi and Jonathan Bertoni and David Wayne Wall
title: A unified vector / scalar floating-point architecture
institution: Digital Western Research Laboratory
address: Palo Alto, CA, USA
pages: v + 23
month: jul
monthnumber: 7
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: WRL research report; 89/8
acknowledgement: ack-nhfb
rawauthor: Norman Paul Jouppi and Jonathan Bertoni and David Wayne Wall
rawtitle: A unified vector\slash scalar floating-point architecture
keywords:
Computer architecture.; Floating-point arithmetic.; MultiTitan (Computer); Scalar field theory.; Supercomputers.; Vector processing (Computer science)

entry:
@TechReport{Jouppi:1989:UVSa,
  author =       "Norman Paul Jouppi and Jonathan Bertoni and David
                 Wayne Wall",
  title =        "A unified vector\slash scalar floating-point
                 architecture",
  institution =  "Digital Western Research Laboratory",
  address =      "Palo Alto, CA, USA",
  pages =        "v + 23",
  month =        jul,
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "WRL research report; 89/8",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture.; Floating-point arithmetic.;
                 MultiTitan (Computer); Scalar field theory.;
                 Supercomputers.; Vector processing (Computer science)",
}


bibtype: article
filename: fparith.bib
label: Jouppi:1989:UVSb
author: N. P. Jouppi and J. Bertoni and D. W. Wall
title: A unified vector / scalar floating-point architecture
journal: j-COMP-ARCH-NEWS
volume: 17
number: 2
pages: 134--143
month: apr
monthnumber: 4
year: 1989
CODEN: CANED2
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Fri May 12 09:40:39 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.12 09:40:39 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/sigarch
rawauthor: N. P. Jouppi and J. Bertoni and D. W. Wall
rawtitle: A unified vector\slash scalar floating-point architecture
entry:
@Article{Jouppi:1989:UVSb,
  author =       "N. P. Jouppi and J. Bertoni and D. W. Wall",
  title =        "A unified vector\slash scalar floating-point
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "134--143",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}


bibtype: misc
filename: fparith.bib
label: Kahan:1989:PCA
author: W. Kahan
title: Paradoxes in Concepts of Accuracy
pages: 134--143
year: 1989
bibdate: Sat Sep 17 18:40:08 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.17 18:40:08 ???
acknowledgement: ack-nhfb
howpublished: Lecture notes from Joint Seminar on Issues and Directions in Scientific Computation, Berkeley
rawauthor: W. Kahan
rawtitle: Paradoxes in Concepts of Accuracy
entry:
@Misc{Kahan:1989:PCA,
  author =       "W. Kahan",
  title =        "Paradoxes in Concepts of Accuracy",
  howpublished = "Lecture notes from Joint Seminar on Issues and
                 Directions in Scientific Computation, Berkeley",
  year =         "1989",
  bibdate =      "Sat Sep 17 18:40:08 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kak:1989:BAS
author: S. C. Kak and A. O. Barbir
booktitle: Proceedings of the Twenty-First Southeastern Symposium on System Theory, 26--28 March 1989
title: The Brahmagupta algorithm for square rooting
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 456--459
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: S. C. Kak and A. O. Barbir
rawbooktitle: Proceedings of the Twenty-First Southeastern Symposium on System Theory, 26--28 March 1989
rawtitle: The {Brahmagupta} algorithm for square rooting
entry:
@InProceedings{Kak:1989:BAS,
  author =       "S. C. Kak and A. O. Barbir",
  booktitle =    "Proceedings of the Twenty-First Southeastern Symposium
                 on System Theory, 26--28 March 1989",
  title =        "The {Brahmagupta} algorithm for square rooting",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "456--459",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "An algorithm for square root evaluation is introduced.
                 Novel features of the algorithm include suitability for
                 parallel processing and multi-initial guesses of the
                 root. An extension of the algorithm to the nth rooting
                 is provided. A VLSI \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kaneko:1989:VRM
title: A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1331--1340
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A {VLSI RISC} with {20-MFLOPS} peak, 64-bit floating-point unit
author:
K. Kaneko and T. Okamoto and M. Nakajima and Y. Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa and H. Kadota

rawauthor:
K. Kaneko and T. Okamoto and M. Nakajima and Y. Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa and H. Kadota

entry:
@Article{Kaneko:1989:VRM,
  author =       "K. Kaneko and T. Okamoto and M. Nakajima and Y.
                 Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa
                 and H. Kadota",
  title =        "A {VLSI RISC} with {20-MFLOPS} peak, 64-bit
                 floating-point unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1331--1340",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "A microprocessor designed as a processing element of a
                 scientific parallel computer system is described. This
                 chip consists of a simple integer processor core and
                 dedicated floating-point hardware and executes 64-bit
                 floating-point addition, subtraction \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kaneko:1989:VRP
title: A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1331--1340
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: Semicond. Research Center, Matsushita Electr. Ind. Co., Ltd., Osaka, Japan
rawtitle: A {VLSI RISC} with 20-{MFLOPS} peak, 64-bit floating-point unit
author:
K. Kaneko and T. Okamoto and M. Nakajima and Y. Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa and H. Kadota

abstract:
A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm.

keywords:
1.2 Micron; 20 MFLOPS; 350 Ns; 50 Ns; 64 Bit; Addition; Dedicated floating-point hardware; Division; Floating-point unit; Harvard-style bus organization; Integer processor core; Microprocessor; Multiplication; N-well CMOS technology; RISC architecture; Scientific parallel computer system; Subtraction; VLSI

thesaurus:
CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Parallel processing; Reduced instruction set computing; VLSI

rawabstract:
A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm.

entry:
@Article{Kaneko:1989:VRP,
  author =       "K. Kaneko and T. Okamoto and M. Nakajima and Y.
                 Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa
                 and H. Kadota",
  title =        "A {VLSI RISC} with 20-{MFLOPS} peak, 64-bit
                 floating-point unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1331--1340",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A microprocessor designed as a processing element of a
                 scientific parallel computer system is described. This
                 chip consists of a simple integer processor core and
                 dedicated floating-point hardware and executes 64-bit
                 floating-point addition, subtraction, and
                 multiplication at a rate of every 50 ns and division
                 every 350 ns. The processor, which employs RISC
                 architecture and Harvard-style bus organization,
                 executes most of the 47 instructions in one 50-ns
                 cycle. The chip is fabricated in 1.2- mu m n-well CMOS
                 technology, containing 440K transistors in a
                 14.4*13.5-mm/sup 2/ die. The authors provide an
                 overview of the processor, especially focusing on the
                 functions for a parallel system, floating-point
                 hardware, and the new divide algorithm.",
  acknowledgement = ack-nhfb,
  affiliation =  "Semicond. Research Center, Matsushita Electr. Ind.
                 Co., Ltd., Osaka, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "1.2 Micron; 20 MFLOPS; 350 Ns; 50 Ns; 64 Bit;
                 Addition; Dedicated floating-point hardware; Division;
                 Floating-point unit; Harvard-style bus organization;
                 Integer processor core; Microprocessor; Multiplication;
                 N-well CMOS technology; RISC architecture; Scientific
                 parallel computer system; Subtraction; VLSI",
  numericalindex = "Computer speed 2.0E+07 FLOPS; Word length 6.4E+01
                 bit; Time 5.0E-08 s; Time 3.5E-07 s; Size 1.2E-06 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Parallel processing; Reduced
                 instruction set computing; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Kawarai:1989:OPM
author: S. Kawarai and T. Murakami
title: An optimization procedure to minimize the roundoff noise in cascade floating-point digital filters
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 884--887
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: S. Kawarai and T. Murakami
rawtitle: An optimization procedure to minimize the roundoff noise in cascade floating-point digital filters
booktitle:
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on. 23--26 May 1989

rawbooktitle:
Acoustics, Speech, and Signal Processing, 1989. {ICASSP-89., 1989} International Conference on. 23--26 May 1989

entry:
@InProceedings{Kawarai:1989:OPM,
  author =       "S. Kawarai and T. Murakami",
  booktitle =    "Acoustics, Speech, and Signal Processing, 1989.
                 {ICASSP-89., 1989} International Conference on. 23--26
                 May 1989",
  title =        "An optimization procedure to minimize the roundoff
                 noise in cascade floating-point digital filters",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "884--887",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors study the roundoff errors in
                 floating-point arithmetic and present an optimization
                 procedure for cascade floating-point digital filters.
                 Applying the isosceles trapezoidal distribution to the
                 error analysis of cascade floating-point \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kawasaki:1989:FPV
author: S. Kawasaki and M. Watabe and S. Morinaga
journal: j-IEEE-MICRO
volume: 9
number: 3
pages: 26--44
month: may
monthnumber: 5
year: 1989
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.31476
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: S. Kawasaki and M. Watabe and S. Morinaga
title:
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming

rawtitle:
A floating-point {VLSI} chip for the {TRON} architecture: an architecture for reliable numerical programming

entry:
@Article{Kawasaki:1989:FPV,
  author =       "S. Kawasaki and M. Watabe and S. Morinaga",
  title =        "A floating-point {VLSI} chip for the {TRON}
                 architecture: an architecture for reliable numerical
                 programming",
  journal =      j-IEEE-MICRO,
  volume =       "9",
  number =       "3",
  pages =        "26--44",
  month =        may # "\slash " # jun,
  year =         "1989",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.31476",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "A description is given of the Gmicro/FPU
                 (floating-point unit), a chip that provides
                 floating-point instructions for both the Gmicro/200 and
                 the Gmicro/300 microprocessors. The VLSI
                 central-processing-unit architecture, for which it is
                 designed, \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Koc:1989:SAI
author: C. K. Koc and P. R. Cappello
title: Systolic arrays for integer Chinese remaindering
crossref: Ercegovac:1989:PSC
pages: 216--223
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Koc.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: {\c{C}}. K. Ko{\c{c}} and P. R. Cappello
rawtitle: Systolic arrays for integer {Chinese} remaindering
entry:
@InProceedings{Koc:1989:SAI,
  author =       "{\c{C}}. K. Ko{\c{c}} and P. R. Cappello",
  title =        "Systolic arrays for integer {Chinese} remaindering",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "216--223",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Koc.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohn:1989:ISM
author: L. Kohn and N. Margulis
title: The i860 64-bit supercomputing microprocessor
crossref: ACM:1989:PSN
pages: 450--456
year: 1989
bibdate: Wed Apr 15 19:32:44 MDT 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.15 19:32:44 MDT
acknowledgement: ack-nhfb
corpsource: Intel Corp., Santa Clara, CA, USA
treatment: P Practical
rawauthor: L. Kohn and N. Margulis
rawtitle: The {i860} 64-bit supercomputing microprocessor
keywords:
64 bit; caches; floating point unit; i860 64-bit supercomputing microprocessor; Intel; memory management; microprocessor chips; multiplier units; parallel architectures; parallelism; pipelined adder; pipelining; reduced instruction set computing; RISC based microprocessor; three-dimensional graphics

entry:
@InProceedings{Kohn:1989:ISM,
  author =       "L. Kohn and N. Margulis",
  title =        "The {i860} 64-bit supercomputing microprocessor",
  crossref =     "ACM:1989:PSN",
  pages =        "450--456",
  year =         "1989",
  bibdate =      "Wed Apr 15 19:32:44 MDT 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  corpsource =   "Intel Corp., Santa Clara, CA, USA",
  keywords =     "64 bit; caches; floating point unit; i860 64-bit
                 supercomputing microprocessor; Intel; memory
                 management; microprocessor chips; multiplier units;
                 parallel architectures; parallelism; pipelined adder;
                 pipelining; reduced instruction set computing; RISC
                 based microprocessor; three-dimensional graphics",
  sponsororg =   "ACM; IEEE",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohn:1989:TM
author: L. Kohn and S.-W. Fu
title: A 1,000,000 Transistor Microprocessor
crossref: Wuorinen:1989:DTP
pages: 54--55, 290
year: 1989
bibdate: Wed Sep 7 22:32:01 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:01 ???
acknowledgement: ack-nj
rawauthor: L. Kohn and S.-W. Fu
rawtitle: A 1,000,000 Transistor Microprocessor
entry:
@InProceedings{Kohn:1989:TM,
  author =       "L. Kohn and S.-W. Fu",
  title =        "A 1,000,000 Transistor Microprocessor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "54--55, 290",
  year =         "1989",
  bibdate =      "Wed Sep 7 22:32:01 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Komori:1989:FPE
title: A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1341--1347
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: LSI Res. and Dev. Lab., Misubishi Electr. Corp., Hyogo, Japan
thesaurus: Large scale integration; Microprocessor chips; Pipeline processing
rawtitle: A 40-{MFLOPS} 32-bit floating-point processor with elastic pipeline scheme
author:
S. Komori and H. Takata and T. Tamura and F. Asai and T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima and H. Nishikawa and H. Terada

abstract:
The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called `latch mode control', is also described.

keywords:
32 Bit; 40 MFLOPS; Automatic power conservation; Component chip; Data buffering capability; Data-driven single-board processor; Elastic pipeline scheme; Floating-point processor; Latch mode control; LSI chip; Microprocessor; Self-timed circuits; Stabilization

rawabstract:
The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called `latch mode control', is also described.

rawauthor:
S. Komori and H. Takata and T. Tamura and F. Asai and T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima and H. Nishikawa and H. Terada

entry:
@Article{Komori:1989:FPE,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A 40-{MFLOPS} 32-bit floating-point processor with
                 elastic pipeline scheme",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1341--1347",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors present a 40-MFLOPS 32-bit floating-point
                 processor (FP) which is a component chip for a
                 data-driven single-board processor. The FP is the first
                 practical LSI chip which has introduced the elastic
                 pipeline scheme. All parts in the FP are autonomously
                 controlled by self-timed circuits, and no system clock
                 is needed for processing. The elastic pipeline scheme
                 provides data buffering capability and stabilization of
                 circuit operation at the same time. Pipelining has been
                 extensively utilized so that high throughput over
                 40-MFLOPS can be achieved. An automatic power
                 conservation technique, called `latch mode control', is
                 also described.",
  acknowledgement = ack-nhfb,
  affiliation =  "LSI Res. and Dev. Lab., Misubishi Electr. Corp.,
                 Hyogo, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); C5130
                 (Microprocessor chips)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "32 Bit; 40 MFLOPS; Automatic power conservation;
                 Component chip; Data buffering capability; Data-driven
                 single-board processor; Elastic pipeline scheme;
                 Floating-point processor; Latch mode control; LSI chip;
                 Microprocessor; Self-timed circuits; Stabilization",
  numericalindex = "Computer speed 4.0E+07 FLOPS; Word length 3.2E+01
                 bit",
  thesaurus =    "Large scale integration; Microprocessor chips;
                 Pipeline processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Komori:1989:MBFa
title: A 40 MFLOPS 32-bit Floating-Point Processor
crossref: Wuorinen:1989:DTP
pages: 46--47, 286
year: 1989
bibdate: Wed Sep 7 22:32:01 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:01 ???
acknowledgement: ack-nj
rawtitle: A 40 {MFLOPS} 32-bit Floating-Point Processor
author:
S. Komori and H. Takata and T. Tamura and F. Asai and T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima and H. Nishikawa and H. Terada

entry:
@InProceedings{Komori:1989:MBFa,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A 40 {MFLOPS} 32-bit Floating-Point Processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "46--47, 286",
  year =         "1989",
  bibdate =      "Wed Sep 7 22:32:01 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Komori:1989:MBFb
title: A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1341--1347
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A {40-MFLOPS} 32-bit floating-point processor with elastic pipeline scheme
entry:
@Article{Komori:1989:MBFb,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A {40-MFLOPS} 32-bit floating-point processor with
                 elastic pipeline scheme",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1341--1347",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "The authors present a 40-MFLOPS 32-bit floating-point
                 processor (FP) which is a component chip for a
                 data-driven single-board processor. The FP is the first
                 practical LSI chip which has introduced the elastic
                 pipeline scheme. All parts in the FP are \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Komori:1989:MFP
title: A 40 MFLOPS 32-bit floating-point processor
crossref: Wuorinen:1989:DTP
pages: 46--47, 286
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Mitsubishi Electr. Corp., Hyogo, Japan
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A 40 {MFLOPS} 32-bit floating-point processor
abstract:
A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.

keywords:
32 Bit; 40 MFLOPS; ALU; Chip specifications; CMOS chip; Data transfer; Distributed execution controls; Elastic pipeline structure; Fabrication process; Floating-point processor; Logic switching speed; Pipeline configuration; Single-board data-driven processor; Subdivided pipeline stages

rawabstract:
A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.

entry:
@InProceedings{Komori:1989:MFP,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A 40 {MFLOPS} 32-bit floating-point processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "46--47, 286",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 40 MFLOPS (million floating-point operations per
                 second), 32-bit floating-point processor (FP) for a
                 single-board data-driven processor is developed using a
                 pipeline configuration called the elastic pipeline
                 structure. Because there is no need to add controls for
                 pipeline flushing by virtue of the data-driven
                 processing principle, it is possible to employ
                 extensively subdivided pipeline stages. The elastic
                 mode of data transfer between pipeline stages and
                 distributed execution controls along the pipeline
                 result in minimum deterioration of the inherent logic
                 switching speed. The structure of the FP is shown
                 together with details of the ALU (arithmetic logic
                 unit) block. The fabrication process and chip
                 specifications are summarized.",
  acknowledgement = ack-nhfb,
  affiliation =  "Mitsubishi Electr. Corp., Hyogo, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "32 Bit; 40 MFLOPS; ALU; Chip specifications; CMOS
                 chip; Data transfer; Distributed execution controls;
                 Elastic pipeline structure; Fabrication process;
                 Floating-point processor; Logic switching speed;
                 Pipeline configuration; Single-board data-driven
                 processor; Subdivided pipeline stages",
  numericalindex = "Computer speed 4.0E+07 FLOPS; Word length 3.2E+01
                 bit",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:1989:ERB
author: Peter Kornerup and David W. Matula
title: Exploiting Redundancy in Bit-Pipelined Rational Arithmetic
crossref: Ercegovac:1989:PSC
pages: 119--126
year: 1989
DOI: https://doi.org/10.1109/ARITH.1989.72817
bibdate: Wed Nov 14 18:29:43 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.14 18:29:43 ???
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Kornerup.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and David W. Matula
rawtitle: Exploiting Redundancy in Bit-Pipelined Rational Arithmetic
abstract:
The authors develop and analyze a redundant continued-fraction representation of the rationals in the implementation of an arithmetic unit for computing the sum, difference, product, quotient, and other useful functions of two rational operands. Their representation of operands and results allows the computations of the unit to be performed in a signed bit-serial, online fashion. Several such units can then be interconnected for the computation of more complicated expressions in a pipelined manner. Redundancy is used to help achieve a small bounded online delay and uniform throughput

rawabstract:
The authors develop and analyze a redundant continued-fraction representation of the rationals in the implementation of an arithmetic unit for computing the sum, difference, product, quotient, and other useful functions of two rational operands. Their representation of operands and results allows the computations of the unit to be performed in a signed bit-serial, online fashion. Several such units can then be interconnected for the computation of more complicated expressions in a pipelined manner. Redundancy is used to help achieve a small bounded online delay and uniform throughput

entry:
@InProceedings{Kornerup:1989:ERB,
  author =       "Peter Kornerup and David W. Matula",
  title =        "Exploiting Redundancy in Bit-Pipelined Rational
                 Arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "119--126",
  year =         "1989",
  DOI =          "https://doi.org/10.1109/ARITH.1989.72817",
  bibdate =      "Wed Nov 14 18:29:43 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Kornerup.pdf",
  abstract =     "The authors develop and analyze a redundant
                 continued-fraction representation of the rationals in
                 the implementation of an arithmetic unit for computing
                 the sum, difference, product, quotient, and other
                 useful functions of two rational operands. Their
                 representation of operands and results allows the
                 computations of the unit to be performed in a signed
                 bit-serial, online fashion. Several such units can then
                 be interconnected for the computation of more
                 complicated expressions in a pipelined manner.
                 Redundancy is used to help achieve a small bounded
                 online delay and uniform throughput",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishna:1989:NAC
author: H. Krishna and Kuo Yu Lin
booktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
title: New algorithms for correcting errors in redundant residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 653--657
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: H. Krishna and Kuo Yu Lin
rawbooktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
rawtitle: New algorithms for correcting errors in redundant residue number systems
entry:
@InProceedings{Krishna:1989:NAC,
  author =       "H. Krishna and Kuo Yu Lin",
  booktitle =    "Twenty-Third Asilomar Conference on Signals, Systems
                 and Computers, 1989",
  title =        "New algorithms for correcting errors in redundant
                 residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "653--657",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishnan:1989:CBN
author: R. Krishnan
booktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 873--877
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Krishnan
rawbooktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
title:
Conventional binary number system (BNS) versus residue number system (RNS) digital signal processing architecture suitable for complex digital filtering

rawtitle:
Conventional binary number system ({BNS}) versus residue number system ({RNS}) digital signal processing architecture suitable for complex digital filtering

entry:
@InProceedings{Krishnan:1989:CBN,
  author =       "R. Krishnan",
  booktitle =    "Twenty-Third Asilomar Conference on Signals, Systems
                 and Computers, 1989",
  title =        "Conventional binary number system ({BNS}) versus
                 residue number system ({RNS}) digital signal processing
                 architecture suitable for complex digital filtering",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "873--877",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishnan:1989:ESA
author: R. Krishnan
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2585--2588
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266996
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Krishnan
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
title:
An efficient systolic array VLSI cell architecture for the implementation of transversal filter based on the quadratic residue number systems

rawtitle:
An efficient systolic array {VLSI} cell architecture for the implementation of transversal filter based on the quadratic residue number systems

entry:
@InProceedings{Krishnan:1989:ESA,
  author =       "R. Krishnan",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "An efficient systolic array {VLSI} cell architecture
                 for the implementation of transversal filter based on
                 the quadratic residue number systems",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2585--2588",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266996",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The author presents efficient direct and indirect
                 implementations of transversal filter architectures
                 using the quadratic residue number system (QRNS). In
                 the case of the direct transversal filter, a systolic
                 array architecture has been developed \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Kulisch:1989:CGS
author: Ulrich Kulisch and Reinhard Kirchner
title: Circuitry for generating sums, especially scalar products
pages: 2585--2588
day: 12
month: sep
monthnumber: 9
year: 1989
bibdate: Mon Dec 29 16:20:01 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.29 16:20:01 ???
URL: http://www.patentstorm.us/patents/4866653/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 4866653
rawauthor: Ulrich Kulisch and Reinhard Kirchner
rawtitle: Circuitry for generating sums, especially scalar products
abstract:
Circuitry for the summation, especially for generation, of scalar products, to which one summand in floating-point representation is conveyed per machine cycle (ZT), in which, after conversion into fixed point representation, it is received in a summing unit with an accumulator (AS1,-AS4) comprising the whole exponent range. The accumulator is subdivided into row sections, which are longer than the mantissa of the summands. Partial exponents (EPK1,-EPK4) generated in an exponent analyzer (EXA) control the mantissa positioner (PM) or are allocated to the mantissas and delivered continuously and cycle-wise to transfer registers (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling summation row-wise. The carriers are allocated to the accumulator sections and intermediately stored in carry memory sections (CS1,-CS4) and are not added digit positionwise to the contents of each adjacent memory section until the sum is output, further carries being continuously processed. Afterwards the rounded result mantissa (ME) is generated in transfer registers (RA1, RA2, RPR) arranged downstream and the result exponent (EE) is generated in an exponent generator (EXG).

rawabstract:
Circuitry for the summation, especially for generation, of scalar products, to which one summand in floating-point representation is conveyed per machine cycle (ZT), in which, after conversion into fixed point representation, it is received in a summing unit with an accumulator (AS1,-AS4) comprising the whole exponent range. The accumulator is subdivided into row sections, which are longer than the mantissa of the summands. Partial exponents (EPK1,-EPK4) generated in an exponent analyzer (EXA) control the mantissa positioner (PM) or are allocated to the mantissas and delivered continuously and cycle-wise to transfer registers (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling summation row-wise. The carriers are allocated to the accumulator sections and intermediately stored in carry memory sections (CS1,-CS4) and are not added digit positionwise to the contents of each adjacent memory section until the sum is output, further carries being continuously processed. Afterwards the rounded result mantissa (ME) is generated in transfer registers (RA1, RA2, RPR) arranged downstream and the result exponent (EE) is generated in an exponent generator (EXG).

entry:
@Misc{Kulisch:1989:CGS,
  author =       "Ulrich Kulisch and Reinhard Kirchner",
  title =        "Circuitry for generating sums, especially scalar
                 products",
  howpublished = "US Patent 4866653",
  day =          "12",
  month =        sep,
  year =         "1989",
  bibdate =      "Mon Dec 29 16:20:01 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/4866653/fulltext.html",
  abstract =     "Circuitry for the summation, especially for
                 generation, of scalar products, to which one summand in
                 floating-point representation is conveyed per machine
                 cycle (ZT), in which, after conversion into fixed point
                 representation, it is received in a summing unit with
                 an accumulator (AS1,-AS4) comprising the whole exponent
                 range. The accumulator is subdivided into row sections,
                 which are longer than the mantissa of the summands.
                 Partial exponents (EPK1,-EPK4) generated in an exponent
                 analyzer (EXA) control the mantissa positioner (PM) or
                 are allocated to the mantissas and delivered
                 continuously and cycle-wise to transfer registers
                 (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling
                 summation row-wise. The carriers are allocated to the
                 accumulator sections and intermediately stored in carry
                 memory sections (CS1,-CS4) and are not added digit
                 positionwise to the contents of each adjacent memory
                 section until the sum is output, further carries being
                 continuously processed. Afterwards the rounded result
                 mantissa (ME) is generated in transfer registers (RA1,
                 RA2, RPR) arranged downstream and the result exponent
                 (EE) is generated in an exponent generator (EXG).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lai:1989:HNS
author: F. S. Lai and C. E. Wu
title: A hybrid number system multiplier for graphics and complex arithmetic applications
crossref: IEEE:1989:ISV
pages: 352--356
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: IBM Thomas J. Watson Res Center, Yorktown-Heights, NY, USA
rawauthor: F. S. Lai and C. E. Wu
rawtitle: A hybrid number system multiplier for graphics and complex arithmetic applications
abstract:
A hybrid multiplier design which supports 32-bit floating-point, 24-bit fixed-point and 32-bit logarithmic number systems is described. Except for additions and subtractions, floating-point operations such as multiplication, division, and square root are all performed in the logarithmic number system domain. A modified squaring approach is adopted for fixed-point multiplications with little extra hardware. The performance of this multiplier is shown to be superior to that of conventional binary multipliers for most graphics and digital signal processing applications, and the size of the multiplier is comparable to that of conventional multipliers in terms of silicon area.

keywords:
Complex arithmetic; Digital signal processing; Division; Fixed-point multiplications; Floating-point operations; Graphics; Hybrid number system multiplier; Logarithmic number; Modified squaring approach; Multiplication; Square root

thesaurus:
Computer graphic equipment; Computerised signal processing; Digital arithmetic; Multiplying circuits

rawabstract:
A hybrid multiplier design which supports 32-bit floating-point, 24-bit fixed-point and 32-bit logarithmic number systems is described. Except for additions and subtractions, floating-point operations such as multiplication, division, and square root are all performed in the logarithmic number system domain. A modified squaring approach is adopted for fixed-point multiplications with little extra hardware. The performance of this multiplier is shown to be superior to that of conventional binary multipliers for most graphics and digital signal processing applications, and the size of the multiplier is comparable to that of conventional multipliers in terms of silicon area.

entry:
@InProceedings{Lai:1989:HNS,
  author =       "F. S. Lai and C. E. Wu",
  title =        "A hybrid number system multiplier for graphics and
                 complex arithmetic applications",
  crossref =     "IEEE:1989:ISV",
  pages =        "352--356",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A hybrid multiplier design which supports 32-bit
                 floating-point, 24-bit fixed-point and 32-bit
                 logarithmic number systems is described. Except for
                 additions and subtractions, floating-point operations
                 such as multiplication, division, and square root are
                 all performed in the logarithmic number system domain.
                 A modified squaring approach is adopted for fixed-point
                 multiplications with little extra hardware. The
                 performance of this multiplier is shown to be superior
                 to that of conventional binary multipliers for most
                 graphics and digital signal processing applications,
                 and the size of the multiplier is comparable to that of
                 conventional multipliers in terms of silicon area.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Thomas J. Watson Res Center, Yorktown-Heights, NY,
                 USA",
  classification = "B1265B (Logic circuits); C5230 (Digital arithmetic
                 methods); C5260 (Digital signal processing); C5540
                 (Terminals and graphic displays)",
  keywords =     "Complex arithmetic; Digital signal processing;
                 Division; Fixed-point multiplications; Floating-point
                 operations; Graphics; Hybrid number system multiplier;
                 Logarithmic number; Modified squaring approach;
                 Multiplication; Square root",
  thesaurus =    "Computer graphic equipment; Computerised signal
                 processing; Digital arithmetic; Multiplying circuits",
}


bibtype: inproceedings
filename: fparith.bib
label: Langston:1989:DBT
author: J. L. Langston and K. Hinman
title: Digital beamforming techniques and processors based on quadratic residue number system techniques
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 609--614
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.103997
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. L. Langston and K. Hinman
rawtitle: Digital beamforming techniques and processors based on quadratic residue number system techniques
booktitle:
IEEE Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

rawbooktitle:
{IEEE} Military Communications Conference, 1989. {MILCOM '89}. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

entry:
@InProceedings{Langston:1989:DBT,
  author =       "J. L. Langston and K. Hinman",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "Digital beamforming techniques and processors based on
                 quadratic residue number system techniques",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "609--614",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.103997",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A very-high-performance digital beamforming processor
                 has been implemented using ASICs (application-specific
                 integrated circuits) fabricated in readily available
                 commercial CMOS process technology by using QRNS
                 (quadratic residue number system) \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Lee:1989:FIR
author: Jeong-A Lee and Tomas Lang
title: Floating-point implementation of redundant CORDIC for QR decomposition
type: Technical report
number: CSD-890044
institution: Computer Science Dept., University of California
address: Los Angeles, CA, USA
pages: 15 + 8
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Decomposition method.; Matrices.
remark: ``July 1989.'' Supported by the National Science Foundation.
acknowledgement: ack-nhfb
rawauthor: Jeong-A Lee and Tomas Lang
rawtitle: Floating-point implementation of redundant {CORDIC} for {QR} decomposition
entry:
@TechReport{Lee:1989:FIR,
  author =       "Jeong-A Lee and Tomas Lang",
  title =        "Floating-point implementation of redundant {CORDIC}
                 for {QR} decomposition",
  type =         "Technical report",
  number =       "CSD-890044",
  institution =  "Computer Science Dept., University of California",
  address =      "Los Angeles, CA, USA",
  pages =        "15 + 8",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Decomposition method.; Matrices.",
  remark =       "``July 1989.'' Supported by the National Science
                 Foundation.",
}


bibtype: article
filename: fparith.bib
label: Lee:1989:MGR
author: Corinna Lee
title: Multistep Gradual Rounding
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 4
pages: 595--600
month: apr
monthnumber: 4
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.21152
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:39 MDT 2011
bibtimestamp: 2011.07.08 19:00:39 MDT
fjournal: IEEE Transactions on Computers
keywords: double rounding
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Corinna Lee
rawtitle: Multistep Gradual Rounding
URL:
http://dlib.computer.org/tc/books/tc1989/pdf/t0593.pdf; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21152; http://www.computer.org/tc/tc1989/t0595abs.htm

abstract:
A value $V$ is to be rounded to an arbitrary precision resulting in the value $ V' $. Conventional rounding technique uses one step to accomplish this. Alternatively, em multistep rounding uses several steps to round the value $V$ to successively shorter precisions with the final rounding step producing the desired value $ V' $. This alternate rounding method is one way to implement, with the minimum of hardware, the denormalization process that the IEEE Floating-Point Standard 754 requires when underflow occurs. There are certain cases for which multistep rounding produces a different result than single-step rounding. To prevent such a em step error, the author introduces a rounding procedure called em gradual rounding that is very similar to conventional rounding with the addition of two tag bits associated with each floating-point register.

rawabstract:
A value $V$ is to be rounded to an arbitrary precision resulting in the value $ V' $. Conventional rounding technique uses one step to accomplish this. Alternatively, {\em multistep rounding\/} uses several steps to round the value $V$ to successively shorter precisions with the final rounding step producing the desired value $ V' $. This alternate rounding method is one way to implement, with the minimum of hardware, the denormalization process that the IEEE Floating-Point Standard 754 requires when underflow occurs. There are certain cases for which multistep rounding produces a different result than single-step rounding. To prevent such a {\em step error}, the author introduces a rounding procedure called {\em gradual rounding} that is very similar to conventional rounding with the addition of two tag bits associated with each floating-point register.

entry:
@Article{Lee:1989:MGR,
  author =       "Corinna Lee",
  title =        "Multistep Gradual Rounding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "4",
  pages =        "595--600",
  month =        apr,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.21152",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://dlib.computer.org/tc/books/tc1989/pdf/t0593.pdf;
                 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21152;
                 http://www.computer.org/tc/tc1989/t0595abs.htm",
  abstract =     "A value $V$ is to be rounded to an arbitrary precision
                 resulting in the value $ V' $. Conventional rounding
                 technique uses one step to accomplish this.
                 Alternatively, {\em multistep rounding\/} uses several
                 steps to round the value $V$ to successively shorter
                 precisions with the final rounding step producing the
                 desired value $ V' $. This alternate rounding method is
                 one way to implement, with the minimum of hardware, the
                 denormalization process that the IEEE Floating-Point
                 Standard 754 requires when underflow occurs. There are
                 certain cases for which multistep rounding produces a
                 different result than single-step rounding. To prevent
                 such a {\em step error}, the author introduces a
                 rounding procedure called {\em gradual rounding} that
                 is very similar to conventional rounding with the
                 addition of two tag bits associated with each
                 floating-point register.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "double rounding",
}


bibtype: article
filename: fparith.bib
label: Lee:1989:QCC
author: Jon Lee
title: A quirk of the CRAY CFT77 compiler: IF (logical) in lieu of IF (arithmetic)
journal: j-J-SUPERCOMPUTING
volume: 3
number: 4
pages: 351--355
month: dec
monthnumber: 12
year: 1989
CODEN: JOSUED
DOI: https://doi.org/10.1007/BF00128170
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Wed Jul 6 11:13:01 MDT 2005
bibtimestamp: 2005.07.06 11:13:01 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0920-8542&volume=3&issue=4&spage=351
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
affiliation: Flight Dynamics Lab., Wright-Patterson AFB, OH, USA
corpsource: Flight Dynamics Lab., Wright-Patterson AFB, OH, USA
journalURL: http://link.springer.com/journal/11227
treatment: X Experimental
rawauthor: Jon Lee
rawtitle: A quirk of the {CRAY CFT77} compiler: {IF} (logical) in lieu of {IF} (arithmetic)
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=3&issue=4; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
CFT77 compiler; CIVIC; computational fluid dynamics code; conditional IF exit; DO-loops; homogeneous turbulence; optimised code; parallel programming; program compilers; vectorization

entry:
@Article{Lee:1989:QCC,
  author =       "Jon Lee",
  title =        "A quirk of the {CRAY CFT77} compiler: {IF} (logical)
                 in lieu of {IF} (arithmetic)",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "3",
  number =       "4",
  pages =        "351--355",
  month =        dec,
  year =         "1989",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/BF00128170",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Wed Jul 6 11:13:01 MDT 2005",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=3&issue=4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0920-8542&volume=3&issue=4&spage=351",
  acknowledgement = ack-nhfb,
  affiliation =  "Flight Dynamics Lab., Wright-Patterson AFB, OH, USA",
  classification = "C5440 (Multiprocessor systems and techniques); C6110
                 (Systems analysis and programming); C6150C (Compilers,
                 interpreters and other processors); C7440 (Civil and
                 mechanical engineering)",
  corpsource =   "Flight Dynamics Lab., Wright-Patterson AFB, OH, USA",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
  keywords =     "CFT77 compiler; CIVIC; computational fluid dynamics
                 code; conditional IF exit; DO-loops; homogeneous
                 turbulence; optimised code; parallel programming;
                 program compilers; vectorization",
  treatment =    "X Experimental",
}


bibtype: book
filename: fparith.bib
label: Levy:1989:CPA
author: Henry M. Levy and Richard H. Eckhouse, Jr.
title: Computer programming and architecture: the VAX
publisher: pub-DP
address: pub-DP:adr
edition: Second
pages: xix + 444
year: 1989
ISBN: 1-55558-015-7 OR 1555580157
ISBN13: 978-1-55558-015-5 OR 9781555580155
LCCN: QA76.8.V32 L48 1989
bibdate: Wed Sep 14 22:51:31 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 22:51:31 ???
acknowledgement: ack-nhfb
rawauthor: Henry M. Levy and Richard H. {Eckhouse, Jr.}
rawtitle: Computer programming and architecture: the {VAX}
entry:
@Book{Levy:1989:CPA,
  author =       "Henry M. Levy and Richard H. {Eckhouse, Jr.}",
  title =        "Computer programming and architecture: the {VAX}",
  publisher =    pub-DP,
  address =      pub-DP:adr,
  edition =      "Second",
  pages =        "xix + 444",
  year =         "1989",
  ISBN =         "1-55558-015-7",
  ISBN-13 =      "978-1-55558-015-5",
  LCCN =         "QA76.8.V32 L48 1989",
  bibdate =      "Wed Sep 14 22:51:31 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lewis:1989:ADB
author: D. M. Lewis and L. K. Yu
title: Algorithm design for a 30-bit integrated logarithmic processor
crossref: Ercegovac:1989:PSC
pages: 192--199
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lewis.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: D. M. Lewis and L. K. Yu
rawtitle: Algorithm design for a 30-bit integrated logarithmic processor
entry:
@InProceedings{Lewis:1989:ADB,
  author =       "D. M. Lewis and L. K. Yu",
  title =        "Algorithm design for a 30-bit integrated logarithmic
                 processor",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "192--199",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lewis.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Lin:1989:LCA
author: H. Lin and H. J. Sips
title: On-line CORDIC algorithms
crossref: Ercegovac:1989:PSC
pages: 26--33
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lin.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: H. Lin and H. J. Sips
rawtitle: On-line {CORDIC} algorithms
entry:
@InProceedings{Lin:1989:LCA,
  author =       "H. Lin and H. J. Sips",
  title =        "On-line {CORDIC} algorithms",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "26--33",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lin.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Lo:1989:CED
author: J.-C. Lo and S. Thanawastien and T. R. N. Rao
title: Concurrent error detection in arithmetic and logical operations using Berger codes
crossref: Ercegovac:1989:PSC
pages: 233--240
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lo.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: J.-C. Lo and S. Thanawastien and T. R. N. Rao
rawtitle: Concurrent error detection in arithmetic and logical operations using {Berger} codes
entry:
@InProceedings{Lo:1989:CED,
  author =       "J.-C. Lo and S. Thanawastien and T. R. N. Rao",
  title =        "Concurrent error detection in arithmetic and logical
                 operations using {Berger} codes",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "233--240",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lo.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Lu:1989:VMI
author: P. Y. Lu and K. Dawallu
title: A VLSI Module for IEEE Floating-Point Multiplication / Division / Square Root
crossref: IEEE:1989:PII
pages: 366--368
year: 1989
bibdate: Wed Nov 06 12:08:38 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.06 12:08:38 ???
acknowledgement: ack-nhfb
affiliation: LSI Logic Corp., Menlo Park, CA, USA
bookpages: xvii + 587
rawauthor: P. Y. Lu and K. Dawallu
rawtitle: A {VLSI} Module for {IEEE} Floating-Point Multiplication\slash Division\slash Square Root
abstract:
The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0- mu m CMOS standard cell technology, the total area of this module is approximately 7.0 mm*6.5 mm, which is just 25% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns. (2 Refs.)

keywords:
1 Micron; 20 Ns; 7 To 6.5 mm; CMOS standard cell technology; Cycle time; Fast floating-point multiplier; Floating point division; Floating point square root; IEEE standards; Iterated result; Mantissa; Multiplier modification; Newton-Ralphson iteration; Rounding algorithm; VLSI module design

thesaurus:
Cellular arrays; CMOS integrated circuits; Digital arithmetic; Dividing circuits; Iterative methods; Modules; Multiplying circuits; VLSI

rawabstract:
The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0- mu m CMOS standard cell technology, the total area of this module is approximately 7.0 mm*6.5 mm, which is just 25\% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns. (2 Refs.)

entry:
@InProceedings{Lu:1989:VMI,
  author =       "P. Y. Lu and K. Dawallu",
  title =        "A {VLSI} Module for {IEEE} Floating-Point
                 Multiplication\slash Division\slash Square Root",
  crossref =     "IEEE:1989:PII",
  bookpages =    "xvii + 587",
  pages =        "366--368",
  year =         "1989",
  bibdate =      "Wed Nov 06 12:08:38 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The major objective of this VLSI module design is to
                 determine how to modify a fast floating-point
                 multiplier so that it can perform division and square
                 root in accordance with IEEE standards. This has been
                 achieved by applying the Newton-Ralphson iteration only
                 on the mantissa and adjusting the iterated result by a
                 rounding algorithm. Using 1.0- mu m CMOS standard cell
                 technology, the total area of this module is
                 approximately 7.0 mm*6.5 mm, which is just 25\% larger
                 than the floating-point multiplier. The module can
                 compute multiplication, division, and square root in 3,
                 31, and 43 cycles, respectively. The cycle time, under
                 nominal conditions, is expected to be 20 ns. (2
                 Refs.)",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "LSI Logic Corp., Menlo Park, CA, USA",
  classification = "B1265B (Logic circuits); B2570D (CMOS integrated
                 circuits); C4130 (Interpolation and function
                 approximation); C5230 (Digital arithmetic methods)",
  keywords =     "1 Micron; 20 Ns; 7 To 6.5 mm; CMOS standard cell
                 technology; Cycle time; Fast floating-point multiplier;
                 Floating point division; Floating point square root;
                 IEEE standards; Iterated result; Mantissa; Multiplier
                 modification; Newton-Ralphson iteration; Rounding
                 algorithm; VLSI module design",
  numericalindex = "Time 2.0E-08 s; Size 1.0E-06 m; Size 6.5E-03 to
                 7.0E-03 m",
  thesaurus =    "Cellular arrays; CMOS integrated circuits; Digital
                 arithmetic; Dividing circuits; Iterative methods;
                 Modules; Multiplying circuits; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Malarkey:1989:RNS
title: Residue-number-system-based optical adaptive processor
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 620--623
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.103999
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawtitle: Residue-number-system-based optical adaptive processor
author:
E. C. Malarkey and G. E. Marx and J. D. Fogarty and D. Mergerian and H. K. Hahn and J. C. Bradley and P. R. Beaudet and R. Fenton

booktitle:
IEEE Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

rawauthor:
E. C. Malarkey and G. E. Marx and J. D. Fogarty and D. Mergerian and H. K. Hahn and J. C. Bradley and P. R. Beaudet and R. Fenton

rawbooktitle:
{IEEE} Military Communications Conference, 1989. {MILCOM '89}. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

entry:
@InProceedings{Malarkey:1989:RNS,
  author =       "E. C. Malarkey and G. E. Marx and J. D. Fogarty and D.
                 Mergerian and H. K. Hahn and J. C. Bradley and P. R.
                 Beaudet and R. Fenton",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "Residue-number-system-based optical adaptive
                 processor",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "620--623",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.103999",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "An optical adaptive processor with 4 degrees of
                 freedom is under development. This processor is based
                 upon the use of optical lookup tables and operates
                 within the residue number system to provide adaptive
                 tap weights for nulling applications. The \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Mansour:1989:CAS
author: Y. Mansour and B. Schieber and P. Tiwari
booktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
title: The complexity of approximating the square root
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 325--330
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: Y. Mansour and B. Schieber and P. Tiwari
rawbooktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
rawtitle: The complexity of approximating the square root
entry:
@InProceedings{Mansour:1989:CAS,
  author =       "Y. Mansour and B. Schieber and P. Tiwari",
  booktitle =    "30th Annual Symposium on Foundations of Computer
                 Science, 1989",
  title =        "The complexity of approximating the square root",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "325--330",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors prove upper and lower bounds for
                 approximately computing the square root using a given
                 set of operations. The bounds are extended to hold for
                 approximating the kth root, for any fixed k. Several
                 tools from approximation \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Marshall:1989:TUT
author: Mark Marshall
title: Techniques for user testing of the 68882
journal: j-MICROPROC-MICROSYS
volume: 13
number: 6
pages: 382--386
month: jul
monthnumber: 7
year: 1989
CODEN: MIMID5
ISSN: 0141-9331 (print), 1872-9436 (electronic) OR 01419331 (print), 18729436 (electronic)
ISSNL: 0141-9331 OR 01419331
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Microprocessors and Microsystems
keywords: floating-point testing
acknowledgement: ack-nhfb
affiliation: NCR Corp., Wichita, KS
reviewer: E. Mallach
rawauthor: Mark Marshall
rawtitle: Techniques for user testing of the 68882
subject:
B. Hardware; B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

entry:
@Article{Marshall:1989:TUT,
  author =       "Mark Marshall",
  title =        "Techniques for user testing of the 68882",
  journal =      j-MICROPROC-MICROSYS,
  volume =       "13",
  number =       "6",
  pages =        "382--386",
  month =        jul # "\slash " # aug,
  year =         "1989",
  CODEN =        "MIMID5",
  ISSN =         "0141-9331 (print), 1872-9436 (electronic)",
  ISSN-L =       "0141-9331",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "NCR Corp., Wichita, KS",
  bibno =        "72545",
  catcode =      "B.5.3; C.5.3; B.5.1",
  content =      "This short, clearly written paper describes how NCR
                 Corporation developed a series of programs to test the
                 Motorola 68882 floating-point coprocessor for
                 Motorola's 68020 and 68030 microprocessors. Integrated
                 circuits are tested for two reasons: to ensure that a
                 properly working unit meets its specifications, and to
                 ensure that a particular unit works properly. As
                 Marshall points out, manufacturers cannot always be
                 relied upon to perform either of these tests perfectly.
                 The programs described in this paper have been used
                 both to monitor the quality of incoming parts and to
                 verify that device mask or specification changes do not
                 effect the part's usability for NCR's
                 purposes.\par

                 This paper describes the methods by which NCR's
                 2700-instruction, 550,000-clock cycle test program was
                 developed and how it works. Since the internal workings
                 of the 68882 are not visible to the user, NCR adopted
                 the functional testing approach. Of particular interest
                 is NCR's sequential approach to the testing proper,
                 which assumes that ``no element is functional unless
                 previously tested.'' While the specifics of each step
                 vary from one microprocessor to another, the principles
                 still apply.\par

                 This is not a research paper. It does not disclose
                 startling new results or advance the frontiers of human
                 knowledge. It does show how state-of-the-art
                 engineering practice can achieve desirable \ldots{}",
  CRclass =      "B.5.3 Reliability and Testing; B.5.3 Test generation;
                 C.5.3 Microcomputers; B.5.1 Design",
  CRnumber =     "9006-0473",
  descriptor =   "Hardware, REGISTER-TRANSFER-LEVEL IMPLEMENTATION,
                 Reliability and Testing, Test generation; Computer
                 Systems Organization, COMPUTER SYSTEM IMPLEMENTATION,
                 Microcomputers; Hardware, REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION, Design",
  fjournal =     "Microprocessors and Microsystems",
  genterm =      "ALGORITHMS; DESIGN; VERIFICATION",
  guideno =      "1989-09211",
  journalabbrev = "Microprocess. Microsyst.",
  keywords =     "floating-point testing",
  reviewer =     "E. Mallach",
  subject =      "B. Hardware; B.5 REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.5
                 REGISTER-TRANSFER-LEVEL IMPLEMENTATION",
}


bibtype: article
filename: fparith.bib
label: Mastrovito:1989:VDM
author: E. D. Mastrovito
title: VLSI designs for multiplication over finite fields $ mathrm GF(2^m) $
journal: j-LECT-NOTES-COMP-SCI
volume: 357
pages: 397--309
year: 1989
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Jun 24 21:09:00 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 21:09:00 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: E. D. Mastrovito
rawtitle: {VLSI} designs for multiplication over finite fields {$ \mathrm {GF}(2^m) $}
entry:
@Article{Mastrovito:1989:VDM,
  author =       "E. D. Mastrovito",
  title =        "{VLSI} designs for multiplication over finite fields
                 {$ \mathrm {GF}(2^m) $}",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "357",
  pages =        "397--309",
  year =         "1989",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Fri Jun 24 21:09:00 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Maytal:1989:DCG
author: B. Maytal and S. Iacobovici and D. B. Alpert and D. Biran and J. Levy and S. Y. Tov
title: Design considerations for a general-purpose microprocessor
journal: j-COMPUTER
volume: 22
number: 1
pages: 66--76
month: jan
monthnumber: 1
year: 1989
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Sat Sep 14 07:29:35 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Misc/IMMD_IV.bib
bibtimestamp: 1996.09.14 07:29:35 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Nat. Semicond., Santa Clara, CA, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
thesaurus: Computer architecture; Microcomputers; Microprocessor chips
rawauthor: B. Maytal and S. Iacobovici and D. B. Alpert and D. Biran and J. Levy and S. Y. Tov
rawtitle: Design considerations for a general-purpose microprocessor
keywords:
32 Bit; Clock frequency; Data-flow monitoring mechanisms; Floating-point operations; General-purpose microprocessor; Instruction-flow; Market requirements; Memory hierarchy; Memory reference transactions; Microarchitecture; Multiprocessing support; NS 32532; On-chip caches; Packaging technologies; Pipeline; System interface; Target applications; VLSI

entry:
@Article{Maytal:1989:DCG,
  author =       "B. Maytal and S. Iacobovici and D. B. Alpert and D.
                 Biran and J. Levy and S. Y. Tov",
  title =        "Design considerations for a general-purpose
                 microprocessor",
  journal =      j-COMPUTER,
  volume =       "22",
  number =       "1",
  pages =        "66--76",
  month =        jan,
  year =         "1989",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Sep 14 07:29:35 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Misc/IMMD_IV.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Nat. Semicond., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "32 Bit; Clock frequency; Data-flow monitoring
                 mechanisms; Floating-point operations; General-purpose
                 microprocessor; Instruction-flow; Market requirements;
                 Memory hierarchy; Memory reference transactions;
                 Microarchitecture; Multiprocessing support; NS 32532;
                 On-chip caches; Packaging technologies; Pipeline;
                 System interface; Target applications; VLSI",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Computer architecture; Microcomputers; Microprocessor
                 chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Milenkovic:1989:DPG
author: V. Milenkovic
booktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 500--505
year: 1989
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
acknowledgement: ack-nhfb
rawauthor: V. Milenkovic
rawbooktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
title:
Double precision geometry: a general technique for calculating line and segment intersections using rounded arithmetic

rawtitle:
Double precision geometry: a general technique for calculating line and segment intersections using rounded arithmetic

entry:
@InProceedings{Milenkovic:1989:DPG,
  author =       "V. Milenkovic",
  booktitle =    "30th Annual Symposium on Foundations of Computer
                 Science, 1989",
  title =        "Double precision geometry: a general technique for
                 calculating line and segment intersections using
                 rounded arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "500--505",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "For the first time it is shown how to reduce the cost
                 of performing specific geometric constructions by using
                 rounded arithmetic instead of exact arithmetic. By
                 exploiting a property of floating-point arithmetic
                 called monotonicity, a technique \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Milutinovic:1989:MSD
author: V. Milutinovic and M. Bettinger and W. Helbig
title: Multiplier / shifter design tradeoffs in a 32-bit microprocessor
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 6
pages: 874--880
month: jun
monthnumber: 6
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.24298
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:40 MDT 2011
bibtimestamp: 2011.07.08 19:00:40 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24298
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: V. Milutinovic and M. Bettinger and W. Helbig
rawtitle: Multiplier\slash shifter design tradeoffs in a 32-bit microprocessor
entry:
@Article{Milutinovic:1989:MSD,
  author =       "V. Milutinovic and M. Bettinger and W. Helbig",
  title =        "Multiplier\slash shifter design tradeoffs in a 32-bit
                 microprocessor",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "6",
  pages =        "874--880",
  month =        jun,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.24298",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24298",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Molnar:1989:MBF
author: K. Molnar and C.-Y. Ho and D. Staver and B. Davis and R. Jerdonek
title: A 40 MHz 64-Bit Floating-Point Co-Processor
crossref: Wuorinen:1989:DTP
pages: 48--49, 287
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Gen. Electr. Corp. Res. and Dev. Center, Schenectady, NY, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips
rawauthor: K. Molnar and C.-Y. Ho and D. Staver and B. Davis and R. Jerdonek
rawtitle: A 40 {MHz} 64-Bit Floating-Point Co-Processor
abstract:
An arithmetic coprocessor capable of executing 64-bit double-precision floating-point, 32-bit single-precision floating-point, and 32-bit integer instructions has been integrated onto a 1.0-cm*1.1-cm chip in a 1.2- mu m, single-poly, double-metal bulk CMOS process. The chip contains 17000 transistors and includes a register file, two accumulators, and separate interface, multiplication, and addition subprocessors. The coprocessor which is the arithmetic unit for a multichip microprocessor system, is packaged in a 132-pin leadless ceramic chip carrier. The coprocessor can be issued a new instruction each 25-ns clock cycle, and 64-bit double-precision arithmetic with full IEEE rounding is executed at a peak rate of 26.7 MFLOPs (million floating-point operations per second). The waveforms of a store instruction operating at 40 MHz are shown.

keywords:
1.2 Micron; 26.7 MFLOPS; 32-Bit integer instructions; 40 MHz; 64 Bit; Accumulators; Addition subprocessors; Arithmetic coprocessor; Double-metal bulk CMOS process; Double-precision floating-point; Floating point coprocessor; Interface subprocessor; Leadless ceramic chip carrier; Multichip microprocessor system; Multiplication subprocessor; Peak rate; Register file; Single-precision floating-point; Store instruction; Waveforms

rawabstract:
An arithmetic coprocessor capable of executing 64-bit double-precision floating-point, 32-bit single-precision floating-point, and 32-bit integer instructions has been integrated onto a 1.0-cm*1.1-cm chip in a 1.2- mu m, single-poly, double-metal bulk CMOS process. The chip contains 17000 transistors and includes a register file, two accumulators, and separate interface, multiplication, and addition subprocessors. The coprocessor which is the arithmetic unit for a multichip microprocessor system, is packaged in a 132-pin leadless ceramic chip carrier. The coprocessor can be issued a new instruction each 25-ns clock cycle, and 64-bit double-precision arithmetic with full IEEE rounding is executed at a peak rate of 26.7 MFLOPs (million floating-point operations per second). The waveforms of a store instruction operating at 40 MHz are shown.

entry:
@InProceedings{Molnar:1989:MBF,
  author =       "K. Molnar and C.-Y. Ho and D. Staver and B. Davis and
                 R. Jerdonek",
  title =        "A 40 {MHz} 64-Bit Floating-Point Co-Processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "48--49, 287",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An arithmetic coprocessor capable of executing 64-bit
                 double-precision floating-point, 32-bit
                 single-precision floating-point, and 32-bit integer
                 instructions has been integrated onto a 1.0-cm*1.1-cm
                 chip in a 1.2- mu m, single-poly, double-metal bulk
                 CMOS process. The chip contains 17000 transistors and
                 includes a register file, two accumulators, and
                 separate interface, multiplication, and addition
                 subprocessors. The coprocessor which is the arithmetic
                 unit for a multichip microprocessor system, is packaged
                 in a 132-pin leadless ceramic chip carrier. The
                 coprocessor can be issued a new instruction each 25-ns
                 clock cycle, and 64-bit double-precision arithmetic
                 with full IEEE rounding is executed at a peak rate of
                 26.7 MFLOPs (million floating-point operations per
                 second). The waveforms of a store instruction operating
                 at 40 MHz are shown.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Gen. Electr. Corp. Res. and Dev. Center, Schenectady,
                 NY, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  keywords =     "1.2 Micron; 26.7 MFLOPS; 32-Bit integer instructions;
                 40 MHz; 64 Bit; Accumulators; Addition subprocessors;
                 Arithmetic coprocessor; Double-metal bulk CMOS process;
                 Double-precision floating-point; Floating point
                 coprocessor; Interface subprocessor; Leadless ceramic
                 chip carrier; Multichip microprocessor system;
                 Multiplication subprocessor; Peak rate; Register file;
                 Single-precision floating-point; Store instruction;
                 Waveforms",
  numericalindex = "Frequency 4.0E+07 Hz; Word length 6.4E+01 bit; Size
                 1.2E-06 m; Computer speed 2.67E+07 FLOPS",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Montuschi:1989:EIH
author: Paolo Montuschi and Luigi Cinimera
title: On the efficient implementation of higher radix square root algorithms
crossref: Ercegovac:1989:PSC
pages: 154--161
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Montuschi.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Paolo Montuschi and Luigi Cinimera
rawtitle: On the efficient implementation of higher radix square root algorithms
entry:
@InProceedings{Montuschi:1989:EIH,
  author =       "Paolo Montuschi and Luigi Cinimera",
  title =        "On the efficient implementation of higher radix square
                 root algorithms",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "154--161",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Montuschi.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "Square root nonrestoring algorithms operating with a
                 radix higher than two (but power of 2) are discussed.
                 Formulas are derived delimiting the feasibility space
                 of the class of algorithms considered as a function of
                 the different parameters. This \ldots{}",
}


bibtype: book
filename: fparith.bib
label: Moshier:1989:MPM
author: Stephen L. B. Moshier
title: Methods and Programs for Mathematical Functions
publisher: pub-ELLIS-HORWOOD
address: pub-ELLIS-HORWOOD:adr
pages: vii + 415
year: 1989
ISBN: 0-7458-0289-3 OR 0745802893
ISBN13: 978-0-7458-0289-3 OR 9780745802893
LCCN: QA331 .M84 1989
MRclass: *65D20, 26-04, 33-04, 65-02, 65C99
bibdate: Thu Sep 01 10:33:40 1994
bibtimestamp: 1994.09.01 10:33:40 ???
URL: http://www.moshier.net/; http://www.netlib.org/cephes
ZMnumber: 0701.65011
acknowledgement: ack-nj
rawauthor: Stephen L. B. Moshier
rawtitle: Methods and Programs for Mathematical Functions
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib

TOC:
Preface / vii 1: Floating Point Arithmetic / 1 1.1 Numeric Data Structures / 1 1.2 Rounding / 5 1.3 Addition and Subtraction / 6 1.4 Multiplication / 7 1.4.1 Long Multiplication in Binary Radix / 8 1.4.2 Multiplication in Word Integer Radix / 8 1.4.3 Fast Multiplication / 9 1.5 Division / 10 1.5.1 Long Division / 10 1.5.2 Division by Taylor Series / 11 1.5.3 Newton--Raphson Division / 11 1.6 C Language / 12 1.7 An Extended Double Arithmetic: ieee.c / 13 1.8 Binary - Decimal Conversion / 46 1.8.1 etoasc.c / 47 1.8.2 asctoe.c / 54 1.9 Analysis of Error / 58 1.9.1 Roundoff and Cancellation / 58 1.9.2 Error Propagation / 60 1.9.3 Error as a Random Variable / 61 1.9.4 Order of Summation / 62 1.10 Complex Arithmetic / 62 1.10.1 cmplx.c / 64 1.10.2 Absolute Value: cabs.c / 67 1.11 Rational Arithmetic / 69 1.11.1 euclid.c / 70 2: Approximation Methods / 75 2.1 Power Series / 75 2.2 Chebyshev Expansions / 76 2.2.1 chbevl.c / 79 2.3 Pade Approximations / 80 2.4 Least Maximum Approximations / 82 2.4.1 Best Polynomial Approximations / 82 2.4.2 Best Rational Approximations / 85 2.4.3 Special Rational Forms / 87 2.5 A Program to Find Best Approximations: remes.c / 88 2.6 Forms of Approximation / 111 2.7 Asymptotic Expansions / 113 2.8 Continued Fractions / 114 2.8.1 Continued Fractions from Recurrences / 115 2.8.2 Recurrences from Differential Equations / 116 2.8.3 Computing Continued Fractions / 117 2.9 Polynomials / 117 2.9.1 polevl.c / 118 2.10 Newton--Raphson Iterations / 119 2.10.1 Division / 120 2.10.2 Exponent Separation / 121 2.10.3 Square Root / 122 2.10.4 sqrt.c / 123 2.10.5 Longhand Square Root / 124 2.10.6 esqrt.c / 124 2.10.7 Cube Root / 126 2.10.8 cbrt.c / 127 3: Software Notes / 129 3.1 Design Strategy / 129 3.2 Testing / 131 3.3 System Utilities / 132 3.3.1 mconf.h / 132 3.3.2 mtherr.c / 134 3.3.3 const.c / 136 3.4 Arithmetic Utilities / 137 3.4.1 efloor.c / 138 3.4.2 efrexp.c / 140 3.4.3 eldexp.c / 140 4: Elementary Functions / 143 4.1 $e^x$ / 143 4.1.1 exp.c / 145 4.2 $ln x$ / 147 4.2.1 log.c / 149 4.3 Argument Transformation for Circular Functions / 152 4.4 Sine and cosine / 153 4.4.1 sin.c / 154 4.4.2 cos.c / 156 4.5 Tangent and Cotangent / 157 4.5.1 tan.c / 158 4.6 Complex Circular Functions / 161 4.7 $sin ^-1 x $ / 162 4.7.1 asin.c / 163 4.8 $cos ^-1 x $ / 165 4.8.1 acos.c / 165 4.9 $tan ^-1 x$ / 166 4.9.1 atan.c / 168 4.9.2 atan2.c / 169 4.10 Complex Inverse Circular Functions / 170 4.11 $sinh x$ / 170 4.11.1 sinh.c / 171 4.12 $cosh x$ / 172 4.12.1 cosh.c / 173 4.13 $tanh x$ / 173 4.13.1 tanh.c / 174 4.14 $sinh ^-1 x $ / 175 4.14.1 asinh.c / 176 4.15 $cosh ^-1 x $ / 177 4.15.1 acosh.c / 178 4.16 $tanh ^-1 x$ / 179 4.16.1 atanh.c / 180 4.17 Power Function / 181 4.17.1 Real Exponent / 182 4.17.2 pow.c / 182 4.17.3 Integer Exponent / 189 4.17.4 powi.c / 190 4.18 Testing / 192 4.19 Single Precision Polynomial Approximations / 193 4.19.1 $cos x$ / 193 4.19.2 $cosh ^-1 x $ / 193 4.19.3 $exp x$ / 196 4.19.4 $ln x$ / 196 4.19.5 $sin x$ / 197 4.19.6 $sin ^-1 x $ / 197 4.19.7 Square Root / 197 4.19.8 $tan x$ / 198 4.19.9 $tan ^-1 x$ / 198 4.19.10 $tanh x$ / 199 4.19.11 $tanh^-1 x$ / 199 5: Probability Distributions and Related Functions / 201 5.1 $n!$ / 202 5.1.1 fac.c / 204 5.2 $Gamma (x)$ / 206 5.2.1 gamma.c / 210 5.2.2 lgam.c / 214 5.3 Incomplete Gamma Integral / 217 5.3.1 igamc.c / 218 5.3.2 igam.c / 220 5.3.3 Functional Inverse of Incomplete Gamma Integral / 221 5.3.4 igami.c / 221 5.4 Gamma Distribution / 222 5.4.1 gdtr c / 222 5.4.2 gdtrc.c / 223 5.5 $chi ^2$ Distribution / 223 5.5.1 chdtrc.c / 224 5.5.2 chdtr.c / 224 5.5.3 chdtrl.c / 224 5.6 Poisson Distribution / 225 5.6.1 pdtrc.c / 225 5.6.2 pdtr.c / 226 5.6.3 pdtri.c / 226 5.7 Beta Function / 227 5.7.1 beta.c / 227 5.8 Incomplete Beta Integral / 229 5.8.1 ibet.c / 231 5.8.2 Functional Inverse of Incomplete Beta Integral / 238 5.9 Beta Distribution / 241 5.9.1 btdtr.c / 241 5.10 Binomial Distribution / 241 5.10.1 bdtrc.c / 242 5.10.2 bdtr.c / 243 5.10.3 bdtri.c / 244 5.11 Negative Binomial Distribution / 244 5.11.1 nbdtr.c / 245 5.11.2 nbdtrc.c / 245 5.12 F Distribution / 246 5.12.1 fdtrc.c / 247 5.12.2 fdtr.c / 247 5.12.3 fdtrci.c / 248 5.13 Student's $t$ distribution / 249 5.13.1 stdtr.c / 250 5.14 Gaussian Distribution / 252 5.14.1 ndtr.c / 254 5.14.2 erfc.c / 256 5.14.3 erf.c / 257 5.14.4 Functional Inverse of Gaussian Distribution / 258 5.14.5 ndtri.c / 259 6: Bessel Functions / 263 6.1 $J_0(x)$ / 263 6.1.1 jO.c / 265 6.2 $Y_0(x)$ / 268 6.2.1 yO.c / 269 6.3 Modulus and Phase / 270 6.4 $J_1(x)$ / 271 6.4.1 jl.c / 272 6.5 $Y_1(x)$ / 275 6.5.1 yl.c / 275 6.6 $J_n(x)$ / 276 6.1 $I_0(x)$ / 277 6.7.1 i0.c / 278 6.8 $I_1(x)$ / 281 6.8.1 i1.c / 283 6.9 $I_nu (x)$ / 285 6.9.1 iv.c / 286 6.10 $K_0(x)$ / 287 6.10.1 kO.c / 287 6.11 $K_1(x)$ / 291 6.11.1 kl.c / 291 6.12 $K_n(x)$ / 294 6.12.1 kn.c / 295 6.13 $J_nu (x)$ / 299 6.13.1 jv.c / 301 6.14 Airy Functions / 315 6.14.1 airy.c / 322 6.15 $Y_n(x)$ / 328 6.15.1 yn.c / 329 6.16 Testing / 330 7: Other Special Functions / 333 7.1 Hypergeometric Functions / 333 7.1.1 $_2F_1$ / 334 7.1.2 hyp2fi.c / 335 7.1.3 $_1F_1$ / 341 7.1.4 hyplfi.c / 342 7.1.5 $_2F_0$ / 346 7.1.6 hyp2ffi.c / 346 7.2 Struve Functions / 348 7.2.1 hypl1f2.c / 348 7.2.2 hyp3f0.c / 349 7.2.3 yv.c / 351 7.2.4 struve.c / 351 7.3 $psi (x)$ / 352 7.3.1 psi.c / 354 7.4 Exponential Integral / 355 7.4.1 en.c / 356 7.5 Sine and Cosine Integrals / 360 7.5.1 sici.c / 362 7.5.2 Hyperbolic Sine and Cosine Integrals / 367 7.5.3 shichi.c / 370 7.6 Dilogarithm / 374 7.6.1 spence.c / 375 7.7 Dawson's Integral / 377 7.7.1 dawsn.c / 378 7.8 Fresnel Integrals / 381 7.8.1 fresnl.c / 383 7.9 Elliptic Functions / 387 7.9.1 $K(m)$ / 387 7.9.2 ellpk.c / 388 7.9.3 $F(phi |m)$ / 389 7.9.4 ellik.c / 390 7.9.5 $E(m)$ / 392 7.9.6 ellpe.c / 392 7.9.7 $E(phi |m)$ / 393 7.9.8 ellie.c / 394 7.9.9 Jacobian Elliptic Functions / 396 7.9.10 ellpj.c / 398 7.10 Zeta Functions / 400 7.10.1 hurwiz.c / 400 7.10.2 Riemann Zeta Function / 402 7.10.3 zetac.c / 405 Bibliography / 411 Index / 413

shortTOC:
Preface / vii 1: Floating Point Arithmetic / 1 2: Approximation Methods / 75 3: Software Notes / 129 4: Elementary Functions / 143 5: Probability Distributions and Related Functions / 201 6: Bessel Functions / 263 7: Other Special Functions / 333 Bibliography / 411 Index / 413

rawshortTOC:
Preface / vii \\ 1: Floating Point Arithmetic / 1 \\ 2: Approximation Methods / 75 \\ 3: Software Notes / 129 \\ 4: Elementary Functions / 143 \\ 5: Probability Distributions and Related Functions / 201 6: Bessel Functions / 263 \\ 7: Other Special Functions / 333 \\ Bibliography / 411 \\ Index / 413

rawTOC:
Preface / vii \\ 1: Floating Point Arithmetic / 1 \\ 1.1 Numeric Data Structures / 1 \\ 1.2 Rounding / 5 \\ 1.3 Addition and Subtraction / 6 \\ 1.4 Multiplication / 7 \\ 1.4.1 Long Multiplication in Binary Radix / 8 \\ 1.4.2 Multiplication in Word Integer Radix / 8 \\ 1.4.3 Fast Multiplication / 9 \\ 1.5 Division / 10 \\ 1.5.1 Long Division / 10 \\ 1.5.2 Division by Taylor Series / 11 \\ 1.5.3 Newton--Raphson Division / 11 \\ 1.6 C Language / 12 \\ 1.7 An Extended Double Arithmetic: ieee.c / 13 \\ 1.8 Binary - Decimal Conversion / 46 \\ 1.8.1 etoasc.c / 47 \\ 1.8.2 asctoe.c / 54 \\ 1.9 Analysis of Error / 58 \\ 1.9.1 Roundoff and Cancellation / 58 \\ 1.9.2 Error Propagation / 60 \\ 1.9.3 Error as a Random Variable / 61 \\ 1.9.4 Order of Summation / 62 \\ 1.10 Complex Arithmetic / 62 \\ 1.10.1 cmplx.c / 64 \\ 1.10.2 Absolute Value: cabs.c / 67 \\ 1.11 Rational Arithmetic / 69 \\ 1.11.1 euclid.c / 70 \\ 2: Approximation Methods / 75 \\ 2.1 Power Series / 75 \\ 2.2 Chebyshev Expansions / 76 \\ 2.2.1 chbevl.c / 79 \\ 2.3 Pad{\'e} Approximations / 80 \\ 2.4 Least Maximum Approximations / 82 \\ 2.4.1 Best Polynomial Approximations / 82 \\ 2.4.2 Best Rational Approximations / 85 \\ 2.4.3 Special Rational Forms / 87 \\ 2.5 A Program to Find Best Approximations: remes.c / 88 \\ 2.6 Forms of Approximation / 111 \\ 2.7 Asymptotic Expansions / 113 \\ 2.8 Continued Fractions / 114 \\ 2.8.1 Continued Fractions from Recurrences / 115 \\ 2.8.2 Recurrences from Differential Equations / 116 \\ 2.8.3 Computing Continued Fractions / 117 \\ 2.9 Polynomials / 117 \\ 2.9.1 polevl.c / 118 \\ 2.10 Newton--Raphson Iterations / 119 \\ 2.10.1 Division / 120 \\ 2.10.2 Exponent Separation / 121 \\ 2.10.3 Square Root / 122 \\ 2.10.4 sqrt.c / 123 \\ 2.10.5 Longhand Square Root / 124 \\ 2.10.6 esqrt.c / 124 \\ 2.10.7 Cube Root / 126 \\ 2.10.8 cbrt.c / 127 \\ 3: Software Notes / 129 \\ 3.1 Design Strategy / 129 \\ 3.2 Testing / 131 \\ 3.3 System Utilities / 132 \\ 3.3.1 mconf.h / 132 \\ 3.3.2 mtherr.c / 134 \\ 3.3.3 const.c / 136 \\ 3.4 Arithmetic Utilities / 137 \\ 3.4.1 efloor.c / 138 \\ 3.4.2 efrexp.c / 140 \\ 3.4.3 eldexp.c / 140 \\ 4: Elementary Functions / 143 \\ 4.1 $e^x$ / 143 \\ 4.1.1 exp.c / 145 \\ 4.2 $\ln x$ / 147 \\ 4.2.1 log.c / 149 \\ 4.3 Argument Transformation for Circular Functions / 152 \\ 4.4 Sine and cosine / 153 \\ 4.4.1 sin.c / 154 \\ 4.4.2 cos.c / 156 \\ 4.5 Tangent and Cotangent / 157 \\ 4.5.1 tan.c / 158 \\ 4.6 Complex Circular Functions / 161 \\ 4.7 $\sin^{-1} x $ / 162 \\ 4.7.1 asin.c / 163 \\ 4.8 $\cos^{-1} x $ / 165 \\ 4.8.1 acos.c / 165 \\ 4.9 $\tan^{-1} x$ / 166 \\ 4.9.1 atan.c / 168 \\ 4.9.2 atan2.c / 169 \\ 4.10 Complex Inverse Circular Functions / 170 \\ 4.11 $\sinh x$ / 170 \\ 4.11.1 sinh.c / 171 \\ 4.12 $\cosh x$ / 172 \\ 4.12.1 cosh.c / 173 \\ 4.13 $\tanh x$ / 173 \\ 4.13.1 tanh.c / 174 \\ 4.14 $\sinh^{-1} x $ / 175 \\ 4.14.1 asinh.c / 176 \\ 4.15 $\cosh^{-1} x $ / 177 \\ 4.15.1 acosh.c / 178 \\ 4.16 $\tanh^{-1} x$ / 179 \\ 4.16.1 atanh.c / 180 \\ 4.17 Power Function / 181 \\ 4.17.1 Real Exponent / 182 \\ 4.17.2 pow.c / 182 \\ 4.17.3 Integer Exponent / 189 \\ 4.17.4 powi.c / 190 \\ 4.18 Testing / 192 \\ 4.19 Single Precision Polynomial Approximations / 193 \\ 4.19.1 $\cos x$ / 193 \\ 4.19.2 $\cosh^{-1} x $ / 193 \\ 4.19.3 $\exp x$ / 196 \\ 4.19.4 $\ln x$ / 196 \\ 4.19.5 $\sin x$ / 197 \\ 4.19.6 $\sin^{-1} x $ / 197 \\ 4.19.7 Square Root / 197 \\ 4.19.8 $\tan x$ / 198 \\ 4.19.9 $\tan^{-1} x$ / 198 \\ 4.19.10 $\tanh x$ / 199 \\ 4.19.11 $tanh^{-1} x$ / 199 \\ 5: Probability Distributions and Related Functions / 201 \\ 5.1 $n!$ / 202 \\ 5.1.1 fac.c / 204 \\ 5.2 $\Gamma(x)$ / 206 \\ 5.2.1 gamma.c / 210 \\ 5.2.2 lgam.c / 214 \\ 5.3 Incomplete Gamma Integral / 217 \\ 5.3.1 igamc.c / 218 \\ 5.3.2 igam.c / 220 \\ 5.3.3 Functional Inverse of Incomplete Gamma Integral / 221 \\ 5.3.4 igami.c / 221 \\ 5.4 Gamma Distribution / 222 \\ 5.4.1 gdtr c / 222 \\ 5.4.2 gdtrc.c / 223 \\ 5.5 $\chi^2$ Distribution / 223 \\ 5.5.1 chdtrc.c / 224 \\ 5.5.2 chdtr.c / 224 \\ 5.5.3 chdtrl.c / 224 \\ 5.6 Poisson Distribution / 225 \\ 5.6.1 pdtrc.c / 225 \\ 5.6.2 pdtr.c / 226 \\ 5.6.3 pdtri.c / 226 \\ 5.7 Beta Function / 227 \\ 5.7.1 beta.c / 227 \\ 5.8 Incomplete Beta Integral / 229 \\ 5.8.1 ibet.c / 231 \\ 5.8.2 Functional Inverse of Incomplete Beta Integral / 238 \\ 5.9 Beta Distribution / 241 \\ 5.9.1 btdtr.c / 241 \\ 5.10 Binomial Distribution / 241 \\ 5.10.1 bdtrc.c / 242 \\ 5.10.2 bdtr.c / 243 \\ 5.10.3 bdtri.c / 244 \\ 5.11 Negative Binomial Distribution / 244 \\ 5.11.1 nbdtr.c / 245 \\ 5.11.2 nbdtrc.c / 245 \\ 5.12 F Distribution / 246 \\ 5.12.1 fdtrc.c / 247 \\ 5.12.2 fdtr.c / 247 \\ 5.12.3 fdtrci.c / 248 \\ 5.13 Student's $t$ distribution / 249 \\ 5.13.1 stdtr.c / 250 \\ 5.14 Gaussian Distribution / 252 \\ 5.14.1 ndtr.c / 254 \\ 5.14.2 erfc.c / 256 \\ 5.14.3 erf.c / 257 \\ 5.14.4 Functional Inverse of Gaussian Distribution / 258 \\ 5.14.5 ndtri.c / 259 \\ 6: Bessel Functions / 263 \\ 6.1 $J_0(x)$ / 263 \\ 6.1.1 jO.c / 265 \\ 6.2 $Y_0(x)$ / 268 \\ 6.2.1 yO.c / 269 \\ 6.3 Modulus and Phase / 270 \\ 6.4 $J_1(x)$ / 271 \\ 6.4.1 jl.c / 272 \\ 6.5 $Y_1(x)$ / 275 \\ 6.5.1 yl.c / 275 \\ 6.6 $J_n(x)$ / 276 \\ 6.1 $I_0(x)$ / 277 \\ 6.7.1 i0.c / 278 \\ 6.8 $I_1(x)$ / 281 \\ 6.8.1 i1.c / 283 \\ 6.9 $I_\nu(x)$ / 285 \\ 6.9.1 iv.c / 286 \\ 6.10 $K_0(x)$ / 287 \\ 6.10.1 kO.c / 287 \\ 6.11 $K_1(x)$ / 291 \\ 6.11.1 kl.c / 291 \\ 6.12 $K_n(x)$ / 294 \\ 6.12.1 kn.c / 295 \\ 6.13 $J_\nu(x)$ / 299 \\ 6.13.1 jv.c / 301 \\ 6.14 Airy Functions / 315 \\ 6.14.1 airy.c / 322 \\ 6.15 $Y_n(x)$ / 328 \\ 6.15.1 yn.c / 329 \\ 6.16 Testing / 330 \\ 7: Other Special Functions / 333 \\ 7.1 Hypergeometric Functions / 333 \\ 7.1.1 $_2F_1$ / 334 \\ 7.1.2 hyp2fi.c / 335 \\ 7.1.3 $_1F_1$ / 341 \\ 7.1.4 hyplfi.c / 342 \\ 7.1.5 $_2F_0$ / 346 \\ 7.1.6 hyp2ffi.c / 346 \\ 7.2 Struve Functions / 348 \\ 7.2.1 hypl1f2.c / 348 \\ 7.2.2 hyp3f0.c / 349 \\ 7.2.3 yv.c / 351 \\ 7.2.4 struve.c / 351 \\ 7.3 $\psi(x)$ / 352 \\ 7.3.1 psi.c / 354 \\ 7.4 Exponential Integral / 355 \\ 7.4.1 en.c / 356 \\ 7.5 Sine and Cosine Integrals / 360 \\ 7.5.1 sici.c / 362 \\ 7.5.2 Hyperbolic Sine and Cosine Integrals / 367 \\ 7.5.3 shichi.c / 370 \\ 7.6 Dilogarithm / 374 \\ 7.6.1 spence.c / 375 \\ 7.7 Dawson's Integral / 377 \\ 7.7.1 dawsn.c / 378 \\ 7.8 Fresnel Integrals / 381 \\ 7.8.1 fresnl.c / 383 \\ 7.9 Elliptic Functions / 387 \\ 7.9.1 $K(m)$ / 387 \\ 7.9.2 ellpk.c / 388 \\ 7.9.3 $F(\phi|m)$ / 389 \\ 7.9.4 ellik.c / 390 \\ 7.9.5 $E(m)$ / 392 \\ 7.9.6 ellpe.c / 392 \\ 7.9.7 $E(\phi|m)$ / 393 \\ 7.9.8 ellie.c / 394 \\ 7.9.9 Jacobian Elliptic Functions / 396 \\ 7.9.10 ellpj.c / 398 \\ 7.10 Zeta Functions / 400 \\ 7.10.1 hurwiz.c / 400 \\ 7.10.2 Riemann Zeta Function / 402 \\ 7.10.3 zetac.c / 405 \\ Bibliography / 411 \\ Index / 413

entry:
@Book{Moshier:1989:MPM,
  author =       "Stephen L. B. Moshier",
  title =        "Methods and Programs for Mathematical Functions",
  publisher =    pub-ELLIS-HORWOOD,
  address =      pub-ELLIS-HORWOOD:adr,
  pages =        "vii + 415",
  year =         "1989",
  ISBN =         "0-7458-0289-3",
  ISBN-13 =      "978-0-7458-0289-3",
  LCCN =         "QA331 .M84 1989",
  MRclass =      "*65D20, 26-04, 33-04, 65-02, 65C99",
  bibdate =      "Thu Sep 01 10:33:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  price =        "US\pounds 48.00",
  URL =          "http://www.moshier.net/;
                 http://www.netlib.org/cephes",
  ZMnumber =     "0701.65011",
  acknowledgement = ack-nj,
  shorttableofcontents = "Preface / vii \\
                 1: Floating Point Arithmetic / 1 \\
                 2: Approximation Methods / 75 \\
                 3: Software Notes / 129 \\
                 4: Elementary Functions / 143 \\
                 5: Probability Distributions and Related Functions /
                 201 6: Bessel Functions / 263 \\
                 7: Other Special Functions / 333 \\
                 Bibliography / 411 \\
                 Index / 413",
  tableofcontents = "Preface / vii \\
                 1: Floating Point Arithmetic / 1 \\
                 1.1 Numeric Data Structures / 1 \\
                 1.2 Rounding / 5 \\
                 1.3 Addition and Subtraction / 6 \\
                 1.4 Multiplication / 7 \\
                 1.4.1 Long Multiplication in Binary Radix / 8 \\
                 1.4.2 Multiplication in Word Integer Radix / 8 \\
                 1.4.3 Fast Multiplication / 9 \\
                 1.5 Division / 10 \\
                 1.5.1 Long Division / 10 \\
                 1.5.2 Division by Taylor Series / 11 \\
                 1.5.3 Newton--Raphson Division / 11 \\
                 1.6 C Language / 12 \\
                 1.7 An Extended Double Arithmetic: ieee.c / 13 \\
                 1.8 Binary - Decimal Conversion / 46 \\
                 1.8.1 etoasc.c / 47 \\
                 1.8.2 asctoe.c / 54 \\
                 1.9 Analysis of Error / 58 \\
                 1.9.1 Roundoff and Cancellation / 58 \\
                 1.9.2 Error Propagation / 60 \\
                 1.9.3 Error as a Random Variable / 61 \\
                 1.9.4 Order of Summation / 62 \\
                 1.10 Complex Arithmetic / 62 \\
                 1.10.1 cmplx.c / 64 \\
                 1.10.2 Absolute Value: cabs.c / 67 \\
                 1.11 Rational Arithmetic / 69 \\
                 1.11.1 euclid.c / 70 \\
                 2: Approximation Methods / 75 \\
                 2.1 Power Series / 75 \\
                 2.2 Chebyshev Expansions / 76 \\
                 2.2.1 chbevl.c / 79 \\
                 2.3 Pad{\'e} Approximations / 80 \\
                 2.4 Least Maximum Approximations / 82 \\
                 2.4.1 Best Polynomial Approximations / 82 \\
                 2.4.2 Best Rational Approximations / 85 \\
                 2.4.3 Special Rational Forms / 87 \\
                 2.5 A Program to Find Best Approximations: remes.c / 88
                 \\
                 2.6 Forms of Approximation / 111 \\
                 2.7 Asymptotic Expansions / 113 \\
                 2.8 Continued Fractions / 114 \\
                 2.8.1 Continued Fractions from Recurrences / 115 \\
                 2.8.2 Recurrences from Differential Equations / 116 \\
                 2.8.3 Computing Continued Fractions / 117 \\
                 2.9 Polynomials / 117 \\
                 2.9.1 polevl.c / 118 \\
                 2.10 Newton--Raphson Iterations / 119 \\
                 2.10.1 Division / 120 \\
                 2.10.2 Exponent Separation / 121 \\
                 2.10.3 Square Root / 122 \\
                 2.10.4 sqrt.c / 123 \\
                 2.10.5 Longhand Square Root / 124 \\
                 2.10.6 esqrt.c / 124 \\
                 2.10.7 Cube Root / 126 \\
                 2.10.8 cbrt.c / 127 \\
                 3: Software Notes / 129 \\
                 3.1 Design Strategy / 129 \\
                 3.2 Testing / 131 \\
                 3.3 System Utilities / 132 \\
                 3.3.1 mconf.h / 132 \\
                 3.3.2 mtherr.c / 134 \\
                 3.3.3 const.c / 136 \\
                 3.4 Arithmetic Utilities / 137 \\
                 3.4.1 efloor.c / 138 \\
                 3.4.2 efrexp.c / 140 \\
                 3.4.3 eldexp.c / 140 \\
                 4: Elementary Functions / 143 \\
                 4.1 $e^x$ / 143 \\
                 4.1.1 exp.c / 145 \\
                 4.2 $\ln x$ / 147 \\
                 4.2.1 log.c / 149 \\
                 4.3 Argument Transformation for Circular Functions /
                 152 \\
                 4.4 Sine and cosine / 153 \\
                 4.4.1 sin.c / 154 \\
                 4.4.2 cos.c / 156 \\
                 4.5 Tangent and Cotangent / 157 \\
                 4.5.1 tan.c / 158 \\
                 4.6 Complex Circular Functions / 161 \\
                 4.7 $\sin^{-1} x $ / 162 \\
                 4.7.1 asin.c / 163 \\
                 4.8 $\cos^{-1} x $ / 165 \\
                 4.8.1 acos.c / 165 \\
                 4.9 $\tan^{-1} x$ / 166 \\
                 4.9.1 atan.c / 168 \\
                 4.9.2 atan2.c / 169 \\
                 4.10 Complex Inverse Circular Functions / 170 \\
                 4.11 $\sinh x$ / 170 \\
                 4.11.1 sinh.c / 171 \\
                 4.12 $\cosh x$ / 172 \\
                 4.12.1 cosh.c / 173 \\
                 4.13 $\tanh x$ / 173 \\
                 4.13.1 tanh.c / 174 \\
                 4.14 $\sinh^{-1} x $ / 175 \\
                 4.14.1 asinh.c / 176 \\
                 4.15 $\cosh^{-1} x $ / 177 \\
                 4.15.1 acosh.c / 178 \\
                 4.16 $\tanh^{-1} x$ / 179 \\
                 4.16.1 atanh.c / 180 \\
                 4.17 Power Function / 181 \\
                 4.17.1 Real Exponent / 182 \\
                 4.17.2 pow.c / 182 \\
                 4.17.3 Integer Exponent / 189 \\
                 4.17.4 powi.c / 190 \\
                 4.18 Testing / 192 \\
                 4.19 Single Precision Polynomial Approximations / 193
                 \\
                 4.19.1 $\cos x$ / 193 \\
                 4.19.2 $\cosh^{-1} x $ / 193 \\
                 4.19.3 $\exp x$ / 196 \\
                 4.19.4 $\ln x$ / 196 \\
                 4.19.5 $\sin x$ / 197 \\
                 4.19.6 $\sin^{-1} x $ / 197 \\
                 4.19.7 Square Root / 197 \\
                 4.19.8 $\tan x$ / 198 \\
                 4.19.9 $\tan^{-1} x$ / 198 \\
                 4.19.10 $\tanh x$ / 199 \\
                 4.19.11 $tanh^{-1} x$ / 199 \\
                 5: Probability Distributions and Related Functions /
                 201 \\
                 5.1 $n!$ / 202 \\
                 5.1.1 fac.c / 204 \\
                 5.2 $\Gamma(x)$ / 206 \\
                 5.2.1 gamma.c / 210 \\
                 5.2.2 lgam.c / 214 \\
                 5.3 Incomplete Gamma Integral / 217 \\
                 5.3.1 igamc.c / 218 \\
                 5.3.2 igam.c / 220 \\
                 5.3.3 Functional Inverse of Incomplete Gamma Integral /
                 221 \\
                 5.3.4 igami.c / 221 \\
                 5.4 Gamma Distribution / 222 \\
                 5.4.1 gdtr c / 222 \\
                 5.4.2 gdtrc.c / 223 \\
                 5.5 $\chi^2$ Distribution / 223 \\
                 5.5.1 chdtrc.c / 224 \\
                 5.5.2 chdtr.c / 224 \\
                 5.5.3 chdtrl.c / 224 \\
                 5.6 Poisson Distribution / 225 \\
                 5.6.1 pdtrc.c / 225 \\
                 5.6.2 pdtr.c / 226 \\
                 5.6.3 pdtri.c / 226 \\
                 5.7 Beta Function / 227 \\
                 5.7.1 beta.c / 227 \\
                 5.8 Incomplete Beta Integral / 229 \\
                 5.8.1 ibet.c / 231 \\
                 5.8.2 Functional Inverse of Incomplete Beta Integral /
                 238 \\
                 5.9 Beta Distribution / 241 \\
                 5.9.1 btdtr.c / 241 \\
                 5.10 Binomial Distribution / 241 \\
                 5.10.1 bdtrc.c / 242 \\
                 5.10.2 bdtr.c / 243 \\
                 5.10.3 bdtri.c / 244 \\
                 5.11 Negative Binomial Distribution / 244 \\
                 5.11.1 nbdtr.c / 245 \\
                 5.11.2 nbdtrc.c / 245 \\
                 5.12 F Distribution / 246 \\
                 5.12.1 fdtrc.c / 247 \\
                 5.12.2 fdtr.c / 247 \\
                 5.12.3 fdtrci.c / 248 \\
                 5.13 Student's $t$ distribution / 249 \\
                 5.13.1 stdtr.c / 250 \\
                 5.14 Gaussian Distribution / 252 \\
                 5.14.1 ndtr.c / 254 \\
                 5.14.2 erfc.c / 256 \\
                 5.14.3 erf.c / 257 \\
                 5.14.4 Functional Inverse of Gaussian Distribution /
                 258 \\
                 5.14.5 ndtri.c / 259 \\
                 6: Bessel Functions / 263 \\
                 6.1 $J_0(x)$ / 263 \\
                 6.1.1 jO.c / 265 \\
                 6.2 $Y_0(x)$ / 268 \\
                 6.2.1 yO.c / 269 \\
                 6.3 Modulus and Phase / 270 \\
                 6.4 $J_1(x)$ / 271 \\
                 6.4.1 jl.c / 272 \\
                 6.5 $Y_1(x)$ / 275 \\
                 6.5.1 yl.c / 275 \\
                 6.6 $J_n(x)$ / 276 \\
                 6.1 $I_0(x)$ / 277 \\
                 6.7.1 i0.c / 278 \\
                 6.8 $I_1(x)$ / 281 \\
                 6.8.1 i1.c / 283 \\
                 6.9 $I_\nu(x)$ / 285 \\
                 6.9.1 iv.c / 286 \\
                 6.10 $K_0(x)$ / 287 \\
                 6.10.1 kO.c / 287 \\
                 6.11 $K_1(x)$ / 291 \\
                 6.11.1 kl.c / 291 \\
                 6.12 $K_n(x)$ / 294 \\
                 6.12.1 kn.c / 295 \\
                 6.13 $J_\nu(x)$ / 299 \\
                 6.13.1 jv.c / 301 \\
                 6.14 Airy Functions / 315 \\
                 6.14.1 airy.c / 322 \\
                 6.15 $Y_n(x)$ / 328 \\
                 6.15.1 yn.c / 329 \\
                 6.16 Testing / 330 \\
                 7: Other Special Functions / 333 \\
                 7.1 Hypergeometric Functions / 333 \\
                 7.1.1 $_2F_1$ / 334 \\
                 7.1.2 hyp2fi.c / 335 \\
                 7.1.3 $_1F_1$ / 341 \\
                 7.1.4 hyplfi.c / 342 \\
                 7.1.5 $_2F_0$ / 346 \\
                 7.1.6 hyp2ffi.c / 346 \\
                 7.2 Struve Functions / 348 \\
                 7.2.1 hypl1f2.c / 348 \\
                 7.2.2 hyp3f0.c / 349 \\
                 7.2.3 yv.c / 351 \\
                 7.2.4 struve.c / 351 \\
                 7.3 $\psi(x)$ / 352 \\
                 7.3.1 psi.c / 354 \\
                 7.4 Exponential Integral / 355 \\
                 7.4.1 en.c / 356 \\
                 7.5 Sine and Cosine Integrals / 360 \\
                 7.5.1 sici.c / 362 \\
                 7.5.2 Hyperbolic Sine and Cosine Integrals / 367 \\
                 7.5.3 shichi.c / 370 \\
                 7.6 Dilogarithm / 374 \\
                 7.6.1 spence.c / 375 \\
                 7.7 Dawson's Integral / 377 \\
                 7.7.1 dawsn.c / 378 \\
                 7.8 Fresnel Integrals / 381 \\
                 7.8.1 fresnl.c / 383 \\
                 7.9 Elliptic Functions / 387 \\
                 7.9.1 $K(m)$ / 387 \\
                 7.9.2 ellpk.c / 388 \\
                 7.9.3 $F(\phi|m)$ / 389 \\
                 7.9.4 ellik.c / 390 \\
                 7.9.5 $E(m)$ / 392 \\
                 7.9.6 ellpe.c / 392 \\
                 7.9.7 $E(\phi|m)$ / 393 \\
                 7.9.8 ellie.c / 394 \\
                 7.9.9 Jacobian Elliptic Functions / 396 \\
                 7.9.10 ellpj.c / 398 \\
                 7.10 Zeta Functions / 400 \\
                 7.10.1 hurwiz.c / 400 \\
                 7.10.2 Riemann Zeta Function / 402 \\
                 7.10.3 zetac.c / 405 \\
                 Bibliography / 411 \\
                 Index / 413",
}


bibtype: manual
filename: fparith.bib
label: Motorola:1989:DIF
title: DSP96002: IEEE floating-point dual-port processor: user's manual
organization: Motorola, Inc.
address: Phoeniz, AZ, USA
pages: various
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.; Signal processing.
remark: Cover title. Spine title: DSP96002 user's manual. ``DSP96002UM/AD''--Cover.
acknowledgement: ack-nhfb
rawtitle: {DSP96002}: {IEEE} floating-point dual-port processor: user's manual
entry:
@Manual{Motorola:1989:DIF,
  title =        "{DSP96002}: {IEEE} floating-point dual-port processor:
                 user's manual",
  organization = "{Motorola, Inc.}",
  address =      "Phoeniz, AZ, USA",
  pages =        "various",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.; Signal processing.",
  remark =       "Cover title. Spine title: DSP96002 user's manual.
                 ``DSP96002UM/AD''--Cover.",
}


bibtype: book
filename: fparith.bib
label: Motorola:1989:MMF
author: Motorola, Inc.
title: MC68881 / MC68882 Floating-Point Coprocessor User's Manual
publisher: pub-PH
address: pub-PH:adr
edition: Second
pages: 409 (various paging)
month: aug
monthnumber: 8
year: 1989
ISBN: 0-13-567009-8 (paperback) OR 0135670098 (paperback)
ISBN13: 978-0-13-567009-5 (paperback) OR 9780135670095 (paperback)
bibdate: Fri Dec 08 13:02:55 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:02:55 ???
URL: https://www.nxp.com/docs/en/reference-manual/MC68881UM.pdf
remark: Spine title: MC68881/882 user's manual. ``MC68881UM/AD REV 2''--Cover.
acknowledgement: ack-nj
rawauthor: {Motorola, Inc.}
rawtitle: {MC68881\slash MC68882} Floating-Point Coprocessor User's Manual
keywords:
Floating-point arithmetic.; microprocessors; Microprocessors --- Handbooks, manuals, etc.; Motorola 68881 (Microprocessor); Motorola 68882 (Microprocessor); technology --- computers and computer technology

entry:
@Book{Motorola:1989:MMF,
  author =       "{Motorola, Inc.}",
  title =        "{MC68881\slash MC68882} Floating-Point Coprocessor
                 User's Manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Second",
  pages =        "409 (various paging)",
  month =        aug,
  year =         "1989",
  ISBN =         "0-13-567009-8 (paperback)",
  ISBN-13 =      "978-0-13-567009-5 (paperback)",
  LCCN =         "????",
  bibdate =      "Fri Dec 08 13:02:55 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.nxp.com/docs/en/reference-manual/MC68881UM.pdf",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  keywords =     "Floating-point arithmetic.; microprocessors;
                 Microprocessors --- Handbooks, manuals, etc.; Motorola
                 68881 (Microprocessor); Motorola 68882
                 (Microprocessor); technology --- computers and computer
                 technology",
  remark =       "Spine title: MC68881/882 user's manual. ``MC68881UM/AD
                 REV 2''--Cover.",
}


bibtype: book
filename: fparith.bib
label: Motorola:1989:MRM
author: Motorola
title: MC88100 RISC Microprocessor User's Manual
publisher: pub-MOTOROLA
address: pub-MOTOROLA:adr
edition: Second
pages: 409 (various paging)
year: 1989
ISBN: 0-13-567090-X OR 013567090X
ISBN13: 978-0-13-567090-3 OR 9780135670903
LCCN: QA76.8.M75 M3 1990
bibdate: Wed Jul 6 14:23:15 1994
bibtimestamp: 1994.07.06 14:23:15 ???
acknowledgement: ack-nhfb
rawauthor: Motorola
rawtitle: {MC88100} {RISC} Microprocessor User's Manual
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib; https://www.math.utah.edu/pub/tex/bib/microchip.bib

TOC:
Overview Features Introduction Execution Units and Register File Execution Model Programming Model Processor States Reset State Flow-Control Instructions Register with 9-Bit Vector Table Index Instruction Categories Programming Tips Instruction Set Opcode Summary Signal Description Data Processor Bus Signals Exceptions Exception Overview Exception Vectors and Vector Base Register (VBR) Exception Priority Exception Processing Instruction Unit Exceptions Integer Overflow Exception (Vector Offset $48) Memory Access Exceptions FPU Exception Processing FPU Exception Processing Registers Timing Factors Execution Example Instruction Set Timing Summary Applications Information Cache Memory Management Units Power and Ground Considerations Master/Checker Operations Synchronization Operations Electrical Characteristics

rawTOC:
Overview \\ Features \\ Introduction \\ Execution Units and Register File \\ Execution Model \\ Programming Model \\ Processor States \\ Reset State \\ Flow-Control Instructions \\ Register with 9-Bit Vector Table Index \\ Instruction Categories \\ Programming Tips \\ Instruction Set \\ Opcode Summary \\ Signal Description \\ Data Processor Bus Signals \\ Exceptions \\ Exception Overview \\ Exception Vectors and Vector Base Register (VBR) \\ Exception Priority \\ Exception Processing \\ Instruction Unit Exceptions \\ Integer Overflow Exception (Vector Offset \$48) \\ Memory Access Exceptions \\ FPU Exception Processing \\ FPU Exception Processing Registers \\ Timing Factors \\ Execution Example \\ Instruction Set Timing Summary \\ Applications Information \\ Cache Memory Management Units \\ Power and Ground Considerations \\ Master/Checker Operations \\ Synchronization Operations \\ Electrical Characteristics

entry:
@Book{Motorola:1989:MRM,
  author =       "Motorola",
  title =        "{MC88100} {RISC} Microprocessor User's Manual",
  publisher =    pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  edition =      "Second",
  year =         "1989",
  ISBN =         "0-13-567090-X",
  ISBN-13 =      "978-0-13-567090-3",
  LCCN =         "QA76.8.M75 M3 1990",
  bibdate =      "Wed Jul 6 14:23:15 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  tableofcontents = "Overview \\
                 Features \\
                 Introduction \\
                 Execution Units and Register File \\
                 Execution Model \\
                 Programming Model \\
                 Processor States \\
                 Reset State \\
                 Flow-Control Instructions \\
                 Register with 9-Bit Vector Table Index \\
                 Instruction Categories \\
                 Programming Tips \\
                 Instruction Set \\
                 Opcode Summary \\
                 Signal Description \\
                 Data Processor Bus Signals \\
                 Exceptions \\
                 Exception Overview \\
                 Exception Vectors and Vector Base Register (VBR) \\
                 Exception Priority \\
                 Exception Processing \\
                 Instruction Unit Exceptions \\
                 Integer Overflow Exception (Vector Offset \$48) \\
                 Memory Access Exceptions \\
                 FPU Exception Processing \\
                 FPU Exception Processing Registers \\
                 Timing Factors \\
                 Execution Example \\
                 Instruction Set Timing Summary \\
                 Applications Information \\
                 Cache Memory Management Units \\
                 Power and Ground Considerations \\
                 Master/Checker Operations \\
                 Synchronization Operations \\
                 Electrical Characteristics",
}


bibtype: article
filename: fparith.bib
label: Mulcahy:1989:FPR
author: L. P. Mulcahy
title: On fixed-point roundoff error analysis
journal: j-IEEE-TRANS-ACOUST-SPEECH
volume: 37
number: 10
pages: 1623
month: oct
monthnumber: 10
year: 1989
CODEN: IETABA
ISSN: 0096-3518 OR 00963518
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Acoustics, Speech, and Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29
rawauthor: L. P. Mulcahy
rawtitle: On fixed-point roundoff error analysis
entry:
@Article{Mulcahy:1989:FPR,
  author =       "L. P. Mulcahy",
  title =        "On fixed-point roundoff error analysis",
  journal =      j-IEEE-TRANS-ACOUST-SPEECH,
  volume =       "37",
  number =       "10",
  pages =        "1623",
  month =        oct,
  year =         "1989",
  CODEN =        "IETABA",
  ISSN =         "0096-3518",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Acoustics, Speech, and Signal
                 Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29",
  summary =      "The author points out the existence of work published
                 by the author (US Department of Commerce, Tech. Rep.
                 AD-A086826, 57 pp., Apr. 1980) prior to the appearance
                 of the paper by Barnes et al. (ibid., vol.ASSP-33,
                 p.595-606, June 1985) covering the same \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Nakayama:1989:BMF
author: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
title: An 80 b, 6.7 MFLOPS floating-point processor with vector / matrix instructions
crossref: Wuorinen:1989:DTP
pages: 52--53, 289
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: NEC, Kawasaki, Japan
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; VLSI
rawauthor: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
rawtitle: An 80 b, 6.7 {MFLOPS} floating-point processor with vector\slash matrix instructions
abstract:
A description is given of an 80-b CMOS VLSI floating-point processor (FPP) in 1.2- mu m double-metal layer CMOS which contains 433000 transistors on an 11.6-mm*14.9-mm die. It operates at 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead pin-grid-array package. The FPP is designed as a coprocessor for 32-b microprocessors. It implements data formats, arithmetic rounding modes, and exception types which are defined by the IEEE 754 standard. The chip can handle single (32 b), double (64 b), and double-extended (80 b) floating-point data formats. The complex-instruction-set-computer- (CISC-) like 78-instruction set includes 22 mathematical functions such as sin, cos, arctan, exp, and log, and 24 vector/matrix operations such as add, multiply, and inner product. The features and performance of the device are summarized.

keywords:
1.2 Micron; 1.5 W; 20 MHz; 6.7 MFLOPS; 80 Bit; Arithmetic rounding modes; CMOS VLSI floating-point processor; Complex instruction set computer; Data formats; Double-metal layer CMOS; Exception types; Mathematical functions; Pin-grid-array package; Power dissipation; Vector/matrix instructions

rawabstract:
A description is given of an 80-b CMOS VLSI floating-point processor (FPP) in 1.2- mu m double-metal layer CMOS which contains 433000 transistors on an 11.6-mm*14.9-mm die. It operates at 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead pin-grid-array package. The FPP is designed as a coprocessor for 32-b microprocessors. It implements data formats, arithmetic rounding modes, and exception types which are defined by the IEEE 754 standard. The chip can handle single (32 b), double (64 b), and double-extended (80 b) floating-point data formats. The complex-instruction-set-computer- (CISC-) like 78-instruction set includes 22 mathematical functions such as sin, cos, arctan, exp, and log, and 24 vector/matrix operations such as add, multiply, and inner product. The features and performance of the device are summarized.

entry:
@InProceedings{Nakayama:1989:BMF,
  author =       "T. Nakayama and S. Kojima and H. Harigai and H.
                 Igarashi and K. Tamada and T. Toba",
  title =        "An 80 b, 6.7 {MFLOPS} floating-point processor with
                 vector\slash matrix instructions",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "52--53, 289",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A description is given of an 80-b CMOS VLSI
                 floating-point processor (FPP) in 1.2- mu m
                 double-metal layer CMOS which contains 433000
                 transistors on an 11.6-mm*14.9-mm die. It operates at
                 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead
                 pin-grid-array package. The FPP is designed as a
                 coprocessor for 32-b microprocessors. It implements
                 data formats, arithmetic rounding modes, and exception
                 types which are defined by the IEEE 754 standard. The
                 chip can handle single (32 b), double (64 b), and
                 double-extended (80 b) floating-point data formats. The
                 complex-instruction-set-computer- (CISC-) like
                 78-instruction set includes 22 mathematical functions
                 such as sin, cos, arctan, exp, and log, and 24
                 vector/matrix operations such as add, multiply, and
                 inner product. The features and performance of the
                 device are summarized.",
  acknowledgement = ack-nhfb,
  affiliation =  "NEC, Kawasaki, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  keywords =     "1.2 Micron; 1.5 W; 20 MHz; 6.7 MFLOPS; 80 Bit;
                 Arithmetic rounding modes; CMOS VLSI floating-point
                 processor; Complex instruction set computer; Data
                 formats; Double-metal layer CMOS; Exception types;
                 Mathematical functions; Pin-grid-array package; Power
                 dissipation; Vector/matrix instructions",
  numericalindex = "Word length 8.0E+01 bit; Computer speed 6.7E+06
                 FLOPS; Size 1.2E-06 m; Frequency 2.0E+07 Hz; Power
                 1.5E+00 W",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; VLSI",
}


bibtype: article
filename: fparith.bib
label: Nakayama:1989:FCV
title: A 6.7-MFLOPS floating-point coprocessor with vector / matrix instructions
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1324--1330
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A 6.7-{MFLOPS} floating-point coprocessor with vector\slash matrix instructions
author:
T. Nakayama and H. Harigai and S. Kojima and H. Kaneko and H. Igarashi and T. Toba and Y. Yamagami and Y. Yano

abstract:
An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.

keywords:
1.2 Micron; 20 MHz; 6.7 MFLOPS; 80 Bit; CMOS process; CORDIC trigonometrical algorithm; Double-metal layer; Floating-point coprocessor; Horizontal-type microinstructions; Mathematical functions; Parallel operations; Pipelined multiplication; SRT division method; Vector/matrix instructions; VLSI microprocessor

thesaurus:
CMOS integrated circuits; Digital arithmetic; Instruction sets; Microprocessor chips; Parallel architectures; Pipeline processing; Satellite computers; VLSI

rawabstract:
An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.

rawauthor:
T. Nakayama and H. Harigai and S. Kojima and H. Kaneko and H. Igarashi and T. Toba and Y. Yamagami and Y. Yano

entry:
@Article{Nakayama:1989:FCV,
  author =       "T. Nakayama and H. Harigai and S. Kojima and H. Kaneko
                 and H. Igarashi and T. Toba and Y. Yamagami and Y.
                 Yano",
  title =        "A 6.7-{MFLOPS} floating-point coprocessor with
                 vector\slash matrix instructions",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1324--1330",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An 80-bit floating-point coprocessor which implements
                 24 vector/matrix instructions and 22 mathematical
                 functions is described. This processor can execute
                 floating-point addition/rounding and pipelined
                 multiplication concurrently, under the control of
                 horizontal-type microinstructions. The SRT division
                 method and CORDIC trigonometrical algorithm are used
                 for a favorable cost/performance implementation. The
                 performance of 6.7 MFLOPS in the vector-matrix
                 multiplication at 20 MHz has been attained by the use
                 of parallel operations. The vector/matrix instruction
                 is about three times faster than conventional add and
                 multiply instructions. The chip has been fabricated in
                 1.2- mu m double-metal layer CMOS process containing
                 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "1.2 Micron; 20 MHz; 6.7 MFLOPS; 80 Bit; CMOS process;
                 CORDIC trigonometrical algorithm; Double-metal layer;
                 Floating-point coprocessor; Horizontal-type
                 microinstructions; Mathematical functions; Parallel
                 operations; Pipelined multiplication; SRT division
                 method; Vector/matrix instructions; VLSI
                 microprocessor",
  numericalindex = "Word length 8.0E+01 bit; Size 1.2E-06 m; Computer
                 speed 6.7E+06 FLOPS; Frequency 2.0E+07 Hz",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Instruction sets; Microprocessor chips; Parallel
                 architectures; Pipeline processing; Satellite
                 computers; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Nakayama:1989:MFPa
author: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
title: An 80b, 6.7 MFLOPS Floating-Point Processor with Vector / Matrix Instructions
crossref: Wuorinen:1989:DTP
pages: 52--53, 289
year: 1989
bibdate: Fri Dec 08 13:04:53 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:04:53 ???
acknowledgement: ack-nj
rawauthor: T. Nakayama and S. Kojima and H. Harigai and H. Igarashi and K. Tamada and T. Toba
rawtitle: An 80b, 6.7 {MFLOPS} Floating-Point Processor with Vector\slash Matrix Instructions
entry:
@InProceedings{Nakayama:1989:MFPa,
  author =       "T. Nakayama and S. Kojima and H. Harigai and H.
                 Igarashi and K. Tamada and T. Toba",
  title =        "An 80b, 6.7 {MFLOPS} Floating-Point Processor with
                 Vector\slash Matrix Instructions",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "52--53, 289",
  year =         "1989",
  bibdate =      "Fri Dec 08 13:04:53 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Nakayama:1989:MFPb
title: A 6.7-MFLOPS Floating-Point Coprocessor with Vector / Matrix Instructions
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1324--1330
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nj
rawtitle: A 6.7-{MFLOPS} Floating-Point Coprocessor with Vector\slash Matrix Instructions
author:
T. Nakayama and H. Harigai and S. Kojima and H. Kaneko and H. Igarashi and T. Toba and Y. Yamagami and Y. Yano

entry:
@Article{Nakayama:1989:MFPb,
  author =       "T. Nakayama and H. Harigai and S. Kojima and H. Kaneko
                 and H. Igarashi and T. Toba and Y. Yamagami and Y.
                 Yano",
  title =        "A 6.7-{MFLOPS} Floating-Point Coprocessor with
                 Vector\slash Matrix Instructions",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1324--1330",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "An 80-bit floating-point coprocessor which implements
                 24 vector/matrix instructions and 22 mathematical
                 functions is described. This processor can execute
                 floating-point addition/rounding and pipelined
                 multiplication concurrently, under the control
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Nowacki:1989:ABQ
author: C. L. Nowacki and J. D. Harris and M. N. Richard
title: Adaptive beamforming in quadratic residue number systems on a cluster array processor
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 624--628
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.104000
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: C. L. Nowacki and J. D. Harris and M. N. Richard
rawtitle: Adaptive beamforming in quadratic residue number systems on a cluster array processor
entry:
@InProceedings{Nowacki:1989:ABQ,
  author =       "C. L. Nowacki and J. D. Harris and M. N. Richard",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "Adaptive beamforming in quadratic residue number
                 systems on a cluster array processor",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "624--628",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.104000",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors describe a quadratic residue number system
                 (QRNS) implementation of the Leverrier algorithm for
                 computing the adjoint and determinant of a matrix on a
                 prototype parallel signal processor, called the cluster
                 array processor (CAP). Some \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ochs:1989:TPF
author: T. Ochs
title: Theory and practice (floating point arithmetic)
journal: j-COMP-LANG-MAG
volume: 6
number: 3
pages: 67--70, 72, 74, 77--78, 80--81
month: mar
monthnumber: 3
year: 1989
CODEN: COMLEF
ISSN: 0749-2839 OR 07492839
bibdate: Tue Dec 12 09:20:14 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:14 MST
fjournal: Computer Language Magazine
acknowledgement: ack-nhfb
thesaurus: Digital arithmetic; Program compilers
rawauthor: T. Ochs
rawtitle: Theory and practice (floating point arithmetic)
abstract:
The IEEE-754 standard for floating point arithmetic has inherent limits. The author presents a guide to NaNs, unnormals, underflows and signal infinite quantities.

keywords:
Compilers; Floating point arithmetic; IEEE-754 standard; NaNs; Signal infinite quantities; Underflows; Unnormals

rawabstract:
The IEEE-754 standard for floating point arithmetic has inherent limits. The author presents a guide to NaNs, unnormals, underflows and signal infinite quantities.

entry:
@Article{Ochs:1989:TPF,
  author =       "T. Ochs",
  title =        "Theory and practice (floating point arithmetic)",
  journal =      j-COMP-LANG-MAG,
  volume =       "6",
  number =       "3",
  pages =        "67--70, 72, 74, 77--78, 80--81",
  month =        mar,
  year =         "1989",
  CODEN =        "COMLEF",
  ISSN =         "0749-2839",
  bibdate =      "Tue Dec 12 09:20:14 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IEEE-754 standard for floating point arithmetic
                 has inherent limits. The author presents a guide to
                 NaNs, unnormals, underflows and signal infinite
                 quantities.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  classification = "C5230 (Digital arithmetic methods); C6150C
                 (Compilers, interpreters and other processors)",
  fjournal =     "Computer Language Magazine",
  keywords =     "Compilers; Floating point arithmetic; IEEE-754
                 standard; NaNs; Signal infinite quantities; Underflows;
                 Unnormals",
  thesaurus =    "Digital arithmetic; Program compilers",
}


bibtype: inproceedings
filename: fparith.bib
label: Petkovsek:1989:CDS
author: M. Petkovsek
title: Contiguous digit sets and local roundings
crossref: Ercegovac:1989:PSC
pages: 136--143
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Petkovsek.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: M. Petkovsek
rawtitle: Contiguous digit sets and local roundings
entry:
@InProceedings{Petkovsek:1989:CDS,
  author =       "M. Petkovsek",
  title =        "Contiguous digit sets and local roundings",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "136--143",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Petkovsek.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Pincin:1989:NAM
author: A. Pincin
title: A new algorithm for multiplication in finite fields
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 7
pages: 1045--1049
month: jul
monthnumber: 7
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.30855
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:40 MDT 2011
bibtimestamp: 2011.07.08 19:00:40 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=30855
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Pincin
rawtitle: A new algorithm for multiplication in finite fields
entry:
@Article{Pincin:1989:NAM,
  author =       "A. Pincin",
  title =        "A new algorithm for multiplication in finite fields",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "7",
  pages =        "1045--1049",
  month =        jul,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.30855",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=30855",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Prince:1989:FTF
author: Timothy Prince
title: Float Trig Functions For The C Preprocessor
journal: j-CUJ
volume: 7
number: 8
pages: 103--??
month: aug
monthnumber: 8
year: 1989
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: Timothy Prince
rawtitle: Float Trig Functions For The {C} Preprocessor
entry:
@Article{Prince:1989:FTF,
  author =       "Timothy Prince",
  title =        "Float Trig Functions For The {C} Preprocessor",
  journal =      j-CUJ,
  volume =       "7",
  number =       "8",
  pages =        "103--??",
  month =        aug,
  year =         "1989",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: inproceedings
filename: fparith.bib
label: Ramamoorthy:1989:HSA
author: P. A. Ramamoorthy and B. Potu
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: High-speed ADC using residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1063--1066
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266615
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: P. A. Ramamoorthy and B. Potu
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: High-speed {ADC} using residue number system
entry:
@InProceedings{Ramamoorthy:1989:HSA,
  author =       "P. A. Ramamoorthy and B. Potu",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "High-speed {ADC} using residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1063--1066",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266615",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "An ADC (analog/digital converter) architecture based
                 on a residue number system (RNS) and multiple folding
                 of the input signal is described. The number of
                 comparators used is equal to the sum of moduli for
                 obtaining the dynamic range desired. An \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Rao:1989:RNF
author: B. D. Rao
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
title: Roundoff noise in floating point state space digital filters
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 724--727
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: B. D. Rao
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
rawtitle: Roundoff noise in floating point state space digital filters
entry:
@InProceedings{Rao:1989:RNF,
  author =       "B. D. Rao",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Roundoff noise in floating point state space digital
                 filters",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "724--727",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The roundoff noise properties of floating-point
                 state-space digital filters are examined. It is shown
                 that the roundoff noise behavior of these filters is
                 related to their coefficient sensitivity. Expressions
                 for the variance of the output roundoff \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ray:1989:MCA
author: G. A. Ray
booktitle: Proceedings of the 32nd Midwest Symposium on Circuits and Systems, 1989
title: Multiple core algorithms for residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 833--836
year: 1989
DOI: https://doi.org/10.1109/MWSCAS.1989.101984
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. A. Ray
rawbooktitle: Proceedings of the 32nd Midwest Symposium on Circuits and Systems, 1989
rawtitle: Multiple core algorithms for residue number systems
entry:
@InProceedings{Ray:1989:MCA,
  author =       "G. A. Ray",
  booktitle =    "Proceedings of the 32nd Midwest Symposium on Circuits
                 and Systems, 1989",
  title =        "Multiple core algorithms for residue number systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "833--836",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.1989.101984",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The core function provides an easily implemented and
                 efficient means for performing the traditionally
                 difficult residue operations. However, two problems
                 with core algorithms are the difficulty in choosing
                 core coefficients and the many iterations \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Rishe:1989:LEN
author: Naphtali Rishe
title: Lexicographic Encoding of Numeric Data Fields
crossref: Ercegovac:1989:PSC
pages: 241--246
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Rishe.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Naphtali Rishe
rawtitle: Lexicographic Encoding of Numeric Data Fields
abstract:
This paper proposes a method of variable-radix representation of numeric data. The method allows compact representation of arbitrary numbers. Among its properties is that bitwise lexicographic comparison ($<$, $>$) is consistent with correct numeric comparison of numbers.

rawabstract:
This paper proposes a method of variable-radix representation of numeric data. The method allows compact representation of arbitrary numbers. Among its properties is that bitwise lexicographic comparison ($<$, $>$) is consistent with correct numeric comparison of numbers.

entry:
@InProceedings{Rishe:1989:LEN,
  author =       "Naphtali Rishe",
  title =        "Lexicographic Encoding of Numeric Data Fields",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "241--246",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Rishe.pdf",
  abstract =     "This paper proposes a method of variable-radix
                 representation of numeric data. The method allows
                 compact representation of arbitrary numbers. Among its
                 properties is that bitwise lexicographic comparison
                 ($<$, $>$) is consistent with correct numeric
                 comparison of numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: book
filename: fparith.bib
label: Robbins:1989:CXM
author: Kay A. Robbins and Steven Robbins
title: The Cray X-MP / Model 24
publisher: pub-SV
address: pub-SV:adr
pages: vi + 165
year: 1989
ISBN: 0-387-97089-4, 3-540-97089-4 OR 0387970894, 3540970894
ISBN13: 978-0-387-97089-9, 978-3-540-97089-7 OR 9780387970899, 9783540970897
LCCN: QA76.8 C72 R63 1989
bibdate: Sat Jan 29 18:17:38 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.01.29 18:17:38 ???
acknowledgement: ack-nhfb
rawauthor: Kay A. Robbins and Steven Robbins
rawtitle: The {Cray X-MP}\slash {Model} 24
entry:
@Book{Robbins:1989:CXM,
  author =       "Kay A. Robbins and Steven Robbins",
  title =        "The {Cray X-MP}\slash {Model} 24",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "vi + 165",
  year =         "1989",
  ISBN =         "0-387-97089-4, 3-540-97089-4",
  ISBN-13 =      "978-0-387-97089-9, 978-3-540-97089-7",
  LCCN =         "QA76.8 C72 R63 1989",
  bibdate =      "Sat Jan 29 18:17:38 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Saffari:1989:PDW
author: B. Saffari
title: Putting DSPs to work
journal: j-BYTE
volume: 14
number: 13
pages: 259--272
month: dec
monthnumber: 12
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:47:21 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:47:21 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
rawauthor: B. Saffari
rawtitle: Putting {DSPs} to work
keywords:
Digital filters; Feature extraction; Floating-point application-specific-IC DSPs; Image processing; Moments; Pattern recognition architecture; Sound; Space correction; Time

thesaurus:
Application specific integrated circuits; Computerised signal processing; Digital signal processing chips

entry:
@Article{Saffari:1989:PDW,
  author =       "B. Saffari",
  title =        "Putting {DSPs} to work",
  journal =      j-BYTE,
  volume =       "14",
  number =       "13",
  pages =        "259--272",
  month =        dec,
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:47:21 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); B6140 (Signal
                 processing and detection); C5130 (Microprocessor
                 chips); C5260 (Digital signal processing)",
  fjournal =     "BYTE Magazine",
  keywords =     "Digital filters; Feature extraction; Floating-point
                 application-specific-IC DSPs; Image processing;
                 Moments; Pattern recognition architecture; Sound; Space
                 correction; Time",
  thesaurus =    "Application specific integrated circuits; Computerised
                 signal processing; Digital signal processing chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Santoro:1989:RAI
author: M. R. Santoro and G. Bewick and M. A. Horowitz
title: Rounding Algorithms for IEEE Multipliers
crossref: Ercegovac:1989:PSC
pages: 176--183
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Santoro.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: M. R. Santoro and G. Bewick and M. A. Horowitz
rawtitle: Rounding Algorithms for {IEEE} Multipliers
entry:
@InProceedings{Santoro:1989:RAI,
  author =       "M. R. Santoro and G. Bewick and M. A. Horowitz",
  title =        "Rounding Algorithms for {IEEE} Multipliers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "176--183",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Santoro.pdf",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  keywords =     "ARITH-9",
  summary =      "Several technology independent rounding algorithms for
                 multiplying normalized numbers are presented. The first
                 is a simple rounding algorithm suitable for software
                 simulation or moderate performance hardware
                 multipliers. The next two algorithms are \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Sasaki:1989:AAD
author: Tateaki Sasaki and Mutsuko Sasaki
journal: J. Inform. Process.
volume: 12
number: 4
pages: 394--403
year: 1989
MRclass: 65G05 (65Y20)
MRnumber: 91h:65069
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
acknowledgement: ack-nhfb
rawauthor: Tateaki Sasaki and Mutsuko Sasaki
title:
Analysis of accuracy decreasing in polynomial remainder sequence with floating-point number coefficients

rawtitle:
Analysis of accuracy decreasing in polynomial remainder sequence with floating-point number coefficients

entry:
@Article{Sasaki:1989:AAD,
  author =       "Tateaki Sasaki and Mutsuko Sasaki",
  title =        "Analysis of accuracy decreasing in polynomial
                 remainder sequence with floating-point number
                 coefficients",
  journal =      "J. Inform. Process.",
  volume =       "12",
  number =       "4",
  pages =        "394--403",
  year =         "1989",
  MRclass =      "65G05 (65Y20)",
  MRnumber =     "91h:65069",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schwarz:1989:IIP
author: Jerry Schwarz
title: Implementing infinite precision arithmetic
crossref: Ercegovac:1989:PSC
pages: 10--17
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Schwarz.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Jerry Schwarz
rawtitle: Implementing infinite precision arithmetic
entry:
@InProceedings{Schwarz:1989:IIP,
  author =       "Jerry Schwarz",
  title =        "Implementing infinite precision arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "10--17",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Schwarz.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Scott:1989:FRM
author: M. Scott
title: Fast rounding in multiprecision floating-slash arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 7
pages: 1049--1052
month: jul
monthnumber: 7
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.30856
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibtimestamp: 2005.07.16 11:25:03 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Scott
rawtitle: Fast rounding in multiprecision floating-slash arithmetic
entry:
@Article{Scott:1989:FRM,
  author =       "M. Scott",
  title =        "Fast rounding in multiprecision floating-slash
                 arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "7",
  pages =        "1049--1052",
  month =        jul,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.30856",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "A computational algorithm is described which quickly
                 rounds large fractions into a fixed-length
                 multiprecision floating-slash representation, using
                 single-precision operations where possible. An easily
                 calculated criterion for terminating the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Shenoy:1989:FBE
author: A. P. Shenoy and R. Kumaresan
title: Fast base extension using a redundant modulus in RNS
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 2
pages: 292--297
month: feb
monthnumber: 2
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.16508
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:38 MDT 2011
bibtimestamp: 2011.07.08 19:00:38 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16508
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. P. Shenoy and R. Kumaresan
rawtitle: Fast base extension using a redundant modulus in {RNS}
entry:
@Article{Shenoy:1989:FBE,
  author =       "A. P. Shenoy and R. Kumaresan",
  title =        "Fast base extension using a redundant modulus in
                 {RNS}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "2",
  pages =        "292--297",
  month =        feb,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.16508",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:38 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16508",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Shimazu:1989:MFP
title: A 50 MHz 24b Floating-Point DSP
crossref: Wuorinen:1989:DTP
pages: 44--45, 285
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-mfc
affiliation: Mitsubishi, Hyogo, Japan
rawtitle: A 50 {MHz} 24b Floating-Point {DSP}
author:
Y. Shimazu and T. Kengaku and T. Fujiyama and E. Teraoka and T. Ohno and T. Tokuda and O. Tomisawa and S. Tsujimichi

abstract:
A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.

keywords:
1 Micron; 24 Bit; 40 Ns; 50 MHz; 600 MW; Built-in self-test; Circuit design techniques; Clock frequency; Communication applications; Data register; Double-metal CMOS; Floating-point digital signal processor; I/O registers; Instruction set; Linear feedback shift registers; Machine cycle time; On-chip IROM; Power dissipation; Serial input registers; Serial output registers; Speech processing; WSi/sub 2/ technology

thesaurus:
CMOS integrated circuits; Digital arithmetic; Digital signal processing chips; Speech analysis and processing

rawabstract:
A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.

rawauthor:
Y. Shimazu and T. Kengaku and T. Fujiyama and E. Teraoka and T. Ohno and T. Tokuda and O. Tomisawa and S. Tsujimichi

entry:
@InProceedings{Shimazu:1989:MFP,
  author =       "Y. Shimazu and T. Kengaku and T. Fujiyama and E.
                 Teraoka and T. Ohno and T. Tokuda and O. Tomisawa and
                 S. Tsujimichi",
  title =        "A 50 {MHz} 24b Floating-Point {DSP}",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "44--45, 285",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 24-bit floating-point digital signal processor (DSP)
                 has been developed primarily for speech processing and
                 communication applications. The chip uses 1.0- mu m
                 double-metal CMOS with tungsten silicide technology.
                 The instruction set is upward compatible with an 18-bit
                 DSP. Novel circuit design techniques allowing 40-ns
                 machine cycle time at 50-MHz clock and less than 600-mW
                 power dissipation are described. A built-in self-test
                 is prepared using on-chip IROM and the two 24-bit
                 linear feedback shift registers which are included in
                 I/O registers such as the data register, the serial
                 input registers, and the serial output registers. The
                 DSP design features are summarized.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  affiliation =  "Mitsubishi, Hyogo, Japan",
  chemicalindex = "WSi2/int Si2/int Si/int W/int WSi2/bin Si2/bin Si/bin
                 W/bin",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); B6130 (Speech analysis and
                 processing techniques); C5130 (Microprocessor chips);
                 C5230 (Digital arithmetic methods); C5260 (Digital
                 signal processing)",
  keywords =     "1 Micron; 24 Bit; 40 Ns; 50 MHz; 600 MW; Built-in
                 self-test; Circuit design techniques; Clock frequency;
                 Communication applications; Data register; Double-metal
                 CMOS; Floating-point digital signal processor; I/O
                 registers; Instruction set; Linear feedback shift
                 registers; Machine cycle time; On-chip IROM; Power
                 dissipation; Serial input registers; Serial output
                 registers; Speech processing; WSi/sub 2/ technology",
  numericalindex = "Frequency 5.0E+07 Hz; Word length 2.4E+01 bit; Time
                 4.0E-08 s; Power 6.0E-01 W; Size 1.0E-06 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic; Digital
                 signal processing chips; Speech analysis and
                 processing",
}


bibtype: article
filename: fparith.bib
label: Sinha:1989:FPA
author: B. P. Sinha and P. K. Srimani
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 3
pages: 424--431
month: mar
monthnumber: 3
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.21128
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:38 MDT 2011
bibtimestamp: 2011.07.08 19:00:38 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21128
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. P. Sinha and P. K. Srimani
title:
Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

rawtitle:
Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

entry:
@Article{Sinha:1989:FPA,
  author =       "B. P. Sinha and P. K. Srimani",
  title =        "Fast parallel algorithms for binary multiplication and
                 their implementation on systolic architectures",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "3",
  pages =        "424--431",
  month =        mar,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.21128",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:38 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21128",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Sit:1989:MFP
author: H. P. Sit and M. R. Nofal and S. Kimn
title: An 80 MFLOPS Floating-point Engine in the Intel i860TM Processor
crossref: IEEE:1989:PII
pages: 374--379
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-mfc
affiliation: Intel Corp., Santa Clara, CA, USA
rawauthor: H. P. Sit and M. R. Nofal and S. Kimn
rawtitle: An 80 {MFLOPS} Floating-point Engine in the {Intel} i860{\TM} Processor
abstract:
The i860 processor is a 64-b microprocessor with 1.02 million transistors. It has a 64-b external data bus and a 32-b external address bus. It is fabricated with Intel's CHMOS IV technology (a 1- mu m double-metal process). The die size is approximately 10 mm*15 mm. First silicon is functional over commercial temperature and voltage ranges with an execution speed of 40 MHz. The floating-point engine consists of a pipelined adder and a pipelined multiplier, incorporates a special hardware to support the dual operation instructions, and operates synchronously with the RISC (reduced-instruction-set computer) core to execute up to three operations per clock. Its high performance lends itself well to a numeric-intensive computation environment, including vector processing.

keywords:
1 Micron; 10 Mm; 15 Mm; 32 Bit; 40 MHz; 64 Bit; 80 MFLOPS; 80 MFLOPS floating-point engine; CHMOS IV technology; CMOS; Commercial temperature; Die size; Double-metal process; Dual operation instructions; Execution speed; Floating-point engine; Intel i860 processor; Numeric-intensive computation environment; Pipelined adder; Pipelined multiplier; Reduced-instruction-set computer; RISC core; Three operations per clock; Vector processing

thesaurus:
CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Reduced instruction set computing

rawabstract:
The i860 processor is a 64-b microprocessor with 1.02 million transistors. It has a 64-b external data bus and a 32-b external address bus. It is fabricated with Intel's CHMOS IV technology (a 1- mu m double-metal process). The die size is approximately 10 mm*15 mm. First silicon is functional over commercial temperature and voltage ranges with an execution speed of 40 MHz. The floating-point engine consists of a pipelined adder and a pipelined multiplier, incorporates a special hardware to support the dual operation instructions, and operates synchronously with the RISC (reduced-instruction-set computer) core to execute up to three operations per clock. Its high performance lends itself well to a numeric-intensive computation environment, including vector processing.

entry:
@InProceedings{Sit:1989:MFP,
  author =       "H. P. Sit and M. R. Nofal and S. Kimn",
  title =        "An 80 {MFLOPS} Floating-point Engine in the {Intel}
                 i860{\TM} Processor",
  crossref =     "IEEE:1989:PII",
  pages =        "374--379",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The i860 processor is a 64-b microprocessor with 1.02
                 million transistors. It has a 64-b external data bus
                 and a 32-b external address bus. It is fabricated with
                 Intel's CHMOS IV technology (a 1- mu m double-metal
                 process). The die size is approximately 10 mm*15 mm.
                 First silicon is functional over commercial temperature
                 and voltage ranges with an execution speed of 40 MHz.
                 The floating-point engine consists of a pipelined adder
                 and a pipelined multiplier, incorporates a special
                 hardware to support the dual operation instructions,
                 and operates synchronously with the RISC
                 (reduced-instruction-set computer) core to execute up
                 to three operations per clock. Its high performance
                 lends itself well to a numeric-intensive computation
                 environment, including vector processing.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  affiliation =  "Intel Corp., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips)",
  keywords =     "1 Micron; 10 Mm; 15 Mm; 32 Bit; 40 MHz; 64 Bit; 80
                 MFLOPS; 80 MFLOPS floating-point engine; CHMOS IV
                 technology; CMOS; Commercial temperature; Die size;
                 Double-metal process; Dual operation instructions;
                 Execution speed; Floating-point engine; Intel i860
                 processor; Numeric-intensive computation environment;
                 Pipelined adder; Pipelined multiplier;
                 Reduced-instruction-set computer; RISC core; Three
                 operations per clock; Vector processing",
  numericalindex = "Word length 6.4E+01 bit; Frequency 4.0E+07 Hz; Word
                 length 3.2E+01 bit; Computer speed 8.0E+07 FLOPS; Size
                 1.0E-06 m; Size 1.0E-02 m; Size 1.5E-02 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Reduced instruction set
                 computing",
}


bibtype: inproceedings
filename: fparith.bib
label: Skavantzos:1989:DFC
author: A. Skavantzos
booktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
title: Designing fast convolvers for residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 497--501
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Skavantzos
rawbooktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
rawtitle: Designing fast convolvers for residue number systems
entry:
@InProceedings{Skavantzos:1989:DFC,
  author =       "A. Skavantzos",
  booktitle =    "Twenty-Third Asilomar Conference on Signals, Systems
                 and Computers, 1989",
  title =        "Designing fast convolvers for residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "497--501",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: article
filename: fparith.bib
label: Smith:1989:CSB
author: S. G. Smith
title: Comments on ``A signed bit-sequential multiplier'' by T. Rhyne and N. R. Strader II
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 9
pages: 1328--1330
month: sep
monthnumber: 9
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.29473
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:41 MDT 2011
bibtimestamp: 2011.07.08 19:00:41 MDT
note: See cite Rhyne:1986:SBS.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29473
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. G. Smith
rawnote: See \cite{Rhyne:1986:SBS}.
rawtitle: Comments on {``A signed bit-sequential multiplier''} by {T. Rhyne} and {N. R. Strader II}
entry:
@Article{Smith:1989:CSB,
  author =       "S. G. Smith",
  title =        "Comments on {``A signed bit-sequential multiplier''}
                 by {T. Rhyne} and {N. R. Strader II}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "9",
  pages =        "1328--1330",
  month =        sep,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.29473",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  note =         "See \cite{Rhyne:1986:SBS}.",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29473",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Spaderna:1989:IFP
author: D. Spaderna and P. Green and K. Tam and T. Datta and M. Kumar
title: An integrated floating point vector processor for DSP and scientific computing
crossref: IEEE:1989:PII
pages: 8--13
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Sharp Microelectron. Technol. Inc., Vancouver, WA, USA
thesaurus: Digital signal processing chips; Parallel architectures
rawauthor: D. Spaderna and P. Green and K. Tam and T. Datta and M. Kumar
rawtitle: An integrated floating point vector processor for {DSP} and scientific computing
abstract:
The architecture of a high-performance floating-point microprocessor intended for computation-intensive applications is presented. Utilizing a massively parallel execution unit, very high bandwidth onchip memory, and extensive parallel address calculation hardware, the processor is expected to achieve peak execution rates of 400 MFLOPS for single-precision floating-point numbers. This type of performance is competitive with that of popular mainframe vector processors.

keywords:
400 MFLOPS; Computation-intensive applications; DSP; Floating-point microprocessor; Integrated floating point vector processor; Mainframe vector processors; Massively parallel execution unit; Onchip memory; Parallel address calculation hardware; Peak execution rates; Scientific computing; Single-precision floating-point numbers

rawabstract:
The architecture of a high-performance floating-point microprocessor intended for computation-intensive applications is presented. Utilizing a massively parallel execution unit, very high bandwidth onchip memory, and extensive parallel address calculation hardware, the processor is expected to achieve peak execution rates of 400 MFLOPS for single-precision floating-point numbers. This type of performance is competitive with that of popular mainframe vector processors.

entry:
@InProceedings{Spaderna:1989:IFP,
  author =       "D. Spaderna and P. Green and K. Tam and T. Datta and
                 M. Kumar",
  title =        "An integrated floating point vector processor for
                 {DSP} and scientific computing",
  crossref =     "IEEE:1989:PII",
  pages =        "8--13",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The architecture of a high-performance floating-point
                 microprocessor intended for computation-intensive
                 applications is presented. Utilizing a massively
                 parallel execution unit, very high bandwidth onchip
                 memory, and extensive parallel address calculation
                 hardware, the processor is expected to achieve peak
                 execution rates of 400 MFLOPS for single-precision
                 floating-point numbers. This type of performance is
                 competitive with that of popular mainframe vector
                 processors.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sharp Microelectron. Technol. Inc., Vancouver, WA,
                 USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5260 (Digital signal processing)",
  keywords =     "400 MFLOPS; Computation-intensive applications; DSP;
                 Floating-point microprocessor; Integrated floating
                 point vector processor; Mainframe vector processors;
                 Massively parallel execution unit; Onchip memory;
                 Parallel address calculation hardware; Peak execution
                 rates; Scientific computing; Single-precision
                 floating-point numbers",
  numericalindex = "Computer speed 4.0E+08 FLOPS",
  thesaurus =    "Digital signal processing chips; Parallel
                 architectures",
}


bibtype: inproceedings
filename: fparith.bib
label: Stearns:1989:SFD
author: C. C. Stearns
title: Subtractive floating-point division and square root for VLSI DSP
crossref: IEE:1989:EEC
pages: 405--409
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
rawauthor: C. C. Stearns
rawtitle: Subtractive floating-point division and square root for {VLSI DSP}
abstract:
This paper describes recent architectural developments in VLSI design for real-time digital signal processing. In particular, floating point division and floating point square root architectures applicable to both adaptive filtering, standard deviation computations, and general purpose processing are discussed. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven feasible and reliable from extensive gate-level simulation and fabrication in silicon.

keywords:
Adaptive filtering; Arithmetic units; CMOS technology; Floating point division; Floating point square root architectures; Gate-level simulation; General purpose processing; Real-time digital signal processing; Semiconductor; Standard deviation computations; VLSI DSP

thesaurus:
Adaptive filters; CMOS integrated circuits; Digital arithmetic; Digital signal processing chips; VLSI

rawabstract:
This paper describes recent architectural developments in VLSI design for real-time digital signal processing. In particular, floating point division and floating point square root architectures applicable to both adaptive filtering, standard deviation computations, and general purpose processing are discussed. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven feasible and reliable from extensive gate-level simulation and fabrication in silicon.

entry:
@InProceedings{Stearns:1989:SFD,
  author =       "C. C. Stearns",
  title =        "Subtractive floating-point division and square root
                 for {VLSI DSP}",
  crossref =     "IEE:1989:EEC",
  pages =        "405--409",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes recent architectural developments
                 in VLSI design for real-time digital signal processing.
                 In particular, floating point division and floating
                 point square root architectures applicable to both
                 adaptive filtering, standard deviation computations,
                 and general purpose processing are discussed. Emphasis
                 here is on the internal architectures of the arithmetic
                 units not on their applications. The research presented
                 in this paper has been proven feasible and reliable
                 from extensive gate-level simulation and fabrication in
                 silicon.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B1270F
                 (Digital filters); B2570D (CMOS integrated circuits);
                 C5230 (Digital arithmetic methods); C5240 (Digital
                 filters); C5260 (Digital signal processing)",
  keywords =     "Adaptive filtering; Arithmetic units; CMOS technology;
                 Floating point division; Floating point square root
                 architectures; Gate-level simulation; General purpose
                 processing; Real-time digital signal processing;
                 Semiconductor; Standard deviation computations; VLSI
                 DSP",
  thesaurus =    "Adaptive filters; CMOS integrated circuits; Digital
                 arithmetic; Digital signal processing chips; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Stearns:1989:SFP
author: C. C. Stearns
booktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
title: Subtractive floating-point division and square root for VLSI DSP
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 405--409
year: 1989
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: C. C. Stearns
rawbooktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
rawtitle: Subtractive floating-point division and square root for {VLSI} {DSP}
entry:
@InProceedings{Stearns:1989:SFP,
  author =       "C. C. Stearns",
  booktitle =    "European Conference on Circuit Theory and Design, 5--8
                 Sep 1989",
  title =        "Subtractive floating-point division and square root
                 for {VLSI} {DSP}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "405--409",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper describes recent architectural developments
                 in VLSI design for real-time digital signal processing.
                 In particular, floating point division and floating
                 point square root architectures applicable to both
                 adaptive filtering, standard \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Tang:1989:TCA
author: P. T. P. Tang
title: Testing Computer Arithmetic by Elementary Number Theory
institution: Mathematics and Computer Science Division, Argonne National Laboratory
month: aug
monthnumber: 8
year: 1989
bibdate: Thu Sep 01 11:57:30 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 11:57:30 ???
keywords: floating-point testing
acknowledgement: ack-nj
rawauthor: P. T. P. Tang
rawtitle: Testing Computer Arithmetic by Elementary Number Theory
entry:
@TechReport{Tang:1989:TCA,
  author =       "P. T. P. Tang",
  title =        "Testing Computer Arithmetic by Elementary Number
                 Theory",
  institution =  "Mathematics and Computer Science Division, Argonne
                 National Laboratory",
  pages =        "??",
  month =        aug,
  year =         "1989",
  bibdate =      "Thu Sep 01 11:57:30 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  keywords =     "floating-point testing",
}


bibtype: article
filename: fparith.bib
label: Tang:1989:TDI
author: Ping Tak Peter Tang
title: Table-Driven Implementation of the Exponential Function in IEEE Floating-Point Arithmetic
journal: j-TOMS
volume: 15
number: 2
pages: 144--157
month: jun
monthnumber: 6
year: 1989
CODEN: ACMSCU
DOI: https://doi.org/10.1145/63522.214389
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sun Sep 04 22:47:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.04 22:47:40 ???
URL: http://www.acm.org/pubs/citations/journals/toms/1989-15-2/p144-tang/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: algorithms
acknowledgement: ack-nj
journalURL: https://dl.acm.org/loi/toms
rawauthor: Ping Tak Peter Tang
rawtitle: Table-Driven Implementation of the Exponential Function in {IEEE} Floating-Point Arithmetic
abstract:
Algorithms and implementation details for the exponential function in both single- and double-precision of IEEE 754 arithmetic are presented here. With a table of moderate size, the implementations need only working-precision arithmetic and are provably accurate to within 0.54 ulp as long as the final result does not underflow. When the final result suffers gradual underflow, the error is still no worse than 0.77 ulp.

subject:
bf G.1.0: Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf G.1.0: Mathematics of Computing, NUMERICAL ANALYSIS, General, Error analysis. bf G.1.0: Mathematics of Computing, NUMERICAL ANALYSIS, General, Numerical algorithms. bf G.4: Mathematics of Computing, MATHEMATICAL SOFTWARE, Algorithm analysis.

rawabstract:
Algorithms and implementation details for the exponential function in both single- and double-precision of IEEE 754 arithmetic are presented here. With a table of moderate size, the implementations need only working-precision arithmetic and are provably accurate to within 0.54 ulp as long as the final result does not underflow. When the final result suffers gradual underflow, the error is still no worse than 0.77 ulp.

entry:
@Article{Tang:1989:TDI,
  author =       "Ping Tak Peter Tang",
  title =        "Table-Driven Implementation of the Exponential
                 Function in {IEEE} Floating-Point Arithmetic",
  journal =      j-TOMS,
  volume =       "15",
  number =       "2",
  pages =        "144--157",
  month =        jun,
  year =         "1989",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/63522.214389",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sun Sep 04 22:47:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/citations/journals/toms/1989-15-2/p144-tang/",
  abstract =     "Algorithms and implementation details for the
                 exponential function in both single- and
                 double-precision of IEEE 754 arithmetic are presented
                 here. With a table of moderate size, the
                 implementations need only working-precision arithmetic
                 and are provably accurate to within 0.54 ulp as long as
                 the final result does not underflow. When the final
                 result suffers gradual underflow, the error is still no
                 worse than 0.77 ulp.",
  acknowledgement = ack-nj,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "algorithms",
  subject =      "{\bf G.1.0}: Mathematics of Computing, NUMERICAL
                 ANALYSIS, General, Computer arithmetic. {\bf G.1.0}:
                 Mathematics of Computing, NUMERICAL ANALYSIS, General,
                 Error analysis. {\bf G.1.0}: Mathematics of Computing,
                 NUMERICAL ANALYSIS, General, Numerical algorithms. {\bf
                 G.4}: Mathematics of Computing, MATHEMATICAL SOFTWARE,
                 Algorithm analysis.",
}


bibtype: book
filename: fparith.bib
label: Thies:1989:PXA
author: Klaus-Dieter Thies
title: PC / XT / AT Numerik Buch toenglish PC / XT / AT Numeric Book endtoenglish
publisher: pub-TEWI
address: pub-TEWI:adr
pages: xiii + 707
year: 1989
ISBN: 3-89362-033-8 OR 3893620338
ISBN13: 978-3-89362-033-3 OR 9783893620333
bibdate: Sat Nov 09 10:09:41 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 10:09:41 ???
acknowledgement: ack-nj
rawauthor: Klaus-Dieter Thies
rawtitle:
{PC\slash {XT}\slash {AT} Numerik Buch} \toenglish {PC\slash XT\slash AT Numeric Book} \endtoenglish

entry:
@Book{Thies:1989:PXA,
  author =       "Klaus-Dieter Thies",
  title =        "{PC\slash {XT}\slash {AT} Numerik Buch} \toenglish
                 {PC\slash XT\slash AT Numeric Book} \endtoenglish",
  publisher =    pub-TEWI,
  address =      pub-TEWI:adr,
  pages =        "xiii + 707",
  year =         "1989",
  ISBN =         "3-89362-033-8",
  ISBN-13 =      "978-3-89362-033-3",
  LCCN =         "????",
  bibdate =      "Sat Nov 09 10:09:41 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Tu:1989:DLD
author: Paul K. Tu and M. D. Ercegovac
title: Design of on-line division unit
crossref: Ercegovac:1989:PSC
pages: 42--49
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Tu.pdf
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, California University, Los Angeles, CA, USA
thesaurus: Digital arithmetic; Large scale integration; Logic arrays
rawauthor: Paul K. Tu and M. D. Ercegovac
rawtitle: Design of on-line division unit
abstract:
A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%.

keywords:
24 Ns Cycle time; ARITH-9; Gate array implementation; LSI Logic LL9320P chip; Online division unit design; Radix-2 floating-point online division algorithm; Utilization factor

rawabstract:
A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78\%.

entry:
@InProceedings{Tu:1989:DLD,
  author =       "Paul K. Tu and M. D. Ercegovac",
  title =        "Design of on-line division unit",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "42--49",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Tu.pdf",
  abstract =     "A gate array implementation of a radix-2
                 floating-point online division algorithm is presented.
                 The design requires 111 equivalent gates per bit and
                 has a cycle time of 24 ns. For 8-b exponent and 24-b
                 mantissa, the design requires 2497 equivalent gates and
                 can fit on an LSI Logic LL9320P chip with a utilization
                 factor 78\%.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, California University,
                 Los Angeles, CA, USA",
  classification = "B1265B (Logic circuits); B2570 (Semiconductor
                 integrated circuits); C5120 (Logic and switching
                 circuits); C5230 (Digital arithmetic methods)",
  keywords =     "24 Ns Cycle time; ARITH-9; Gate array implementation;
                 LSI Logic LL9320P chip; Online division unit design;
                 Radix-2 floating-point online division algorithm;
                 Utilization factor",
  numericalindex = "Time 2.4E-08 s",
  thesaurus =    "Digital arithmetic; Large scale integration; Logic
                 arrays",
}


bibtype: inproceedings
filename: fparith.bib
label: Turner:1989:SIS
author: Peter R. Turner
title: A software implementation of SLI arithmetic
crossref: Ercegovac:1989:PSC
pages: 18--24
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turner.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Peter R. Turner
rawtitle: A software implementation of {SLI} arithmetic
entry:
@InProceedings{Turner:1989:SIS,
  author =       "Peter R. Turner",
  title =        "A software implementation of {SLI} arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "18--24",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turner.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Turrini:1989:OGD
author: Silvio Turrini
title: Optimal group distribution in carry-skip adders
crossref: Ercegovac:1989:PSC
pages: 96--103
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turrini.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Silvio Turrini
rawtitle: Optimal group distribution in carry-skip adders
entry:
@InProceedings{Turrini:1989:OGD,
  author =       "Silvio Turrini",
  title =        "Optimal group distribution in carry-skip adders",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "96--103",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Turrini.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Unguru:1989:BRB
author: Sabetai Unguru
journal: j-ISIS
volume: 80
number: 2
pages: 298--299
month: jun
monthnumber: 6
year: 1989
CODEN: ISISA4
ISSN: 0021-1753 (print), 1545-6994 (electronic) OR 00211753 (print), 15456994 (electronic)
ISSNL: 0021-1753 OR 00211753
bibdate: Tue Jul 30 21:23:50 MDT 2013
bibtimestamp: 2013.07.30 21:23:50 MDT
URL: http://www.jstor.org/stable/234607
fjournal: Isis
acknowledgement: ack-nhfb
journalURL: http://www.jstor.org/journal/isis
rawauthor: Sabetai Unguru
title:
Book Review: booktitle A Mathematical History of Division in Extreme and Mean Ratio by Roger Herz-Fischler

bibsource:
http://www.jstor.org/action/showPublication?journalCode=isis; http://www.jstor.org/stable/i211193; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/isis1980.bib

rawtitle:
Book Review: {{\booktitle{A Mathematical History of Division in Extreme and Mean Ratio}} by Roger Herz-Fischler}

entry:
@Article{Unguru:1989:BRB,
  author =       "Sabetai Unguru",
  title =        "Book Review: {{\booktitle{A Mathematical History of
                 Division in Extreme and Mean Ratio}} by Roger
                 Herz-Fischler}",
  journal =      j-ISIS,
  volume =       "80",
  number =       "2",
  pages =        "298--299",
  month =        jun,
  year =         "1989",
  CODEN =        "ISISA4",
  ISSN =         "0021-1753 (print), 1545-6994 (electronic)",
  ISSN-L =       "0021-1753",
  bibdate =      "Tue Jul 30 21:23:50 MDT 2013",
  bibsource =    "http://www.jstor.org/action/showPublication?journalCode=isis;
                 http://www.jstor.org/stable/i211193;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/isis1980.bib",
  URL =          "http://www.jstor.org/stable/234607",
  acknowledgement = ack-nhfb,
  fjournal =     "Isis",
  journal-URL =  "http://www.jstor.org/journal/isis",
}


bibtype: article
filename: fparith.bib
label: VanVeen:1989:MBC
author: B. D. Van Veen and R. Baraniuk
title: Matrix based computation of floating-point roundoff noise
journal: j-IEEE-TRANS-ACOUST-SPEECH
volume: 37
number: 12
pages: 1995--1998
month: dec
monthnumber: 12
year: 1989
CODEN: IETABA
ISSN: 0096-3518 OR 00963518
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Acoustics, Speech, and Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29
rawauthor: B. D. {Van Veen} and R. Baraniuk
rawtitle: Matrix based computation of floating-point roundoff noise
entry:
@Article{VanVeen:1989:MBC,
  author =       "B. D. {Van Veen} and R. Baraniuk",
  title =        "Matrix based computation of floating-point roundoff
                 noise",
  journal =      j-IEEE-TRANS-ACOUST-SPEECH,
  volume =       "37",
  number =       "12",
  pages =        "1995--1998",
  month =        dec,
  year =         "1989",
  CODEN =        "IETABA",
  ISSN =         "0096-3518",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Acoustics, Speech, and Signal
                 Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29",
  summary =      "A matrix-based procedure is presented for computing
                 the output roundoff power for filters implemented with
                 floating-point arithmetic. The filter's computational
                 structure is represented in terms of a product of
                 matrices, known as a factored state \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Vassiliadis:1989:GPO
author: S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan
title: A General Proof for Overlapped Multiple-Bit Scanning Multiplications
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 2
pages: 172--183
month: feb
monthnumber: 2
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.16494
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:37 MDT 2011
bibtimestamp: 2011.07.08 19:00:37 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16494
fjournal: IEEE Transactions on Computers
acknowledgement: ack-mfc
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan
rawtitle: A General Proof for Overlapped Multiple-Bit Scanning Multiplications
entry:
@Article{Vassiliadis:1989:GPO,
  author =       "S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan",
  title =        "A General Proof for Overlapped Multiple-Bit Scanning
                 Multiplications",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "2",
  pages =        "172--183",
  month =        feb,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.16494",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:37 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16494",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Vassiliadis:1989:SMF
author: S. Vassiliadis and D. S. Lemon and M. Putrino
title: S/370 sign-magnitude floating-point adder
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 4
pages: 1062--1070
month: aug
monthnumber: 8
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: IBM Corp., Endicott, NY, USA
thesaurus: Adders; Bipolar integrated circuits; Carry logic; Integrated logic circuits; NAND circuits
rawauthor: S. Vassiliadis and D. S. Lemon and M. Putrino
rawtitle: {S/370} sign-magnitude floating-point adder
abstract:
A 56-bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal (4LM) bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39 x 7.39 mm super(2) and it is mounted on a metalized ceramic (MC) substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 model 60 (9375) Engineering Scientific Accelerator (ESA) card.

keywords:
algorithms; arithmetic circuits; Carry lookahead scheme; Chip die size; design; End-around carry; Engineering scientific accelerator card; Error-detecting logic; floating point arithmetic; Four-level metal bipolar master-slice technology; IBM 9370 Model 60; logic circuits; Metallized ceramic substrate; NAND gates; S/370; Sign-magnitude floating-point adder

rawabstract:
A 56-bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal (4LM) bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39 x 7.39 mm super(2) and it is mounted on a metalized ceramic (MC) substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 model 60 (9375) Engineering Scientific Accelerator (ESA) card.

entry:
@Article{Vassiliadis:1989:SMF,
  author =       "S. Vassiliadis and D. S. Lemon and M. Putrino",
  title =        "{S/370} sign-magnitude floating-point adder",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "4",
  pages =        "1062--1070",
  month =        aug,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 56-bit S/370 sign-magnitude adder for floating-point
                 operations implemented in a four-level metal (4LM)
                 bipolar master-slice technology is described. The
                 design of the two-to-one adder is based on a carry
                 lookahead scheme with implicit calculation of the
                 end-around carry. The implementation of the
                 floating-point adder and the error-detecting logic
                 requires one chip of 7500 automatically placed and
                 wired NAND gates. The chip die size is 7.39 x 7.39 mm
                 super(2) and it is mounted on a metalized ceramic (MC)
                 substrate. The floating-point sign-magnitude adder chip
                 is used in the IBM 9370 model 60 (9375) Engineering
                 Scientific Accelerator (ESA) card.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Endicott, NY, USA",
  classification = "B1265B (Logic circuits); B2570B (Bipolar integrated
                 circuits); C5120 (Logic and switching circuits)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "algorithms; arithmetic circuits; Carry lookahead
                 scheme; Chip die size; design; End-around carry;
                 Engineering scientific accelerator card;
                 Error-detecting logic; floating point arithmetic;
                 Four-level metal bipolar master-slice technology; IBM
                 9370 Model 60; logic circuits; Metallized ceramic
                 substrate; NAND gates; S/370; Sign-magnitude
                 floating-point adder",
  summary =      "A 56 bit S/370 sign-magnitude adder for floating-point
                 operations implemented in a four-level metal bipolar
                 master-slice technology is described. The design of the
                 two-to-one adder is based on a carry lookahead scheme
                 with implicit calculation of the \ldots{}",
  thesaurus =    "Adders; Bipolar integrated circuits; Carry logic;
                 Integrated logic circuits; NAND circuits",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1989:FSAa
author: H. Volzke
journal: j-MC
volume: 1
pages: 66--73
year: 1989
ISSN: 0720-4442, 0941-777x, 0943-5409 OR 07204442, 0941777x, 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 4: Die Konvertierungsroutinen toenglish Floating-point Arithmetic and its IEEE Specification. Part 4: Conversion Routines endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 4: Die Konvertierungsroutinen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 4: Conversion Routines} \endtoenglish

entry:
@Article{Voelzke:1989:FSAa,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 4: Die
                 Konvertierungsroutinen} \toenglish {Floating-point
                 Arithmetic and its IEEE Specification. Part 4:
                 Conversion Routines} \endtoenglish",
  journal =      j-MC,
  volume =       "1",
  pages =        "66--73",
  year =         "1989",
  ISSN =         "0720-4442, 0941-777x, 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1989:FSAb
author: H. Volzke
journal: j-MC
volume: 2
pages: 65--71
year: 1989
ISSN: 0720-4442, 0941-777x, 0943-5409 OR 07204442, 0941777x, 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 5: Ein- und Ausgabefunktionen toenglish Floating-point Arithmetic and its IEEE Specification. Part 5: Input and Output Functions endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 5: Ein- und Ausgabefunktionen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 5: Input and Output Functions} \endtoenglish

entry:
@Article{Voelzke:1989:FSAb,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 5: Ein- und
                 Ausgabefunktionen} \toenglish {Floating-point
                 Arithmetic and its IEEE Specification. Part 5: Input
                 and Output Functions} \endtoenglish",
  journal =      j-MC,
  volume =       "2",
  pages =        "65--71",
  year =         "1989",
  ISSN =         "0720-4442, 0941-777x, 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Vulchanov:1989:SCR
author: N. L. Vulchanov and M. M. Konstantinov
title: Safe calculation of the relative machine precision in floating-point computing environments
journal: j-C-R-ACAD-BULGARE-SCI
volume: 42
number: 2
pages: 45--48
year: 1989
CODEN: DBANAD
ISSN: 0366-8681 OR 03668681
MRclass: 65G99
MRnumber: 991 451
bibdate: Fri Dec 8 08:24:14 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:14 ???
fjournal: Comptes rendus de l'Academie bulgare des sciences
acknowledgement: ack-nhfb
rawauthor: N. L. Vulchanov and M. M. Konstantinov
rawtitle: Safe calculation of the relative machine precision in floating-point computing environments
entry:
@Article{Vulchanov:1989:SCR,
  author =       "N. L. Vulchanov and M. M. Konstantinov",
  title =        "Safe calculation of the relative machine precision in
                 floating-point computing environments",
  journal =      j-C-R-ACAD-BULGARE-SCI,
  volume =       "42",
  number =       "2",
  pages =        "45--48",
  year =         "1989",
  CODEN =        "DBANAD",
  ISSN =         "0366-8681",
  MRclass =      "65G99",
  MRnumber =     "991 451",
  bibdate =      "Fri Dec 8 08:24:14 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Comptes rendus de l'Acad{\'e}mie bulgare des
                 sciences",
}


bibtype: article
filename: fparith.bib
label: Wagner:1989:EDD
author: Neal R. Wagner and Paul Putter
title: Error detecting decimal digits
journal: j-CACM
volume: 32
number: 1
pages: 106--110
month: jan
monthnumber: 1
year: 1989
CODEN: CACMA2
DOI: https://doi.org/10.1145/63238.63246
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Thu May 30 09:41:10 MDT 1996
bibtimestamp: 1996.05.30 09:41:10 MDT
URL: http://www.acm.org/pubs/toc/Abstracts/0001-0782/63246.html
fjournal: Communications of the ACM
keywords: decimal floating-point arithmetic; reliability
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawauthor: Neal R. Wagner and Paul Putter
rawtitle: Error detecting decimal digits
bibsource:
ftp://ftp.ira.uka.de/pub/bibliography/Misc/IMMD_IV.bib; http://www.acm.org/pubs/toc/; https://www.math.utah.edu/pub/tex/bib/cacm1980.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We were recently engaged by a large mail-order house to act as consultants on their use of check digits for detecting errors in account numbers. Since we were not experts in coding theory, we looked in reference books such as Error Correcting Codes [7] and asked colleagues who were familiar with coding theory. Uniformly, the answer was: There is no field of order 10; the theory only works over a field. This article relates our experiences and presents several of the simple decimal-oriented error detection schemes that are available, but not widely known.

subject:
bf B.4.5: Hardware, INPUT/OUTPUT AND DATA COMMUNICATIONS, Reliability, Testing, and Fault-Tolerance, Error-checking. bf E.4: Data, CODING AND INFORMATION THEORY, Nonsecret encoding schemes.

rawabstract:
We were recently engaged by a large mail-order house to act as consultants on their use of check digits for detecting errors in account numbers. Since we were not experts in coding theory, we looked in reference books such as Error Correcting Codes [7] and asked colleagues who were familiar with coding theory. Uniformly, the answer was: There is no field of order 10; the theory only works over a field. This article relates our experiences and presents several of the simple decimal-oriented error detection schemes that are available, but not widely known.

entry:
@Article{Wagner:1989:EDD,
  author =       "Neal R. Wagner and Paul Putter",
  title =        "Error detecting decimal digits",
  journal =      j-CACM,
  volume =       "32",
  number =       "1",
  pages =        "106--110",
  month =        jan,
  year =         "1989",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/63238.63246",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Thu May 30 09:41:10 MDT 1996",
  bibsource =    "ftp://ftp.ira.uka.de/pub/bibliography/Misc/IMMD_IV.bib;
                 http://www.acm.org/pubs/toc/;
                 https://www.math.utah.edu/pub/tex/bib/cacm1980.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/toc/Abstracts/0001-0782/63246.html",
  abstract =     "We were recently engaged by a large mail-order house
                 to act as consultants on their use of check digits for
                 detecting errors in account numbers. Since we were not
                 experts in coding theory, we looked in reference books
                 such as Error Correcting Codes [7] and asked colleagues
                 who were familiar with coding theory. Uniformly, the
                 answer was: There is no field of order 10; the theory
                 only works over a field. This article relates our
                 experiences and presents several of the simple
                 decimal-oriented error detection schemes that are
                 available, but not widely known.",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
  keywords =     "decimal floating-point arithmetic; reliability",
  review =       "ACM CR 9002-0109",
  subject =      "{\bf B.4.5}: Hardware, INPUT/OUTPUT AND DATA
                 COMMUNICATIONS, Reliability, Testing, and
                 Fault-Tolerance, Error-checking. {\bf E.4}: Data,
                 CODING AND INFORMATION THEORY, Nonsecret encoding
                 schemes.",
}


bibtype: article
filename: fparith.bib
label: Wang:1989:ADF
author: C. C. Wang
title: An algorithm to design finite field multipliers using a self-dual normal basis
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 10
pages: 1457--1460
month: oct
monthnumber: 10
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.35840
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:42 MDT 2011
bibtimestamp: 2011.07.08 19:00:42 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=35840
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. C. Wang
rawtitle: An algorithm to design finite field multipliers using a self-dual normal basis
entry:
@Article{Wang:1989:ADF,
  author =       "C. C. Wang",
  title =        "An algorithm to design finite field multipliers using
                 a self-dual normal basis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "10",
  pages =        "1457--1460",
  month =        oct,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.35840",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=35840",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:1989:MBC
title: A 34-MFLOP 32-bit CMOS floating point processor
crossref: IEEE:1989:ISV
pages: 361--364
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Electron. Res and Service Organ., Hsing-Chu, Taiwan
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A 34-{MFLOP} 32-bit {CMOS} floating point processor
author:
Song-Tine Wang and Chi-Suan Wang and Morries Wang and Shyh-Rurong Wang and Jhy-Kun Wang and Ching-Lu Hon and Row-Ming Yang and Wei-Hsiung Chuang and Te-Tsoung Tsai and Ming-Yuan Jang and Gwo-Jeng Pun

abstract:
A 34-MFLOP 32-bit floating-point processor in 2- mu m CMOS technology is presented. In order to achieve the high speed of floating-point operation, the authors use such techniques as hierarchical design parallel circuits, and a three-stage pipeline that has been optimized with equal delay in each stage. It is shown that the CIC81232Y (multiplier) and CIC81233Y (arithmetic and logic circuit) are fully compatible with WTL1232 and WTL1233 in function, but the speeds are 1.7 times faster.

keywords:
32 Bit; 32-Bit floating-point processor; 34 MFLOPS; Arithmetic circuit; CIC81232Y; CIC81233Y; CMOS technology; Hierarchical design parallel circuits; Logic circuit; Multiplier; Three-stage pipeline

rawabstract:
A 34-MFLOP 32-bit floating-point processor in 2- mu m CMOS technology is presented. In order to achieve the high speed of floating-point operation, the authors use such techniques as hierarchical design parallel circuits, and a three-stage pipeline that has been optimized with equal delay in each stage. It is shown that the CIC81232Y (multiplier) and CIC81233Y (arithmetic and logic circuit) are fully compatible with WTL1232 and WTL1233 in function, but the speeds are 1.7 times faster.

rawauthor:
Song-Tine Wang and Chi-Suan Wang and Morries Wang and Shyh-Rurong Wang and Jhy-Kun Wang and Ching-Lu Hon and Row-Ming Yang and Wei-Hsiung Chuang and Te-Tsoung Tsai and Ming-Yuan Jang and Gwo-Jeng Pun

entry:
@InProceedings{Wang:1989:MBC,
  author =       "Song-Tine Wang and Chi-Suan Wang and Morries Wang and
                 Shyh-Rurong Wang and Jhy-Kun Wang and Ching-Lu Hon and
                 Row-Ming Yang and Wei-Hsiung Chuang and Te-Tsoung Tsai
                 and Ming-Yuan Jang and Gwo-Jeng Pun",
  title =        "A 34-{MFLOP} 32-bit {CMOS} floating point processor",
  crossref =     "IEEE:1989:ISV",
  pages =        "361--364",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 34-MFLOP 32-bit floating-point processor in 2- mu m
                 CMOS technology is presented. In order to achieve the
                 high speed of floating-point operation, the authors use
                 such techniques as hierarchical design parallel
                 circuits, and a three-stage pipeline that has been
                 optimized with equal delay in each stage. It is shown
                 that the CIC81232Y (multiplier) and CIC81233Y
                 (arithmetic and logic circuit) are fully compatible
                 with WTL1232 and WTL1233 in function, but the speeds
                 are 1.7 times faster.",
  acknowledgement = ack-nhfb,
  affiliation =  "Electron. Res and Service Organ., Hsing-Chu, Taiwan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "32 Bit; 32-Bit floating-point processor; 34 MFLOPS;
                 Arithmetic circuit; CIC81232Y; CIC81233Y; CMOS
                 technology; Hierarchical design parallel circuits;
                 Logic circuit; Multiplier; Three-stage pipeline",
  numericalindex = "Word length 3.2E+01 bit; Computer speed 3.4E+07
                 FLOPS",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: mastersthesis
filename: fparith.bib
label: Ward:1989:BFP
author: Kenneth L. Ward
title: A block floating point distributed arithmetic finite impulse response filter
type: Thesis (M.S.)
school: University of Florida
address: Gainesville, FL, USA
pages: 361--364
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital filters (Mathematics); Filters (Mathematics); Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Kenneth L. Ward
rawtitle: A block floating point distributed arithmetic finite impulse response filter
entry:
@MastersThesis{Ward:1989:BFP,
  author =       "Kenneth L. Ward",
  title =        "A block floating point distributed arithmetic finite
                 impulse response filter",
  type =         "Thesis ({M.S.})",
  school =       "University of Florida",
  address =      "Gainesville, FL, USA",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics); Filters (Mathematics);
                 Floating-point arithmetic.",
}


bibtype: article
filename: fparith.bib
label: Wichmann:1989:SPI
author: B. A. Wichmann
journal: j-SIGPLAN
volume: 24
number: 6
pages: 20--22
month: jun
monthnumber: 6
year: 1989
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:40 MST 2003
bibsource: Compendex database; http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:15:40 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliationaddress: Teddington, Engl
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
rawauthor: B. A. Wichmann
title:
Scientific processing in ISO-Pascal: a proposal to get the benefits of mixed precision floating-point

abstract:
Although Pascal is a very popular language for teaching and for use on microprocessors, it has not been very successful for scientific calculations. Apart from the pre-eminence of FORTRAN in this application area, several technical defects in Pascal have inhibited its use. One defect has been the problem in Pascal as defined by Jensen and Wirth of the inability to handle arrays of varying size as parameters to procedures. The level 1 option in ISO-Pascal addressed this defect by means of conformant arrays, albeit in a somewhat inelegant fashion. Array handling in ISO-Pascal can now be regarded as adequate since level 1 validated compilers are available for the majority of widely available machines. This note addresses another defect of Pascal, that no facility is provided to handle floating point types of more than one precision.

keywords:
algorithms; Computer Programming Languages; design; Floating Point Computation; iso-pascal; languages; pascal; Scientific Computing; standardization; Standards

subject:
D.2.1 Software, SOFTWARE ENGINEERING, Requirements/Specifications D.3.2 Software, PROGRAMMING LANGUAGES, Language Classifications, Pascal E.1 Data, DATA STRUCTURES, Arrays

rawabstract:
Although Pascal is a very popular language for teaching and for use on microprocessors, it has not been very successful for scientific calculations. Apart from the pre-eminence of FORTRAN in this application area, several technical defects in Pascal have inhibited its use. One defect has been the problem in Pascal as defined by Jensen and Wirth of the inability to handle arrays of varying size as parameters to procedures. The level 1 option in ISO-Pascal addressed this defect by means of conformant arrays, albeit in a somewhat inelegant fashion. Array handling in ISO-Pascal can now be regarded as adequate since level 1 validated compilers are available for the majority of widely available machines. This note addresses another defect of Pascal, that no facility is provided to handle floating point types of more than one precision.

rawtitle:
Scientific processing in {ISO-Pascal}: a proposal to get the benefits of mixed precision floating-point

entry:
@Article{Wichmann:1989:SPI,
  author =       "B. A. Wichmann",
  title =        "Scientific processing in {ISO-Pascal}: a proposal to
                 get the benefits of mixed precision floating-point",
  journal =      j-SIGPLAN,
  volume =       "24",
  number =       "6",
  pages =        "20--22",
  month =        jun,
  year =         "1989",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:40 MST 2003",
  bibsource =    "Compendex database; http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Although Pascal is a very popular language for
                 teaching and for use on microprocessors, it has not
                 been very successful for scientific calculations. Apart
                 from the pre-eminence of FORTRAN in this application
                 area, several technical defects in Pascal have
                 inhibited its use. One defect has been the problem in
                 Pascal as defined by Jensen and Wirth of the inability
                 to handle arrays of varying size as parameters to
                 procedures. The level 1 option in ISO-Pascal addressed
                 this defect by means of conformant arrays, albeit in a
                 somewhat inelegant fashion. Array handling in
                 ISO-Pascal can now be regarded as adequate since level
                 1 validated compilers are available for the majority of
                 widely available machines. This note addresses another
                 defect of Pascal, that no facility is provided to
                 handle floating point types of more than one
                 precision.",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Teddington, Engl",
  classification = "723; 902",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "algorithms; Computer Programming Languages; design;
                 Floating Point Computation; iso-pascal; languages;
                 pascal; Scientific Computing; standardization;
                 Standards",
  subject =      "D.2.1 Software, SOFTWARE ENGINEERING,
                 Requirements/Specifications \\ D.3.2 Software,
                 PROGRAMMING LANGUAGES, Language Classifications, Pascal
                 \\ E.1 Data, DATA STRUCTURES, Arrays",
}


bibtype: article
filename: fparith.bib
label: Wichmann:1989:TFS
author: B. A. Wichmann
title: Towards a formal specification of floating point
journal: j-COMP-J
volume: 32
number: 5
pages: 432--436
month: oct
monthnumber: 10
year: 1989
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
MRclass: 65G99 (65Y10)
MRnumber: 91b:65055
bibdate: Wed Dec 13 18:44:32 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.13 18:44:32 ???
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Department of Trade and Ind., NPL, Teddington, UK
corpsource: Department of Trade and Ind., NPL, Teddington, UK
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Digital arithmetic; Formal specification
treatment: P Practical
rawauthor: B. A. Wichmann
rawtitle: Towards a formal specification of floating point
abstract:
Although the concept of floating point is well understood, a formal mathematical treatment appears to be new. The paper presents a formal definition of floating point using the Vienna Development Method (VDM). The relationship between this definition and the informal definition in the Ada Standard and the work of W. S. Brown (1981) is discussed.

keywords:
digital arithmetic; Floating point; floating point; Formal specification; formal specification; Method; Vienna Development; Vienna Development Method

rawabstract:
Although the concept of floating point is well understood, a formal mathematical treatment appears to be new. The paper presents a formal definition of floating point using the Vienna Development Method (VDM). The relationship between this definition and the informal definition in the Ada Standard and the work of W. S. Brown (1981) is discussed.

entry:
@Article{Wichmann:1989:TFS,
  author =       "B. A. Wichmann",
  title =        "Towards a formal specification of floating point",
  journal =      j-COMP-J,
  volume =       "32",
  number =       "5",
  pages =        "432--436",
  month =        oct,
  year =         "1989",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  MRclass =      "65G99 (65Y10)",
  MRnumber =     "91b:65055",
  bibdate =      "Wed Dec 13 18:44:32 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Although the concept of floating point is well
                 understood, a formal mathematical treatment appears to
                 be new. The paper presents a formal definition of
                 floating point using the Vienna Development Method
                 (VDM). The relationship between this definition and the
                 informal definition in the Ada Standard and the work of
                 W. S. Brown (1981) is discussed.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Trade and Ind., NPL, Teddington, UK",
  classification = "C5230 (Digital arithmetic methods); C6110B (Software
                 engineering techniques)",
  corpsource =   "Department of Trade and Ind., NPL, Teddington, UK",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "digital arithmetic; Floating point; floating point;
                 Formal specification; formal specification; Method;
                 Vienna Development; Vienna Development Method",
  pubcountry =   "UK",
  thesaurus =    "Digital arithmetic; Formal specification",
  treatment =    "P Practical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Wittman:1989:SCU
author: Susan Jean Wittman
title: Servo compensation using a floating point digital signal processor
type: Thesis (M.S.)
school: Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics
address: Cambridge, MA, USA
pages: 60
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
note: Supervised by James K. Roberge
acknowledgement: ack-nhfb
rawauthor: Susan Jean Wittman
rawnote: Supervised by James K. Roberge
rawtitle: Servo compensation using a floating point digital signal processor
entry:
@MastersThesis{Wittman:1989:SCU,
  author =       "Susan Jean Wittman",
  title =        "Servo compensation using a floating point digital
                 signal processor",
  type =         "Thesis ({M.S.})",
  school =       "Massachusetts Institute of Technology, Dept. of
                 Aeronautics and Astronautics",
  address =      "Cambridge, MA, USA",
  pages =        "60",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Supervised by James K. Roberge",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Zeng:1989:RNP
author: B. Zeng and Y. Neuvo
booktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
title: Roundoff noise properties of lattice filters employing floating-point arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 233--237
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: B. Zeng and Y. Neuvo
rawbooktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
rawtitle: Roundoff noise properties of lattice filters employing floating-point arithmetic
entry:
@InProceedings{Zeng:1989:RNP,
  author =       "B. Zeng and Y. Neuvo",
  booktitle =    "European Conference on Circuit Theory and Design, 5--8
                 Sep 1989",
  title =        "Roundoff noise properties of lattice filters employing
                 floating-point arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "233--237",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The roundoff noise properties of general lattice
                 filters are studied for floating-point implementations
                 using the concept of dummy multipliers. The main
                 efforts are devoted to the Gray-Markel recursive
                 structures. It is shown that the roundoff noise
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Zorpette:1989:PGD
author: Glenn Zorpette
title: Parkinson's gun director
journal: j-IEEE-SPECTRUM
volume: 26
number: 4
pages: 43--43
month: apr
monthnumber: 4
year: 1989
CODEN: IEESAM
DOI: https://doi.org/10.1109/6.24154
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Mon Jan 20 06:41:24 2020
bibtimestamp: 2020.01.20 06:41:24 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: Glenn Zorpette
rawtitle: {Parkinson}'s gun director
keywords:
antiaircraft guns; Arithmetic; Automatic control; Cities and towns; controllers; Crystallization; electromechanical system; gun director; Guns; Laboratories; M-9; magnetic clutches; operational amplifiers; Operational amplifiers; position control; potentiometer; Psychology; Springs; Telephony; weapons

entry:
@Article{Zorpette:1989:PGD,
  author =       "Glenn Zorpette",
  title =        "{Parkinson}'s gun director",
  journal =      j-IEEE-SPECTRUM,
  volume =       "26",
  number =       "4",
  pages =        "43--43",
  month =        apr,
  year =         "1989",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/6.24154",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Mon Jan 20 06:41:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum1980.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "antiaircraft guns; Arithmetic; Automatic control;
                 Cities and towns; controllers; Crystallization;
                 electromechanical system; gun director; Guns;
                 Laboratories; M-9; magnetic clutches; operational
                 amplifiers; Operational amplifiers; position control;
                 potentiometer; Psychology; Springs; Telephony;
                 weapons",
}


bibtype: article
filename: fparith.bib
label: Alsup:1990:MFA
author: M. Alsup
title: Motorola's 88000 Family Architecture
journal: j-IEEE-MICRO
volume: 10
number: 3
pages: 48--66
month: may
monthnumber: 5
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.56325
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Wed Sep 7 22:32:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:42 ???
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: M. Alsup
rawtitle: {Motorola}'s 88000 Family Architecture
entry:
@Article{Alsup:1990:MFA,
  author =       "M. Alsup",
  title =        "{Motorola}'s 88000 Family Architecture",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "48--66",
  month =        may # "\slash " # jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.56325",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1990:MUF
author: Anonymous
title: Motorola unveils 96002 floating point processor
journal: Integrated circuits international
pages: 3--??
month: jul
monthnumber: 7
year: 1990
ISSN: 0263-6522 OR 02636522
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Motorola} unveils 96002 floating point processor
entry:
@Article{Anonymous:1990:MUF,
  author =       "Anonymous",
  title =        "{Motorola} unveils 96002 floating point processor",
  journal =      "Integrated circuits international",
  pages =        "3--??",
  month =        jul,
  year =         "1990",
  ISSN =         "0263-6522",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: mastersthesis
filename: fparith.bib
label: Ansari:1990:MBF
author: Ahmad Ansari
title: A $ 3 times 3 $ multipurpose bus-connected floating-point array processor
type: Thesis (M.S.)
school: University of Florida
address: Gainesville, FL, USA
pages: vi + 127
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Ahmad Ansari
rawtitle: A $ 3 \times 3 $ multipurpose bus-connected floating-point array processor
entry:
@MastersThesis{Ansari:1990:MBF,
  author =       "Ahmad Ansari",
  title =        "A $ 3 \times 3 $ multipurpose bus-connected
                 floating-point array processor",
  type =         "Thesis ({M.S.})",
  school =       "University of Florida",
  address =      "Gainesville, FL, USA",
  pages =        "vi + 127",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Arnold:1990:RLA
author: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
title: Redundant logarithmic arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 1077--1086
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57046
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:03 MDT 2011
bibtimestamp: 2011.07.07 14:20:03 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57046
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Wyoming University, Laramie, WY, USA
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Number theory; Redundancy; Table lookup
rawauthor: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
rawtitle: Redundant logarithmic arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

abstract:
A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic.

keywords:
29-Bit redundant logarithmic unit; 32 Bit subtraction; Arithmetic unit; Data values; Division; Ill-conditioned; Iterated multiplications; Memory requirement; Online arithmetic; Redundant logarithmic arithmetic; Redundant logarithmic number system; Square root; Storage requirements; Table lookups

rawabstract:
A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic.

entry:
@Article{Arnold:1990:RLA,
  author =       "M. G. Arnold and T. A. Bailey and J. R. Cowles and J.
                 J. Cupal",
  title =        "Redundant logarithmic arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "1077--1086",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57046",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:03 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57046",
  abstract =     "A number system that offers advantages in some
                 situations over conventional floating point and
                 sign/logarithmic number systems is described. Redundant
                 logarithmic arithmetic, like conventional logarithmic
                 arithmetic, relies on table lookups to make the
                 arithmetic unit simpler than an equivalent floating
                 point unit. The cost of 32 bit subtraction in a
                 redundant logarithmic number system is lower than
                 previously published logarithmic subtraction methods.
                 The total memory requirement for a 29-bit redundant
                 logarithmic unit is 16 K words compared to 22 K words
                 by the best previously published conventional sign
                 logarithm unit, assuming similar addition techniques
                 are employed. A redundant logarithmic number system can
                 be implemented with online arithmetic, which would be
                 impractical for a conventional sign logarithm number
                 system. The disadvantages of redundant arithmetic are
                 typical of redundant number systems. First, the
                 redundancy doubles the storage requirements for data
                 values. Second, the representation can become
                 ill-conditioned, especially as a result of iterated
                 multiplications. Third, division and square root
                 operations are more difficult to implement in redundant
                 logarithmic arithmetic.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Wyoming University,
                 Laramie, WY, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C1160 (Combinatorial mathematics); C1210B
                 (Reliability theory); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "29-Bit redundant logarithmic unit; 32 Bit subtraction;
                 Arithmetic unit; Data values; Division;
                 Ill-conditioned; Iterated multiplications; Memory
                 requirement; Online arithmetic; Redundant logarithmic
                 arithmetic; Redundant logarithmic number system; Square
                 root; Storage requirements; Table lookups",
  thesaurus =    "Digital arithmetic; Number theory; Redundancy; Table
                 lookup",
}


bibtype: article
filename: fparith.bib
label: Aspray:1990:BBS
author: William Aspray
title: Back to Basics: The Stored Program Concept
journal: j-IEEE-SPECTRUM
volume: 27
number: 9
pages: 51--51
month: sep
monthnumber: 9
year: 1990
CODEN: IEESAM
DOI: https://doi.org/10.1109/6.58457
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Wed Jan 15 12:40:28 2020
bibtimestamp: 2020.01.15 12:40:28 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: William Aspray
rawtitle: Back to Basics: The Stored Program Concept
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib; https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum1990.bib

abstract:
The history and early development of the stored program concept are briefly described. This refers to the ability of a calculating machine to store its instructions in its internal memory and process them in its arithmetic unit, so that in the course of a computation they may be not just executed but also modified at electronic speeds. John von Neumann, a faculty member of the Institute for Advanced Study in Princeton, NJ, participated in the discussions in which the idea was elaborated, wrote the first report of the concept, placed it in a theoretical context, and built his own computer, which was the early model for a number of others, including the important commercially manufactured IBM 701. J. Presper Eckert and John Mauchly perhaps first conceived of the stored program concept and developed most of the plans for implementing it in the Edvac, and later incorporated it in the Univac and other computers produced by their company. Several British computer scientists, notably Maurice Wilkes, were the first to implement the idea in machines initially designed to embody this feature.

keywords:
arithmetic unit; calculating machine; Computer aided instruction; Computer aided manufacturing; Computer architecture; Context modeling; Digital arithmetic; file organisation; history; History; internal memory; Laboratories; Military computing; Prototypes; storage allocation; stored program concept; Virtual manufacturing

rawabstract:
The history and early development of the stored program concept are briefly described. This refers to the ability of a calculating machine to store its instructions in its internal memory and process them in its arithmetic unit, so that in the course of a computation they may be not just executed but also modified at electronic speeds. John von Neumann, a faculty member of the Institute for Advanced Study in Princeton, NJ, participated in the discussions in which the idea was elaborated, wrote the first report of the concept, placed it in a theoretical context, and built his own computer, which was the early model for a number of others, including the important commercially manufactured IBM 701. J. Presper Eckert and John Mauchly perhaps first conceived of the stored program concept and developed most of the plans for implementing it in the Edvac, and later incorporated it in the Univac and other computers produced by their company. Several British computer scientists, notably Maurice Wilkes, were the first to implement the idea in machines initially designed to embody this feature.

entry:
@Article{Aspray:1990:BBS,
  author =       "William Aspray",
  title =        "Back to Basics: The Stored Program Concept",
  journal =      j-IEEE-SPECTRUM,
  volume =       "27",
  number =       "9",
  pages =        "51--51",
  month =        sep,
  year =         "1990",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/6.58457",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Wed Jan 15 12:40:28 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum1990.bib",
  abstract =     "The history and early development of the stored
                 program concept are briefly described. This refers to
                 the ability of a calculating machine to store its
                 instructions in its internal memory and process them in
                 its arithmetic unit, so that in the course of a
                 computation they may be not just executed but also
                 modified at electronic speeds. John von Neumann, a
                 faculty member of the Institute for Advanced Study in
                 Princeton, NJ, participated in the discussions in which
                 the idea was elaborated, wrote the first report of the
                 concept, placed it in a theoretical context, and built
                 his own computer, which was the early model for a
                 number of others, including the important commercially
                 manufactured IBM 701. J. Presper Eckert and John
                 Mauchly perhaps first conceived of the stored program
                 concept and developed most of the plans for
                 implementing it in the Edvac, and later incorporated it
                 in the Univac and other computers produced by their
                 company. Several British computer scientists, notably
                 Maurice Wilkes, were the first to implement the idea in
                 machines initially designed to embody this feature.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "arithmetic unit; calculating machine; Computer aided
                 instruction; Computer aided manufacturing; Computer
                 architecture; Context modeling; Digital arithmetic;
                 file organisation; history; History; internal memory;
                 Laboratories; Military computing; Prototypes; storage
                 allocation; stored program concept; Virtual
                 manufacturing",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajwa:1990:FFP
author: A. Bajwa and R. Steck
title: A fast floating point unit in the i960 general-purpose embedded processor family
crossref: Wescon:1990:WCR
pages: 218--222
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Intel Corp., Hillsboro, OR, USA
thesaurus: Computer architecture; Digital arithmetic; Microprocessor chips; Reduced instruction set computing
rawauthor: A. Bajwa and R. Steck
rawtitle: A fast floating point unit in the i960 general-purpose embedded processor family
abstract:
Fast, cheap floating point arithmetic is required in many embedded processor applications. This paper describes a next-generation floating point unit designed as an integrated functional unit on Intel's i960 family of 32-bit embedded RISC processors. High performance is achieved by utilizing two separate, concurrent floating point execution units with wide datapaths, both internally and to general-purpose registers. Hardware system cost is reduced by integrating the FPU on the main processor while software development cost is minimized by using the i960 Numerics Architecture supported by standard i960 family development tools.

keywords:
32 Bit; 32-Bit embedded RISC processors; Concurrent floating point execution units; Embedded processor applications; Fast floating point unit; Floating point arithmetic; FPU; General-purpose embedded processor family; General-purpose registers; I960; I960 family; I960 Numerics Architecture; Integrated functional unit; Intel; Wide datapaths

rawabstract:
Fast, cheap floating point arithmetic is required in many embedded processor applications. This paper describes a next-generation floating point unit designed as an integrated functional unit on Intel's i960 family of 32-bit embedded RISC processors. High performance is achieved by utilizing two separate, concurrent floating point execution units with wide datapaths, both internally and to general-purpose registers. Hardware system cost is reduced by integrating the FPU on the main processor while software development cost is minimized by using the i960 Numerics Architecture supported by standard i960 family development tools.

entry:
@InProceedings{Bajwa:1990:FFP,
  author =       "A. Bajwa and R. Steck",
  title =        "A fast floating point unit in the i960 general-purpose
                 embedded processor family",
  crossref =     "Wescon:1990:WCR",
  pages =        "218--222",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Fast, cheap floating point arithmetic is required in
                 many embedded processor applications. This paper
                 describes a next-generation floating point unit
                 designed as an integrated functional unit on Intel's
                 i960 family of 32-bit embedded RISC processors. High
                 performance is achieved by utilizing two separate,
                 concurrent floating point execution units with wide
                 datapaths, both internally and to general-purpose
                 registers. Hardware system cost is reduced by
                 integrating the FPU on the main processor while
                 software development cost is minimized by using the
                 i960 Numerics Architecture supported by standard i960
                 family development tools.",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp., Hillsboro, OR, USA",
  availability = "Western Periodicals Co., 13000 Rayner Street, North
                 Hollywood, CA 91605, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5230 (Digital arithmetic methods)",
  keywords =     "32 Bit; 32-Bit embedded RISC processors; Concurrent
                 floating point execution units; Embedded processor
                 applications; Fast floating point unit; Floating point
                 arithmetic; FPU; General-purpose embedded processor
                 family; General-purpose registers; I960; I960 family;
                 I960 Numerics Architecture; Integrated functional unit;
                 Intel; Wide datapaths",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Computer architecture; Digital arithmetic;
                 Microprocessor chips; Reduced instruction set
                 computing",
}


bibtype: techreport
filename: fparith.bib
label: Barlow:1990:EAU
author: Jesse Louis Barlow and Richard J. Zaccone
title: Error analysis in unnormalized floating point arithmetic
type: Technical report
number: CS-90-23
institution: Pennsylvania State University, Department of Computer Science
address: University Park, PA, USA
pages: 9
month: apr
monthnumber: 4
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer arithmetic.; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Jesse Louis Barlow and Richard J. Zaccone
rawtitle: Error analysis in unnormalized floating point arithmetic
note:
Supported by the Air Force Office of Scientific Research. Supported by the National Science Foundation. Supported by the Office of Naval Research.

abstract:
The need to construct architectures in VLSI has focused attention on unnormalized floating point arithmetic. Certain unnormalized arithmetics allow one to `pipe on digits,' thus producing significant speed up in computation and making the input problems of special purpose devices such as systolic arrays easier to solve. We consider the error analysis implications of using unnormalized arithmetic in numerical algorithms. We also give specifications for its implementation. Our discussion centers on the example of Gaussian elimination. We show that the use of unnormalized arithmetic requires changes in the analysis of this algorithm. We will show that only for certain classes of matrices that include diagonally dominant matrices (either row or column), Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic. However, if the diagonal elements of the upper triangular matrix are post normalized, then Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic for all matrices.

rawabstract:
The need to construct architectures in VLSI has focused attention on unnormalized floating point arithmetic. Certain unnormalized arithmetics allow one to `pipe on digits,' thus producing significant speed up in computation and making the input problems of special purpose devices such as systolic arrays easier to solve. We consider the error analysis implications of using unnormalized arithmetic in numerical algorithms. We also give specifications for its implementation. Our discussion centers on the example of Gaussian elimination. We show that the use of unnormalized arithmetic requires changes in the analysis of this algorithm. We will show that only for certain classes of matrices that include diagonally dominant matrices (either row or column), Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic. However, if the diagonal elements of the upper triangular matrix are post normalized, then Gaussian elimination is as stable in unnormalized arithmetic as in normalized arithmetic for all matrices.

rawnote:
Supported by the Air Force Office of Scientific Research. Supported by the National Science Foundation. Supported by the Office of Naval Research.

entry:
@TechReport{Barlow:1990:EAU,
  author =       "Jesse Louis Barlow and Richard J. Zaccone",
  title =        "Error analysis in unnormalized floating point
                 arithmetic",
  type =         "Technical report",
  number =       "CS-90-23",
  institution =  "Pennsylvania State University, Department of Computer
                 Science",
  address =      "University Park, PA, USA",
  pages =        "9",
  month =        apr,
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Supported by the Air Force Office of Scientific
                 Research. Supported by the National Science Foundation.
                 Supported by the Office of Naval Research.",
  abstract =     "The need to construct architectures in VLSI has
                 focused attention on unnormalized floating point
                 arithmetic. Certain unnormalized arithmetics allow one
                 to `pipe on digits,' thus producing significant speed
                 up in computation and making the input problems of
                 special purpose devices such as systolic arrays easier
                 to solve. We consider the error analysis implications
                 of using unnormalized arithmetic in numerical
                 algorithms. We also give specifications for its
                 implementation. Our discussion centers on the example
                 of Gaussian elimination. We show that the use of
                 unnormalized arithmetic requires changes in the
                 analysis of this algorithm. We will show that only for
                 certain classes of matrices that include diagonally
                 dominant matrices (either row or column), Gaussian
                 elimination is as stable in unnormalized arithmetic as
                 in normalized arithmetic. However, if the diagonal
                 elements of the upper triangular matrix are post
                 normalized, then Gaussian elimination is as stable in
                 unnormalized arithmetic as in normalized arithmetic for
                 all matrices.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer arithmetic.; Floating-point arithmetic.",
}


bibtype: mastersthesis
filename: fparith.bib
label: Bhargava:1990:DFP
author: Ish Kumar Bhargava
title: Design of a floating point data acquisition system and a development system for the NC 4016
type: Electrical Engineering Thesis (M.S.)
school: University of Missouri--Rolla
address: Rolla, MO, USA
pages: ix + 107
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Ish Kumar Bhargava
rawtitle: Design of a floating point data acquisition system and a development system for the {NC} 4016
entry:
@MastersThesis{Bhargava:1990:DFP,
  author =       "Ish Kumar Bhargava",
  title =        "Design of a floating point data acquisition system and
                 a development system for the {NC} 4016",
  type =         "Electrical Engineering Thesis ({M.S.})",
  school =       "University of Missouri--Rolla",
  address =      "Rolla, MO, USA",
  pages =        "ix + 107",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Birman:1990:DWS
title: Developing the WTL3170 / 3171 Sparc Floating-Point Coprocessors
journal: j-IEEE-MICRO
volume: 10
number: 1
pages: 55--64
month: jan
monthnumber: 1
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.46769
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawtitle: Developing the {WTL3170\slash 3171 Sparc} Floating-Point Coprocessors
author:
Mark Birman and Allen Samuels and George Chu and Chuk Ting and Larry Hu and John McLeod and John Barnes

abstract:
Contending with dual floating-point interfaces at both 25 and 40 MHz posed an extraordinary challenge in coprocessor development.

rawabstract:
Contending with dual floating-point interfaces at both 25 and 40 MHz posed an extraordinary challenge in coprocessor development.

rawauthor:
Mark Birman and Allen Samuels and George Chu and Chuk Ting and Larry Hu and John McLeod and John Barnes

entry:
@Article{Birman:1990:DWS,
  author =       "Mark Birman and Allen Samuels and George Chu and Chuk
                 Ting and Larry Hu and John McLeod and John Barnes",
  title =        "Developing the {WTL3170\slash 3171 Sparc}
                 Floating-Point Coprocessors",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "1",
  pages =        "55--64",
  month =        jan # "\slash " # feb,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.46769",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Contending with dual floating-point interfaces at both
                 25 and 40 MHz posed an extraordinary challenge in
                 coprocessor development.",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "The development of the first two members in a family
                 of scalable-processor-architecture (Sparc)-compatible
                 parts is described. With varying frequency and latency
                 performance, the chips work with the first two integer
                 unit (IU) implementations from \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Blevins:1990:BHI
author: D. W. Blevins and E. W. Davis and R. A. Heaton and J. H. Feif
title: BLITZEN: a Highly Integrated Massively Parallel Machine
journal: j-J-PAR-DIST-COMP
volume: 8
number: 2
pages: 150--160
month: feb
monthnumber: 2
year: 1990
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 17:13:17 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 17:13:17 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: P Practical
rawauthor: D. W. Blevins and E. W. Davis and R. A. Heaton and J. H. Feif
rawtitle: {BLITZEN}: a Highly Integrated Massively Parallel Machine
keywords:
1.25 micron; 20 MHz; architecture; BLITZEN; CMOS design rules; CMOS integrated circuits; computer architecture; global; highly integrated massively parallel machine; IEEE standard 32-bit floating point; local control features; memory address; microprocessor chips; multiplication; parallel processing; static RAM; VLSI

entry:
@Article{Blevins:1990:BHI,
  author =       "D. W. Blevins and E. W. Davis and R. A. Heaton and J.
                 H. Feif",
  title =        "{BLITZEN}: a Highly Integrated Massively Parallel
                 Machine",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "8",
  number =       "2",
  pages =        "150--160",
  month =        feb,
  year =         "1990",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 17:13:17 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5440
                 (Multiprocessor systems and techniques)",
  corpsource =   "Microelectron. Center of North Carolina, Research
                 Triangle Park, NC, USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "1.25 micron; 20 MHz; architecture; BLITZEN; CMOS
                 design rules; CMOS integrated circuits; computer
                 architecture; global; highly integrated massively
                 parallel machine; IEEE standard 32-bit floating point;
                 local control features; memory address; microprocessor
                 chips; multiplication; parallel processing; static RAM;
                 VLSI",
  treatment =    "P Practical",
}


bibtype: inbook
filename: fparith.bib
label: Branham:1990:PFP
author: Richard L. Branham
booktitle: Scientific Data Analysis: An Introduction to Overdetermined Systems
title: Properties of Floating-Point Numbers
publisher: pub-SV
address: pub-SV:adr
pages: 1--19
year: 1990
DOI: https://doi.org/10.1007/978-1-4612-3362-6_1
ISBN: 1-4612-3362-3 (e-book), 1-4612-7981-X OR 1461233623 (ebook), 146127981X
ISBN13: 978-1-4612-3362-6 (e-book), 978-1-4612-7981-5 OR 9781461233626 (ebook), 9781461279815
LCCN: QA76.9.D35
bibdate: Sat Dec 31 11:59:38 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.12.31 11:59:38 ???
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
bookpages: x + 237 + 36
rawauthor: Richard L. Branham
rawbooktitle: Scientific Data Analysis: An Introduction to Overdetermined Systems
rawtitle: Properties of Floating-Point Numbers
remark:
This introductory chapter discusses floating-point arithmetic in VAX binary, IBM System / 360 hexadecimal, and Sharp pocket calculator decimal formats, but has no mention of IEEE 754 arithmetic. It discusses the failure in floating-point arithmetic of the associative, cancellation, and distributive laws of exact arithmetic. In the context of accurate floating-point summation, it describes Kahan's compensated summation algorithm, Linz' binary-subdivision summation algorithm, and Wolfe's cascaded accumulator algorithm, all implemented in Fortran code given in the chapter figures. It also treats the error in summation in rounded and truncated arithmetic, and mentions the importance of guard digits.

TOC:
Properties of Floating-Point Numbers Matrices, Norms, and Condition Numbers Sparse Matrices Introduction to Overdetermined Systems Linear Least Squares The L1 Method Nonlinear Methods The Singular Value Decomposition Index

rawTOC:
Properties of Floating-Point Numbers \\ Matrices, Norms, and Condition Numbers \\ Sparse Matrices \\ Introduction to Overdetermined Systems \\ Linear Least Squares \\ The L1 Method \\ Nonlinear Methods \\ The Singular Value Decomposition \\ Index

entry:
@InBook{Branham:1990:PFP,
  author =       "Richard L. Branham",
  booktitle =    "Scientific Data Analysis: An Introduction to
                 Overdetermined Systems",
  title =        "Properties of Floating-Point Numbers",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  bookpages =    "x + 237 + 36",
  pages =        "1--19",
  year =         "1990",
  DOI =          "https://doi.org/10.1007/978-1-4612-3362-6_1",
  ISBN =         "1-4612-3362-3 (e-book), 1-4612-7981-X",
  ISBN-13 =      "978-1-4612-3362-6 (e-book), 978-1-4612-7981-5",
  LCCN =         "QA76.9.D35",
  bibdate =      "Sat Dec 31 11:59:38 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
  remark =       "This introductory chapter discusses floating-point
                 arithmetic in VAX binary, IBM System\slash 360
                 hexadecimal, and Sharp pocket calculator decimal
                 formats, but has no mention of IEEE 754 arithmetic. It
                 discusses the failure in floating-point arithmetic of
                 the associative, cancellation, and distributive laws of
                 exact arithmetic. In the context of accurate
                 floating-point summation, it describes Kahan's
                 compensated summation algorithm, Linz'
                 binary-subdivision summation algorithm, and Wolfe's
                 cascaded accumulator algorithm, all implemented in
                 Fortran code given in the chapter figures. It also
                 treats the error in summation in rounded and truncated
                 arithmetic, and mentions the importance of guard
                 digits.",
  tableofcontents = "Properties of Floating-Point Numbers \\
                 Matrices, Norms, and Condition Numbers \\
                 Sparse Matrices \\
                 Introduction to Overdetermined Systems \\
                 Linear Least Squares \\
                 The L1 Method \\
                 Nonlinear Methods \\
                 The Singular Value Decomposition \\
                 Index",
}


bibtype: inproceedings
filename: fparith.bib
label: Buck:1990:PAN
author: P. D. Buck and S. L. Day and D. Gonzalez
title: Problems with Ada numeric routines
crossref: Anonymous:1990:PAN
pages: 195--204
year: 1990
bibdate: Tue Dec 12 09:20:21 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:20:21 MST
acknowledgement: ack-nhfb
affiliation: Nat. University, San Diego, CA, USA
thesaurus: Ada; Data structures; Digital arithmetic; Software portability; Symbol manipulation
rawauthor: P. D. Buck and S. L. Day and D. Gonzalez
rawtitle: Problems with {Ada} numeric routines
abstract:
Computer programmers believe that their systems will always perform as expected. Standardization of computer languages has been a major advance towards this goal. The Ada language was intended to further advance this goal by rigorously defining the language. In addition the language was intended to improve the portability of programs. The authors' experience shows that the definition of the Ada language does not ensure mathematical algorithms will function consistently across multiple hardware environments. The method used by the language designers to specify the floating point data types appears to be the cause of the problem.

keywords:
Ada; Floating point data types; Mathematical algorithms; Multiple hardware environments; Numeric routines; Portability

rawabstract:
Computer programmers believe that their systems will always perform as expected. Standardization of computer languages has been a major advance towards this goal. The Ada language was intended to further advance this goal by rigorously defining the language. In addition the language was intended to improve the portability of programs. The authors' experience shows that the definition of the Ada language does not ensure mathematical algorithms will function consistently across multiple hardware environments. The method used by the language designers to specify the floating point data types appears to be the cause of the problem.

entry:
@InProceedings{Buck:1990:PAN,
  author =       "P. D. Buck and S. L. Day and D. Gonzalez",
  title =        "Problems with {Ada} numeric routines",
  crossref =     "Anonymous:1990:PAN",
  pages =        "195--204",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Computer programmers believe that their systems will
                 always perform as expected. Standardization of computer
                 languages has been a major advance towards this goal.
                 The Ada language was intended to further advance this
                 goal by rigorously defining the language. In addition
                 the language was intended to improve the portability of
                 programs. The authors' experience shows that the
                 definition of the Ada language does not ensure
                 mathematical algorithms will function consistently
                 across multiple hardware environments. The method used
                 by the language designers to specify the floating point
                 data types appears to be the cause of the problem.",
  acknowledgement = ack-nhfb,
  affiliation =  "Nat. University, San Diego, CA, USA",
  classification = "C6120 (File organisation); C6130 (Data handling
                 techniques); C6140D (High level languages)",
  keywords =     "Ada; Floating point data types; Mathematical
                 algorithms; Multiple hardware environments; Numeric
                 routines; Portability",
  thesaurus =    "Ada; Data structures; Digital arithmetic; Software
                 portability; Symbol manipulation",
}


bibtype: article
filename: fparith.bib
label: Bursky:1990:FMC
author: D. Bursky
title: Floating-point math chip delivers 200 mflops peak
journal: j-ELECTRONIC-DESIGN
volume: 38
number: 4
pages: 51--52, 54, 55
month: feb
monthnumber: 2
year: 1990
CODEN: ELODAW
ISSN: 0013-4872 (print), 1944-9550 (electronic) OR 00134872 (print), 19449550 (electronic)
ISSNL: 0013-4872 OR 00134872
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: Electronic Design
acknowledgement: ack-nhfb
rawauthor: D. Bursky
rawtitle: Floating-point math chip delivers 200 mflops peak
abstract:
By exploiting its latest process improvements and a three-layer metal interconnection capability, Bipolar Integrated Technology has managed to boost floating-point throughput three- to five-fold over its previous-generation circuits. The new B3130, a single-chip double-precision floating-point processor with 64-bit data buses, can deliver up to 200 MFLOPS of peak throughput. With more than 55000 equivalent gates and multiple 64-bit data buses (plus eight parity bits on each bus), the chip is the highest-complexity ECL chip to be sold commercially. By employing a high degree of integration, the single chip packs a 64-bit ALU, a 54-bit parallel multiplier (for the mantissa), and a 64-bit divide/square root unit. The chip's architecture is optimized for vector processing, but it can also perform scalar calculations. In addition, the wide data buses and pipelining support eliminate the loading and unloading bottlenecks that frequently degrade chip performance.

keywords:
200 MFLOPS; 64 Bit; ALU; B3130; Bipolar Integrated Technology; Bipolar microprocessor; Divide/square root unit; Double-precision; ECL chip; Floating-point processor; Multiple data buses; Parallel multiplier; Pipelining support; Scalar calculations; Three-layer metal interconnection; Vector processing

thesaurus:
Bipolar integrated circuits; Digital arithmetic; Emitter-coupled logic; Microprocessor chips; Parallel architectures; Parallel machines; Pipeline processing; VLSI

rawabstract:
By exploiting its latest process improvements and a three-layer metal interconnection capability, Bipolar Integrated Technology has managed to boost floating-point throughput three- to five-fold over its previous-generation circuits. The new B3130, a single-chip double-precision floating-point processor with 64-bit data buses, can deliver up to 200 MFLOPS of peak throughput. With more than 55000 equivalent gates and multiple 64-bit data buses (plus eight parity bits on each bus), the chip is the highest-complexity ECL chip to be sold commercially. By employing a high degree of integration, the single chip packs a 64-bit ALU, a 54-bit parallel multiplier (for the mantissa), and a 64-bit divide/square root unit. The chip's architecture is optimized for vector processing, but it can also perform scalar calculations. In addition, the wide data buses and pipelining support eliminate the loading and unloading bottlenecks that frequently degrade chip performance.

entry:
@Article{Bursky:1990:FMC,
  author =       "D. Bursky",
  title =        "Floating-point math chip delivers 200 mflops peak",
  journal =      j-ELECTRONIC-DESIGN,
  volume =       "38",
  number =       "4",
  pages =        "51--52, 54, 55",
  month =        feb,
  year =         "1990",
  CODEN =        "ELODAW",
  ISSN =         "0013-4872 (print), 1944-9550 (electronic)",
  ISSN-L =       "0013-4872",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "By exploiting its latest process improvements and a
                 three-layer metal interconnection capability, Bipolar
                 Integrated Technology has managed to boost
                 floating-point throughput three- to five-fold over its
                 previous-generation circuits. The new B3130, a
                 single-chip double-precision floating-point processor
                 with 64-bit data buses, can deliver up to 200 MFLOPS of
                 peak throughput. With more than 55000 equivalent gates
                 and multiple 64-bit data buses (plus eight parity bits
                 on each bus), the chip is the highest-complexity ECL
                 chip to be sold commercially. By employing a high
                 degree of integration, the single chip packs a 64-bit
                 ALU, a 54-bit parallel multiplier (for the mantissa),
                 and a 64-bit divide/square root unit. The chip's
                 architecture is optimized for vector processing, but it
                 can also perform scalar calculations. In addition, the
                 wide data buses and pipelining support eliminate the
                 loading and unloading bottlenecks that frequently
                 degrade chip performance.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); B2570B
                 (Bipolar integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "Electronic Design",
  keywords =     "200 MFLOPS; 64 Bit; ALU; B3130; Bipolar Integrated
                 Technology; Bipolar microprocessor; Divide/square root
                 unit; Double-precision; ECL chip; Floating-point
                 processor; Multiple data buses; Parallel multiplier;
                 Pipelining support; Scalar calculations; Three-layer
                 metal interconnection; Vector processing",
  numericalindex = "Computer speed 2.0E+08 FLOPS; Word length 6.4E+01
                 bit",
  thesaurus =    "Bipolar integrated circuits; Digital arithmetic;
                 Emitter-coupled logic; Microprocessor chips; Parallel
                 architectures; Parallel machines; Pipeline processing;
                 VLSI",
}


bibtype: article
filename: fparith.bib
label: Carter:1990:RSD
author: T. M. Carter and J. E. Robertson
title: Radix-$ 16 $ signed-digit division
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 12
pages: 1424--1433
month: dec
monthnumber: 12
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.61063
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:05 MDT 2011
bibtimestamp: 2011.07.07 14:20:05 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=61063
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. M. Carter and J. E. Robertson
rawtitle: Radix-$ 16 $ signed-digit division
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

entry:
@Article{Carter:1990:RSD,
  author =       "T. M. Carter and J. E. Robertson",
  title =        "Radix-$ 16 $ signed-digit division",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "12",
  pages =        "1424--1433",
  month =        dec,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.61063",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:05 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=61063",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Carter:1990:STA
author: T. M. Carter and J. E. Robertson
title: The set theory of arithmetic decomposition
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 8
pages: 993--1005
month: aug
monthnumber: 8
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.57037
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:03 MDT 2011
bibtimestamp: 2011.07.07 14:20:03 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57037
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. M. Carter and J. E. Robertson
rawtitle: The set theory of arithmetic decomposition
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

entry:
@Article{Carter:1990:STA,
  author =       "T. M. Carter and J. E. Robertson",
  title =        "The set theory of arithmetic decomposition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "8",
  pages =        "993--1005",
  month =        aug,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.57037",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:03 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57037",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1990:DIH
author: J. T. Chen and W. K. Jenkins and I. A. Hein and W. D. O'Brien, Jr.
booktitle: IEEE International Symposium on Circuits and Systems, 1--3 May 1990
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2893--2896
year: 1990
DOI: https://doi.org/10.1109/ISCAS.1990.112615
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. T. Chen and W. K. Jenkins and I. A. Hein and W. D. {O'Brien, Jr.}
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 1--3 May 1990
title:
Design and implementation of a high speed residue number system correlator for ultrasonic time domain blood flow measurement

rawtitle:
Design and implementation of a high speed residue number system correlator for ultrasonic time domain blood flow measurement

entry:
@InProceedings{Chen:1990:DIH,
  author =       "J. T. Chen and W. K. Jenkins and I. A. Hein and W. D.
                 {O'Brien, Jr.}",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 1--3 May 1990",
  title =        "Design and implementation of a high speed residue
                 number system correlator for ultrasonic time domain
                 blood flow measurement",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2893--2896",
  year =         "1990",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1990.112615",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The design and operation of a high-speed residue
                 number system (RNS) digital correlator is presented for
                 implementing the correlation function in a real-time
                 ultrasonic blood flow measurement system. This
                 architecture allows for both high-speed \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chren:1990:NRN
author: W. A. Chren, Jr.
title: A new residue number system division algorithm
journal: j-COMPUT-MATH-APPL
volume: 19
number: 7
pages: 13--29
year: 1990
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 19:01:19 MST 2017
bibtimestamp: 2017.03.01 19:01:19 MST
URL: http://www.sciencedirect.com/science/article/pii/089812219090190U
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: W. A. {Chren, Jr.}
rawtitle: A new residue number system division algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/computmathappl1990.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Chren:1990:NRN,
  author =       "W. A. {Chren, Jr.}",
  title =        "A new residue number system division algorithm",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "19",
  number =       "7",
  pages =        "13--29",
  month =        "????",
  year =         "1990",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 19:01:19 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/089812219090190U",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Ciminiera:1990:HRS
author: L. Ciminiera and P. Montuschi
title: Higher radix square rooting
journal: j-IEEE-TRANS-COMPUT
volume: 39
number: 10
pages: 1220--1231
month: oct
monthnumber: 10
year: 1990
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.59853
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 14:20:04 MDT 2011
bibtimestamp: 2011.07.07 14:20:04 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=59853
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: L. Ciminiera and P. Montuschi
rawtitle: Higher radix square rooting
entry:
@Article{Ciminiera:1990:HRS,
  author =       "L. Ciminiera and P. Montuschi",
  title =        "Higher radix square rooting",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "39",
  number =       "10",
  pages =        "1220--1231",
  month =        oct,
  year =         "1990",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.59853",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 14:20:04 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=59853",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "A general discussion on nonrestoring square root
                 algorithms is presented, showing bounds and constraints
                 delimiting the space of feasible algorithms, for all
                 the choices of radix, digit set and representation of
                 the partial remainder. Two classes of \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Clinger:1990:HRF
author: William D. Clinger
title: How to Read Floating Point Numbers Accurately
journal: j-SIGPLAN
volume: 25
number: 6
pages: 92--101
month: jun
monthnumber: 6
year: 1990
CODEN: SINODQ
DOI: https://doi.org/10.1145/93548.93557
ISBN: 0-89791-364-7 OR 0897913647
ISBN13: 978-0-89791-364-5 OR 9780897913645
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:53 MST 2003
bibtimestamp: 2003.12.14 09:15:53 MST
URL: http://www.acm.org:80/pubs/citations/proceedings/pldi/93542/p92-clinger/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Oregon University, Eugene, OR, USA
annote: Published as part of the Proceedings of PLDI'90.
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
thesaurus: Digital arithmetic; Mathematics computing; Number theory; Standards
rawauthor: William D. Clinger
rawtitle: How to Read Floating Point Numbers Accurately
bibsource:
Compendex database; ftp://garbo.uwasa.fi/pc/doc-soft/fpbiblio.txt; http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/pldi/93542/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigplan1990.bib

note:
See also output algorithms in cite Knuth:1990:SPW,Steele:1990:HPF,Burger:1996:PFP,Abbott:1999:ASS,Steele:2004:RHP.

abstract:
Consider the problem of converting decimal scientific notation for a number into the best binary floating point approximation to that number, for some fixed precision. This problem cannot be solved using arithmetic of any fixed precision. Hence the IEEE Standard for Binary Floating-Point Arithmetic does not require the result of such a conversion to be the best approximation. This paper presents an efficient algorithm that always finds the best approximation. The algorithm uses a few extra bits of precision to compute an IEEE-conforming approximation while testing an intermediate result to determine whether the approximation could be other than the best. If the approximation might not be the best, then the best approximation is determined by a few simple operations on multiple-precision integers, where the precision is determined by the input. When using 64 bits of precision to compute IEEE double precision results, the algorithm avoids higher-precision arithmetic over 99% of the time.

keywords:
algorithms; Best binary floating point approximation; Computer Programming Languages; Computers, Digital --- Computational Methods; Decimal scientific notation; Design; Efficient algorithm; experimentation; Fixed precision; Floating point numbers; Floating Point Numbers; Higher-precision arithmetic; IEEE double precision results; IEEE Standard; IEEE-conforming approximation; Intermediate result; Multiple-precision integers

subject:
bf F.2.1 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms and Problems. bf G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf G.1.2 Mathematics of Computing, NUMERICAL ANALYSIS, Approximation.

rawabstract:
Consider the problem of converting decimal scientific notation for a number into the best binary floating point approximation to that number, for some fixed precision. This problem cannot be solved using arithmetic of any fixed precision. Hence the IEEE Standard for Binary Floating-Point Arithmetic does not require the result of such a conversion to be the best approximation. This paper presents an efficient algorithm that always finds the best approximation. The algorithm uses a few extra bits of precision to compute an IEEE-conforming approximation while testing an intermediate result to determine whether the approximation could be other than the best. If the approximation might not be the best, then the best approximation is determined by a few simple operations on multiple-precision integers, where the precision is determined by the input. When using 64 bits of precision to compute IEEE double precision results, the algorithm avoids higher-precision arithmetic over 99\% of the time.

rawnote:
See also output algorithms in \cite{Knuth:1990:SPW,Steele:1990:HPF,Burger:1996:PFP,Abbott:1999:ASS,Steele:2004:RHP}.

entry:
@Article{Clinger:1990:HRF,
  author =       "William D. Clinger",
  title =        "How to Read Floating Point Numbers Accurately",
  journal =      j-SIGPLAN,
  volume =       "25",
  number =       "6",
  pages =        "92--101",
  month =        jun,
  year =         "1990",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/93548.93557",
  ISBN =         "0-89791-364-7",
  ISBN-13 =      "978-0-89791-364-5",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:53 MST 2003",
  bibsource =    "Compendex database;
                 ftp://garbo.uwasa.fi/pc/doc-soft/fpbiblio.txt;
                 http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/pldi/93542/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan1990.bib",
  note =         "See also output algorithms in
                 \cite{Knuth:1990:SPW,Steele:1990:HPF,Burger:1996:PFP,Abbott:1999:ASS,Steele:2004:RHP}.",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/pldi/93542/p92-clinger/",
  abstract =     "Consider the problem of converting decimal scientific
                 notation for a number into the best binary floating
                 point approximation to that number, for some fixed
                 precision. This problem cannot be solved using
                 arithmetic of any fixed precision. Hence the IEEE
                 Standard for Binary Floating-Point Arithmetic does not
                 require the result of such a conversion to be the best
                 approximation. This paper presents an efficient
                 algorithm that always finds the best approximation. The
                 algorithm uses a few extra bits of precision to compute
                 an IEEE-conforming approximation while testing an
                 intermediate result to determine whether the
                 approximation could be other than the best. If the
                 approximation might not be the best, then the best
                 approximation is determined by a few simple operations
                 on multiple-precision integers, where the precision is
                 determined by the input. When using 64 bits of
                 precision to compute IEEE double precision results, the
                 algorithm avoids higher-precision arithmetic over 99\%
                 of the time.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Oregon University, Eugene, OR, USA",
  annote =       "Published as part of the Proceedings of PLDI'90.",
  classification = "722; 723; C1160 (Combinatorial mathematics); C5230
                 (Digital arithmetic methods); C7310 (Mathematics)",
  confdate =     "20-22 June 1990",
  conference =   "Proceedings of the ACM SIGPLAN '90 Conference on
                 Programming Language Design and Implementation",
  conferenceyear = "1990",
  conflocation = "White Plains, NY, USA",
  confsponsor =  "ACM",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "algorithms; Best binary floating point approximation;
                 Computer Programming Languages; Computers, Digital ---
                 Computational Methods; Decimal scientific notation;
                 Design; Efficient algorithm; experimentation; Fixed
                 precision; Floating point numbers; Floating Point
                 Numbers; Higher-precision arithmetic; IEEE double
                 precision results; IEEE Standard; IEEE-conforming
                 approximation; Intermediate result; Multiple-precision
                 integers",
  meetingaddress = "White Plains, NY, USA",
  meetingdate =  "Jun 20--22 1990",
  meetingdate2 = "06/20--22/90",
  sponsor =      "Assoc for Computing Machinery, Special Interest Group
                 on Programming Languages",
  subject =      "{\bf F.2.1} Theory of Computation, ANALYSIS OF
                 ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms
                 and Problems. {\bf G.1.0} Mathematics of Computing,
                 NUMERICAL ANALYSIS, General, Computer arithmetic. {\bf
                 G.1.2} Mathematics of Computing, NUMERICAL ANALYSIS,
                 Approximation.",
  thesaurus =    "Digital arithmetic; Mathematics computing; Number
                 theory; Standards",
}


bibtype: article
filename: fparith.bib
label: Codenotti:1990:ATT
author: B. Codenotti and G. Lotti and F. Romani
title: Area-time trade-offs for matrix-vector multiplication
journal: j-J-PAR-DIST-COMP
volume: 8
number: 1
pages: 52--59
month: jan
monthnumber: 1
year: 1990
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliation: Inst di Elaborazione dell'Informazione-CNR
affiliationaddress: Pisa, Italy
corpsource: Istituto di Elaborazione dell'Inf., CNR, Pisa, Italy
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: T Theoretical or Mathematical
rawauthor: B. Codenotti and G. Lotti and F. Romani
rawtitle: Area-time trade-offs for matrix-vector multiplication
keywords:
algebra; area-time complexity; Area-Time Trade-Offs; arithmetic; computation; computational complexity; Computer Systems, Digital; Computers, Digital--Computational Methods; I/O conventions; information flow; integrated logic circuits; Mathematical Techniques--Matrix Algebra; matrix; Matrix-Vector Multiplication; matrix-vector multiplication; operations; Parallel Processing; sparse matrix; VLSI

entry:
@Article{Codenotti:1990:ATT,
  author =       "B. Codenotti and G. Lotti and F. Romani",
  title =        "Area-time trade-offs for matrix-vector
                 multiplication",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "8",
  number =       "1",
  pages =        "52--59",
  month =        jan,
  year =         "1990",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst di Elaborazione dell'Informazione-CNR",
  affiliationaddress = "Pisa, Italy",
  classification = "722; 723; 921; B0290H (Linear algebra); B1265B
                 (Logic circuits); C4140 (Linear algebra); C4240
                 (Programming and algorithm theory)",
  corpsource =   "Istituto di Elaborazione dell'Inf., CNR, Pisa, Italy",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "algebra; area-time complexity; Area-Time Trade-Offs;
                 arithmetic; computation; computational complexity;
                 Computer Systems, Digital; Computers,
                 Digital--Computational Methods; I/O conventions;
                 information flow; integrated logic circuits;
                 Mathematical Techniques--Matrix Algebra; matrix;
                 Matrix-Vector Multiplication; matrix-vector
                 multiplication; operations; Parallel Processing; sparse
                 matrix; VLSI",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Cosnard:1990:STF
author: Michel Cosnard and Jean Duprat and Yves Robert
title: Systolic triangularization over finite fields
journal: j-J-PAR-DIST-COMP
volume: 9
number: 3
pages: 252--260
month: jul
monthnumber: 7
year: 1990
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliation: Ecole Normale Superieure de Lyon Lab LIP-IMAG
affiliationaddress: Lyon, Fr
corpsource: IMAG, Ecole Normale Superieure de Lyon, France
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical; T Theoretical or Mathematical
rawauthor: Michel Cosnard and Jean Duprat and Yves Robert
rawtitle: Systolic triangularization over finite fields
keywords:
architecture; arithmetic number; computer algebra; Computer Programming--Algorithms; Computer Systems, Digital--Parallel Processing; Computers, Digital; digital arithmetic; finite fields; Gaussian Elimination; Gaussian elimination; large dense linear systems; linear algebra; Mathematical Techniques--Linear Algebra; Modular Multiplication Algorithm; parallel architectures; partial; pivoting; Special Purpose Application; systolic; Systolic Arrays; Systolic Triangularization; systolic triangularization; theory

entry:
@Article{Cosnard:1990:STF,
  author =       "Michel Cosnard and Jean Duprat and Yves Robert",
  title =        "Systolic triangularization over finite fields",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "9",
  number =       "3",
  pages =        "252--260",
  month =        jul,
  year =         "1990",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Ecole Normale Superieure de Lyon Lab LIP-IMAG",
  affiliationaddress = "Lyon, Fr",
  classification = "722; 723; 921; C4140 (Linear algebra); C5220
                 (Computer architecture); C5230 (Digital arithmetic
                 methods)",
  corpsource =   "IMAG, Ecole Normale Superieure de Lyon, France",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "architecture; arithmetic number; computer algebra;
                 Computer Programming--Algorithms; Computer Systems,
                 Digital--Parallel Processing; Computers, Digital;
                 digital arithmetic; finite fields; Gaussian
                 Elimination; Gaussian elimination; large dense linear
                 systems; linear algebra; Mathematical
                 Techniques--Linear Algebra; Modular Multiplication
                 Algorithm; parallel architectures; partial; pivoting;
                 Special Purpose Application; systolic; Systolic Arrays;
                 Systolic Triangularization; systolic triangularization;
                 theory",
  treatment =    "P Practical; T Theoretical or Mathematical",
}


bibtype: manual
filename: fparith.bib
label: Cyrix:1990:FCU
title: FasMath CX-83D87 User's Manual: High Performance CMOS Math Processor
publisher: Cyrix Corp.
address: Richardson, TX, USA
pages: 115 + 5 + 3
year: 1990
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
URL: https://www.ardent-tool.com/CPU/docs/Cyrix/387/83d87.pdf
acknowledgement: ack-nhfb
rawtitle: {FasMath CX-83D87} User's Manual: High Performance {CMOS} Math Processor
keywords:
Cyrix CX-83D87 (Microprocessor); Cyrix CX-83S87 (Microprocessor); Floating-point arithmetic; Integrated circuits --- Very large scale integration; Metal oxide semiconductors, Complementary

entry:
@Manual{Cyrix:1990:FCU,
  title =        "{FasMath CX-83D87} User's Manual: High Performance
                 {CMOS} Math Processor",
  publisher =    "Cyrix Corp.",
  address =      "Richardson, TX, USA",
  pages =        "115 + 5 + 3",
  year =         "1990",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.ardent-tool.com/CPU/docs/Cyrix/387/83d87.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "Cyrix CX-83D87 (Microprocessor); Cyrix CX-83S87
                 (Microprocessor); Floating-point arithmetic; Integrated
                 circuits --- Very large scale integration; Metal oxide
                 semiconductors, Complementary",
}


bibtype: article
filename: fparith.bib
label: Darley:1990:TFC
title: The TMS390C602A Floating-Point Coprocessor for Sparc Systems
journal: j-IEEE-MICRO
volume: 10
number: 3
pages: 36--47
month: may
monthnumber: 5
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.56324
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Feb 24 15:01:45 MST 1996
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: IEEE Micro
language: English
acknowledgement: ack-nhfb
affiliation: Texas Instrum. Inc., Dallas, TX, USA
journalURL: http://www.computer.org/csdl/mags/mi/index.html
thesaurus: Digital arithmetic; Microprocessor chips
rawtitle: The {TMS390C602A} Floating-Point Coprocessor for {Sparc} Systems
author:
Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/microchip.bib

abstract:
A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)

keywords:
Addition; Compare; Convert; Division; Linpack benchmark; Multiplication; Sparc systems; Square root; Subtraction; TMS390C601 integer unit; TMS390C602A floating-point coprocessor; TMS390C602A floating-point unit; Two-chip configuration

rawabstract:
A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)

rawauthor:
Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang

entry:
@Article{Darley:1990:TFC,
  author =       "Merrick Darley and Bill Kronlage and David Bural and
                 Bob Churchill and David Pulling and Paul Wang and Rick
                 Iwamoto and Larry Yang",
  title =        "The {TMS390C602A} Floating-Point Coprocessor for
                 {Sparc} Systems",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "36--47",
  month =        may # "\slash " # jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.56324",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 processor execute single- or double-precision
                 floating-point instructions concurrently with IU
                 operations is described. Dedicated floating-point
                 hardware in the FPU increases the performance of the
                 system. Running at clock periods as small as 20 ns, the
                 chip should deliver 5.5 million double-precision
                 floating-point operations per second under the Linpack
                 benchmark (50-MHz clock rate). The FPU provides single-
                 and double-precision arithmetic functions: addition,
                 subtraction, multiplication, division, square root,
                 compare, and convert. To minimize its math unit's
                 latency, the FPU uses a highly parallel architecture
                 requiring separate math units to optimize additions and
                 multiplications. Traps stop the execution of a program
                 to jump to software routine for handling data-dependent
                 errors or to execute instructions not implemented in
                 the hardware. Benchmark results are presented. (4
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Texas Instrum. Inc., Dallas, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Addition; Compare; Convert; Division; Linpack
                 benchmark; Multiplication; Sparc systems; Square root;
                 Subtraction; TMS390C601 integer unit; TMS390C602A
                 floating-point coprocessor; TMS390C602A floating-point
                 unit; Two-chip configuration",
  language =     "English",
  pubcountry =   "USA",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Darley:1990:TFP
title: The TMS390C602A Floating-Point Coprocessor for Sparc Systems
journal: j-IEEE-MICRO
volume: 10
number: 3
pages: 36--47
month: may
monthnumber: 5
year: 1990
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.56324
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-mfc
affiliation: Texas Instrum. Inc., Dallas, TX, USA
journalURL: http://www.computer.org/csdl/mags/mi/index.html
thesaurus: Digital arithmetic; Microprocessor chips
rawtitle: The {TMS390C602A} Floating-Point Coprocessor for {Sparc} Systems
author:
Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang

abstract:
A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)

keywords:
Addition; Compare; Convert; Division; Linpack benchmark; Multiplication; Sparc systems; Square root; Subtraction; TMS390C601 integer unit; TMS390C602A floating-point coprocessor; TMS390C602A floating-point unit; Two-chip configuration

entry:
@Article{Darley:1990:TFP,
  author =       "Merrick Darley and Bill Kronlage and David Bural and
                 Bob Churchill and David Pulling and Paul Wang and Rick
                 Iwamoto and Larry Yang",
  title =        "The {TMS390C602A} Floating-Point Coprocessor for
                 {Sparc} Systems",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "36--47",
  month =        may # "\slash " # jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.56324",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 processor execute single- or double-precision
                 floating-point instructions concurrently with IU
                 operations is described. Dedicated floating-point
                 hardware in the FPU increases the performance of the
                 system. Running at clock periods as small as 20 ns, the
                 chip should deliver 5.5 million double-precision
                 floating-point operations per second under the Linpack
                 benchmark (50-MHz clock rate). The FPU provides single-
                 and double-precision arithmetic functions: addition,
                 subtraction, multiplication, division, square root,
                 compare, and convert. To minimize its math unit's
                 latency, the FPU uses a highly parallel architecture
                 requiring separate math units to optimize additions and
                 multiplications. Traps stop the execution of a program
                 to jump to software routine for handling data-dependent
                 errors or to execute instructions not implemented in
                 the hardware. Benchmark results are presented. (4
                 Refs.)",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  affiliation =  "Texas Instrum. Inc., Dallas, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Addition; Compare; Convert; Division; Linpack
                 benchmark; Multiplication; Sparc systems; Square root;
                 Subtraction; TMS390C601 integer unit; TMS390C602A
                 floating-point coprocessor; TMS390C602A floating-point
                 unit; Two-chip configuration",
  summary =      "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 \ldots{}",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: inproceedings
filename: fparith.bib
label: deLange:1990:ASI
author: A. A. J. de Lange and A. J. van der Hoeven and E. F. Deprettere and P. Dewilde
booktitle: [Proceedings] EURO ASIC `90
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 62--67
year: 1990
DOI: https://doi.org/10.1109/EASIC.1990.207911
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: A. A. J. de Lange and A. J. van der Hoeven and E. F. Deprettere and P. Dewilde
rawbooktitle: {[Proceedings] EURO ASIC `90}
title:
An application specific IC for digital signal processing: the floating point pipeline CORDIC processor

keywords:
Application specific integrated circuits; Array signal processing; Digital integrated circuits; Digital signal processing; Hardware; Pipelines; Radar antennas; Radar signal processing; Signal processing algorithms; Vectors

rawtitle:
An application specific {IC} for digital signal processing: the floating point pipeline {CORDIC} processor

entry:
@InProceedings{deLange:1990:ASI,
  author =       "A. A. J. de Lange and A. J. van der Hoeven and E. F.
                 Deprettere and P. Dewilde",
  booktitle =    "{[Proceedings] EURO ASIC `90}",
  title =        "An application specific {IC} for digital signal
                 processing: the floating point pipeline {CORDIC}
                 processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "62--67",
  year =         "1990",
  DOI =          "https://doi.org/10.1109/EASIC.1990.207911",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Application specific integrated circuits; Array signal
                 processing; Digital integrated circuits; Digital signal
                 processing; Hardware; Pipelines; Radar antennas; Radar
                 signal processing; Signal processing algorithms;
                 Vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: deLange:1990:RTA
author: A. A. J. de Lange and E. F. Deprettere and A. J. van der Veen and J. Bu
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1013--1016 (vol. 2)
year: 1990
DOI: https://doi.org/10.1109/ICASSP.1990.116062
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1109/ICASSP.1990
rawauthor: A. A. J. de Lange and E. F. Deprettere and A. J. van der Veen and J. Bu
booktitle:
Proceedings of the ICASSP International Conference on Acoustic, Speech, and Signal Processing April 1990

title:
Real Time Applications of the Floating Point Pipeline CORDIC Processor in Massive-Parallel Pipelined DSP Algorithms

keywords:
Application software; Array signal processing; Computer graphics; Digital arithmetic; Multiprocessing systems; Pipelines; Speech processing; System testing; Very large scale integration

rawbooktitle:
{Proceedings of the ICASSP International Conference on Acoustic, Speech, and Signal Processing April 1990}

rawtitle:
Real Time Applications of the Floating Point Pipeline {CORDIC} Processor in Massive-Parallel Pipelined {DSP} Algorithms

entry:
@InProceedings{deLange:1990:RTA,
  author =       "A. A. J. de Lange and E. F. Deprettere and A. J. van
                 der Veen and J. Bu",
  editor =       "????",
  booktitle =    "{Proceedings of the ICASSP International Conference on
                 Acoustic, Speech, and Signal Processing April 1990}",
  title =        "Real Time Applications of the Floating Point Pipeline
                 {CORDIC} Processor in Massive-Parallel Pipelined {DSP}
                 Algorithms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1013--1016 (vol. 2)",
  year =         "1990",
  DOI =          "https://doi.org/10.1109/ICASSP.1990.116062",
  ISBN =         "",
  ISBN-13 =      "",
  LCCN =         "",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1109/ICASSP.1990",
  keywords =     "Application software; Array signal processing;
                 Computer graphics; Digital arithmetic; Multiprocessing
                 systems; Pipelines; Speech processing; System testing;
                 Very large scale integration",
}


bibtype: book
filename: fparith.bib
label: Dewar:1990:MPV
author: Robert B. K. Dewar and Matthew Smosna
title: Microprocessors: a programmer's view
publisher: pub-MCGRAW-HILL
address: pub-MCGRAW-HILL:adr
pages: xvii + 462
year: 1990
ISBN: 0-07-016638-2, 0-07-016639-0 (soft) OR 0070166382, 0070166390 (soft)
ISBN13: 978-0-07-016638-7, 978-0-07-016639-4 (soft) OR 9780070166387, 9780070166394 (soft)
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Microprocessors --- Programming.
acknowledgement: ack-nhfb
rawauthor: Robert B. K. Dewar and Matthew Smosna
rawtitle: Microprocessors: a programmer's view
remark:
Microprocessors --- Introduction to the 80386 --- Addressing and memory on the 80386 --- Tasking, virtual memory, and exceptions to the 80386 --- Microprocessors and floating-point arithmetic --- 68030 user programming model --- 68030 supervisor state --- Introduction to RISC architectures --- MIPS processors --- SPARC architecture --- Intel i860 --- IBM RISC chips --- INMOS transputer - - Future of microprocessor design.

entry:
@Book{Dewar:1990:MPV,
  author =       "Robert B. K. Dewar and Matthew Smosna",
  title =        "Microprocessors: a programmer's view",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xvii + 462",
  year =         "1990",
  ISBN =         "0-07-016638-2, 0-07-016639-0 (soft)",
  ISBN-13 =      "978-0-07-016638-7, 978-0-07-016639-4 (soft)",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Microprocessors --- Programming.",
  remark =       "Microprocessors --- Introduction to the 80386 ---
                 Addressing and memory on the 80386 --- Tasking, virtual
                 memory, and exceptions to the 80386 --- Microprocessors
                 and floating-point arithmetic --- 68030 user
                 programming model --- 68030 supervisor state ---
                 Introduction to RISC architectures --- MIPS processors
                 --- SPARC architecture --- Intel i860 --- IBM RISC
                 chips --- INMOS transputer - - Future of microprocessor
                 design.",
}


bibtype: inproceedings
filename: fparith.bib
label: Dixon:1990:HPB
author: G. Dixon
title: A high performance block floating point DSP chip-set
crossref: IEE:1990:ICV
pages: 9/1--7
year: 1990
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Plessey Res. Caswell, Towcester, UK
rawauthor: G. Dixon
rawtitle: A high performance block floating point {DSP} chip-set
abstract:
This paper describes the design and development of two ASICs which form the processing kernel of a high performance sonar signal processor; namely a 24-bit Block Floating Point Arithmetic Unit (BFPAU), and a Table Memory And Address Modifier (TMAAM). The system is based upon a 24-bit block floating point data format which is a compromise between fixed and floating point data; possessing the advantage of reducing the data storage requirement compared to true floating point while allowing arithmetic to be performed in the faster fixed-point format whilst retaining the extended dynamic range provided by floating point. The BFPAU and TMAAM perform the arithmetic processing; the BFPAU is the central arithmetic processor aimed at sonar signal processing in general and beamforming in particular, while the TMAAM provides a range of essential support functions such as look-up tables for trigonometric functions, address generation, exponent control and normalisation and program sequencing. Two blocks of dual-port RAM provide storage for system I/O data transfers, together with two blocks of RAM providing working data storage for the BFPAU. A block of video RAM is used to store address and control sequences for the processing element.

keywords:
Address generation; Arithmetic processing; ASICs; Beamforming; Block floating point DSP chip-set; Data format; Data storage requirement; Dual-port RAM; Dynamic range; Exponent control; Fixed-point format; Look-up tables; Normalisation; Program sequencing; Sonar signal processor; System I/O data transfers; Video RAM; Working data storage

thesaurus:
Application specific integrated circuits; Digital signal processing chips; Random-access storage; Sonar

rawabstract:
This paper describes the design and development of two ASICs which form the processing kernel of a high performance sonar signal processor; namely a 24-bit Block Floating Point Arithmetic Unit (BFPAU), and a Table Memory And Address Modifier (TMAAM). The system is based upon a 24-bit block floating point data format which is a compromise between fixed and floating point data; possessing the advantage of reducing the data storage requirement compared to true floating point while allowing arithmetic to be performed in the faster fixed-point format whilst retaining the extended dynamic range provided by floating point. The BFPAU and TMAAM perform the arithmetic processing; the BFPAU is the central arithmetic processor aimed at sonar signal processing in general and beamforming in particular, while the TMAAM provides a range of essential support functions such as look-up tables for trigonometric functions, address generation, exponent control and normalisation and program sequencing. Two blocks of dual-port RAM provide storage for system I/O data transfers, together with two blocks of RAM providing working data storage for the BFPAU. A block of video RAM is used to store address and control sequences for the processing element.

entry:
@InProceedings{Dixon:1990:HPB,
  author =       "G. Dixon",
  title =        "A high performance block floating point {DSP}
                 chip-set",
  crossref =     "IEE:1990:ICV",
  pages =        "9/1--7",
  year =         "1990",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes the design and development of two
                 ASICs which form the processing kernel of a high
                 performance sonar signal processor; namely a 24-bit
                 Block Floating Point Arithmetic Unit (BFPAU), and a
                 Table Memory And Address Modifier (TMAAM). The system
                 is based upon a 24-bit block floating point data format
                 which is a compromise between fixed and floating point
                 data; possessing the advantage of reducing the data
                 storage requirement compared to true floating point
                 while allowing arithmetic to be performed in the faster
                 fixed-point format whilst retaining the extended
                 dynamic range provided by floating point. The BFPAU and
                 TMAAM perform the arithmetic processing; the BFPAU is
                 the central arithmetic processor aimed at sonar signal
                 processing in general and beamforming in particular,
                 while the TMAAM provides a range of essential support
                 functions such as look-up tables for trigonometric
                 functions, address generation, exponent control and
                 normalisation and program sequencing. Two blocks of
                 dual-port RAM provide storage for system I/O data
                 transfers, together with two blocks of RAM providing
                 working data storage for the BFPAU. A block of video
                 RAM is used to store address and control sequences for
                 the processing element.",
  acknowledgement = ack-nhfb,
  affiliation =  "Plessey Res. Caswell, Towcester, UK",
  classification = "B1265F (Microprocessors and microcomputers); B6320E
                 (Sonar and acoustic radar)",
  keywords =     "Address generation; Arithmetic processing; ASICs;
                 Beamforming; Block floating point DSP chip-set; Data
                 format; Data storage requirement; Dual-port RAM;
                 Dynamic range; Exponent control; Fixed-point format;
                 Look-up tables; Normalisation; Program sequencing;
                 Sonar signal processor; System I/O data transfers;
                 Video RAM; Working data storage",
  thesaurus =    "Application specific integrated circuits; Digital
                 signal processing chips; Random-access storage; Sonar",
}


bibtype: article
filename: fparith.bib
label: Dotzel:1990:DMG
author: Gunter Dotzel
journal: j-SIGPLAN
volume: 25
number: 12
pages: 85--88
month: dec
monthnumber: 12
year: 1990
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:00 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:16:00 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: ModulaWare GmbH, Erlangen, West Germany
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
thesaurus: Modula; Modula listings; Program compilers; Program testing
rawauthor: G{\"u}nter Dotzel
title:
Does Modula-2 generate racehorses? Comparison of compiler generated code quality for floating point arithmetic

abstract:
A simple example serves to demonstrate the code quality generated by two different Modula-2 compilers. The two compilers are called the Zurich/Hamburger and the Erlanger. The author lists the Modula-2 source program, shows an excerpt of the machine code listing generated by the Erlanger and presents that of the Zurich/Hamburger. The differences in code quality concerning instruction count, code size and execution speed are discussed and summarized. The author also presents the main program module used for the benchmarks and a short description of the development history of Modula-2 and Modula/R.

keywords:
Benchmarks; Code size; Compiler generated code quality; Development history; Erlanger; Execution speed; Floating point arithmetic; Instruction count; Machine code listing; Main program module; Modula-2 compilers; Modula-2 source program; Modula/R; Zurich/Hamburger

rawabstract:
A simple example serves to demonstrate the code quality generated by two different Modula-2 compilers. The two compilers are called the Zurich/Hamburger and the Erlanger. The author lists the Modula-2 source program, shows an excerpt of the machine code listing generated by the Erlanger and presents that of the Zurich/Hamburger. The differences in code quality concerning instruction count, code size and execution speed are discussed and summarized. The author also presents the main program module used for the benchmarks and a short description of the development history of Modula-2 and Modula/R.

rawtitle:
Does {Modula-2} generate racehorses? {Comparison} of compiler generated code quality for floating point arithmetic

entry:
@Article{Dotzel:1990:DMG,
  author =       "G{\"u}nter Dotzel",
  title =        "Does {Modula-2} generate racehorses? {Comparison} of
                 compiler generated code quality for floating point
                 arithmetic",
  journal =      j-SIGPLAN,
  volume =       "25",
  number =       "12",
  pages =        "85--88",
  month =        dec,
  year =         "1990",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:00 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A simple example serves to demonstrate the code
                 quality generated by two different Modula-2 compilers.
                 The two compilers are called the Zurich/Hamburger and
                 the Erlanger. The author lists the Modula-2 source
                 program, shows an excerpt of the machine code listing
                 generated by the Erlanger and presents that of the
                 Zurich/Hamburger. The differences in code quality
                 concerning instruction count, code size and execution
                 speed are discussed and summarized. The author also
                 presents the main program module used for the
                 benchmarks and a short description of the development
                 history of Modula-2 and Modula/R.",
  acknowledgement = ack-nhfb,
  affiliation =  "ModulaWare GmbH, Erlangen, West Germany",
  classification = "C6140D (High level languages); C6150C (Compilers,
                 interpreters and other processors); C6150G (Diagnostic,
                 testing, debugging and evaluating systems)",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "Benchmarks; Code size; Compiler generated code
                 quality; Development history; Erlanger; Execution
                 speed; Floating point arithmetic; Instruction count;
                 Machine code listing; Main program module; Modula-2
                 compilers; Modula-2 source program; Modula/R;
                 Zurich/Hamburger",
  thesaurus =    "Modula; Modula listings; Program compilers; Program
                 testing",
}


