# bibtab

bibtype: phdthesis
filename: fparith.bib
label: Wang:1998:CAP
author: Shaoyun Wang
title: A CORDIC arithmetic processor
type: Ph.D. thesis
school: The University of Texas at Austin
address: Austin, TX, USA
pages: 136
year: 1998
ISBN: 0-591-91832-3 OR 0591918323
ISBN13: 978-0-591-91832-8 OR 9780591918328
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
advisor: Swartzlander, Earl E., Jr.
rawauthor: Shaoyun Wang
rawtitle: A {CORDIC} arithmetic processor
URL:
https://login.ezproxy.lib.utah.edu/login?url=https://www.proquest.com/dissertations-theses/cordic-arithmetic-processor/docview/304459653/se-2

keywords:
0544:Electrical engineering; 0984:Computer science; Applied sciences; Arithmetic processor; Computer science; Coordinate rotation; Cordic; Electrical engineering; Plane rotation

entry:
@PhdThesis{Wang:1998:CAP,
  author =       "Shaoyun Wang",
  title =        "A {CORDIC} arithmetic processor",
  type =         "{Ph.D.} thesis",
  school =       "The University of Texas at Austin",
  address =      "Austin, TX, USA",
  pages =        "136",
  year =         "1998",
  ISBN =         "0-591-91832-3",
  ISBN-13 =      "978-0-591-91832-8",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://login.ezproxy.lib.utah.edu/login?url=https://www.proquest.com/dissertations-theses/cordic-arithmetic-processor/docview/304459653/se-2",
  acknowledgement = ack-nhfb,
  advisor =      "Swartzlander, Earl E., Jr.",
  keywords =     "0544:Electrical engineering; 0984:Computer science;
                 Applied sciences; Arithmetic processor; Computer
                 science; Coordinate rotation; Cordic; Electrical
                 engineering; Plane rotation",
  ris-m1 =       "9838156",
}


bibtype: inproceedings
filename: fparith.bib
label: Wei:1998:RAC
author: Shugang Wei and Kensuke Shimizu
title: Residue Arithmetic Circuits Based on Signed-Digit Multi-Valued Arithmetic Circuits
crossref: Sasao:1998:ISM
pages: 276--281
year: 1998
DOI: https://doi.org/10.1109/ISMVL.1998.679470
MRclass: 68M07
MRnumber: MR1676993
bibdate: Fri Jun 24 19:50:29 2005
bibtimestamp: 2005.06.24 19:50:29 ???
URL: http://csdl.computer.org/dl/proceedings/ismvl/1998/8371/00/83710276.pdf
acknowledgement: ack-nhfb
rawauthor: Shugang Wei and Kensuke Shimizu
rawtitle: Residue Arithmetic Circuits Based on Signed-Digit Multi-Valued Arithmetic Circuits
bibsource:
http://www.informatik.uni-trier.de/~ley/db/conf/ismvl/ismvl1998.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Multiple-valued residue arithmetic circuits using integers $ 4^p $ and $ 4^p pm 1 $ as moduli of residue number system (RNS) are presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a radix-4 signed-digit(SD) number system is introduced, and the compact SD adder based on the multiple-valued current-mode circuits is applied for the implementation of high-speed and compact residue arithmetic circuits. The modulo $m$ addition, $ m = 4^p $ or $ m = 4^p pm 1 $, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. Modulo $m$ multiplier can be compactly constructed using a binary modulo $m$ SD adder tree based on the multiple-valued addition circuits, and the modulo m multiplication can be performed in a time proportional to $ log _2 p $.

rawabstract:
Multiple-valued residue arithmetic circuits using integers $ 4^p $ and $ 4^p \pm 1 $ as moduli of residue number system (RNS) are presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a radix-4 signed-digit(SD) number system is introduced, and the compact SD adder based on the multiple-valued current-mode circuits is applied for the implementation of high-speed and compact residue arithmetic circuits. The modulo $m$ addition, $ m = 4^p $ or $ m = 4^p \pm 1 $, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. Modulo $m$ multiplier can be compactly constructed using a binary modulo $m$ SD adder tree based on the multiple-valued addition circuits, and the modulo m multiplication can be performed in a time proportional to $ \log_2 p $.

entry:
@InProceedings{Wei:1998:RAC,
  author =       "Shugang Wei and Kensuke Shimizu",
  title =        "Residue Arithmetic Circuits Based on Signed-Digit
                 Multi-Valued Arithmetic Circuits",
  crossref =     "Sasao:1998:ISM",
  pages =        "276--281",
  year =         "1998",
  DOI =          "https://doi.org/10.1109/ISMVL.1998.679470",
  MRclass =      "68M07",
  MRnumber =     "MR1676993",
  bibdate =      "Fri Jun 24 19:50:29 2005",
  bibsource =    "http://www.informatik.uni-trier.de/~ley/db/conf/ismvl/ismvl1998.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/dl/proceedings/ismvl/1998/8371/00/83710276.pdf",
  abstract =     "Multiple-valued residue arithmetic circuits using
                 integers $ 4^p $ and $ 4^p \pm 1 $ as moduli of residue
                 number system (RNS) are presented. Conventional residue
                 arithmetic circuits have been designed using binary
                 number arithmetic system, but the carry propagation
                 arises which limits the speed of arithmetic operations
                 in residue modules. In this paper, a radix-4
                 signed-digit(SD) number system is introduced, and the
                 compact SD adder based on the multiple-valued
                 current-mode circuits is applied for the implementation
                 of high-speed and compact residue arithmetic circuits.
                 The modulo $m$ addition, $ m = 4^p $ or $ m = 4^p \pm 1
                 $, can be performed by an SD adder or an
                 end-around-carry SD adder with the multiple-valued
                 circuits and the addition time is independent of the
                 word length of operands. Modulo $m$ multiplier can be
                 compactly constructed using a binary modulo $m$ SD
                 adder tree based on the multiple-valued addition
                 circuits, and the modulo m multiplication can be
                 performed in a time proportional to $ \log_2 p $.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Weiss:1998:FPM
author: S. Weiss and A. Goldstein
title: Floating point micropipeline performance
journal: j-J-SYST-ARCH
volume: 45
number: 1
pages: 15--29
month: oct
monthnumber: 10
year: 1998
CODEN: JSARFB
ISSN: 1383-7621 (print), 1873-6165 (electronic) OR 13837621 (print), 18736165 (electronic)
ISSNL: 1383-7621 OR 13837621
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Journal of Systems Architecture
acknowledgement: ack-nhfb
rawauthor: S. Weiss and A. Goldstein
rawtitle: Floating point micropipeline performance
entry:
@Article{Weiss:1998:FPM,
  author =       "S. Weiss and A. Goldstein",
  title =        "Floating point micropipeline performance",
  journal =      j-J-SYST-ARCH,
  volume =       "45",
  number =       "1",
  pages =        "15--29",
  month =        oct,
  year =         "1998",
  CODEN =        "JSARFB",
  ISSN =         "1383-7621 (print), 1873-6165 (electronic)",
  ISSN-L =       "1383-7621",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Systems Architecture",
  pagecount =    "15",
}


bibtype: article
filename: fparith.bib
label: Wu:1998:LCB
author: Huapeng Wu and M. A. Hasan
title: Low complexity bit-parallel multipliers for a class of finite fields
journal: j-IEEE-TRANS-COMPUT
volume: 47
number: 8
pages: 883--887
month: aug
monthnumber: 8
year: 1998
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.707588
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 09:35:55 MDT 2011
bibtimestamp: 2011.07.06 09:35:55 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=707588
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Huapeng Wu and M. A. Hasan
rawtitle: Low complexity bit-parallel multipliers for a class of finite fields
entry:
@Article{Wu:1998:LCB,
  author =       "Huapeng Wu and M. A. Hasan",
  title =        "Low complexity bit-parallel multipliers for a class of
                 finite fields",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "47",
  number =       "8",
  pages =        "883--887",
  month =        aug,
  year =         "1998",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.707588",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 09:35:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=707588",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wu:1998:NLC
author: H. Wu and M. A. Hasan and I. F. Blake
title: New low-complexity bit-parallel finite field multipliers using weakly dual bases
journal: j-IEEE-TRANS-COMPUT
volume: 47
number: 11
pages: 1223--1234
month: nov
monthnumber: 11
year: 1998
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.736433
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 09:35:56 MDT 2011
bibtimestamp: 2011.07.06 09:35:56 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=736433
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Wu and M. A. Hasan and I. F. Blake
rawtitle: New low-complexity bit-parallel finite field multipliers using weakly dual bases
entry:
@Article{Wu:1998:NLC,
  author =       "H. Wu and M. A. Hasan and I. F. Blake",
  title =        "New low-complexity bit-parallel finite field
                 multipliers using weakly dual bases",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "47",
  number =       "11",
  pages =        "1223--1234",
  month =        nov,
  year =         "1998",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.736433",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 09:35:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=736433",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Abbott:1999:ASS
journal: j-IBM-JRD
volume: 43
number: 5/6
pages: 723--760
month: sep
monthnumber: 9
year: 1999
CODEN: IBMJAE
DOI: https://doi.org/10.1147/rd.435.0723
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Mon Feb 03 07:08:45 2003
bibtimestamp: 2003.02.03 07:08:45 ???
URL: http://www.research.ibm.com/journal/rd/435/abbott.html
fjournal: IBM Journal of Research and Development
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
author:
P. H. Abbott and D. G. Brush and C. W. Clark III and C. J. Crone and J. R. Ehrman and G. W. Ewart and C. A. Goodrich and M. Hack and J. S. Kapernick and B. J. Minchau and W. C. Shepard and R. M. Smith, Sr. and R. Tallman and S. Walkowiak and A. Watanabe and W. R. White

title:
Architecture and software support in IBM S/390 Parallel Enterprise Servers for IEEE Floating-Point arithmetic

note:
Besides important history of the development of the S/360 floating-point architecture, this paper has a good description of IBM's algorithm for exact decimal-to-binary conversion, complementing earlier ones cite Steele:1990:HPF,Clinger:1990:HRF,Knuth:1990:SPW,Burger:1996:PFP,Steele:2004:RHP.

rawauthor:
P. H. Abbott and D. G. Brush and C. W. {Clark III} and C. J. Crone and J. R. Ehrman and G. W. Ewart and C. A. Goodrich and M. Hack and J. S. Kapernick and B. J. Minchau and W. C. Shepard and R. M. {Smith, Sr.} and R. Tallman and S. Walkowiak and A. Watanabe and W. R. White

rawnote:
Besides important history of the development of the S/360 floating-point architecture, this paper has a good description of IBM's algorithm for exact decimal-to-binary conversion, complementing earlier ones \cite{Steele:1990:HPF,Clinger:1990:HRF,Knuth:1990:SPW,Burger:1996:PFP,Steele:2004:RHP}.

rawtitle:
Architecture and software support in {IBM S/390 Parallel Enterprise Servers} for {IEEE} Floating-Point arithmetic

entry:
@Article{Abbott:1999:ASS,
  author =       "P. H. Abbott and D. G. Brush and C. W. {Clark III} and
                 C. J. Crone and J. R. Ehrman and G. W. Ewart and C. A.
                 Goodrich and M. Hack and J. S. Kapernick and B. J.
                 Minchau and W. C. Shepard and R. M. {Smith, Sr.} and R.
                 Tallman and S. Walkowiak and A. Watanabe and W. R.
                 White",
  title =        "Architecture and software support in {IBM S/390
                 Parallel Enterprise Servers} for {IEEE} Floating-Point
                 arithmetic",
  journal =      j-IBM-JRD,
  volume =       "43",
  number =       "5/6",
  pages =        "723--760",
  month =        sep # "\slash " # nov,
  year =         "1999",
  CODEN =        "IBMJAE",
  DOI =          "https://doi.org/10.1147/rd.435.0723",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Mon Feb 03 07:08:45 2003",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ibmjrd.bib",
  note =         "Besides important history of the development of the
                 S/360 floating-point architecture, this paper has a
                 good description of IBM's algorithm for exact
                 decimal-to-binary conversion, complementing earlier
                 ones
                 \cite{Steele:1990:HPF,Clinger:1990:HRF,Knuth:1990:SPW,Burger:1996:PFP,Steele:2004:RHP}.",
  URL =          "http://www.research.ibm.com/journal/rd/435/abbott.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Agarwal:1999:SAM
author: Rames C. Agarwal and Fred G. Gustavson and Martin S. Schmookler
title: Series Approximation Methods for Divide and Square Root in the Power3TM Processor
crossref: Koren:1999:ISC
pages: 116--123
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Rames C. Agarwal and Fred G. Gustavson and Martin S. Schmookler
rawtitle: Series Approximation Methods for Divide and Square Root in the {Power3\TM{}} Processor
URL:
http://euler.ecs.umass.edu/paper/final/paper-144.pdf; http://euler.ecs.umass.edu/paper/final/paper-144.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Agarwal.pdf

abstract:
The Power3 processor is a 64-bit implementation of the PowerPCTM architecture and is the successor to the Power2TM processor for workstations and servers which require high performance floating point capability. The previous processors used Newton--Raphson algorithms for their implementations of divide and square root. The Power3 processor has a longer pipeline latency, which would substantially increase the latency for these instructions. Instead, new algorithms based on power series approximations were developed which provide significantly better performance than the Newton- Raphson algorithm for this processor. This paper describes the algorithms, and then shows how both the series based algorithms and the Newton--Raphson algorithms are affected by pipeline length. For the Power3, the power series algorithms reduce the divide latency by over 20% and the square root latency by 35%.

rawabstract:
The Power3 processor is a 64-bit implementation of the PowerPC\TM{} architecture and is the successor to the Power2\TM{} processor for workstations and servers which require high performance floating point capability. The previous processors used Newton--Raphson algorithms for their implementations of divide and square root. The Power3 processor has a longer pipeline latency, which would substantially increase the latency for these instructions. Instead, new algorithms based on power series approximations were developed which provide significantly better performance than the Newton- Raphson algorithm for this processor. This paper describes the algorithms, and then shows how both the series based algorithms and the Newton--Raphson algorithms are affected by pipeline length. For the Power3, the power series algorithms reduce the divide latency by over 20\% and the square root latency by 35\%.

entry:
@InProceedings{Agarwal:1999:SAM,
  author =       "Rames C. Agarwal and Fred G. Gustavson and Martin S.
                 Schmookler",
  title =        "Series Approximation Methods for Divide and Square
                 Root in the {Power3\TM{}} Processor",
  crossref =     "Koren:1999:ISC",
  pages =        "116--123",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-144.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-144.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Agarwal.pdf",
  abstract =     "The Power3 processor is a 64-bit implementation of the
                 PowerPC\TM{} architecture and is the successor to the
                 Power2\TM{} processor for workstations and servers
                 which require high performance floating point
                 capability. The previous processors used
                 Newton--Raphson algorithms for their implementations of
                 divide and square root. The Power3 processor has a
                 longer pipeline latency, which would substantially
                 increase the latency for these instructions. Instead,
                 new algorithms based on power series approximations
                 were developed which provide significantly better
                 performance than the Newton- Raphson algorithm for this
                 processor. This paper describes the algorithms, and
                 then shows how both the series based algorithms and the
                 Newton--Raphson algorithms are affected by pipeline
                 length. For the Power3, the power series algorithms
                 reduce the divide latency by over 20\% and the square
                 root latency by 35\%.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Ait-Ameur:1999:RRE
author: Y. Ait-Ameur
title: Refinement of rational end-points real numbers by means of floating-point numbers
journal: j-SCI-COMPUT-PROGRAM
volume: 33
number: 2
pages: 133--162
month: feb
monthnumber: 2
year: 1999
CODEN: SCPGD4
ISSN: 0167-6423 (print), 1872-7964 (electronic) OR 01676423 (print), 18727964 (electronic)
ISSNL: 0167-6423 OR 01676423
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Science of Computer Programming
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01676423
rawauthor: Y. Ait-Ameur
rawtitle: Refinement of rational end-points real numbers by means of floating-point numbers
entry:
@Article{Ait-Ameur:1999:RRE,
  author =       "Y. Ait-Ameur",
  title =        "Refinement of rational end-points real numbers by
                 means of floating-point numbers",
  journal =      j-SCI-COMPUT-PROGRAM,
  volume =       "33",
  number =       "2",
  pages =        "133--162",
  month =        feb,
  year =         "1999",
  CODEN =        "SCPGD4",
  ISSN =         "0167-6423 (print), 1872-7964 (electronic)",
  ISSN-L =       "0167-6423",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Science of Computer Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01676423",
  pagecount =    "30",
}


bibtype: article
filename: fparith.bib
label: Allender:1999:BDA
author: Eric Allender and Andris Ambainis and David A. Mix Barrington and Samir Datta and Huong LeThanh
title: Bounded Depth Arithmetic Circuits: Counting and Closure
journal: j-LECT-NOTES-COMP-SCI
volume: 1644
pages: 149--??
year: 1999
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Feb 5 11:54:23 MST 2002
bibtimestamp: 2002.02.05 11:54:23 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Eric Allender and Andris Ambainis and David A. Mix Barrington and Samir Datta and Huong L{\^e}Thanh
rawtitle: Bounded Depth Arithmetic Circuits: Counting and Closure
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t1644.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/1644/16440149.htm; http://link.springer-ny.com/link/service/series/0558/papers/1644/16440149.pdf

entry:
@Article{Allender:1999:BDA,
  author =       "Eric Allender and Andris Ambainis and David A. Mix
                 Barrington and Samir Datta and Huong L{\^e}Thanh",
  title =        "Bounded Depth Arithmetic Circuits: Counting and
                 Closure",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1644",
  pages =        "149--??",
  year =         "1999",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Feb 5 11:54:23 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t1644.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/1644/16440149.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/1644/16440149.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Anderson:1999:DAF
author: I. J. Anderson
title: A Distillation Algorithm for Floating-Point Summation
journal: j-SIAM-J-SCI-COMP
volume: 20
number: 5
pages: 1797--1806
month: sep
monthnumber: 9
year: 1999
CODEN: SJOCE3
DOI: https://doi.org/10.1137/S1064827596314200
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Sat Jul 17 19:14:38 MDT 1999
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/20/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.07.17 19:14:38 MDT
URL: http://epubs.siam.org/sam-bin/dbq/article/31420
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: I. J. Anderson
rawtitle: A Distillation Algorithm for Floating-Point Summation
abstract:
The addition of two or more floating-point numbers is fundamental to numerical computations. This paper describes an efficient ``distillation'' style algorithm which produces a precise sum by exploiting the natural accuracy of compensated cancellation. The algorithm is applicable to all sets of data but is particularly appropriate for ill-conditioned data, where standard methods fail due to the accumulation of rounding error and its subsequent exposure by cancellation. The method uses only standard floating-point arithmetic and does not rely on the radix used by the arithmetic model, the architecture of specific machines, or the use of accumulators.

rawabstract:
The addition of two or more floating-point numbers is fundamental to numerical computations. This paper describes an efficient ``distillation'' style algorithm which produces a precise sum by exploiting the natural accuracy of compensated cancellation. The algorithm is applicable to all sets of data but is particularly appropriate for ill-conditioned data, where standard methods fail due to the accumulation of rounding error and its subsequent exposure by cancellation. The method uses only standard floating-point arithmetic and does not rely on the radix used by the arithmetic model, the architecture of specific machines, or the use of accumulators.

entry:
@Article{Anderson:1999:DAF,
  author =       "I. J. Anderson",
  title =        "A Distillation Algorithm for Floating-Point
                 Summation",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "20",
  number =       "5",
  pages =        "1797--1806",
  month =        sep,
  year =         "1999",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/S1064827596314200",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Sat Jul 17 19:14:38 MDT 1999",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/20/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/31420",
  abstract =     "The addition of two or more floating-point numbers is
                 fundamental to numerical computations. This paper
                 describes an efficient ``distillation'' style algorithm
                 which produces a precise sum by exploiting the natural
                 accuracy of compensated cancellation. The algorithm is
                 applicable to all sets of data but is particularly
                 appropriate for ill-conditioned data, where standard
                 methods fail due to the accumulation of rounding error
                 and its subsequent exposure by cancellation. The method
                 uses only standard floating-point arithmetic and does
                 not rely on the radix used by the arithmetic model, the
                 architecture of specific machines, or the use of
                 accumulators.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:1999:SLH
author: Anonymous
title: Standard libraries for the Haskell 98 programming language
pages: 1797--1806
month: feb
monthnumber: 2
year: 1999
bibdate: Wed Jan 29 16:42:05 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.01.29 16:42:05 ???
URL: http://www.haskell.org/definition/haskell98-library.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Anonymous
rawtitle: Standard libraries for the {Haskell 98} programming language
remark:
From cite Steele:2004:RHP: ``a comment that appears in the code for the function floatToDigits in the Haskell 98 library [p. 14 of this article] says that the code is based on Burger and Dybvig's work cite Burger:1996:PFP.

entry:
@Misc{Anonymous:1999:SLH,
  author =       "Anonymous",
  title =        "Standard libraries for the {Haskell 98} programming
                 language",
  howpublished = "World-Wide Web document",
  month =        feb,
  year =         "1999",
  bibdate =      "Wed Jan 29 16:42:05 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.haskell.org/definition/haskell98-library.pdf",
  acknowledgement = ack-nhfb,
  remark =       "From \cite{Steele:2004:RHP}: ``a comment that appears
                 in the code for the function floatToDigits in the
                 Haskell 98 library [p. 14 of this article] says that
                 the code is based on Burger and Dybvig's work
                 \cite{Burger:1996:PFP}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Antelo:1999:VHR
author: E. Antelo and T. Lang and J. D. Bruguera
booktitle: Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No. 99CB36336)
title: Very-high radix CORDIC vectoring with scalings and selection by rounding
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 204--213
year: 1999
DOI: https://doi.org/10.1109/ARITH.1999.762846
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
keywords: Contracts; Costs; Polynomials
acknowledgement: ack-nhfb
rawauthor: E. Antelo and T. Lang and J. D. Bruguera
rawbooktitle: {Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No. 99CB36336)}
rawtitle: Very-high radix {CORDIC} vectoring with scalings and selection by rounding
entry:
@InProceedings{Antelo:1999:VHR,
  author =       "E. Antelo and T. Lang and J. D. Bruguera",
  booktitle =    "{Proceedings 14th IEEE Symposium on Computer
                 Arithmetic (Cat. No. 99CB36336)}",
  title =        "Very-high radix {CORDIC} vectoring with scalings and
                 selection by rounding",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "204--213",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ARITH.1999.762846",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Contracts; Costs; Polynomials",
}


bibtype: inproceedings
filename: fparith.bib
label: Antelo:1999:VRC
author: Elisardo Antelo and Tomas Lang and Javier D. Bruguera
title: Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding
crossref: Koren:1999:ISC
pages: 204--213
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Elisardo Antelo and Tom{\'a}s Lang and Javier D. Bruguera
rawtitle: Very-High Radix {CORDIC} Vectoring with Scalings and Selection by Rounding
URL:
http://euler.ecs.umass.edu/paper/final/paper-154.pdf; http://euler.ecs.umass.edu/paper/final/paper-154.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Antelo.pdf

abstract:
A very-high radix algorithm and implementation for circular CORDIC in vectoring mode is presented. As for division, to simplify the selection function, the operands are pre-scaled. However, in the CORDIC algorithm the coordinate x varies during the execution so several scalings might be needed; we show that two scalings are sufficient. Moreover, the compensation of the variable scale factor is done by computing the logarithm of the scale factor and performing the compensation by an exponential. Estimations of the delay for 32-bit precision show a speed up of about two with respect to the radix-4 case with redundant addition. This speed up is obtained at the cost of an increase in the hardware complexity, which is moderate for the pipelined implementation.

rawabstract:
A very-high radix algorithm and implementation for circular CORDIC in vectoring mode is presented. As for division, to simplify the selection function, the operands are pre-scaled. However, in the CORDIC algorithm the coordinate x varies during the execution so several scalings might be needed; we show that two scalings are sufficient. Moreover, the compensation of the variable scale factor is done by computing the logarithm of the scale factor and performing the compensation by an exponential. Estimations of the delay for 32-bit precision show a speed up of about two with respect to the radix-4 case with redundant addition. This speed up is obtained at the cost of an increase in the hardware complexity, which is moderate for the pipelined implementation.

entry:
@InProceedings{Antelo:1999:VRC,
  author =       "Elisardo Antelo and Tom{\'a}s Lang and Javier D.
                 Bruguera",
  title =        "Very-High Radix {CORDIC} Vectoring with Scalings and
                 Selection by Rounding",
  crossref =     "Koren:1999:ISC",
  pages =        "204--213",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-154.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-154.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Antelo.pdf",
  abstract =     "A very-high radix algorithm and implementation for
                 circular CORDIC in vectoring mode is presented. As for
                 division, to simplify the selection function, the
                 operands are pre-scaled. However, in the CORDIC
                 algorithm the coordinate x varies during the execution
                 so several scalings might be needed; we show that two
                 scalings are sufficient. Moreover, the compensation of
                 the variable scale factor is done by computing the
                 logarithm of the scale factor and performing the
                 compensation by an exponential. Estimations of the
                 delay for 32-bit precision show a speed up of about two
                 with respect to the radix-4 case with redundant
                 addition. This speed up is obtained at the cost of an
                 increase in the hardware complexity, which is moderate
                 for the pipelined implementation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
  summary =      "A very-high radix algorithm and implementation for
                 circular CORDIC in vectoring mode is presented. As for
                 division, to simplify the selection function, the
                 operands are pre-scaled. However in the CORDIC
                 algorithm the coordinate x varies during the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Aoki:1999:RCA
author: Takafumi Aoki and Ken-ichi Hoshi and Tatsuo Higuchi
title: Redundant Complex Arithmetic and Its Application to Complex Multiplier Design
crossref: IEEE:1999:PII
pages: 200--207
year: 1999
DOI: https://doi.org/10.1109/ISMVL.1999.779717
bibdate: Sat Aug 22 08:46:40 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.08.22 08:46:40 ???
acknowledgement: ack-nhfb
rawauthor: Takafumi Aoki and Ken-ichi Hoshi and Tatsuo Higuchi
rawtitle: Redundant Complex Arithmetic and Its Application to Complex Multiplier Design
abstract:
This paper presents a class of complex number representations called Redundant Complex Number Systems (RCNSs), which are useful for designing VLSI signal processors with complex arithmetic capability. A redundant complex: number system is defined as an imaginary-radix number system having a redundant integer digit set. This makes possible the construction of high-speed complex arithmetic circuits: examples include a complex-number parallel adder with no carry propagation chain, and a complex-number multiplier using fast binary-tree addition structure. This paper also presents the experimental fabrication of the RCNS-based complex multiplier in 0.5 $ mu $ m CMOS technology

rawabstract:
This paper presents a class of complex number representations called Redundant Complex Number Systems (RCNSs), which are useful for designing VLSI signal processors with complex arithmetic capability. A redundant complex: number system is defined as an imaginary-radix number system having a redundant integer digit set. This makes possible the construction of high-speed complex arithmetic circuits: examples include a complex-number parallel adder with no carry propagation chain, and a complex-number multiplier using fast binary-tree addition structure. This paper also presents the experimental fabrication of the RCNS-based complex multiplier in 0.5 $ \mu $ m CMOS technology

entry:
@InProceedings{Aoki:1999:RCA,
  author =       "Takafumi Aoki and Ken-ichi Hoshi and Tatsuo Higuchi",
  title =        "Redundant Complex Arithmetic and Its Application to
                 Complex Multiplier Design",
  crossref =     "IEEE:1999:PII",
  pages =        "200--207",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ISMVL.1999.779717",
  bibdate =      "Sat Aug 22 08:46:40 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a class of complex number
                 representations called Redundant Complex Number Systems
                 (RCNSs), which are useful for designing VLSI signal
                 processors with complex arithmetic capability. A
                 redundant complex: number system is defined as an
                 imaginary-radix number system having a redundant
                 integer digit set. This makes possible the construction
                 of high-speed complex arithmetic circuits: examples
                 include a complex-number parallel adder with no carry
                 propagation chain, and a complex-number multiplier
                 using fast binary-tree addition structure. This paper
                 also presents the experimental fabrication of the
                 RCNS-based complex multiplier in 0.5 $ \mu $ m CMOS
                 technology",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bach:1999:NTS
author: E. Bach and K. Huber
title: Note on taking square-roots modulo $N$
journal: j-IEEE-TRANS-INF-THEORY
volume: 45
number: 2
pages: 807--809
month: mar
monthnumber: 3
year: 1999
CODEN: IETTAW
DOI: https://doi.org/10.1109/18.749034
ISSN: 0018-9448 (print), 1557-9654 (electronic) OR 00189448 (print), 15579654 (electronic)
ISSNL: 0018-9448 OR 00189448
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
fjournal: IEEE Transactions on Information Theory
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=18
rawauthor: E. Bach and K. Huber
rawtitle: Note on taking square-roots modulo {$N$}
entry:
@Article{Bach:1999:NTS,
  author =       "E. Bach and K. Huber",
  title =        "Note on taking square-roots modulo {$N$}",
  journal =      j-IEEE-TRANS-INF-THEORY,
  volume =       "45",
  number =       "2",
  pages =        "807--809",
  month =        mar,
  year =         "1999",
  CODEN =        "IETTAW",
  DOI =          "https://doi.org/10.1109/18.749034",
  ISSN =         "0018-9448 (print), 1557-9654 (electronic)",
  ISSN-L =       "0018-9448",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Information Theory",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=18",
  summary =      "In this article it is shown how Gauss' (1981) famous
                 cyclotomic sum formula can be used for extracting
                 square-roots modulo \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Batten:1999:IBO
author: D. Batten and S. Jinturkar and J. Glossner and M. Schulte and R. Peri and P. D'arcy
title: Interactions Between Optimizations and a New Type of DSP Intrinsic Function
pages: 807--809
year: 1999
bibdate: Sun Mar 04 11:05:23 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:05:23 ???
note: Shortened version in cite Batten:1999:IFB.
URL: http://mesa.ece.wisc.edu/publications/cp_1999-09.pdf
acknowledgement: ack-nhfb
rawauthor: D. Batten and S. Jinturkar and J. Glossner and M. Schulte and R. Peri and P. D'arcy
rawnote: Shortened version in \cite{Batten:1999:IFB}.
rawtitle: Interactions Between Optimizations and a New Type of {DSP} Intrinsic Function
booktitle:
Proceedings of the International Conference on Signal Processing Applications and Technologies, Orlando, Florida, November, 1999

rawbooktitle:
Proceedings of the International Conference on Signal Processing Applications and Technologies, Orlando, Florida, November, 1999

entry:
@InProceedings{Batten:1999:IBO,
  author =       "D. Batten and S. Jinturkar and J. Glossner and M.
                 Schulte and R. Peri and P. D'arcy",
  editor =       "????",
  booktitle =    "Proceedings of the International Conference on Signal
                 Processing Applications and Technologies, Orlando,
                 Florida, November, 1999",
  title =        "Interactions Between Optimizations and a New Type of
                 {DSP} Intrinsic Function",
  publisher =    "????",
  address =      "????",
  year =         "1999",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sun Mar 04 11:05:23 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Shortened version in \cite{Batten:1999:IFB}.",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-09.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Batten:1999:IFB
author: D. Batten and P. D'arcy
title: Intrinsic Functions Boost Compilers
journal: Electrical Engineering Times
volume: 1085
pages: 104--104
month: nov
monthnumber: 11
year: 1999
bibdate: Sun Mar 04 11:06:22 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:06:22 ???
acknowledgement: ack-nhfb
rawauthor: D. Batten and P. D'arcy
rawtitle: Intrinsic Functions Boost Compilers
entry:
@Article{Batten:1999:IFB,
  author =       "D. Batten and P. D'arcy",
  title =        "Intrinsic Functions Boost Compilers",
  journal =      "Electrical Engineering Times",
  volume =       "1085",
  pages =        "104--104",
  month =        nov,
  year =         "1999",
  bibdate =      "Sun Mar 04 11:06:22 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Beaumont-Smith:1999:RLI
author: A. Beaumont-Smith and N. Burgess and S. Lefrere and C. C. Lim
title: Reduced Latency IEEE Floating-Point Standard Adder Architectures
crossref: Koren:1999:ISC
pages: 35--43
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: A. Beaumont-Smith and N. Burgess and S. Lefrere and C. C. Lim
rawtitle: Reduced Latency {IEEE} Floating-Point Standard Adder Architectures
URL:
http://euler.ecs.umass.edu/paper/final/paper-163.pdf; http://euler.ecs.umass.edu/paper/final/paper-163.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Beaumont_Smith.pdf

abstract:
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses ``flagged prefix addition'' to merge rounding with the significand addition. The floating-point adder is implemented in $ 0.5 mu $ m CMOS, measures $ 1.8 $ mm$^2$, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.

rawabstract:
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses ``flagged prefix addition'' to merge rounding with the significand addition. The floating-point adder is implemented in $ 0.5 \mu $ m CMOS, measures $ 1.8 $ mm$^2$, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.

entry:
@InProceedings{Beaumont-Smith:1999:RLI,
  author =       "A. Beaumont-Smith and N. Burgess and S. Lefrere and C.
                 C. Lim",
  title =        "Reduced Latency {IEEE} Floating-Point Standard Adder
                 Architectures",
  crossref =     "Koren:1999:ISC",
  pages =        "35--43",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-163.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-163.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Beaumont_Smith.pdf",
  abstract =     "The design and implementation of a double precision
                 floating-point IEEE-754 standard adder is described
                 which uses ``flagged prefix addition'' to merge
                 rounding with the significand addition. The
                 floating-point adder is implemented in $ 0.5 \mu $ m
                 CMOS, measures $ 1.8 $ mm$^2$, has a 3-cycle latency
                 and implements all rounding modes. A modified version
                 of this floating-point adder can perform accumulation
                 in 2-cycles with a small amount of extra hardware for
                 use in a parallel processor node. This is achieved by
                 feeding back the previous un-normalised but correctly
                 rounded result together with the normalisation
                 distance. A 2-cycle latency floating-point adder
                 architecture with potentially the same cycle time that
                 also employs flagged prefix addition is described. It
                 also incorporates a fast prediction scheme for the true
                 subtraction of significands with an exponent difference
                 of 1, with one less adder.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic; correct rounding;
                 floating-point arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Benschop:1999:MML
author: Nico Fritz Benschop
title: Multiplier for the multiplication of at least two figures in an original format
pages: 35--43
day: 13
month: jul
monthnumber: 7
year: 1999
bibdate: Fri Jun 24 15:16:03 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 15:16:03 ???
URL: https://patents.google.com/patent/US5923888A
remark: Patent filed 15 December 1997, granted 13 July 1999, expected expiration on 15 December 2017.
acknowledgement: ack-nhfb
howpublished: US Patent number 5,923,888.
rawauthor: Nico Fritz Benschop
rawtitle: Multiplier for the multiplication of at least two figures in an original format
abstract:
The invention relates to a multiplier for the multiplication of at least two figures in an original format. Each of said figures is fed to a first converter for conversion of each of said figures in the product of a first binary number representing a power of 2, and a second binary number representing a signed power of 3, the exponents of the powers of 2 of the concerning figures being fed to a first adder and the exponents of the powers of 3 of the concerning figures being fed to a second adder, whereby the combined respective outputs of the first adder and the second adder represent the multiplied value of said figures, and the resulting powers of 2 and 3 as available at the outputs of the first and second adder being fed to a second converter for conversion of the multiplied value into the original format.

rawabstract:
The invention relates to a multiplier for the multiplication of at least two figures in an original format. Each of said figures is fed to a first converter for conversion of each of said figures in the product of a first binary number representing a power of 2, and a second binary number representing a signed power of 3, the exponents of the powers of 2 of the concerning figures being fed to a first adder and the exponents of the powers of 3 of the concerning figures being fed to a second adder, whereby the combined respective outputs of the first adder and the second adder represent the multiplied value of said figures, and the resulting powers of 2 and 3 as available at the outputs of the first and second adder being fed to a second converter for conversion of the multiplied value into the original format.

entry:
@Misc{Benschop:1999:MML,
  author =       "Nico Fritz Benschop",
  title =        "Multiplier for the multiplication of at least two
                 figures in an original format",
  howpublished = "US Patent number 5,923,888.",
  day =          "13",
  month =        jul,
  year =         "1999",
  bibdate =      "Fri Jun 24 15:16:03 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US5923888A",
  abstract =     "The invention relates to a multiplier for the
                 multiplication of at least two figures in an original
                 format. Each of said figures is fed to a first
                 converter for conversion of each of said figures in the
                 product of a first binary number representing a power
                 of 2, and a second binary number representing a signed
                 power of 3, the exponents of the powers of 2 of the
                 concerning figures being fed to a first adder and the
                 exponents of the powers of 3 of the concerning figures
                 being fed to a second adder, whereby the combined
                 respective outputs of the first adder and the second
                 adder represent the multiplied value of said figures,
                 and the resulting powers of 2 and 3 as available at the
                 outputs of the first and second adder being fed to a
                 second converter for conversion of the multiplied value
                 into the original format.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 15 December 1997, granted 13 July 1999,
                 expected expiration on 15 December 2017.",
}


bibtype: inproceedings
filename: fparith.bib
label: Bhardwaj:1999:RCM
author: M. Bhardwaj and T. Srikanthan and C. T. Clarke
crossref: Koren:1999:ISC
pages: 168--175
year: 1999
DOI: https://doi.org/10.1109/ARITH.1999.762842
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: M. Bhardwaj and T. Srikanthan and C. T. Clarke
title:
A Reverse Converter for the $4$-Moduli Superset $ 2^n - 1 $, $ 2^n $, $ 2^n + 1 $, $ 2^(n + 1) + 1 $

URL:
http://euler.ecs.umass.edu/paper/final/paper-137.pdf; http://euler.ecs.umass.edu/paper/final/paper-137.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Bhardwaj.pdf

abstract:
The authors propose an extension to the popular $ 2^n - 1, 2^n, 2^n + 1 $ moduli set by adding a fourth modulus $ 2^n + 1 + 1 $. This extension leads to higher parallelism while keeping the forward conversion and modular arithmetic units simple. The main challenge of efficient reverse conversion is met by three techniques described for the first time. Firstly, we reverse convert linear combinations of moduli hence reducing the number of non-zero bits in the Booth encoded multiplicands from $n$ to merely 2. Secondly, it is shown that division by 3, if introduced at the right stage, can be implemented very efficiently and can, in turn, reduce the cost of the converter. To implement VLSI efficient modulo reduction, we propose two techniques-multiple split tables (MST) and a modified division algorithm (MDA). It is shown that the MST can reduce exponential ROM requirements to quadratic ROM requirements while the MDA can reduce these further to linear requirements. As a result of these innovations, the proposed reverse converter uses simple shift and add operations and needs a lookup with only 6 entries. The delay of the converter is approximately $ 10 n + 13 $ full adder delays and the area cost is quadratic in $n$.

rawabstract:
The authors propose an extension to the popular $ \{ 2^n - 1, 2^n, 2^n + 1 \} $ moduli set by adding a fourth modulus $ 2^{n + 1} + 1 $. This extension leads to higher parallelism while keeping the forward conversion and modular arithmetic units simple. The main challenge of efficient reverse conversion is met by three techniques described for the first time. Firstly, we reverse convert linear combinations of moduli hence reducing the number of non-zero bits in the Booth encoded multiplicands from $n$ to merely 2. Secondly, it is shown that division by 3, if introduced at the right stage, can be implemented very efficiently and can, in turn, reduce the cost of the converter. To implement VLSI efficient modulo reduction, we propose two techniques-multiple split tables (MST) and a modified division algorithm (MDA). It is shown that the MST can reduce exponential ROM requirements to quadratic ROM requirements while the MDA can reduce these further to linear requirements. As a result of these innovations, the proposed reverse converter uses simple shift and add operations and needs a lookup with only 6 entries. The delay of the converter is approximately $ 10 n + 13 $ full adder delays and the area cost is quadratic in $n$.

rawtitle:
A Reverse Converter for the $4$-Moduli Superset $ \{ 2^n - 1 $, $ 2^n $, $ 2^n + 1 $, $ 2^(n + 1) + 1 \} $

entry:
@InProceedings{Bhardwaj:1999:RCM,
  author =       "M. Bhardwaj and T. Srikanthan and C. T. Clarke",
  title =        "A Reverse Converter for the $4$-Moduli Superset $ \{
                 2^n - 1 $, $ 2^n $, $ 2^n + 1 $, $ 2^(n + 1) + 1 \} $",
  crossref =     "Koren:1999:ISC",
  pages =        "168--175",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ARITH.1999.762842",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-137.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-137.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Bhardwaj.pdf",
  abstract =     "The authors propose an extension to the popular $ \{
                 2^n - 1, 2^n, 2^n + 1 \} $ moduli set by adding a
                 fourth modulus $ 2^{n + 1} + 1 $. This extension leads
                 to higher parallelism while keeping the forward
                 conversion and modular arithmetic units simple. The
                 main challenge of efficient reverse conversion is met
                 by three techniques described for the first time.
                 Firstly, we reverse convert linear combinations of
                 moduli hence reducing the number of non-zero bits in
                 the Booth encoded multiplicands from $n$ to merely 2.
                 Secondly, it is shown that division by 3, if introduced
                 at the right stage, can be implemented very efficiently
                 and can, in turn, reduce the cost of the converter. To
                 implement VLSI efficient modulo reduction, we propose
                 two techniques-multiple split tables (MST) and a
                 modified division algorithm (MDA). It is shown that the
                 MST can reduce exponential ROM requirements to
                 quadratic ROM requirements while the MDA can reduce
                 these further to linear requirements. As a result of
                 these innovations, the proposed reverse converter uses
                 simple shift and add operations and needs a lookup with
                 only 6 entries. The delay of the converter is
                 approximately $ 10 n + 13 $ full adder delays and the
                 area cost is quadratic in $n$.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Bhardwaj:1999:VCA
author: M. Bhardwaj and T. Srikanthan and C. T. Clarke
title: VLSI Costs of Arithmetic Parallelism: a Residue Reverse Conversion Perspective
crossref: Koren:1999:ISC
pages: 176--185
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: M. Bhardwaj and T. Srikanthan and C. T. Clarke
rawtitle: {VLSI} Costs of Arithmetic Parallelism: a Residue Reverse Conversion Perspective
URL:
http://euler.ecs.umass.edu/paper/final/paper-138.pdf; http://euler.ecs.umass.edu/paper/final/paper-138.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Bhardwaj_VLSI.pdf

abstract:
This paper reports how VLSI cost metrics (area, delay, power) of residue reverse converters scale with the cardinality and dynamic range of moduli sets. The study uses CMAC reverse converters, reported previously by the authors to be the most efficient known to date in terms of area and delay. In all, 134 reverse converters with dynamic ranges from 32 to 120 bits and set cardinalities ranging from 4 to 20 are actually constructed and analyzed. It is seen that area, delay and power costs are cardinality insensitive once the cardinality exceeds a threshold (usually between five to eight). For cardinalities beyond this threshold, conversion costs are essentially dynamic range dependent. This insensitivity is explained in detail by noting the counterbalancing effects of the various sub-units of a CMAC reverse converter. Since practical implementations of RNS usually employ cardinalities beyond the abovementioned thresholds, the significance of this study is its conclusion that increasing the set cardinality in most implementations will have a marginal, if any, effect on VLSI reverse conversion costs.

rawabstract:
This paper reports how VLSI cost metrics (area, delay, power) of residue reverse converters scale with the cardinality and dynamic range of moduli sets. The study uses CMAC reverse converters, reported previously by the authors to be the most efficient known to date in terms of area and delay. In all, 134 reverse converters with dynamic ranges from 32 to 120 bits and set cardinalities ranging from 4 to 20 are actually constructed and analyzed. It is seen that area, delay and power costs are cardinality insensitive once the cardinality exceeds a threshold (usually between five to eight). For cardinalities beyond this threshold, conversion costs are essentially dynamic range dependent. This insensitivity is explained in detail by noting the counterbalancing effects of the various sub-units of a CMAC reverse converter. Since practical implementations of RNS usually employ cardinalities beyond the abovementioned thresholds, the significance of this study is its conclusion that increasing the set cardinality in most implementations will have a marginal, if any, effect on VLSI reverse conversion costs.

entry:
@InProceedings{Bhardwaj:1999:VCA,
  author =       "M. Bhardwaj and T. Srikanthan and C. T. Clarke",
  title =        "{VLSI} Costs of Arithmetic Parallelism: a Residue
                 Reverse Conversion Perspective",
  crossref =     "Koren:1999:ISC",
  pages =        "176--185",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-138.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-138.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Bhardwaj_VLSI.pdf",
  abstract =     "This paper reports how VLSI cost metrics (area, delay,
                 power) of residue reverse converters scale with the
                 cardinality and dynamic range of moduli sets. The study
                 uses CMAC reverse converters, reported previously by
                 the authors to be the most efficient known to date in
                 terms of area and delay. In all, 134 reverse converters
                 with dynamic ranges from 32 to 120 bits and set
                 cardinalities ranging from 4 to 20 are actually
                 constructed and analyzed. It is seen that area, delay
                 and power costs are cardinality insensitive once the
                 cardinality exceeds a threshold (usually between five
                 to eight). For cardinalities beyond this threshold,
                 conversion costs are essentially dynamic range
                 dependent. This insensitivity is explained in detail by
                 noting the counterbalancing effects of the various
                 sub-units of a CMAC reverse converter. Since practical
                 implementations of RNS usually employ cardinalities
                 beyond the abovementioned thresholds, the significance
                 of this study is its conclusion that increasing the set
                 cardinality in most implementations will have a
                 marginal, if any, effect on VLSI reverse conversion
                 costs.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Blum:1999:MME
author: Thomas Blum and Christoph Paar
title: Montgomery Modular Exponentiation on Reconfigurable Hardware
crossref: Koren:1999:ISC
pages: 70--77
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Thomas Blum and Christoph Paar
rawtitle: {Montgomery} Modular Exponentiation on Reconfigurable Hardware
URL:
http://euler.ecs.umass.edu/paper/final/paper-133.pdf; http://euler.ecs.umass.edu/paper/final/paper-133.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Blum.pdf

abstract:
It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operand and modulus.par Unlike previous approaches, we systematically implement and compare several variants of our new architecture for different bit lengths. We provide absolute area and timing measures for each architecture. The results allow conclusions about the feasibility and time-space trade-offs of our architecture for implementation on Xilinx XC4000 series FPGAs. As a major practical result we show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.

rawabstract:
It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operand and modulus.\par Unlike previous approaches, we systematically implement and compare several variants of our new architecture for different bit lengths. We provide absolute area and timing measures for each architecture. The results allow conclusions about the feasibility and time-space trade-offs of our architecture for implementation on Xilinx XC4000 series FPGAs. As a major practical result we show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.

entry:
@InProceedings{Blum:1999:MME,
  author =       "Thomas Blum and Christoph Paar",
  title =        "{Montgomery} Modular Exponentiation on Reconfigurable
                 Hardware",
  crossref =     "Koren:1999:ISC",
  pages =        "70--77",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-133.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-133.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Blum.pdf",
  abstract =     "It is widely recognized that security issues will play
                 a crucial role in the majority of future computer and
                 communication systems. Central tools for achieving
                 system security are cryptographic algorithms. For
                 performance as well as for physical security reasons,
                 it is often advantageous to realize cryptographic
                 algorithms in hardware. In order to overcome the
                 well-known drawback of reduced flexibility that is
                 associated with traditional ASIC solutions, this
                 contribution proposes arithmetic architectures which
                 are optimized for modern field programmable gate arrays
                 (FPGAs). The proposed architectures perform modular
                 exponentiation with very long integers. This operation
                 is at the heart of many practical public-key algorithms
                 such as RSA and discrete logarithm schemes. We combine
                 the Montgomery modular multiplication algorithm with a
                 new systolic array design, which is capable of
                 processing a variable number of bits per array cell.
                 The designs are flexible, allowing any choice of
                 operand and modulus.\par

                 Unlike previous approaches, we systematically implement
                 and compare several variants of our new architecture
                 for different bit lengths. We provide absolute area and
                 timing measures for each architecture. The results
                 allow conclusions about the feasibility and time-space
                 trade-offs of our architecture for implementation on
                 Xilinx XC4000 series FPGAs. As a major practical result
                 we show that it is possible to implement modular
                 exponentiation at secure bit lengths on a single
                 commercially available FPGA.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: techreport
filename: fparith.bib
label: Boldo:1999:CRE
author: Sylvie Boldo
type: Report
institution: INRIA, Projet Spaces, LORIA, Campus Scientifique
address: B.P. 239, 54506 Vandoeuvre-les-Nancy Cedex, France
pages: 29
year: 1999
bibdate: Tue Nov 23 11:00:03 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.23 11:00:03 ???
note: Under the direction of Paul Zimmermann.
URL: http://perso.ens-lyon.fr/sylvie.boldo/doc/mpfr.ps
language: French
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo
rawnote: Under the direction of Paul Zimmermann.
title:
Calcul rapide et exact de fonctions elementaires en precision arbitraire par la moyenne arithmetico-geometrique. (French) [Rapid and exact computation of elementary functions in arbitrary precision by the arithmetic-geometric mean]

rawtitle:
Calcul rapide et exact de fonctions {\'e}l{\'e}mentaires en pr{\'e}cision arbitraire par la moyenne arithm{\'e}tico-g{\'e}om{\'e}trique. ({French}) [Rapid and exact computation of elementary functions in arbitrary precision by the arithmetic-geometric mean]

entry:
@TechReport{Boldo:1999:CRE,
  author =       "Sylvie Boldo",
  title =        "Calcul rapide et exact de fonctions
                 {\'e}l{\'e}mentaires en pr{\'e}cision arbitraire par la
                 moyenne arithm{\'e}tico-g{\'e}om{\'e}trique. ({French})
                 [Rapid and exact computation of elementary functions in
                 arbitrary precision by the arithmetic-geometric mean]",
  type =         "Report",
  institution =  "INRIA, Projet Spaces, LORIA, Campus Scientifique",
  address =      "B.P. 239, 54506 Vandoeuvre-l{\`e}s-Nancy Cedex,
                 France",
  pages =        "29",
  year =         "1999",
  bibdate =      "Tue Nov 23 11:00:03 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Under the direction of Paul Zimmermann.",
  URL =          "http://perso.ens-lyon.fr/sylvie.boldo/doc/mpfr.ps",
  acknowledgement = ack-nhfb,
  language =     "French",
}


bibtype: inproceedings
filename: fparith.bib
label: Brent:1999:CAP
author: Richard P. Brent
title: Computer Arithmetic --- a Programmer's Perspective
crossref: Koren:1999:ISC
pages: 2--2
year: 1999
bibdate: Wed Jan 20 09:38:39 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.01.20 09:38:39 ???
keywords: ARITH-14
remark: Abstract only: no text of the paper available.
acknowledgement: ack-nhfb
rawauthor: Richard P. Brent
rawtitle: Computer Arithmetic --- a Programmer's Perspective
URL:
http://euler.ecs.umass.edu/paper/final/brentr.pdf; http://euler.ecs.umass.edu/paper/final/brentr.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Brent.pdf

abstract:
Advances in computer hardware often have little impact until they become accessible to programmers using high-level languages. For example, the IEEE floating-point arithmetic standard provides various rounding modes and exceptions, but it is difficult or impossible to take advantage of these from most high-level languages, so the full capabilities of IEEE-compatible hardware are seldom used. When they are used by writing in machine or assembly language, there is a high cost in program development and testing time, lack of portability, and difficulty of software maintenance.par In this talk we discuss several areas in which computer hardware, especially arithmetic hardware, can or should significantly influence programming language design. These include: vector units, floating-point exception handling, floating-point rounding modes, high/extended precision registers/arithmetic, and use of unusual number systems. Relevant application areas include interval arithmetic, high-precision integer arithmetic for computer algebra and cryptography, and testing of hardware by comparison with software simulations.

rawabstract:
Advances in computer hardware often have little impact until they become accessible to programmers using high-level languages. For example, the IEEE floating-point arithmetic standard provides various rounding modes and exceptions, but it is difficult or impossible to take advantage of these from most high-level languages, so the full capabilities of IEEE-compatible hardware are seldom used. When they are used by writing in machine or assembly language, there is a high cost in program development and testing time, lack of portability, and difficulty of software maintenance.\par In this talk we discuss several areas in which computer hardware, especially arithmetic hardware, can or should significantly influence programming language design. These include: vector units, floating-point exception handling, floating-point rounding modes, high/extended precision registers/arithmetic, and use of unusual number systems. Relevant application areas include interval arithmetic, high-precision integer arithmetic for computer algebra and cryptography, and testing of hardware by comparison with software simulations.

entry:
@InProceedings{Brent:1999:CAP,
  author =       "Richard P. Brent",
  title =        "Computer Arithmetic --- a Programmer's Perspective",
  crossref =     "Koren:1999:ISC",
  pages =        "2--2",
  year =         "1999",
  bibdate =      "Wed Jan 20 09:38:39 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/brentr.pdf;
                 http://euler.ecs.umass.edu/paper/final/brentr.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Brent.pdf",
  abstract =     "Advances in computer hardware often have little impact
                 until they become accessible to programmers using
                 high-level languages. For example, the IEEE
                 floating-point arithmetic standard provides various
                 rounding modes and exceptions, but it is difficult or
                 impossible to take advantage of these from most
                 high-level languages, so the full capabilities of
                 IEEE-compatible hardware are seldom used. When they are
                 used by writing in machine or assembly language, there
                 is a high cost in program development and testing time,
                 lack of portability, and difficulty of software
                 maintenance.\par

                 In this talk we discuss several areas in which computer
                 hardware, especially arithmetic hardware, can or should
                 significantly influence programming language design.
                 These include: vector units, floating-point exception
                 handling, floating-point rounding modes, high/extended
                 precision registers/arithmetic, and use of unusual
                 number systems. Relevant application areas include
                 interval arithmetic, high-precision integer arithmetic
                 for computer algebra and cryptography, and testing of
                 hardware by comparison with software simulations.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14",
  remark =       "Abstract only: no text of the paper available.",
}


bibtype: article
filename: fparith.bib
label: Bronnimann:1999:SDR
author: Herve Bronnimann and Ioannis Z. Emiris and Victor Y. Pan and Sylvain Pion
title: Sign determination in residue number systems
journal: j-THEOR-COMP-SCI
volume: 210
number: 1
pages: 173--197
day: 06
month: jan
monthnumber: 1
year: 1999
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Mon Jul 19 22:22:18 MDT 1999
bibtimestamp: 1999.07.19 22:22:18 MDT
URL: http://www.elsevier.com/cas/tree/store/tcs/sub/1999/210/1/2931.pdf
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Herve Bronnimann and Ioannis Z. Emiris and Victor Y. Pan and Sylvain Pion
rawtitle: Sign determination in residue number systems
bibsource:
http://www.elsevier.com/cgi-bin/cas/tree/store/tcs/cas_free/browse/browse.cgi?year=1999&volume=210&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Bronnimann:1999:SDR,
  author =       "Herve Bronnimann and Ioannis Z. Emiris and Victor Y.
                 Pan and Sylvain Pion",
  title =        "Sign determination in residue number systems",
  journal =      j-THEOR-COMP-SCI,
  volume =       "210",
  number =       "1",
  pages =        "173--197",
  day =          "06",
  month =        jan,
  year =         "1999",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Mon Jul 19 22:22:18 MDT 1999",
  bibsource =    "http://www.elsevier.com/cgi-bin/cas/tree/store/tcs/cas_free/browse/browse.cgi?year=1999&volume=210&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.elsevier.com/cas/tree/store/tcs/sub/1999/210/1/2931.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: inproceedings
filename: fparith.bib
label: Bui:1999:DSI
author: H. Bui and S. Tahar
booktitle: 1999 IEEE Canadian Conference on Electrical and Computer Engineering, 9--12 May 1999
title: Design and synthesis of an IEEE-754 exponential function
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 450--455
year: 1999
bibdate: Sat Jul 16 17:14:11 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 17:14:11 MDT
acknowledgement: ack-nhfb
rawauthor: H. Bui and S. Tahar
rawbooktitle: 1999 {IEEE} Canadian Conference on Electrical and Computer Engineering, 9--12 May 1999
rawtitle: Design and synthesis of an {IEEE-754} exponential function
entry:
@InProceedings{Bui:1999:DSI,
  author =       "H. Bui and S. Tahar",
  booktitle =    "1999 {IEEE} Canadian Conference on Electrical and
                 Computer Engineering, 9--12 May 1999",
  title =        "Design and synthesis of an {IEEE-754} exponential
                 function",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "450--455",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 17:14:11 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "We have designed a floating-point exponential function
                 using the table-driven method. The algorithm was first
                 implemented using sequential VHDL and later translated
                 to Concurrent Verilog. The main part of the work
                 consisted of creating modules that \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Burgess:1999:EIR
author: N. Burgess and S. Knowles
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: Efficient implementation of rounding units
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1489--1493
year: 1999
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
acknowledgement: ack-nhfb
rawauthor: N. Burgess and S. Knowles
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: Efficient implementation of rounding units
entry:
@InProceedings{Burgess:1999:EIR,
  author =       "N. Burgess and S. Knowles",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "Efficient implementation of rounding units",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1489--1493",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper shows how IEEE 754 floating-point standard
                 compliant rounding may be merged with carry-propagate
                 addition in high-performance FPU designs. The paper
                 considers addition/subtraction, multiplication and
                 divide/square root operations and \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Burgess:1999:FIS
author: Neil Burgess and Luigi Ciminiera
title: Fifteenth IEEE Symposium on Computer Arithmetic: Foreword
crossref: Koren:1999:ISC
pages: ix--ix
year: 1999
bibdate: Sat Nov 17 21:53:37 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 21:53:37 ???
keywords: ARITH-14
acknowledgement: ack-nhfb
rawauthor: Neil Burgess and Luigi Ciminiera
rawtitle: {Fifteenth IEEE Symposium on Computer Arithmetic}: Foreword
URL:
http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_contents.pdf; http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_foreword.pdf; http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_preface.pdf

entry:
@InProceedings{Burgess:1999:FIS,
  author =       "Neil Burgess and Luigi Ciminiera",
  title =        "{Fifteenth IEEE Symposium on Computer Arithmetic}:
                 Foreword",
  crossref =     "Koren:1999:ISC",
  pages =        "ix--ix",
  year =         "1999",
  bibdate =      "Sat Nov 17 21:53:37 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_contents.pdf;
                 http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_foreword.pdf;
                 http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_preface.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14",
}


bibtype: article
filename: fparith.bib
label: Cappuccino:1999:HSS
author: G. Cappuccino and G. Cocorullo and P. Corsonello and S. Perri
title: High speed self-timed pipelined datapath for square rooting
volume: 146
number: 1
pages: 16--22
month: feb
monthnumber: 2
year: 1999
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: G. Cappuccino and G. Cocorullo and P. Corsonello and S. Perri
rawtitle: High speed self-timed pipelined datapath for square rooting
journal:
Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems]

entry:
@Article{Cappuccino:1999:HSS,
  author =       "G. Cappuccino and G. Cocorullo and P. Corsonello and
                 S. Perri",
  title =        "High speed self-timed pipelined datapath for square
                 rooting",
  journal =      "Circuits, Devices and Systems, IEE Proceedings [see
                 also IEE Proceedings G- Circuits, Devices and
                 Systems]",
  volume =       "146",
  number =       "1",
  pages =        "16--22",
  month =        feb,
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors describe a new high-performance self-timed
                 circuit for asynchronous square rooting. The new
                 architecture is based on a modified nonrestoring
                 algorithm. An asynchronous pipelined cellular array
                 without auxiliary system for the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chren:1999:DSM
author: W. A. Chren, Jr.
title: Delta-sigma modulator with large OSR using the one-hot residue number system
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 46
number: 8
pages: 1002--1008
month: aug
monthnumber: 8
year: 1999
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.782041
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=16972
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: W. A. {Chren, Jr.}
rawtitle: Delta-sigma modulator with large {OSR} using the one-hot residue number system
entry:
@Article{Chren:1999:DSM,
  author =       "W. A. {Chren, Jr.}",
  title =        "Delta-sigma modulator with large {OSR} using the
                 one-hot residue number system",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "46",
  number =       "8",
  pages =        "1002--1008",
  month =        aug,
  year =         "1999",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.782041",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=16972",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  keywords =     "residue arithmetic; residue number system",
  summary =      "A digital delta-sigma modulator using the one-hot
                 residue number system (OHRNS) is presented. It exhibits
                 a large oversampling ratio (OSR) in comparison with
                 equivalent binary designs. Its second-order
                 architecture employs a two-stage cascade \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Christensen:1999:BFP
author: E. L. Christensen
title: Block floating point for radar data
journal: j-IEEE-TRANS-AEROSP-ELECTRON-SYST
volume: 35
number: 1
pages: 308--318
month: jan
monthnumber: 1
year: 1999
CODEN: IEARAX
ISSN: 0018-9251 (print), 1557-9603 (electronic) OR 00189251 (print), 15579603 (electronic)
ISSNL: 0018-9251 OR 00189251
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Aerospace and Electronic Systems
acknowledgement: ack-nhfb
rawauthor: E. L. Christensen
rawtitle: Block floating point for radar data
entry:
@Article{Christensen:1999:BFP,
  author =       "E. L. Christensen",
  title =        "Block floating point for radar data",
  journal =      j-IEEE-TRANS-AEROSP-ELECTRON-SYST,
  volume =       "35",
  number =       "1",
  pages =        "308--318",
  month =        jan,
  year =         "1999",
  CODEN =        "IEARAX",
  ISSN =         "0018-9251 (print), 1557-9603 (electronic)",
  ISSN-L =       "0018-9251",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Aerospace and Electronic
                 Systems",
  summary =      "Integer, floating point, and block floating point
                 (BFP) data formats are analyzed and compared in order
                 to establish the mathematical tools for selection of an
                 optimal format which fulfils the demands of high
                 resolution radar (SAR) data to large \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chung:1999:RAC
author: Sei-Jong Chung
title: Recursive algorithm with C++ program for floating-point arithmetic
journal: j-SIGCSE
volume: 31
number: 2
pages: 28--30
month: jun
monthnumber: 6
year: 1999
CODEN: SIGSD3
DOI: https://doi.org/10.1145/571535.571562
ISSN: 0097-8418 (print), 2331-3927 (electronic) OR 00978418 (print), 23313927 (electronic)
ISSNL: 0097-8418 OR 00978418
bibdate: Sat Nov 17 16:56:38 MST 2012
bibtimestamp: 2012.11.17 16:56:38 MST
fjournal: SIGCSE Bulletin (ACM Special Interest Group on Computer Science Education)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J688
rawauthor: Sei-Jong Chung
rawtitle: Recursive algorithm with {C++} program for floating-point arithmetic
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigcse1990.bib

abstract:
Floating point Arithmetic is a topic included in virtually all textbooks for Computer Systems (CS 3: ACM's Curriculum Recommendation) or for Computer Organization (CS 4: ACM's Curriculum Recommendation). This paper presents a mathematical optimization model for the topic. The problem of converting real (float) numbers into binary equivalents is first modeled as a Zero-One Integer Programming problem. Then, a Recursive Algorithm is formulated for Floating-Point Formats. Computer programs are written in both C and C++ for a 32-bit floating-point format, using the recursive algorithm. [The computer programs are available at the email ldots .]

rawabstract:
Floating point Arithmetic is a topic included in virtually all textbooks for Computer Systems (CS 3: ACM's Curriculum Recommendation) or for Computer Organization (CS 4: ACM's Curriculum Recommendation). This paper presents a mathematical optimization model for the topic. The problem of converting real (float) numbers into binary equivalents is first modeled as a Zero-One Integer Programming problem. Then, a Recursive Algorithm is formulated for Floating-Point Formats. Computer programs are written in both C and C++ for a 32-bit floating-point format, using the recursive algorithm. [The computer programs are available at the email \ldots{}.]

entry:
@Article{Chung:1999:RAC,
  author =       "Sei-Jong Chung",
  title =        "Recursive algorithm with {C++} program for
                 floating-point arithmetic",
  journal =      j-SIGCSE,
  volume =       "31",
  number =       "2",
  pages =        "28--30",
  month =        jun,
  year =         "1999",
  CODEN =        "SIGSD3",
  DOI =          "https://doi.org/10.1145/571535.571562",
  ISSN =         "0097-8418 (print), 2331-3927 (electronic)",
  ISSN-L =       "0097-8418",
  bibdate =      "Sat Nov 17 16:56:38 MST 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigcse1990.bib",
  abstract =     "Floating point Arithmetic is a topic included in
                 virtually all textbooks for Computer Systems (CS 3:
                 ACM's Curriculum Recommendation) or for Computer
                 Organization (CS 4: ACM's Curriculum Recommendation).
                 This paper presents a mathematical optimization model
                 for the topic. The problem of converting real (float)
                 numbers into binary equivalents is first modeled as a
                 Zero-One Integer Programming problem. Then, a Recursive
                 Algorithm is formulated for Floating-Point Formats.
                 Computer programs are written in both C and C++ for a
                 32-bit floating-point format, using the recursive
                 algorithm. [The computer programs are available at the
                 email \ldots{}.]",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGCSE Bulletin (ACM Special Interest Group on
                 Computer Science Education)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J688",
}


bibtype: article
filename: fparith.bib
label: Cilio:1999:FPF
author: A. Cilio and H. Corporaal
title: Floating Point to Fixed Point Conversion of C Code
journal: j-LECT-NOTES-COMP-SCI
volume: 1575
pages: 229--243
year: 1999
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 14 06:09:05 MDT 1999
bibtimestamp: 1999.09.14 06:09:05 MDT
fjournal: Lecture Notes in Computer Science
keywords: CC; compiler construction; ETAPS; software
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: A. Cilio and H. Corporaal
rawtitle: Floating Point to Fixed Point Conversion of {C} Code
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs1999a.bib

entry:
@Article{Cilio:1999:FPF,
  author =       "A. Cilio and H. Corporaal",
  title =        "Floating Point to Fixed Point Conversion of {C} Code",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1575",
  pages =        "229--243",
  year =         "1999",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 14 06:09:05 MDT 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs1999a.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "CC; compiler construction; ETAPS; software",
}


bibtype: article
filename: fparith.bib
label: Clarke:1999:VSD
author: Edmund M. Clarke and Steven M. German and Xudong Zhao
title: Verifying the SRT Division Algorithm Using Theorem Proving Techniques
journal: j-FORM-METHODS-SYST-DES
volume: 14
number: 1
pages: 7--44
month: jan
monthnumber: 1
year: 1999
CODEN: FMSDE6
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Sat Jun 02 09:21:29 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 09:21:29 ???
note: Special issue on arithmetic circuits.
URL: http://www.wkap.nl/jrnltoc.htm/0925-9856; http://www.wkap.nl/oasis.htm/194806
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: Edmund M. Clarke and Steven M. German and Xudong Zhao
rawnote: Special issue on arithmetic circuits.
rawtitle: Verifying the {SRT} Division Algorithm Using Theorem Proving Techniques
entry:
@Article{Clarke:1999:VSD,
  author =       "Edmund M. Clarke and Steven M. German and Xudong
                 Zhao",
  title =        "Verifying the {SRT} Division Algorithm Using Theorem
                 Proving Techniques",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "14",
  number =       "1",
  pages =        "7--44",
  month =        jan,
  year =         "1999",
  CODEN =        "FMSDE6",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Sat Jun 02 09:21:29 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special issue on arithmetic circuits.",
  URL =          "http://www.wkap.nl/jrnltoc.htm/0925-9856;
                 http://www.wkap.nl/oasis.htm/194806",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: article
filename: fparith.bib
label: Clouser:1999:MSF
title: A 600-MHz superscalar floating-point processor
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 34
number: 7
pages: 1026--1029
month: jul
monthnumber: 7
year: 1999
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A {600-MHz} superscalar floating-point processor
author:
J. Clouser and M. Matson and R. Badeau and R. Dupcak and S. Samudrala and R. Allmon and N. Fairbanks

rawauthor:
J. Clouser and M. Matson and R. Badeau and R. Dupcak and S. Samudrala and R. Allmon and N. Fairbanks

entry:
@Article{Clouser:1999:MSF,
  author =       "J. Clouser and M. Matson and R. Badeau and R. Dupcak
                 and S. Samudrala and R. Allmon and N. Fairbanks",
  title =        "A {600-MHz} superscalar floating-point processor",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "34",
  number =       "7",
  pages =        "1026--1029",
  month =        jul,
  year =         "1999",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "The floating-point unit of a 600-MHz, out-of order,
                 superscalar RISC Alpha microprocessor is described. The
                 unit achieves 59 SpecFP95 and can transfer register
                 data at up to 9.6 GB/s. It has two independent
                 pipelines for multiply and add/subtract \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Coleman:1999:BLA
author: J. N. Coleman and E. I. Chester
title: A $ 32 $-Bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point
crossref: Koren:1999:ISC
pages: 142--151
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: J. N. Coleman and E. I. Chester
rawtitle: A $ 32 $-Bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point
URL:
http://euler.ecs.umass.edu/paper/final/paper-160.pdf; http://euler.ecs.umass.edu/paper/final/paper-160.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Coleman.pdf

abstract:
As an alternative to floating-point, several papers have proposed the use of a logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a non-linear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately, and show that these operations are thereby competitive with their floating-point equivalents. We then show that the average performance of the logarithmic system exceeds floating-point, in terms of both speed and accuracy.

rawabstract:
As an alternative to floating-point, several papers have proposed the use of a logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a non-linear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately, and show that these operations are thereby competitive with their floating-point equivalents. We then show that the average performance of the logarithmic system exceeds floating-point, in terms of both speed and accuracy.

entry:
@InProceedings{Coleman:1999:BLA,
  author =       "J. N. Coleman and E. I. Chester",
  title =        "A $ 32 $-Bit Logarithmic Arithmetic Unit and Its
                 Performance Compared to Floating-Point",
  crossref =     "Koren:1999:ISC",
  pages =        "142--151",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-160.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-160.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Coleman.pdf",
  abstract =     "As an alternative to floating-point, several papers
                 have proposed the use of a logarithmic number system,
                 in which a real number is represented as a fixed-point
                 logarithm. Multiplication and division therefore
                 proceed in minimal time with no rounding error.
                 However, the system can only offer an overall advantage
                 if addition and subtraction can be performed with speed
                 and accuracy at least equal to that of floating-point,
                 but these operations require the interpolation of a
                 non-linear function which has hitherto been either
                 time-consuming or inaccurate. We present a procedure by
                 which additions and subtractions can be performed
                 rapidly and accurately, and show that these operations
                 are thereby competitive with their floating-point
                 equivalents. We then show that the average performance
                 of the logarithmic system exceeds floating-point, in
                 terms of both speed and accuracy.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Collavizza:1999:CPC
author: H. Collavizza and F. Delobel and M. Rueher
title: Comparing Partial Consistencies
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 213--228
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: H. Collavizza and F. Delobel and M. Rueher
rawtitle: Comparing Partial Consistencies
remark:
Papers from Scientific computing, computer arithmetic and validated numerics (SCAN '98), September 1998, Budapest, Hungary.

entry:
@Article{Collavizza:1999:CPC,
  author =       "H. Collavizza and F. Delobel and M. Rueher",
  title =        "Comparing Partial Consistencies",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "213--228",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: techreport
filename: fparith.bib
label: Connors:1999:SOF
author: Daniel A. Connors and Yoji Yamada and Wen-mei W. Hwu
title: A Software-Oriented Floating-Point Format for Enhancing Automotive Control Systems
type: Report
address: Urbana, IL 61801, USA
pages: 213--228
day: 11
month: aug
monthnumber: 8
year: 1999
bibdate: Thu Jun 09 18:01:33 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.09 18:01:33 ???
URL: http://rogue.colorado.edu/draco/papers/case-98-float.pd
acknowledgement: ack-nhfb
rawauthor: Daniel A. Connors and Yoji Yamada and Wen-mei W. Hwu
rawtitle: A Software-Oriented Floating-Point Format for Enhancing Automotive Control Systems
institution:
Department of Electrical and Computer Engineering, The Coordinated Science Laboratory, University of Illinois

note:
Updated version of paper presented at the em Workshop on Compiler and Architecture Support for Embedded Computing Systems (CASES98), December, 1998.

remark:
Describes an embedded system with 32-bit floating point with a 24-bit significand, 5-bit signed exponent in excess-15 base-8 representation, with a single zero, no hidden bit, no NaN, no Infinity, and no subnormals.

rawnote:
Updated version of paper presented at the {\em Workshop on Compiler and Architecture Support for Embedded Computing Systems (CASES98), December, 1998}.

entry:
@TechReport{Connors:1999:SOF,
  author =       "Daniel A. Connors and Yoji Yamada and Wen-mei W. Hwu",
  title =        "A Software-Oriented Floating-Point Format for
                 Enhancing Automotive Control Systems",
  type =         "Report",
  institution =  "Department of Electrical and Computer Engineering, The
                 Coordinated Science Laboratory, University of
                 Illinois",
  address =      "Urbana, IL 61801, USA",
  day =          "11",
  month =        aug,
  year =         "1999",
  bibdate =      "Thu Jun 09 18:01:33 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Updated version of paper presented at the {\em
                 Workshop on Compiler and Architecture Support for
                 Embedded Computing Systems (CASES98), December,
                 1998}.",
  URL =          "http://rogue.colorado.edu/draco/papers/case-98-float.pd",
  acknowledgement = ack-nhfb,
  remark =       "Describes an embedded system with 32-bit floating
                 point with a 24-bit significand, 5-bit signed exponent
                 in excess-15 base-8 representation, with a single zero,
                 no hidden bit, no NaN, no Infinity, and no
                 subnormals.",
}


bibtype: article
filename: fparith.bib
label: Constales:1999:PSS
author: Denis Constales
title: Problems and Solutions: Solutions: 10568. Subtracting Square Roots Repeatedly
journal: j-AMER-MATH-MONTHLY
volume: 106
number: 2
pages: 167--167
month: feb
monthnumber: 2
year: 1999
CODEN: AMMYAE
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
bibdate: Wed Dec 29 06:14:39 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.12.29 06:14:39 ???
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: https://www.jstor.org/journals/00029890.htm
rawauthor: Denis Constales
rawtitle: Problems and Solutions: Solutions: 10568. Subtracting Square Roots Repeatedly
entry:
@Article{Constales:1999:PSS,
  author =       "Denis Constales",
  title =        "Problems and Solutions: Solutions: 10568. Subtracting
                 Square Roots Repeatedly",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "106",
  number =       "2",
  pages =        "167--167",
  month =        feb,
  year =         "1999",
  CODEN =        "AMMYAE",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  bibdate =      "Wed Dec 29 06:14:39 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "https://www.jstor.org/journals/00029890.htm",
  xxnote =       "See problem \cite{Knuth:1997:xxx}",
}


bibtype: article
filename: fparith.bib
label: Conway:1999:FCM
author: R. Conway and J. Nelson
title: Fast converter for 3 moduli RNS using new property of CRT
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 8
pages: 852--860
month: aug
monthnumber: 8
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.795127
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:58 MDT 2011
bibtimestamp: 2011.07.06 08:46:58 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=795127
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Conway and J. Nelson
rawtitle: Fast converter for 3 moduli {RNS} using new property of {CRT}
entry:
@Article{Conway:1999:FCM,
  author =       "R. Conway and J. Nelson",
  title =        "Fast converter for 3 moduli {RNS} using new property
                 of {CRT}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "8",
  pages =        "852--860",
  month =        aug,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.795127",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:58 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=795127",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea-Hasegan:1999:CPO
author: Marius A. Cornea-Hasegan and Roger A. Golliver and Peter Markstein
crossref: Koren:1999:ISC
pages: 96--105
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Marius A. Cornea-Hasegan and Roger A. Golliver and Peter Markstein
title:
Correctness proofs outline for Newton--Raphson based floating-point divide and square root algorithms

URL:
http://euler.ecs.umass.edu/paper/final/paper-121.pdf; http://euler.ecs.umass.edu/paper/final/paper-121.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Cornea_Hasegan.pdf

abstract:
This paper describes a study of a class of algorithms for the floating-point divide and square root operations, based on the Newton--Raphson iterative method. The two main goals were:par (1) Proving the IEEE correctness of these iterative floating-point algorithms, i.e. compliance with the IEEE-754 standard for binary floating-point operations [1]. The focus was on software driven iterative algorithms, instead of the hardware based implementations that dominated until now.par (2) Identifying the special cases of operands that require software assistance due to possible overflow, underflow, or loss of precision of intermediate results.par This study was initiated in an attempt to prove the IEEE correctness for a class of divide and square root algorithms based on the Newton--Raphson iterative methods. As more insight into the inner workings of these algorithms was gained, it became obvious that a formal study and proof were necessary in order to achieve the desired objectives. The result is a complete and rigorous proof of IEEE correctness for floating-point divide and square root algorithms based on the Newton--Raphson iterative method. Even more, the method used in proving the IEEE correctness of the square root algorithm is applicable in principle to any iterative algorithm, not only based on the Newton--Raphson method. Conditions requiring Software Assistance (SWA) were also determined, and were used to identify cases when alternate algorithms are needed to generate correct results. Overall, this is one important step toward flawless implementation of these floating-point operations based on software implementations.

rawabstract:
This paper describes a study of a class of algorithms for the floating-point divide and square root operations, based on the Newton--Raphson iterative method. The two main goals were:\par (1) Proving the IEEE correctness of these iterative floating-point algorithms, i.e. compliance with the IEEE-754 standard for binary floating-point operations [1]. The focus was on software driven iterative algorithms, instead of the hardware based implementations that dominated until now.\par (2) Identifying the special cases of operands that require software assistance due to possible overflow, underflow, or loss of precision of intermediate results.\par This study was initiated in an attempt to prove the IEEE correctness for a class of divide and square root algorithms based on the Newton--Raphson iterative methods. As more insight into the inner workings of these algorithms was gained, it became obvious that a formal study and proof were necessary in order to achieve the desired objectives. The result is a complete and rigorous proof of IEEE correctness for floating-point divide and square root algorithms based on the Newton--Raphson iterative method. Even more, the method used in proving the IEEE correctness of the square root algorithm is applicable in principle to any iterative algorithm, not only based on the Newton--Raphson method. Conditions requiring Software Assistance (SWA) were also determined, and were used to identify cases when alternate algorithms are needed to generate correct results. Overall, this is one important step toward flawless implementation of these floating-point operations based on software implementations.

rawtitle:
Correctness proofs outline for {Newton--Raphson} based floating-point divide and square root algorithms

entry:
@InProceedings{Cornea-Hasegan:1999:CPO,
  author =       "Marius A. Cornea-Hasegan and Roger A. Golliver and
                 Peter Markstein",
  title =        "Correctness proofs outline for {Newton--Raphson} based
                 floating-point divide and square root algorithms",
  crossref =     "Koren:1999:ISC",
  pages =        "96--105",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-121.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-121.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Cornea_Hasegan.pdf",
  abstract =     "This paper describes a study of a class of algorithms
                 for the floating-point divide and square root
                 operations, based on the Newton--Raphson iterative
                 method. The two main goals were:\par

                 (1) Proving the IEEE correctness of these iterative
                 floating-point algorithms, i.e. compliance with the
                 IEEE-754 standard for binary floating-point operations
                 [1]. The focus was on software driven iterative
                 algorithms, instead of the hardware based
                 implementations that dominated until now.\par

                 (2) Identifying the special cases of operands that
                 require software assistance due to possible overflow,
                 underflow, or loss of precision of intermediate
                 results.\par

                 This study was initiated in an attempt to prove the
                 IEEE correctness for a class of divide and square root
                 algorithms based on the Newton--Raphson iterative
                 methods. As more insight into the inner workings of
                 these algorithms was gained, it became obvious that a
                 formal study and proof were necessary in order to
                 achieve the desired objectives. The result is a
                 complete and rigorous proof of IEEE correctness for
                 floating-point divide and square root algorithms based
                 on the Newton--Raphson iterative method. Even more, the
                 method used in proving the IEEE correctness of the
                 square root algorithm is applicable in principle to any
                 iterative algorithm, not only based on the
                 Newton--Raphson method. Conditions requiring Software
                 Assistance (SWA) were also determined, and were used to
                 identify cases when alternate algorithms are needed to
                 generate correct results. Overall, this is one
                 important step toward flawless implementation of these
                 floating-point operations based on software
                 implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
  summary =      "This paper describes a study of a class of algorithms
                 for the floating-point divide and square root
                 operations, based on the Newton--Raphson iterative
                 method. The two main goals were. (1) Proving the IEEE
                 correctness of these iterative floating-point
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Cornea-Hasegan:1999:IFP
author: Marius Cornea-Hasegan and Bob Norin
title: IA-64 Floating-Point Operations and the IEEE Standard for Binary Floating-Point Arithmetic
journal: j-INTEL-TECH-J
volume: Q4
pages: 16
day: 22
month: nov
monthnumber: 11
year: 1999
ISSN: 1535-766X OR 1535766X
bibdate: Fri Jun 01 06:02:08 2001
bibtimestamp: 2001.06.01 06:02:08 ???
acknowledgement: ack-nhfb
rawauthor: Marius Cornea-Hasegan and Bob Norin
rawtitle: {IA-64} Floating-Point Operations and the {IEEE} Standard for Binary Floating-Point Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/intel-tech-j.bib

URL:
http://developer.intel.com/technology/itj/q41999/articles/art_6.htm; http://developer.intel.com/technology/itj/q41999/pdf/ia64fpbf.pdf; http://gec.di.uminho.pt/discip/minf/ac0203/icca03/ia64fpbf1.pdf

entry:
@Article{Cornea-Hasegan:1999:IFP,
  author =       "Marius Cornea-Hasegan and Bob Norin",
  title =        "{IA-64} Floating-Point Operations and the {IEEE}
                 Standard for Binary Floating-Point Arithmetic",
  journal =      j-INTEL-TECH-J,
  volume =       "Q4",
  pages =        "16",
  day =          "22",
  month =        nov,
  year =         "1999",
  ISSN =         "1535-766X",
  bibdate =      "Fri Jun 01 06:02:08 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/intel-tech-j.bib",
  URL =          "http://developer.intel.com/technology/itj/q41999/articles/art_6.htm;
                 http://developer.intel.com/technology/itj/q41999/pdf/ia64fpbf.pdf;
                 http://gec.di.uminho.pt/discip/minf/ac0203/icca03/ia64fpbf1.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Corsonello:1999:HPS
author: P. Corsonello and S. Perri
title: High performance square rooting circuit using hybrid radix-$2$ adders
journal: j-ELECT-LETTERS
volume: 35
number: 3
pages: 185--186
day: 4
month: feb
monthnumber: 2
year: 1999
CODEN: ELLEAK
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
fjournal: Electronics Letters
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: P. Corsonello and S. Perri
rawtitle: High performance square rooting circuit using hybrid radix-$2$ adders
entry:
@Article{Corsonello:1999:HPS,
  author =       "P. Corsonello and S. Perri",
  title =        "High performance square rooting circuit using hybrid
                 radix-$2$ adders",
  journal =      j-ELECT-LETTERS,
  volume =       "35",
  number =       "3",
  pages =        "185--186",
  day =          "4",
  month =        feb,
  year =         "1999",
  CODEN =        "ELLEAK",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
  summary =      "A new high performance bit parallel architecture for
                 computing square roots is proposed. The architecture
                 implements a non-restoring algorithm and is structured
                 as a pipelined cellular array. To improve the
                 performance, hybrid radix-$2$ adders are \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Crandall:1999:VIM
author: Richard E. Crandall and Jason Klivington
title: Vector implementation of multiprecision arithmetic
type: Report
institution: Advanced Computation Group, Apple Computer
address: Cupertino, CA, USA
pages: 11
day: 25
month: oct
monthnumber: 10
year: 1999
bibdate: Tue Mar 19 09:06:09 2013
bibtimestamp: 2013.03.19 09:06:09 ???
URL: http://images.apple.com/acg/pdf/G4multiprecision.pdf
acknowledgement: ack-nhfb
rawauthor: Richard E. Crandall and Jason Klivington
rawtitle: Vector implementation of multiprecision arithmetic
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/c/crandall-richard-e.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@TechReport{Crandall:1999:VIM,
  author =       "Richard E. Crandall and Jason Klivington",
  title =        "Vector implementation of multiprecision arithmetic",
  type =         "Report",
  institution =  "Advanced Computation Group, Apple Computer",
  address =      "Cupertino, CA, USA",
  pages =        "11",
  day =          "25",
  month =        oct,
  year =         "1999",
  bibdate =      "Tue Mar 19 09:06:09 2013",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/c/crandall-richard-e.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://images.apple.com/acg/pdf/G4multiprecision.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Cucker:1999:CED
author: Felipe Cucker and Steve Smale
title: Complexity estimates depending on condition and round-off error
journal: j-J-ACM
volume: 46
number: 1
pages: 113--184
month: jan
monthnumber: 1
year: 1999
CODEN: JACOAH
ISSN: 0004-5411 (print), 1557-735X (electronic) OR 00045411 (print), 1557735X (electronic)
ISSNL: 0004-5411 OR 00045411
bibdate: Tue May 25 18:51:21 MDT 1999
bibtimestamp: 1999.05.25 18:51:21 MDT
URL: http://www.acm.org:80/pubs/citations/journals/jacm/1999-46-1/p113-cucker/
fjournal: Journal of the ACM
keywords: algorithms; theory
acknowledgement: ack-nhfb
ajournal: J. Assoc. Comput. Mach.
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J401
rawauthor: Felipe Cucker and Steve Smale
rawtitle: Complexity estimates depending on condition and round-off error
bibsource:
http://www.acm.org/pubs/contents/journals/jacm/1999-46/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This paper has two agendas. One is to develop the foundations of round-off in computation. The other is to describe an algorithm for deciding feasibility for polynomial systems of equations and inequalities together with its complexity analysis and its round-off properties. Each role reinforces the other.

subject:
bf F.2.1 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms and Problems. bf G.1.5 Mathematics of Computing, NUMERICAL ANALYSIS, Roots of Nonlinear Equations.

rawabstract:
This paper has two agendas. One is to develop the foundations of round-off in computation. The other is to describe an algorithm for deciding feasibility for polynomial systems of equations and inequalities together with its complexity analysis and its round-off properties. Each role reinforces the other.

entry:
@Article{Cucker:1999:CED,
  author =       "Felipe Cucker and Steve Smale",
  title =        "Complexity estimates depending on condition and
                 round-off error",
  journal =      j-J-ACM,
  volume =       "46",
  number =       "1",
  pages =        "113--184",
  month =        jan,
  year =         "1999",
  CODEN =        "JACOAH",
  ISSN =         "0004-5411 (print), 1557-735X (electronic)",
  ISSN-L =       "0004-5411",
  bibdate =      "Tue May 25 18:51:21 MDT 1999",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jacm/1999-46/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org:80/pubs/citations/journals/jacm/1999-46-1/p113-cucker/",
  abstract =     "This paper has two agendas. One is to develop the
                 foundations of round-off in computation. The other is
                 to describe an algorithm for deciding feasibility for
                 polynomial systems of equations and inequalities
                 together with its complexity analysis and its round-off
                 properties. Each role reinforces the other.",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Assoc. Comput. Mach.",
  fjournal =     "Journal of the ACM",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J401",
  keywords =     "algorithms; theory",
  subject =      "{\bf F.2.1} Theory of Computation, ANALYSIS OF
                 ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms
                 and Problems. {\bf G.1.5} Mathematics of Computing,
                 NUMERICAL ANALYSIS, Roots of Nonlinear Equations.",
}


bibtype: techreport
filename: fparith.bib
label: Cuyt:1999:UR
author: Annie Cuyt and Peter Kuterna and Brigitte Verdonk and Dennis Verschaeren
title: Underflow revisited
type: Technical report
institution: University of Antwerp (UIA)
address: Antwerp, Belgium
pages: 113--184
year: 1999
bibdate: Mon Feb 25 12:26:10 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.25 12:26:10 ???
URL: ftp://wins.uia.ac.be/pub/preprints/99/underflow.ps
acknowledgement: ack-nhfb
rawauthor: Annie Cuyt and Peter Kuterna and Brigitte Verdonk and Dennis Verschaeren
rawtitle: Underflow revisited
entry:
@TechReport{Cuyt:1999:UR,
  author =       "Annie Cuyt and Peter Kuterna and Brigitte Verdonk and
                 Dennis Verschaeren",
  title =        "Underflow revisited",
  type =         "Technical report",
  institution =  "University of Antwerp (UIA)",
  address =      "Antwerp, Belgium",
  year =         "1999",
  bibdate =      "Mon Feb 25 12:26:10 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://wins.uia.ac.be/pub/preprints/99/underflow.ps",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Darcy:1999:JEF
author: J. D. Darcy
editor: Robert F. Enenkel
booktitle: CASCON 1998 Workshop Report, Numerical Computing: Compiler and Library Support
title: Java's evolving floating-point support: The good, the bad, and the ugly
publisher: IBM Center for Advanced Studies
address: Toronto, ON, Canada
pages: 2--10
year: 1999
bibdate: Sun May 28 18:36:17 2006
bibtimestamp: 2006.05.28 18:36:17 ???
note: Technical report TR-74.165-n.
URL: https://www-927.ibm.com/ibm/cas/publications/TR-74.165/n/numcomp6.pdf
acknowledgement: ack-nhfb
rawauthor: J. D. Darcy
rawbooktitle: {CASCON 1998} Workshop Report, Numerical Computing: Compiler and Library Support
raweditor: Robert F. Enenkel
rawnote: Technical report TR-74.165-n.
rawtitle: {Java}'s evolving floating-point support: The good, the bad, and the ugly
bibsource:
https://www-927.ibm.com/ibm/cas/publications/TR-74.165/TR-74.165.shtml; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@InProceedings{Darcy:1999:JEF,
  author =       "J. D. Darcy",
  editor =       "Robert F. Enenkel",
  booktitle =    "{CASCON 1998} Workshop Report, Numerical Computing:
                 Compiler and Library Support",
  title =        "{Java}'s evolving floating-point support: The good,
                 the bad, and the ugly",
  publisher =    "IBM Center for Advanced Studies",
  address =      "Toronto, ON, Canada",
  pages =        "2--10",
  year =         "1999",
  bibdate =      "Sun May 28 18:36:17 2006",
  bibsource =    "https://www-927.ibm.com/ibm/cas/publications/TR-74.165/TR-74.165.shtml;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Technical report TR-74.165-n.",
  URL =          "https://www-927.ibm.com/ibm/cas/publications/TR-74.165/n/numcomp6.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Daumas:1999:DFP
author: Marc Daumas and C. Finot
title: Division of Floating Point Expansions with an Application to the Computation of a Determinant
journal: j-J-UCS
volume: 5
number: 6
pages: 323--??
day: 28
month: jun
monthnumber: 6
year: 1999
ISSN: 0948-6968 OR 09486968
ISSNL: 0948-6968 OR 09486968
bibdate: Thu Oct 12 14:21:59 MDT 2000
bibsource: http://www.jucs.org/jucs; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.10.12 14:21:59 MDT
URL: http://www.jucs.org/jucs_5_6/division_of_floating_point
fjournal: J.UCS: Journal of Universal Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.jucs.org/jucs
rawauthor: Marc Daumas and C. Finot
rawtitle: Division of Floating Point Expansions with an Application to the Computation of a Determinant
entry:
@Article{Daumas:1999:DFP,
  author =       "Marc Daumas and C. Finot",
  title =        "Division of Floating Point Expansions with an
                 Application to the Computation of a Determinant",
  journal =      j-J-UCS,
  volume =       "5",
  number =       "6",
  pages =        "323--??",
  day =          "28",
  month =        jun,
  year =         "1999",
  CODEN =        "????",
  ISSN =         "0948-6968",
  ISSN-L =       "0948-6968",
  bibdate =      "Thu Oct 12 14:21:59 MDT 2000",
  bibsource =    "http://www.jucs.org/jucs;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.jucs.org/jucs_5_6/division_of_floating_point",
  acknowledgement = ack-nhfb,
  fjournal =     "J.UCS: Journal of Universal Computer Science",
  journal-URL =  "http://www.jucs.org/jucs",
}


bibtype: inproceedings
filename: fparith.bib
label: Daumas:1999:MFP
author: Marc Daumas
title: Multiplications of Floating Point Expansions
crossref: Koren:1999:ISC
pages: 250--257
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Marc Daumas
rawtitle: Multiplications of Floating Point Expansions
URL:
http://euler.ecs.umass.edu/paper/final/paper-102.pdf; http://euler.ecs.umass.edu/paper/final/paper-102.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Daumas.pdf

abstract:
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of any multiple precision application will be dramatically enhanced by adequate use of floating point expansions. We present in this work three multiplication algorithms faster and more integrated than the stepwise algorithm proposed earlier. We have tested these new algorithms on an application that computes the determinant of a matrix. In the absence of overflow or underflow, the process is error free and possibly more efficient than its integer based counterpart.

rawabstract:
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of any multiple precision application will be dramatically enhanced by adequate use of floating point expansions. We present in this work three multiplication algorithms faster and more integrated than the stepwise algorithm proposed earlier. We have tested these new algorithms on an application that computes the determinant of a matrix. In the absence of overflow or underflow, the process is error free and possibly more efficient than its integer based counterpart.

entry:
@InProceedings{Daumas:1999:MFP,
  author =       "Marc Daumas",
  title =        "Multiplications of Floating Point Expansions",
  crossref =     "Koren:1999:ISC",
  pages =        "250--257",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-102.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-102.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Daumas.pdf",
  abstract =     "In modern computers, the floating point unit is the
                 part of the processor delivering the highest computing
                 power and getting most attention from the design team.
                 Performance of any multiple precision application will
                 be dramatically enhanced by adequate use of floating
                 point expansions. We present in this work three
                 multiplication algorithms faster and more integrated
                 than the stepwise algorithm proposed earlier. We have
                 tested these new algorithms on an application that
                 computes the determinant of a matrix. In the absence of
                 overflow or underflow, the process is error free and
                 possibly more efficient than its integer based
                 counterpart.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Denise:1999:URG
author: A. Denise and P. Zimmermann
title: Uniform random generation of decomposable structures using floating-point arithmetic
journal: j-THEOR-COMP-SCI
volume: 218
number: 2
pages: 233--248
day: 26
month: may
monthnumber: 5
year: 1999
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: A. Denise and P. Zimmermann
rawtitle: Uniform random generation of decomposable structures using floating-point arithmetic
entry:
@Article{Denise:1999:URG,
  author =       "A. Denise and P. Zimmermann",
  title =        "Uniform random generation of decomposable structures
                 using floating-point arithmetic",
  journal =      j-THEOR-COMP-SCI,
  volume =       "218",
  number =       "2",
  pages =        "233--248",
  day =          "26",
  month =        may,
  year =         "1999",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
  pagecount =    "16",
}


bibtype: article
filename: fparith.bib
label: Dimitrov:1999:TAD
author: V. S. Dimitrov and G. A. Jullien and W. C. Miller
title: Theory and Applications for a Double-Base Number System
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 10
pages: 1098--1106
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.805158
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Nov 14 18:56:28 2007
bibtimestamp: 2007.11.14 18:56:28 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: V. S. Dimitrov and G. A. Jullien and W. C. Miller
rawtitle: Theory and Applications for a Double-Base Number System
entry:
@Article{Dimitrov:1999:TAD,
  author =       "V. S. Dimitrov and G. A. Jullien and W. C. Miller",
  title =        "Theory and Applications for a Double-Base Number
                 System",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "10",
  pages =        "1098--1106",
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.805158",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Nov 14 18:56:28 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Dimitrova:1999:VCF
author: N. S. Dimitrova and S. M. Markov
title: Verified Computation of Fast Decreasing Polynomials
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 229--240
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: N. S. Dimitrova and S. M. Markov
rawtitle: Verified Computation of Fast Decreasing Polynomials
remark:
Papers from Scientific computing, computer arithmetic and validated numerics (SCAN '98), September 1998, Budapest, Hungary.

entry:
@Article{Dimitrova:1999:VCF,
  author =       "N. S. Dimitrova and S. M. Markov",
  title =        "Verified Computation of Fast Decreasing Polynomials",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "229--240",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: misc
filename: fparith.bib
label: Dyke-Lewis:1999:MAP
author: M. D. V. Dyke-Lewis and W. Meeker
title: Method and Apparatus for performing fast floating point operations
pages: 229--240
day: 12
month: oct
monthnumber: 10
year: 1999
bibdate: Fri Nov 28 15:17:46 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 15:17:46 ???
note: U.S. Patent No. 5,966,085.
acknowledgement: ack-nhfb
rawauthor: M. D. V. Dyke-Lewis and W. Meeker
rawnote: U.S. Patent No. 5,966,085.
rawtitle: Method and Apparatus for performing fast floating point operations
entry:
@Misc{Dyke-Lewis:1999:MAP,
  author =       "M. D. V. Dyke-Lewis and W. Meeker",
  title =        "Method and Apparatus for performing fast floating
                 point operations",
  day =          "12",
  month =        oct,
  year =         "1999",
  bibdate =      "Fri Nov 28 15:17:46 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 5,966,085.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Dyllong:1999:ADC
author: E. Dyllong and W. Luther and W. Otten
title: An Accurate Distance-Calculation Algorithm for Convex Polyhedra
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 241--253
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: E. Dyllong and W. Luther and W. Otten
rawtitle: An Accurate Distance-Calculation Algorithm for Convex Polyhedra
remark:
Papers from Scientific computing, computer arithmetic and validated numerics (SCAN '98), September 1998, Budapest, Hungary.

entry:
@Article{Dyllong:1999:ADC,
  author =       "E. Dyllong and W. Luther and W. Otten",
  title =        "An Accurate Distance-Calculation Algorithm for Convex
                 Polyhedra",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "241--253",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: manual
filename: fparith.bib
label: ECDG:1999:IER
author: European Commission Directorate General II
title: The Introduction of the Euro and the Rounding of Currency Amounts
organization: European Commission Directorate General II Economic and Financial Affairs
address: Brussels, Belgium
pages: 32
month: feb
monthnumber: 2
year: 1999
bibdate: Fri Nov 28 11:18:05 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 11:18:05 ???
note: II/28/99-EN Euro Papers No. 22. Earlier edition dated March 1998.
acknowledgement: ack-nhfb
rawauthor: {European Commission Directorate General II}
rawnote: II/28/99-EN Euro Papers No. 22. Earlier edition dated March 1998.
rawtitle: The Introduction of the Euro and the Rounding of Currency Amounts
entry:
@Manual{ECDG:1999:IER,
  author =       "{European Commission Directorate General II}",
  title =        "The Introduction of the Euro and the Rounding of
                 Currency Amounts",
  organization = "European Commission Directorate General II Economic
                 and Financial Affairs",
  address =      "Brussels, Belgium",
  pages =        "32",
  month =        feb,
  year =         "1999",
  bibdate =      "Fri Nov 28 11:18:05 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "II/28/99-EN Euro Papers No. 22. Earlier edition dated
                 March 1998.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Edalat:1999:NIE
author: A. Edalat and M. Krznaric
title: Numerical Integration with Exact Real Arithmetic
journal: j-LECT-NOTES-COMP-SCI
volume: 1644
pages: 90--??
year: 1999
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Mon Sep 13 16:57:02 MDT 1999
bibtimestamp: 1999.09.13 16:57:02 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: A. Edalat and M. Krznaric
rawtitle: Numerical Integration with Exact Real Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs1999b.bib

entry:
@Article{Edalat:1999:NIE,
  author =       "A. Edalat and M. Krznaric",
  title =        "Numerical Integration with Exact Real Arithmetic",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1644",
  pages =        "90--??",
  year =         "1999",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon Sep 13 16:57:02 MDT 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs1999b.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: techreport
filename: fparith.bib
label: Ercegovac:1999:IGD
author: Milos D. Ercegovac and Laurent Imbert and David W. Matula and Jean-Michel Muller and Guoheng Wei
title: Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
type: Research Report
number: 99-41
institution: Laboratoire de l'Informatique du Parallelisme
address: Lyon, France
pages: ii + 17
month: sep
monthnumber: 9
year: 1999
bibdate: Mon Dec 11 07:53:15 2023
bibtimestamp: 2023.12.11 07:53:15 ???
URL: https://inria.hal.science/inria-00072909/file/RR1999-41.pdf
acknowledgement: ack-nhfb
rawtitle: Improving {Goldschmidt} Division, Square Root, and Square Root Reciprocal
abstract:
The aim of this paper is to accelerate division, square root and square root reciprocal computations, when Goldschmidt method is used on a pipelined multiplier. This is done by replacing the last iteration by the addition of a correcting term that can be looked up during the early iterations. We describe several variants of the Goldschmidt algorithm assuming 4-cycle pipelined multiplier and discuss obtained number of cycles and error achieved. Extensions to other than 4-cycle multipliers are given

keywords:
Computer Arithmetic; Convergence division; Division; Goldschmidt iteration; Square root; Square root reciprocal

rawabstract:
The aim of this paper is to accelerate division, square root and square root reciprocal computations, when Goldschmidt method is used on a pipelined multiplier. This is done by replacing the last iteration by the addition of a correcting term that can be looked up during the early iterations. We describe several variants of the Goldschmidt algorithm assuming 4-cycle pipelined multiplier and discuss obtained number of cycles and error achieved. Extensions to other than 4-cycle multipliers are given

rawauthor:
Milo{\v{s}} D. Ercegovac and Laurent Imbert and David W. Matula and Jean-Michel Muller and Guoheng Wei

entry:
@TechReport{Ercegovac:1999:IGD,
  author =       "Milo{\v{s}} D. Ercegovac and Laurent Imbert and David
                 W. Matula and Jean-Michel Muller and Guoheng Wei",
  title =        "Improving {Goldschmidt} Division, Square Root, and
                 Square Root Reciprocal",
  type =         "Research Report",
  number =       "99-41",
  institution =  "Laboratoire de l'Informatique du Parall{\'e}lisme",
  address =      "Lyon, France",
  pages =        "ii + 17",
  month =        sep,
  year =         "1999",
  bibdate =      "Mon Dec 11 07:53:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/inria-00072909/file/RR1999-41.pdf",
  abstract =     "The aim of this paper is to accelerate division,
                 square root and square root reciprocal computations,
                 when Goldschmidt method is used on a pipelined
                 multiplier. This is done by replacing the last
                 iteration by the addition of a correcting term that can
                 be looked up during the early iterations. We describe
                 several variants of the Goldschmidt algorithm assuming
                 4-cycle pipelined multiplier and discuss obtained
                 number of cycles and error achieved. Extensions to
                 other than 4-cycle multipliers are given",
  acknowledgement = ack-nhfb,
  keywords =     "Computer Arithmetic; Convergence division; Division;
                 Goldschmidt iteration; Square root; Square root
                 reciprocal",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1999:LPB
author: M. Ercegovac and D. Kirovski and M. Potkonjak
booktitle: Proceedings of the 36th Design Automation Conference, 21--25 June 1999
title: Low-power behavioral synthesis optimization using multiple precision arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 568--573
year: 1999
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
rawauthor: M. Ercegovac and D. Kirovski and M. Potkonjak
rawbooktitle: Proceedings of the 36th Design Automation Conference, 21--25 June 1999
rawtitle: Low-power behavioral synthesis optimization using multiple precision arithmetic
entry:
@InProceedings{Ercegovac:1999:LPB,
  author =       "M. Ercegovac and D. Kirovski and M. Potkonjak",
  booktitle =    "Proceedings of the 36th Design Automation Conference,
                 21--25 June 1999",
  title =        "Low-power behavioral synthesis optimization using
                 multiple precision arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "568--573",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Many modern multimedia applications such as image and
                 video processing are characterized by a unique
                 combination of arithmetic and computational features:
                 fixed-point arithmetic, a variety of short data types,
                 high degree of instruction-level \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Even:1999:CTR
author: Guy Even and Peter-Michael Seidel
title: A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
crossref: Koren:1999:ISC
pages: 225--232
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Guy Even and Peter-Michael Seidel
rawtitle: A Comparison of Three Rounding Algorithms for {IEEE} Floating-Point Multiplication
URL:
http://euler.ecs.umass.edu/paper/final/paper-100.pdf; http://euler.ecs.umass.edu/paper/final/paper-100.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Even.pdf

abstract:
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner [23] and of Quach et al. [18]. For each rounding algorithm, a logical description and a block diagram is given and the latency is analyzed.par We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al., and 16 logic levels in the algorithm of Yu and Zyner.

rawabstract:
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner [23] and of Quach et al. [18]. For each rounding algorithm, a logical description and a block diagram is given and the latency is analyzed.\par We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al., and 16 logic levels in the algorithm of Yu and Zyner.

entry:
@InProceedings{Even:1999:CTR,
  author =       "Guy Even and Peter-Michael Seidel",
  title =        "A Comparison of Three Rounding Algorithms for {IEEE}
                 Floating-Point Multiplication",
  crossref =     "Koren:1999:ISC",
  pages =        "225--232",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-100.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-100.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Even.pdf",
  abstract =     "A new IEEE compliant floating-point rounding algorithm
                 for computing the rounded product from a carry-save
                 representation of the product is presented. The new
                 rounding algorithm is compared with the rounding
                 algorithms of Yu and Zyner [23] and of Quach et al.
                 [18]. For each rounding algorithm, a logical
                 description and a block diagram is given and the
                 latency is analyzed.\par

                 We conclude that the new rounding algorithm is the
                 fastest rounding algorithm, provided that an injection
                 (which depends only on the rounding mode and the sign)
                 can be added in during the reduction of the partial
                 products into a carry-save encoded digit string. In
                 double precision the latency of the new rounding
                 algorithm is 12 logic levels compared to 14 logic
                 levels in the algorithm of Quach et al., and 16 logic
                 levels in the algorithm of Yu and Zyner.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Eweda:1999:REA
author: E. Eweda and W. M. Younis and S. H. El-Ramly
booktitle: Proceedings of the Sixteenth National Radio Science Conference 1999: NRSC '99
title: Roundoff error analysis of the tracking performance of the block LMS algorithm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: C30/1--C30/9
year: 1999
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: E. Eweda and W. M. Younis and S. H. El-Ramly
rawbooktitle: Proceedings of the Sixteenth National Radio Science Conference 1999: {NRSC '99}
rawtitle: Roundoff error analysis of the tracking performance of the block {LMS} algorithm
entry:
@InProceedings{Eweda:1999:REA,
  author =       "E. Eweda and W. M. Younis and S. H. El-Ramly",
  booktitle =    "Proceedings of the Sixteenth National Radio Science
                 Conference 1999: {NRSC '99}",
  title =        "Roundoff error analysis of the tracking performance of
                 the block {LMS} algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "C30/1--C30/9",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The paper is concerned with analyzing the roundoff
                 error effect on the tracking performance of the block
                 least mean square (BLMS) algorithm when used in the
                 adaptive identification of a time-varying plant.
                 Rounding quantization is assumed. \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Farid:1999:RCA
author: T. Farid and D. Zerbino
title: Realization of Complex Arithmetic on Cellular Automata
journal: j-LECT-NOTES-COMP-SCI
volume: 1662
pages: 479--??
year: 1999
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Mon Sep 13 16:57:02 MDT 1999
bibtimestamp: 1999.09.13 16:57:02 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: T. Farid and D. Zerbino
rawtitle: Realization of Complex Arithmetic on Cellular Automata
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs1999b.bib

entry:
@Article{Farid:1999:RCA,
  author =       "T. Farid and D. Zerbino",
  title =        "Realization of Complex Arithmetic on Cellular
                 Automata",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1662",
  pages =        "479--??",
  year =         "1999",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon Sep 13 16:57:02 MDT 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs1999b.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Fateman:1999:SEN
author: Richard J. Fateman
title: Symbolic execution and NaNs: diagnostic tools for tracking scientific computation
journal: j-SIGSAM
volume: 33
number: 3
pages: 25--26
month: sep
monthnumber: 9
year: 1999
CODEN: SIGSBZ
ISSN: 0163-5824 (print), 1557-9492 (electronic) OR 01635824 (print), 15579492 (electronic)
ISSNL: 0163-5824 OR 01635824
bibdate: Fri Feb 8 18:27:06 MST 2002
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.08 18:27:06 MST
fjournal: SIGSAM Bulletin
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: Richard J. Fateman
rawtitle: Symbolic execution and {NaNs}: diagnostic tools for tracking scientific computation
entry:
@Article{Fateman:1999:SEN,
  author =       "Richard J. Fateman",
  title =        "Symbolic execution and {NaNs}: diagnostic tools for
                 tracking scientific computation",
  journal =      j-SIGSAM,
  volume =       "33",
  number =       "3",
  pages =        "25--26",
  month =        sep,
  year =         "1999",
  CODEN =        "SIGSBZ",
  ISSN =         "0163-5824 (print), 1557-9492 (electronic)",
  ISSN-L =       "0163-5824",
  bibdate =      "Fri Feb 8 18:27:06 MST 2002",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGSAM Bulletin",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: inproceedings
filename: fparith.bib
label: Fernandez:1999:NID
author: P. G. Fernandez and A. Garcia and J. Ramirez and L. Parrilla and A. Lloris
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: A new implementation of the discrete cosine transform in the residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1302--1306
year: 1999
DOI: https://doi.org/10.1109/ACSSC.1999.831917
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: P. G. Fernandez and A. Garcia and J. Ramirez and L. Parrilla and A. Lloris
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: A new implementation of the discrete cosine transform in the residue number system
entry:
@InProceedings{Fernandez:1999:NID,
  author =       "P. G. Fernandez and A. Garcia and J. Ramirez and L.
                 Parrilla and A. Lloris",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "A new implementation of the discrete cosine transform
                 in the residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1302--1306",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ACSSC.1999.831917",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A field-programmable logic (FPL) implementation of a
                 discrete cosine transform (DCT) based on the residue
                 number system (RNS) is presented. Compared with a
                 binary distributed arithmetic implementation, the
                 presented architecture provides \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Fiore:1999:PMU
author: P. D. Fiore
title: Parallel multiplication using fast sorting networks
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 6
pages: 640--645
month: jun
monthnumber: 6
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.773800
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:58 MDT 2011
bibtimestamp: 2011.07.06 08:46:58 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=773800
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. D. Fiore
rawtitle: Parallel multiplication using fast sorting networks
entry:
@Article{Fiore:1999:PMU,
  author =       "P. D. Fiore",
  title =        "Parallel multiplication using fast sorting networks",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "6",
  pages =        "640--645",
  month =        jun,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.773800",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:58 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=773800",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Flynn:1999:FDA
author: Patrick Hung and Hossam Fahmy and Oskar Mencer and Michael J. Flynn
editor: IEEE
booktitle: Asilomar Conference on Signals, Systems, and Computers, California, Nov. 1999
title: Fast Division Algorithm with a Small Lookup Table
publisher: pub-IEEE
address: pub-IEEE:adr
pages: ??--??
year: 1999
bibdate: Mon Jul 18 17:26:03 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.18 17:26:03 ???
URL: ftp://arith.stanford.edu/tr/asil99div.ps.gz
acknowledgement: ack-nhfb
rawauthor: Patrick Hung and Hossam Fahmy and Oskar Mencer and Michael J. Flynn
rawbooktitle: Asilomar Conference on Signals, Systems, and Computers, California, Nov. 1999
raweditor: {IEEE}
rawtitle: Fast Division Algorithm with a Small Lookup Table
abstract:
This paper presents a new division algorithm, which requires two multiplication operations and a single lookup in a small table. The division algorithm takes two steps. The table lookup and the first multiplication are processed concurrently in the first step, and the second multiplication is executed in the next step. This divider uses a single multiplier and a lookup table with $ 2^m(2 m + 1) $ bits to produce $ 2 m $-bit results that are guaranteed correct to one ulp. By using a multiplier and a KB lookup table, the basic algorithm generates a 24-bit result in two cycles.

rawabstract:
This paper presents a new division algorithm, which requires two multiplication operations and a single lookup in a small table. The division algorithm takes two steps. The table lookup and the first multiplication are processed concurrently in the first step, and the second multiplication is executed in the next step. This divider uses a single multiplier and a lookup table with $ 2^m(2 m + 1) $ bits to produce $ 2 m $-bit results that are guaranteed correct to one ulp. By using a multiplier and a KB lookup table, the basic algorithm generates a 24-bit result in two cycles.

entry:
@InProceedings{Flynn:1999:FDA,
  author =       "Patrick Hung and Hossam Fahmy and Oskar Mencer and
                 Michael J. Flynn",
  editor =       "{IEEE}",
  booktitle =    "Asilomar Conference on Signals, Systems, and
                 Computers, California, Nov. 1999",
  title =        "Fast Division Algorithm with a Small Lookup Table",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "??--??",
  year =         "1999",
  bibdate =      "Mon Jul 18 17:26:03 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://arith.stanford.edu/tr/asil99div.ps.gz",
  abstract =     "This paper presents a new division algorithm, which
                 requires two multiplication operations and a single
                 lookup in a small table. The division algorithm takes
                 two steps. The table lookup and the first
                 multiplication are processed concurrently in the first
                 step, and the second multiplication is executed in the
                 next step. This divider uses a single multiplier and a
                 lookup table with $ 2^m(2 m + 1) $ bits to produce $ 2
                 m $-bit results that are guaranteed correct to one ulp.
                 By using a multiplier and a KB lookup table, the basic
                 algorithm generates a 24-bit result in two cycles.",
  acknowledgement = ack-nhfb,
  pagecount =    "4",
}


bibtype: inproceedings
filename: fparith.bib
label: Freking:1999:MMM
author: W. L. Freking and K. K. Parhi
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: Montgomery modular multiplication and exponentiation in the residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1312--1316
year: 1999
DOI: https://doi.org/10.1109/ACSSC.1999.831919
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. L. Freking and K. K. Parhi
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: {Montgomery} modular multiplication and exponentiation in the residue number system
entry:
@InProceedings{Freking:1999:MMM,
  author =       "W. L. Freking and K. K. Parhi",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "{Montgomery} modular multiplication and exponentiation
                 in the residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1312--1316",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ACSSC.1999.831919",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Modular exponentiation and its constituent operation,
                 modular multiplication, are fundamental to numerous
                 public-key cryptography schemes including RSA.
                 Efficient hardware implementations via ASIC or
                 coprocessor approaches are essential to high-
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Frommer:1999:VEB
author: A. Frommer and A. Weinberg
title: Verified Error Bounds for Linear Systems Through the Lanczos Process
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 255--267
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: A. Frommer and A. Weinberg
rawtitle: Verified Error Bounds for Linear Systems Through the {Lanczos} Process
entry:
@Article{Frommer:1999:VEB,
  author =       "A. Frommer and A. Weinberg",
  title =        "Verified Error Bounds for Linear Systems Through the
                 {Lanczos} Process",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "255--267",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: article
filename: fparith.bib
label: Garcia:1999:LSS
author: A. Garcia and A. Lloris
title: A look-up scheme for scaling in the RNS
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 7
pages: 748--751
month: jul
monthnumber: 7
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.780883
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:58 MDT 2011
bibtimestamp: 2011.07.06 08:46:58 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=780883
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Garcia and A. Lloris
rawtitle: A look-up scheme for scaling in the {RNS}
entry:
@Article{Garcia:1999:LSS,
  author =       "A. Garcia and A. Lloris",
  title =        "A look-up scheme for scaling in the {RNS}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "7",
  pages =        "748--751",
  month =        jul,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.780883",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:58 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=780883",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Gay:1999:SAF
author: David M. Gay and Eric Grosse
title: Self-adapting Fortran 77 Machine Constants: Comment on Algorithm 528
journal: j-TOMS
volume: 25
number: 1
pages: 123--126
month: mar
monthnumber: 3
year: 1999
CODEN: ACMSCU
DOI: https://doi.org/10.1145/305658.305711
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Oct 20 12:38:08 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.10.20 12:38:08 ???
note: See cite Fox:1978:AFP.
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: algorithms; d1mach; languages; machine environment parameters
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: David M. Gay and Eric Grosse
rawnote: See \cite{Fox:1978:AFP}.
rawtitle: Self-adapting {Fortran 77} Machine Constants: Comment on {Algorithm 528}
URL:
http://cm.bell-labs.com/who/ehg/mach/d1mach.ps; http://www.acm.org/pubs/citations/journals/toms/cgi-bin/TOMSbibget?Gay:1999:SAF; http://www.acm.org/pubs/citations/journals/toms/cgi-bin/TOMScitation?Fox:1978:AFP; http://www.acm.org:80/pubs/citations/journals/toms/1999-25-1/p123-gay/

abstract:
This note discusses user dissatisfaction with the need to uncomment data statements in Algorithm 528, comments on alternative approaches tried by the community, and proposes a solution that is both automatic and safe.

subject:
bf D.3.2 Software, PROGRAMMING LANGUAGES, Language Classifications, FORTRAN 77. bf G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic.

rawabstract:
This note discusses user dissatisfaction with the need to uncomment data statements in Algorithm 528, comments on alternative approaches tried by the community, and proposes a solution that is both automatic and safe.

entry:
@Article{Gay:1999:SAF,
  author =       "David M. Gay and Eric Grosse",
  title =        "Self-adapting {Fortran 77} Machine Constants: Comment
                 on {Algorithm 528}",
  journal =      j-TOMS,
  volume =       "25",
  number =       "1",
  pages =        "123--126",
  month =        mar,
  year =         "1999",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/305658.305711",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Oct 20 12:38:08 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Fox:1978:AFP}.",
  URL =          "http://cm.bell-labs.com/who/ehg/mach/d1mach.ps;
                 http://www.acm.org/pubs/citations/journals/toms/cgi-bin/TOMSbibget?Gay:1999:SAF;
                 http://www.acm.org/pubs/citations/journals/toms/cgi-bin/TOMScitation?Fox:1978:AFP;
                 http://www.acm.org:80/pubs/citations/journals/toms/1999-25-1/p123-gay/",
  abstract =     "This note discusses user dissatisfaction with the need
                 to uncomment data statements in Algorithm 528, comments
                 on alternative approaches tried by the community, and
                 proposes a solution that is both automatic and safe.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "algorithms; d1mach; languages; machine environment
                 parameters",
  subject =      "{\bf D.3.2} Software, PROGRAMMING LANGUAGES, Language
                 Classifications, FORTRAN 77. {\bf G.1.0} Mathematics of
                 Computing, NUMERICAL ANALYSIS, General, Computer
                 arithmetic.",
}


bibtype: article
filename: fparith.bib
label: German:1999:ISI
author: Steven M. German
title: Introduction to the Special Issue on Verification of Arithmetic Hardware
journal: j-FORM-METHODS-SYST-DES
volume: 14
number: 1
pages: 5--6
month: jan
monthnumber: 1
year: 1999
CODEN: FMSDE6
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Sat Jun 02 09:20:18 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 09:20:18 ???
URL: http://www.wkap.nl/jrnltoc.htm/0925-9856; http://www.wkap.nl/oasis.htm/194805
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: Steven M. German
rawtitle: Introduction to the Special Issue on Verification of Arithmetic Hardware
entry:
@Article{German:1999:ISI,
  author =       "Steven M. German",
  title =        "Introduction to the Special Issue on Verification of
                 Arithmetic Hardware",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "14",
  number =       "1",
  pages =        "5--6",
  month =        jan,
  year =         "1999",
  CODEN =        "FMSDE6",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Sat Jun 02 09:20:18 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.wkap.nl/jrnltoc.htm/0925-9856;
                 http://www.wkap.nl/oasis.htm/194805",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: inproceedings
filename: fparith.bib
label: Gerwig:1999:FPU
author: Guenter Gerwig and Michael Kroener
title: Floating-Point Unit in Standard Cell Design with $ 116 $ bit Wide Dataflow
crossref: Koren:1999:ISC
pages: 266--273
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Guenter Gerwig and Michael Kroener
rawtitle: Floating-Point Unit in Standard Cell Design with $ 116 $ bit Wide Dataflow
URL:
http://euler.ecs.umass.edu/paper/final/paper-132.pdf; http://euler.ecs.umass.edu/paper/final/paper-132.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Gerwig.pdf

abstract:
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the register array, there are no other dataflow macros used; it is fully designed with standard cell books and is placed flat with a timing driven placement algorithm. This design method allows more `irregular' structures than usually found in custom designs.par An overview of the floating-point unit is given and some interesting design items are shown: a 120 bit-wide true-complement adder with precounting of leading zero digits, a signed multiplier with bit-optimized Wallace tree, intensive forwarding in source equal target cases and the checking method.

rawabstract:
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the register array, there are no other dataflow macros used; it is fully designed with standard cell books and is placed flat with a timing driven placement algorithm. This design method allows more `irregular' structures than usually found in custom designs.\par An overview of the floating-point unit is given and some interesting design items are shown: a 120 bit-wide true-complement adder with precounting of leading zero digits, a signed multiplier with bit-optimized Wallace tree, intensive forwarding in source equal target cases and the checking method.

entry:
@InProceedings{Gerwig:1999:FPU,
  author =       "Guenter Gerwig and Michael Kroener",
  title =        "Floating-Point Unit in Standard Cell Design with $ 116
                 $ bit Wide Dataflow",
  crossref =     "Koren:1999:ISC",
  pages =        "266--273",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-132.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-132.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Gerwig.pdf",
  abstract =     "The floating-point unit of a S/390 CMOS microprocessor
                 is described. It contains a 116 bit fraction dataflow
                 for addition and subtraction and a 64 bit-wide
                 multiplier. Besides the register array, there are no
                 other dataflow macros used; it is fully designed with
                 standard cell books and is placed flat with a timing
                 driven placement algorithm. This design method allows
                 more `irregular' structures than usually found in
                 custom designs.\par

                 An overview of the floating-point unit is given and
                 some interesting design items are shown: a 120 bit-wide
                 true-complement adder with precounting of leading zero
                 digits, a signed multiplier with bit-optimized Wallace
                 tree, intensive forwarding in source equal target cases
                 and the checking method.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Gizopoulos:1999:EBS
author: D. Gizopoulos and A. Paschalis and Y. Zorian
title: An effective built-in self-test scheme for parallel multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 9
pages: 936--950
month: sep
monthnumber: 9
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.795222
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:59 MDT 2011
bibtimestamp: 2011.07.06 08:46:59 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=795222
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Gizopoulos and A. Paschalis and Y. Zorian
rawtitle: An effective built-in self-test scheme for parallel multipliers
entry:
@Article{Gizopoulos:1999:EBS,
  author =       "D. Gizopoulos and A. Paschalis and Y. Zorian",
  title =        "An effective built-in self-test scheme for parallel
                 multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "9",
  pages =        "936--950",
  month =        sep,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.795222",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:59 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=795222",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Gorshtein:1999:MAM
author: V. Y. Gorshtein and V. T. Khlobystov
pages: 936--950
day: 5
month: oct
monthnumber: 10
year: 1999
bibdate: Fri Nov 28 15:32:30 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 15:32:30 ???
note: U.S. Patent No. 5,963,461.
acknowledgement: ack-nhfb
rawauthor: V. Y. Gorshtein and V. T. Khlobystov
rawnote: U.S. Patent No. 5,963,461.
title:
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization

rawtitle:
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization

entry:
@Misc{Gorshtein:1999:MAM,
  author =       "V. Y. Gorshtein and V. T. Khlobystov",
  title =        "Multiplication apparatus and methods which generate a
                 shift amount by which the product of the significands
                 is shifted for normalization or denormalization",
  day =          "5",
  month =        oct,
  year =         "1999",
  bibdate =      "Fri Nov 28 15:32:30 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 5,963,461.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Gueron:1999:FFP
author: Shay Gueron
title: Flying in a floating (point) world
journal: International Journal of Computers for Mathematical Learning
volume: 4
number: 2--3
pages: 225--234
month: may
monthnumber: 5
year: 1999
DOI: https://doi.org/10.1023/A:1009818429410
ISSN: 1382-3892 (print), 1573-1766 (electronic) OR 13823892 (print), 15731766 (electronic)
ISSNL: 1382-3892 OR 13823892
bibdate: Wed Jul 01 15:36:52 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.07.01 15:36:52 ???
URL: http://www.springerlink.com/content/j071k8608t578153/
acknowledgement: ack-nhfb
journalURL: https://link.springer.com/journal/10758
rawauthor: Shay Gueron
rawtitle: Flying in a floating (point) world
entry:
@Article{Gueron:1999:FFP,
  author =       "Shay Gueron",
  title =        "Flying in a floating (point) world",
  journal =      "International Journal of Computers for Mathematical
                 Learning",
  volume =       "4",
  number =       "2--3",
  pages =        "225--234",
  month =        may,
  year =         "1999",
  DOI =          "https://doi.org/10.1023/A:1009818429410",
  ISSN =         "1382-3892 (print), 1573-1766 (electronic)",
  ISSN-L =       "1382-3892",
  bibdate =      "Wed Jul 01 15:36:52 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/content/j071k8608t578153/",
  acknowledgement = ack-nhfb,
  journal-URL =  "https://link.springer.com/journal/10758",
}


bibtype: inproceedings
filename: fparith.bib
label: Gustavson:1999:FMA
author: Fred G. Gustavson and Jose E. Moreira and Robert F. Enenk
publisher: pub-IBM
address: pub-IBM:adr
pages: 4
year: 1999
bibdate: Fri Nov 26 15:40:34 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.26 15:40:34 ???
note: Dedicated to Cleve Moler on his 60th birthday.
acknowledgement: ack-nhfb
rawauthor: Fred G. Gustavson and Jos{\'e} E. Moreira and Robert F. Enenk
rawnote: Dedicated to Cleve Moler on his 60th birthday.
booktitle:
CASCON '99: Proceedings of the 1999 Conference of the Centre for Advanced Studies on Collaborative Research. November 8--11, 1999, Mississauga, Ontario, Canada

title:
The fused multiply-add instruction leads to algorithms for extended-precision floating point: applications to Java and high-performance computing

rawbooktitle:
{CASCON '99}: Proceedings of the 1999 Conference of the Centre for Advanced Studies on Collaborative Research. November 8--11, 1999, Mississauga, Ontario, Canada

rawtitle:
The fused multiply-add instruction leads to algorithms for extended-precision floating point: applications to {Java} and high-performance computing

entry:
@InProceedings{Gustavson:1999:FMA,
  author =       "Fred G. Gustavson and Jos{\'e} E. Moreira and Robert
                 F. Enenk",
  editor =       "????",
  booktitle =    "{CASCON '99}: Proceedings of the 1999 Conference of
                 the Centre for Advanced Studies on Collaborative
                 Research. November 8--11, 1999, Mississauga, Ontario,
                 Canada",
  title =        "The fused multiply-add instruction leads to algorithms
                 for extended-precision floating point: applications to
                 {Java} and high-performance computing",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  pages =        "4",
  year =         "1999",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Nov 26 15:40:34 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Dedicated to Cleve Moler on his 60th birthday.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Handlogten:1999:MAP
author: G. H. Handlogten
title: Method and apparatus to perform pipelined denormalization of floating-point results
pages: 4
day: 24
month: aug
monthnumber: 8
year: 1999
bibdate: Fri Nov 28 15:37:38 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 15:37:38 ???
note: U.S. Patent No. 5,943,249.
acknowledgement: ack-nhfb
rawauthor: G. H. Handlogten
rawnote: U.S. Patent No. 5,943,249.
rawtitle: Method and apparatus to perform pipelined denormalization of floating-point results
entry:
@Misc{Handlogten:1999:MAP,
  author =       "G. H. Handlogten",
  title =        "Method and apparatus to perform pipelined
                 denormalization of floating-point results",
  day =          "24",
  month =        aug,
  year =         "1999",
  bibdate =      "Fri Nov 28 15:37:38 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 5,943,249.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Harrison:1999:CTF
author: John Harrison and Ted Kubaska and Shane Story and Ping Tak Peter Tang
title: The Computation of Transcendental Functions on the IA-64 Architecture
journal: j-INTEL-TECH-J
volume: Q4
pages: 7
day: 22
month: nov
monthnumber: 11
year: 1999
bibdate: Fri Jun 01 06:02:08 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.01 06:02:08 ???
acknowledgement: ack-nhfb
rawauthor: John Harrison and Ted Kubaska and Shane Story and Ping Tak Peter Tang
rawtitle: The Computation of Transcendental Functions on the {IA-64} Architecture
URL:
http://developer.intel.com/technology/itj/q41999/articles/art_5.htm; http://developer.intel.com/technology/itj/q41999/pdf/transendental.pdf

entry:
@Article{Harrison:1999:CTF,
  author =       "John Harrison and Ted Kubaska and Shane Story and Ping
                 Tak Peter Tang",
  title =        "The Computation of Transcendental Functions on the
                 {IA-64} Architecture",
  journal =      j-INTEL-TECH-J,
  volume =       "Q4",
  pages =        "7",
  day =          "22",
  month =        nov,
  year =         "1999",
  bibdate =      "Fri Jun 01 06:02:08 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://developer.intel.com/technology/itj/q41999/articles/art_5.htm;
                 http://developer.intel.com/technology/itj/q41999/pdf/transendental.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Harrison:1999:MCT
author: John Harrison
editor: Yves Bertot and Gilles Dowek and Andre Hirschowitz and Christine Paulin and Laurent Thery
booktitle: Theorem Proving in Higher Order Logics: 12th International Conference, TPHOLs'99
title: A Machine-Checked Theory of Floating Point Arithmetic
journal: j-LECT-NOTES-COMP-SCI
volume: 1690
pages: 113--130
year: 1999
CODEN: LNCSD9
DOI: https://doi.org/10.1007/3-540-48256-3_9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Jun 5 10:53:14 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.05 10:53:14 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-jh
journalURL: http://link.springer.com/bookseries/558
rawauthor: John Harrison
rawbooktitle: Theorem Proving in Higher Order Logics: 12th International Conference, {TPHOLs'99}
raweditor: Yves Bertot and Gilles Dowek and Andr{\'e} Hirschowitz and Christine Paulin and Laurent Th{\'e}ry
rawtitle: A Machine-Checked Theory of Floating Point Arithmetic
URL:
http://www.cl.cam.ac.uk/users/jrh/papers/fparith.html; http://www.cl.cam.ac.uk/~jrh13/papers/fparith.pdf

entry:
@Article{Harrison:1999:MCT,
  author =       "John Harrison",
  editor =       "Yves Bertot and Gilles Dowek and Andr{\'e} Hirschowitz
                 and Christine Paulin and Laurent Th{\'e}ry",
  booktitle =    "Theorem Proving in Higher Order Logics: 12th
                 International Conference, {TPHOLs'99}",
  title =        "A Machine-Checked Theory of Floating Point
                 Arithmetic",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1690",
  pages =        "113--130",
  year =         "1999",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/3-540-48256-3_9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Jun 5 10:53:14 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cl.cam.ac.uk/users/jrh/papers/fparith.html;
                 http://www.cl.cam.ac.uk/~jrh13/papers/fparith.pdf",
  acknowledgement = ack-jh,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Hayashi:1999:SRR
author: Takao Hayashi
journal: j-HIST-SCI-2
volume: 9
number: 2
pages: 135--153
month: nov
monthnumber: 11
year: 1999
CODEN: HISCDU
ISSN: 0285-4821 OR 02854821
ISSNL: 0285-4821 OR 02854821
MRclass: 01A32
MRnumber: 1762168
MRreviewer: A. I. Volodarski{\u\i}
bibdate: Sat Oct 6 17:22:25 2018
bibtimestamp: 2018.10.06 17:22:25 ???
acknowledgement: ack-nhfb
journalURL: http://hssj.info/
rawauthor: Takao Hayashi
title:
A set of rules for the root-extraction prescribed by the sixteenth-century Indian mathematicians, Nilakantha Somastuvan and Sankara Variyar

bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histscijpn.bib

fjournal:
Historia Scientiarum. Second Series. International Journal of the History of Science Society of Japan

rawtitle:
A set of rules for the root-extraction prescribed by the sixteenth-century {Indian} mathematicians, {N{\=\i}laka{\d{n}}{\d{t}}ha Somastuvan} and {{\'S}a{\.n}kara V{\=a}riyar}

entry:
@Article{Hayashi:1999:SRR,
  author =       "Takao Hayashi",
  title =        "A set of rules for the root-extraction prescribed by
                 the sixteenth-century {Indian} mathematicians,
                 {N{\=\i}laka{\d{n}}{\d{t}}ha Somastuvan} and
                 {{\'S}a{\.n}kara V{\=a}riyar}",
  journal =      j-HIST-SCI-2,
  volume =       "9",
  number =       "2",
  pages =        "135--153",
  month =        nov,
  year =         "1999",
  CODEN =        "HISCDU",
  ISSN =         "0285-4821",
  ISSN-L =       "0285-4821",
  MRclass =      "01A32",
  MRnumber =     "1762168",
  MRreviewer =   "A. I. Volodarski{\u\i}",
  bibdate =      "Sat Oct 6 17:22:25 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histscijpn.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Scientiarum. Second Series. International
                 Journal of the History of Science Society of Japan",
  journal-URL =  "http://hssj.info/",
}


bibtype: article
filename: fparith.bib
label: Heindl:1999:RIH
author: G. Heindl
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 269--278
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: G. Heindl
title:
A Representation of the Interval Hull of a Tolerance Polyhedron Describing Inclusions of Function Values and Slopes

rawtitle:
A Representation of the Interval Hull of a Tolerance Polyhedron Describing Inclusions of Function Values and Slopes

entry:
@Article{Heindl:1999:RIH,
  author =       "G. Heindl",
  title =        "A Representation of the Interval Hull of a Tolerance
                 Polyhedron Describing Inclusions of Function Values and
                 Slopes",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "269--278",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: article
filename: fparith.bib
label: Hiasat:1999:SCV
author: Ahmad A. Hiasat and Hoda Abdel-Aty-Zohdy
title: Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm
journal: j-COMP-J
volume: 42
number: 3
pages: 232--240
year: 1999
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Thu Sep 2 06:09:59 MDT 1999
bibtimestamp: 1999.09.02 06:09:59 MDT
fjournal: The Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Ahmad A. Hiasat and Hoda Abdel-Aty-Zohdy
rawtitle: Semi-Custom {VLSI} Design and Implementation of a New Efficient {RNS} Division Algorithm
bibsource:
http://www3.oup.co.uk/computer_journal/hdb/Volume_42/Issue_03/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www3.oup.co.uk/computer_journal/hdb/Volume_42/Issue_03/420232.sgm.abs.html; http://www3.oup.co.uk/computer_journal/hdb/Volume_42/Issue_03/pdf/420232.pdf

entry:
@Article{Hiasat:1999:SCV,
  author =       "Ahmad A. Hiasat and Hoda Abdel-Aty-Zohdy",
  title =        "Semi-Custom {VLSI} Design and Implementation of a New
                 Efficient {RNS} Division Algorithm",
  journal =      j-COMP-J,
  volume =       "42",
  number =       "3",
  pages =        "232--240",
  month =        "????",
  year =         "1999",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Thu Sep 2 06:09:59 MDT 1999",
  bibsource =    "http://www3.oup.co.uk/computer_journal/hdb/Volume_42/Issue_03/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/hdb/Volume_42/Issue_03/420232.sgm.abs.html;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_42/Issue_03/pdf/420232.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: mastersthesis
filename: fparith.bib
label: Hirn:1999:GBI
author: Ulrich Hirn
title: Groebner bases implementation using modular and floating point arithmetic
type: Dipl.-Arb.
school: Technische Universitat Graz
address: Graz, Austria
pages: 87
year: 1999
bibdate: Thu May 09 09:37:46 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 09:37:46 ???
acknowledgement: ack-nhfb
rawauthor: Ulrich Hirn
rawtitle: {Groebner} bases implementation using modular and floating point arithmetic
entry:
@MastersThesis{Hirn:1999:GBI,
  author =       "Ulrich Hirn",
  title =        "{Groebner} bases implementation using modular and
                 floating point arithmetic",
  type =         "{Dipl.-Arb.}",
  school =       "Technische Universit{\"a}t Graz",
  address =      "Graz, Austria",
  pages =        "87",
  year =         "1999",
  bibdate =      "Thu May 09 09:37:46 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hormigo:1999:ISC
author: J. Hormigo and J. Villalba and E. L. Zapata
title: Interval Sine and Cosine Functions Computation Based on Variable Precision CORDIC Algorithm
crossref: Koren:1999:ISC
pages: 186--193
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: J. Hormigo and J. Villalba and E. L. Zapata
rawtitle: Interval Sine and Cosine Functions Computation Based on Variable Precision {CORDIC} Algorithm
URL:
http://euler.ecs.umass.edu/paper/final/paper-128.pdf; http://euler.ecs.umass.edu/paper/final/paper-128.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Hormigo.pdf

abstract:
In this paper we design a CORDIC architecture for variable-precision, and a new algorithm is proposed to perform the interval sine and cosine functions. This system allows us to specify the precision to perform the sine and cosine functions, and control the accuracy of the result, in such a way that recomputation of inaccurate results can be carried out with higher precision. An important reduction in the number of iterations is obtained by taking advantage of the differential angle, and the number of cycles per iteration is reduced by avoiding the additions of the leading all zero words. As a consequence, the computation time of the interval function evaluation obtained is close to that of a point function evaluation. The problem of the large table of angles and the scale factor compensation involved in a high precision CORDIC has been solved efficiently.

rawabstract:
In this paper we design a CORDIC architecture for variable-precision, and a new algorithm is proposed to perform the interval sine and cosine functions. This system allows us to specify the precision to perform the sine and cosine functions, and control the accuracy of the result, in such a way that recomputation of inaccurate results can be carried out with higher precision. An important reduction in the number of iterations is obtained by taking advantage of the differential angle, and the number of cycles per iteration is reduced by avoiding the additions of the leading all zero words. As a consequence, the computation time of the interval function evaluation obtained is close to that of a point function evaluation. The problem of the large table of angles and the scale factor compensation involved in a high precision CORDIC has been solved efficiently.

entry:
@InProceedings{Hormigo:1999:ISC,
  author =       "J. Hormigo and J. Villalba and E. L. Zapata",
  title =        "Interval Sine and Cosine Functions Computation Based
                 on Variable Precision {CORDIC} Algorithm",
  crossref =     "Koren:1999:ISC",
  pages =        "186--193",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-128.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-128.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Hormigo.pdf",
  abstract =     "In this paper we design a CORDIC architecture for
                 variable-precision, and a new algorithm is proposed to
                 perform the interval sine and cosine functions. This
                 system allows us to specify the precision to perform
                 the sine and cosine functions, and control the accuracy
                 of the result, in such a way that recomputation of
                 inaccurate results can be carried out with higher
                 precision. An important reduction in the number of
                 iterations is obtained by taking advantage of the
                 differential angle, and the number of cycles per
                 iteration is reduced by avoiding the additions of the
                 leading all zero words. As a consequence, the
                 computation time of the interval function evaluation
                 obtained is close to that of a point function
                 evaluation. The problem of the large table of angles
                 and the scale factor compensation involved in a high
                 precision CORDIC has been solved efficiently.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Hung:1999:FDA
author: P. Hung and H. Fahmy and O. Mencer and M. J. Flynn
title: Fast division algorithm with a small lookup table
crossref: Matthews:1999:CRT
volume: 2
pages: 1465--1468
year: 1999
DOI: https://doi.org/10.1109/ACSSC.1999.831992
bibdate: Sat Oct 9 12:45:46 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:45:46 ???
acknowledgement: ack-nhfb
rawauthor: P. Hung and H. Fahmy and O. Mencer and M. J. Flynn
rawtitle: Fast division algorithm with a small lookup table
abstract:
This paper presents a new division algorithm, which requires two multiplication operations and a single lookup in a small table. The division algorithm takes two steps. The table lookup and the first multiplication are processed concurrently in the first step, and the second multiplication is executed in the next step. This divider uses a single multiplier and a lookup table with $ 2 m (2 m + 1) $ bits to produce $2$ $m$-bit results that are guaranteed correct to one ulp. By using a multiplier and a 12.5 KB lookup table, the basic algorithm generates a 24-bit result in two cycles

rawabstract:
This paper presents a new division algorithm, which requires two multiplication operations and a single lookup in a small table. The division algorithm takes two steps. The table lookup and the first multiplication are processed concurrently in the first step, and the second multiplication is executed in the next step. This divider uses a single multiplier and a lookup table with $ 2 m (2 m + 1) $ bits to produce $2$ $m$-bit results that are guaranteed correct to one ulp. By using a multiplier and a 12.5 KB lookup table, the basic algorithm generates a 24-bit result in two cycles

entry:
@InProceedings{Hung:1999:FDA,
  author =       "P. Hung and H. Fahmy and O. Mencer and M. J. Flynn",
  title =        "Fast division algorithm with a small lookup table",
  crossref =     "Matthews:1999:CRT",
  volume =       "2",
  pages =        "1465--1468",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ACSSC.1999.831992",
  bibdate =      "Sat Oct 9 12:45:46 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a new division algorithm, which
                 requires two multiplication operations and a single
                 lookup in a small table. The division algorithm takes
                 two steps. The table lookup and the first
                 multiplication are processed concurrently in the first
                 step, and the second multiplication is executed in the
                 next step. This divider uses a single multiplier and a
                 lookup table with $ 2 m (2 m + 1) $ bits to produce $2$
                 $m$-bit results that are guaranteed correct to one ulp.
                 By using a multiplier and a 12.5 KB lookup table, the
                 basic algorithm generates a 24-bit result in two
                 cycles",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hyogo:1999:LVF
author: A. Hyogo and Y. Fukutomi and K. Sekine
title: Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 274--277
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: A. Hyogo and Y. Fukutomi and K. Sekine
rawtitle: Low voltage four-quadrant analog multiplier using square-root circuit based on {CMOS} pair
booktitle:
Proceedings of the 1999 IEEE International Symposium on Circuits and Systems: ISCAS '99, 2 June 1999

rawbooktitle:
Proceedings of the 1999 {IEEE} International Symposium on Circuits and Systems: {ISCAS '99}, 2 June 1999

entry:
@InProceedings{Hyogo:1999:LVF,
  author =       "A. Hyogo and Y. Fukutomi and K. Sekine",
  booktitle =    "Proceedings of the 1999 {IEEE} International Symposium
                 on Circuits and Systems: {ISCAS '99}, 2 June 1999",
  title =        "Low voltage four-quadrant analog multiplier using
                 square-root circuit based on {CMOS} pair",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "274--277",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "We proposed a square-root circuit based on CMOS pairs.
                 In this paper, we propose a low voltage four-quadrant
                 analog multiplier using the square-root circuit. Also
                 we confirmed this operation by PSpice \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ide:1999:GFP
crossref: Hosticka:1999:EPE
pages: 106--109
year: 1999
bibdate: Sat Jun 02 08:23:03 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 08:23:03 ???
acknowledgement: ack-nhfb
author:
N. Ide and M. Hirano and Y. Endo and S. Yoshioka and H. Murakami and A. Kunimatsu and T. Sato and T. Kamei and T. Okada and M. Suzuoki

title:
2.44 GFLOPS 300MHz floating-point vector processing unit for high performance $3$D graphics computing

rawauthor:
N. Ide and M. Hirano and Y. Endo and S. Yoshioka and H. Murakami and A. Kunimatsu and T. Sato and T. Kamei and T. Okada and M. Suzuoki

rawtitle:
{2.44 GFLOPS 300MHz} floating-point vector processing unit for high performance {$3$D} graphics computing

entry:
@InProceedings{Ide:1999:GFP,
  author =       "N. Ide and M. Hirano and Y. Endo and S. Yoshioka and
                 H. Murakami and A. Kunimatsu and T. Sato and T. Kamei
                 and T. Okada and M. Suzuoki",
  title =        "{2.44 GFLOPS 300MHz} floating-point vector processing
                 unit for high performance {$3$D} graphics computing",
  crossref =     "Hosticka:1999:EPE",
  pages =        "106--109",
  year =         "1999",
  bibdate =      "Sat Jun 02 08:23:03 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Iordache:1999:ARS
author: Cristina Iordache and David W. Matula
journal: j-ELECT-NOTES-THEOR-COMP-SCI
volume: 24
pages: 34--62
month: apr
monthnumber: 4
year: 1999
DOI: https://doi.org/10.1016/S1571-0661(05)80621-8
ISSN: 1571-0661 OR 15710661
ISSNL: 1571-0661 OR 15710661
bibdate: Fri Jun 24 20:23:13 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 20:23:13 ???
fjournal: Electronic Notes in Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15710661
rawauthor: Cristina Iordache and David W. Matula
title:
Analysis of Reciprocal and Square Root Reciprocal Instructions in the AMD K6-2 Implementation of 3DNow!

abstract:
Reciprocal and root reciprocal functions at ``half'' and IEEE single precision formats are specified in the AMD 3DNow! instruction set. Implementations in the recently released AMD K6-2 microprocessor are analyzed herein by exhaustive computation and timing loops to ascertain the accuracy and monotonicity properties of the output and throughput / latency cycle counts. Periodicities in stepwise function output were observed and employed to construct an underlying bipartite table that can serve as the core of the respective reciprocal function outputs. The recommended RISC instruction macros generated single precision reciprocals and root reciprocals accurate to a unit in the last place. However, the root reciprocal functions failed to satisfy the desirable monotonicity property typically implemented as an industry standard for elementary functions on x86 floating point units. Reasons for the failure are provided and an adjusted table is shown to satisfy the monotonicity standard. Results are summarized in Table 1 and described in the body of this report.

rawabstract:
Reciprocal and root reciprocal functions at ``half'' and IEEE single precision formats are specified in the AMD 3DNow! instruction set. Implementations in the recently released AMD K6-2 microprocessor are analyzed herein by exhaustive computation and timing loops to ascertain the accuracy and monotonicity properties of the output and throughput\slash latency cycle counts. Periodicities in stepwise function output were observed and employed to construct an underlying bipartite table that can serve as the core of the respective reciprocal function outputs. The recommended RISC instruction macros generated single precision reciprocals and root reciprocals accurate to a unit in the last place. However, the root reciprocal functions failed to satisfy the desirable monotonicity property typically implemented as an industry standard for elementary functions on x86 floating point units. Reasons for the failure are provided and an adjusted table is shown to satisfy the monotonicity standard. Results are summarized in Table 1 and described in the body of this report.

rawtitle:
Analysis of Reciprocal and Square Root Reciprocal Instructions in the {AMD K6-2} Implementation of {3DNow!}

entry:
@Article{Iordache:1999:ARS,
  author =       "Cristina Iordache and David W. Matula",
  title =        "Analysis of Reciprocal and Square Root Reciprocal
                 Instructions in the {AMD K6-2} Implementation of
                 {3DNow!}",
  journal =      j-ELECT-NOTES-THEOR-COMP-SCI,
  volume =       "24",
  pages =        "34--62",
  month =        apr,
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/S1571-0661(05)80621-8",
  ISSN =         "1571-0661",
  ISSN-L =       "1571-0661",
  bibdate =      "Fri Jun 24 20:23:13 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Reciprocal and root reciprocal functions at ``half''
                 and IEEE single precision formats are specified in the
                 AMD 3DNow! instruction set. Implementations in the
                 recently released AMD K6-2 microprocessor are analyzed
                 herein by exhaustive computation and timing loops to
                 ascertain the accuracy and monotonicity properties of
                 the output and throughput\slash latency cycle counts.
                 Periodicities in stepwise function output were observed
                 and employed to construct an underlying bipartite table
                 that can serve as the core of the respective reciprocal
                 function outputs. The recommended RISC instruction
                 macros generated single precision reciprocals and root
                 reciprocals accurate to a unit in the last place.
                 However, the root reciprocal functions failed to
                 satisfy the desirable monotonicity property typically
                 implemented as an industry standard for elementary
                 functions on x86 floating point units. Reasons for the
                 failure are provided and an adjusted table is shown to
                 satisfy the monotonicity standard. Results are
                 summarized in Table 1 and described in the body of this
                 report.",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronic Notes in Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15710661",
}


bibtype: inproceedings
filename: fparith.bib
label: Iordache:1999:IPR
author: Cristina Iordache and David W. Matula
title: On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal
crossref: Koren:1999:ISC
pages: 233--240
year: 1999
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
keywords: ARITH-14; computer arithmetic; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Cristina Iordache and David W. Matula
rawtitle: On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal
URL:
http://euler.ecs.umass.edu/paper/final/paper-164.pdf; http://euler.ecs.umass.edu/paper/final/paper-164.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Iordache.pdf

abstract:
Quotients, reciprocals, square roots and square root reciprocals all have the property that infinitely precise p-bit rounded results for p-bit input operands can be obtained from approximate results of bounded accuracy. We investigate lower bounds on the number of bits of an approximation accurate to a unit in the last place sufficient to guarantee that correct round and sticky bits can be determined. Known lower bounds for quotients and square roots are given and/or sharpened, and a new lower bound for root reciprocals is proved. Specifically for reciprocals, quotients and square roots, tight bounds of order $ 2 p + O(1) $ are presented. For infinitely precise rounding of the root reciprocal a lower bound can be found at $ 3 p + O(1) $, but exhaustive testing for small sizes of the operand suggests that in practice $ (2 + epsilon )p $ for small $ epsilon $ is usually sufficient. Algorithms can be designed for obtaining the round and sticky bits based on the bit pattern of an approximation computed to the required accuracy. We show that some improvement of the known lower bound for reciprocals and division is achievable at the cost of somewhat more complex hardware for rounding. Tests for the exactness of the quotient and square root are also provided.

rawabstract:
Quotients, reciprocals, square roots and square root reciprocals all have the property that infinitely precise p-bit rounded results for p-bit input operands can be obtained from approximate results of bounded accuracy. We investigate lower bounds on the number of bits of an approximation accurate to a unit in the last place sufficient to guarantee that correct round and sticky bits can be determined. Known lower bounds for quotients and square roots are given and/or sharpened, and a new lower bound for root reciprocals is proved. Specifically for reciprocals, quotients and square roots, tight bounds of order $ 2 p + O(1) $ are presented. For infinitely precise rounding of the root reciprocal a lower bound can be found at $ 3 p + O(1) $, but exhaustive testing for small sizes of the operand suggests that in practice $ (2 + \epsilon)p $ for small $ \epsilon $ is usually sufficient. Algorithms can be designed for obtaining the round and sticky bits based on the bit pattern of an approximation computed to the required accuracy. We show that some improvement of the known lower bound for reciprocals and division is achievable at the cost of somewhat more complex hardware for rounding. Tests for the exactness of the quotient and square root are also provided.

entry:
@InProceedings{Iordache:1999:IPR,
  author =       "Cristina Iordache and David W. Matula",
  title =        "On Infinitely Precise Rounding for Division, Square
                 Root, Reciprocal and Square Root Reciprocal",
  crossref =     "Koren:1999:ISC",
  pages =        "233--240",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-164.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-164.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Iordache.pdf",
  abstract =     "Quotients, reciprocals, square roots and square root
                 reciprocals all have the property that infinitely
                 precise p-bit rounded results for p-bit input operands
                 can be obtained from approximate results of bounded
                 accuracy. We investigate lower bounds on the number of
                 bits of an approximation accurate to a unit in the last
                 place sufficient to guarantee that correct round and
                 sticky bits can be determined. Known lower bounds for
                 quotients and square roots are given and/or sharpened,
                 and a new lower bound for root reciprocals is proved.
                 Specifically for reciprocals, quotients and square
                 roots, tight bounds of order $ 2 p + O(1) $ are
                 presented. For infinitely precise rounding of the root
                 reciprocal a lower bound can be found at $ 3 p + O(1)
                 $, but exhaustive testing for small sizes of the
                 operand suggests that in practice $ (2 + \epsilon)p $
                 for small $ \epsilon $ is usually sufficient.
                 Algorithms can be designed for obtaining the round and
                 sticky bits based on the bit pattern of an
                 approximation computed to the required accuracy. We
                 show that some improvement of the known lower bound for
                 reciprocals and division is achievable at the cost of
                 somewhat more complex hardware for rounding. Tests for
                 the exactness of the quotient and square root are also
                 provided.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic; correct rounding;
                 floating-point arithmetic",
  summary =      "Quotients, reciprocals, square roots and square root
                 reciprocals all have the property that infinitely
                 precise p-bit rounded results for p-bit input operands
                 can be obtained from approximate results of bounded
                 accuracy. We investigate lower bounds \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Jamieson:1999:NRF
author: M. J. Jamieson
title: Notes: On rational function approximations to square roots
journal: j-AMER-MATH-MONTHLY
volume: 106
number: 1
pages: 50--52
month: jan
monthnumber: 1
year: 1999
CODEN: AMMYAE
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
MRclass: 11Yxx
MRnumber: 1 674 202
bibdate: Tue Jun 22 10:29:34 MDT 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.06.22 10:29:34 MDT
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: https://www.jstor.org/journals/00029890.htm
rawauthor: M. J. Jamieson
rawtitle: Notes: On rational function approximations to square roots
entry:
@Article{Jamieson:1999:NRF,
  author =       "M. J. Jamieson",
  title =        "Notes: On rational function approximations to square
                 roots",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "106",
  number =       "1",
  pages =        "50--52",
  month =        jan,
  year =         "1999",
  CODEN =        "AMMYAE",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  MRclass =      "11Yxx",
  MRnumber =     "1 674 202",
  bibdate =      "Tue Jun 22 10:29:34 MDT 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "https://www.jstor.org/journals/00029890.htm",
}


bibtype: article
filename: fparith.bib
label: Jamieson:1999:RFA
author: M. J. Jamieson
title: On rational function approximations to square roots
journal: j-AMER-MATH-MONTHLY
volume: 106
number: 1
pages: 50--52
year: 1999
CODEN: AMMYAE
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
MRclass: 11Yxx
MRnumber: 1 674 202
bibdate: Tue Jun 22 10:29:34 MDT 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.06.22 10:29:34 MDT
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: https://www.jstor.org/journals/00029890.htm
rawauthor: M. J. Jamieson
rawtitle: On rational function approximations to square roots
entry:
@Article{Jamieson:1999:RFA,
  author =       "M. J. Jamieson",
  title =        "On rational function approximations to square roots",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "106",
  number =       "1",
  pages =        "50--52",
  year =         "1999",
  CODEN =        "AMMYAE",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  MRclass =      "11Yxx",
  MRnumber =     "1 674 202",
  bibdate =      "Tue Jun 22 10:29:34 MDT 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "https://www.jstor.org/journals/00029890.htm",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeong:1999:CPT
author: Cheol-Ho Jeong and Woo-Chan Park and Tack-Don Dan and Shin-Dug Kim
title: Cost / performance Trade-off in Floating-point Unit Design for $3$D Geometry Processor
crossref: IEEE:1999:AAF
pages: 104--107
year: 1999
DOI: https://doi.org/10.1109/APASIC.1999.824039
bibdate: Fri Jun 24 12:18:17 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 12:18:17 ???
acknowledgement: ack-nhfb
rawauthor: Cheol-Ho Jeong and Woo-Chan Park and Tack-Don Dan and Shin-Dug Kim
rawtitle: Cost\slash performance Trade-off in Floating-point Unit Design for {$3$D} Geometry Processor
entry:
@InProceedings{Jeong:1999:CPT,
  author =       "Cheol-Ho Jeong and Woo-Chan Park and Tack-Don Dan and
                 Shin-Dug Kim",
  title =        "Cost\slash performance Trade-off in Floating-point
                 Unit Design for {$3$D} Geometry Processor",
  crossref =     "IEEE:1999:AAF",
  pages =        "104--107",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/APASIC.1999.824039",
  bibdate =      "Fri Jun 24 12:18:17 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Jones:1999:BAT
author: Douglas W. Jones
title: BCD Arithmetic, a tutorial
pages: 104--107
year: 1999
bibdate: Tue Jan 22 07:13:24 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2013.01.22 07:13:24 ???
URL: http://homepage.cs.uiowa.edu/~jones/bcd/bcd.html
acknowledgement: ack-nhfb
howpublished: Web tutorial.
rawauthor: Douglas W. Jones
rawtitle: {BCD} Arithmetic, a tutorial
entry:
@Misc{Jones:1999:BAT,
  author =       "Douglas W. Jones",
  title =        "{BCD} Arithmetic, a tutorial",
  howpublished = "Web tutorial.",
  year =         "1999",
  bibdate =      "Tue Jan 22 07:13:24 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://homepage.cs.uiowa.edu/~jones/bcd/bcd.html",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Jones:1999:BDC
author: Douglas W. Jones
title: Binary to Decimal Conversion in Limited Precision
pages: 104--107
year: 1999
bibdate: Tue Jan 22 07:13:24 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2013.01.22 07:13:24 ???
URL: http://homepage.cs.uiowa.edu/~jones/bcd/decimal.html
acknowledgement: ack-nhfb
howpublished: Web tutorial.
rawauthor: Douglas W. Jones
rawtitle: Binary to Decimal Conversion in Limited Precision
entry:
@Misc{Jones:1999:BDC,
  author =       "Douglas W. Jones",
  title =        "Binary to Decimal Conversion in Limited Precision",
  howpublished = "Web tutorial.",
  year =         "1999",
  bibdate =      "Tue Jan 22 07:13:24 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://homepage.cs.uiowa.edu/~jones/bcd/decimal.html",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Jones:1999:MDT
author: Douglas W. Jones
title: Modulus without Division, a tutorial
pages: 104--107
year: 1999
bibdate: Tue Jan 22 07:13:24 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2013.01.22 07:13:24 ???
URL: http://homepage.cs.uiowa.edu/~jones/bcd/mod.shtml
acknowledgement: ack-nhfb
howpublished: Web tutorial.
rawauthor: Douglas W. Jones
rawtitle: Modulus without Division, a tutorial
entry:
@Misc{Jones:1999:MDT,
  author =       "Douglas W. Jones",
  title =        "Modulus without Division, a tutorial",
  howpublished = "Web tutorial.",
  year =         "1999",
  bibdate =      "Tue Jan 22 07:13:24 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://homepage.cs.uiowa.edu/~jones/bcd/mod.shtml",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Jones:1999:RMT
author: Douglas W. Jones
title: Reciprocal Multiplication, a tutorial
pages: 104--107
year: 1999
bibdate: Tue Jan 22 07:13:24 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2013.01.22 07:13:24 ???
URL: http://homepage.cs.uiowa.edu/~jones/bcd/divide.html
acknowledgement: ack-nhfb
howpublished: Web tutorial.
rawauthor: Douglas W. Jones
rawtitle: Reciprocal Multiplication, a tutorial
entry:
@Misc{Jones:1999:RMT,
  author =       "Douglas W. Jones",
  title =        "Reciprocal Multiplication, a tutorial",
  howpublished = "Web tutorial.",
  year =         "1999",
  bibdate =      "Tue Jan 22 07:13:24 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://homepage.cs.uiowa.edu/~jones/bcd/divide.html",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jullien:1999:HDP
author: G. A. Jullien and V. S. Dimitrov and B. Li and W. C. Miller and A. Lee and M. Ahmadi
editor: IEEE
title: A Hybrid DBNS Processor for DSP Computation
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 5--8
year: 1999
DOI: https://doi.org/10.1109/ISCAS.1999.777792
LCCN: TK7801 .I22 1999
bibdate: Sat May 14 17:21:37 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.05.14 17:21:37 ???
note: IEEE catalog number 99CH36349.
keywords: Double-Based Number System (DBNS)
acknowledgement: ack-nhfb
bookpages: liv + 565
rawauthor: G. A. Jullien and V. S. Dimitrov and B. Li and W. C. Miller and A. Lee and M. Ahmadi
raweditor: {IEEE}
rawnote: IEEE catalog number 99CH36349.
rawtitle: A Hybrid {DBNS} Processor for {DSP} Computation
booktitle:
Proceedings of the 1999 IEEE International Symposium on Circuits and Systems: ISCAS '99, May 30--June 2 1999, Orlando, Florida

ISBN:
0-7803-5471-0 (softbound), 0-7803-5472-9 (casebound), 0-7803-5473-7 (microfiche) OR 0780354710 (softbound), 0780354729 (casebound), 0780354737 (microfiche)

ISBN13:
978-0-7803-5471-5 (softbound), 978-0-7803-5472-2 (casebound), 978-0-7803-5473-9 (microfiche) OR 9780780354715 (softbound), 9780780354722 (casebound), 9780780354739 (microfiche)

rawbooktitle:
{Proceedings of the 1999 IEEE International Symposium on Circuits and Systems: ISCAS '99, May 30--June 2 1999, Orlando, Florida}

entry:
@InProceedings{Jullien:1999:HDP,
  author =       "G. A. Jullien and V. S. Dimitrov and B. Li and W. C.
                 Miller and A. Lee and M. Ahmadi",
  editor =       "{IEEE}",
  booktitle =    "{Proceedings of the 1999 IEEE International Symposium
                 on Circuits and Systems: ISCAS '99, May 30--June 2
                 1999, Orlando, Florida}",
  title =        "A Hybrid {DBNS} Processor for {DSP} Computation",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "liv + 565",
  pages =        "5--8",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ISCAS.1999.777792",
  ISBN =         "0-7803-5471-0 (softbound), 0-7803-5472-9 (casebound),
                 0-7803-5473-7 (microfiche)",
  ISBN-13 =      "978-0-7803-5471-5 (softbound), 978-0-7803-5472-2
                 (casebound), 978-0-7803-5473-9 (microfiche)",
  LCCN =         "TK7801 .I22 1999",
  bibdate =      "Sat May 14 17:21:37 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IEEE catalog number 99CH36349.",
  acknowledgement = ack-nhfb,
  keywords =     "Double-Based Number System (DBNS)",
}


bibtype: misc
filename: fparith.bib
label: Kahan:1999:SRD
author: W. Kahan
title: Square Root Without Division
pages: 3
day: 23
month: feb
monthnumber: 2
year: 1999
bibdate: Mon Apr 25 18:01:49 2005
bibtimestamp: 2005.04.25 18:01:49 ???
URL: http://www.cs.berkeley.edu/~wkahan/ieee754status/reciprt.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: W. Kahan
rawtitle: Square Root Without Division
entry:
@Misc{Kahan:1999:SRD,
  author =       "W. Kahan",
  title =        "Square Root Without Division",
  howpublished = "World-Wide Web document",
  pages =        "3",
  day =          "23",
  month =        feb,
  year =         "1999",
  bibdate =      "Mon Apr 25 18:01:49 2005",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~wkahan/ieee754status/reciprt.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kaplan:1999:JVA
author: Bonnie Kaplan
title: John V. Atanasoff (1903--1995) interview: August 10, 1972
journal: Computer Oral History Collection, Smithsonian Institution Press
pages: 3
year: 1999
bibdate: Fri Aug 08 08:33:46 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.08 08:33:46 ???
note: Article No. 17.
acknowledgement: ack-nhfb
rawauthor: Bonnie Kaplan
rawnote: Article No. 17.
rawtitle: {John V. Atanasoff} (1903--1995) interview: {August 10, 1972}
abstract:
The conversation begins with Atanasoff's method of adding and counting---an idea he conceived of while in a honky-tonk bar in Illinois in 1937. This concept of addition was to be performed by logic and not by successive inching of a dial. Atanasoff further remarks that his interest in electronic computation began by thinking along the Eccles-Jordan lines. The Eccles-Jordan circuit was used for part of the operation and intended to do successive impulses. Further comments about the Eccles-Jordan circuitry are made. The use of vacuum tubes in Atanasoff's machine was prompted be economy. Vacuum tube circuits were fast enough to solve the sums of all digits and thus economize on time and material. The use of base two for arithmetic was employed because it was simpler. The use of dual triodes (6F8G and then ultimately the 6C8G) in the circuitry was also based on economy--original cost and space. The difference between these two tubes is discussed. Comments on the machines ability to do subtraction using [Comptu's?] complements. Atanasoff decided to use the complements in the memory in order to subtract. This use of complements was not original to Atanasoff. Atanasoff explains his use of lower base numbers opposed to larger. The simplest way of storing numbers up to 25 is by coding them into numbers probably with a base of two. Numbers associated with the base of two were associated with a simpler logical system. While Atanasoff experimented with larger base numbers, he found them to unsatisfactory. Atanasoff discussed his decision to use base two with George Gross and William Mercer who did the calculations which were needed for the base ten- base two conversion table. While doing the conversions on the machine, the addition was automatically carried out in the computing machine. Atanasoff explains the concept of a floating grid. This type of grid implied that it did not have a bias resistor to the ground, it was not connected. Normal grids in vacuum tubes are connected to the ground. Another of Atanasoff's addition to the machine was the use of a dielectric sheet to record the base two numbers. The dielectric had difficulty working since Atanasoff could never find a satisfactory paper on which to record the readings. Atanasoff discusses his desire to have worked for IBM despite the rebuffs he had received over the years. He notes that he wanted to be more in the mainstream of the development of computers with funding, and the possibilities of research. IBM seemed to provide the best possible future for computing. This transcript concludes with several miscellaneous questions based on the court transcripts from the litigation Honeywell vs. Sperry-Rand. Individuals mentioned include: Ernest Anderson, Clifford Berry, George Gross, James Elder, Norman Fulmer, and Hazeltine.

rawabstract:
The conversation begins with Atanasoff's method of adding and counting---an idea he conceived of while in a honky-tonk bar in Illinois in 1937. This concept of addition was to be performed by logic and not by successive inching of a dial. Atanasoff further remarks that his interest in electronic computation began by thinking along the Eccles-Jordan lines. The Eccles-Jordan circuit was used for part of the operation and intended to do successive impulses. Further comments about the Eccles-Jordan circuitry are made. The use of vacuum tubes in Atanasoff's machine was prompted be economy. Vacuum tube circuits were fast enough to solve the sums of all digits and thus economize on time and material. The use of base two for arithmetic was employed because it was simpler. The use of dual triodes (6F8G and then ultimately the 6C8G) in the circuitry was also based on economy--original cost and space. The difference between these two tubes is discussed. Comments on the machines ability to do subtraction using [Comptu's?] complements. Atanasoff decided to use the complements in the memory in order to subtract. This use of complements was not original to Atanasoff. Atanasoff explains his use of lower base numbers opposed to larger. The simplest way of storing numbers up to 25 is by coding them into numbers probably with a base of two. Numbers associated with the base of two were associated with a simpler logical system. While Atanasoff experimented with larger base numbers, he found them to unsatisfactory. Atanasoff discussed his decision to use base two with George Gross and William Mercer who did the calculations which were needed for the base ten- base two conversion table. While doing the conversions on the machine, the addition was automatically carried out in the computing machine. Atanasoff explains the concept of a floating grid. This type of grid implied that it did not have a bias resistor to the ground, it was not connected. Normal grids in vacuum tubes are connected to the ground. Another of Atanasoff's addition to the machine was the use of a dielectric sheet to record the base two numbers. The dielectric had difficulty working since Atanasoff could never find a satisfactory paper on which to record the readings. Atanasoff discusses his desire to have worked for IBM despite the rebuffs he had received over the years. He notes that he wanted to be more in the mainstream of the development of computers with funding, and the possibilities of research. IBM seemed to provide the best possible future for computing. This transcript concludes with several miscellaneous questions based on the court transcripts from the litigation Honeywell vs. Sperry-Rand. Individuals mentioned include: Ernest Anderson, Clifford Berry, George Gross, James Elder, Norman Fulmer, and Hazeltine.

entry:
@Article{Kaplan:1999:JVA,
  author =       "Bonnie Kaplan",
  title =        "{John V. Atanasoff} (1903--1995) interview: {August
                 10, 1972}",
  journal =      "Computer Oral History Collection, Smithsonian
                 Institution Press",
  year =         "1999",
  bibdate =      "Fri Aug 08 08:33:46 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Article No. 17.",
  abstract =     "The conversation begins with Atanasoff's method of
                 adding and counting---an idea he conceived of while in
                 a honky-tonk bar in Illinois in 1937. This concept of
                 addition was to be performed by logic and not by
                 successive inching of a dial. Atanasoff further remarks
                 that his interest in electronic computation began by
                 thinking along the Eccles-Jordan lines. The
                 Eccles-Jordan circuit was used for part of the
                 operation and intended to do successive impulses.
                 Further comments about the Eccles-Jordan circuitry are
                 made. The use of vacuum tubes in Atanasoff's machine
                 was prompted be economy. Vacuum tube circuits were fast
                 enough to solve the sums of all digits and thus
                 economize on time and material. The use of base two for
                 arithmetic was employed because it was simpler. The use
                 of dual triodes (6F8G and then ultimately the 6C8G) in
                 the circuitry was also based on economy--original cost
                 and space. The difference between these two tubes is
                 discussed. Comments on the machines ability to do
                 subtraction using [Comptu's?] complements. Atanasoff
                 decided to use the complements in the memory in order
                 to subtract. This use of complements was not original
                 to Atanasoff. Atanasoff explains his use of lower base
                 numbers opposed to larger. The simplest way of storing
                 numbers up to 25 is by coding them into numbers
                 probably with a base of two. Numbers associated with
                 the base of two were associated with a simpler logical
                 system. While Atanasoff experimented with larger base
                 numbers, he found them to unsatisfactory. Atanasoff
                 discussed his decision to use base two with George
                 Gross and William Mercer who did the calculations which
                 were needed for the base ten- base two conversion
                 table. While doing the conversions on the machine, the
                 addition was automatically carried out in the computing
                 machine. Atanasoff explains the concept of a floating
                 grid. This type of grid implied that it did not have a
                 bias resistor to the ground, it was not connected.
                 Normal grids in vacuum tubes are connected to the
                 ground. Another of Atanasoff's addition to the machine
                 was the use of a dielectric sheet to record the base
                 two numbers. The dielectric had difficulty working
                 since Atanasoff could never find a satisfactory paper
                 on which to record the readings. Atanasoff discusses
                 his desire to have worked for IBM despite the rebuffs
                 he had received over the years. He notes that he wanted
                 to be more in the mainstream of the development of
                 computers with funding, and the possibilities of
                 research. IBM seemed to provide the best possible
                 future for computing. This transcript concludes with
                 several miscellaneous questions based on the court
                 transcripts from the litigation Honeywell vs.
                 Sperry-Rand. Individuals mentioned include: Ernest
                 Anderson, Clifford Berry, George Gross, James Elder,
                 Norman Fulmer, and Hazeltine.",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Kaplan:1999:NNH
author: Robert Kaplan
title: The Nothing That Is: a Natural History of Zero
publisher: pub-OXFORD
address: pub-OXFORD:adr
pages: xii + 225
year: 1999
ISBN: 0-19-512842-7 OR 0195128427
ISBN13: 978-0-19-512842-0 OR 9780195128420
LCCN: QA141 .K36 1999
bibdate: Mon Dec 06 16:15:22 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.12.06 16:15:22 ???
acknowledgement: ack-nhfb
rawauthor: Robert Kaplan
rawtitle: The Nothing That Is: a Natural History of Zero
entry:
@Book{Kaplan:1999:NNH,
  author =       "Robert Kaplan",
  title =        "The Nothing That Is: a Natural History of Zero",
  publisher =    pub-OXFORD,
  address =      pub-OXFORD:adr,
  pages =        "xii + 225",
  year =         "1999",
  ISBN =         "0-19-512842-7",
  ISBN-13 =      "978-0-19-512842-0",
  LCCN =         "QA141 .K36 1999",
  bibdate =      "Mon Dec 06 16:15:22 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$22.00",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Karamcheti:1999:CLR
author: V. Karamcheti and C. Li and I. Pechtchanski and C. Yap
title: A core library for robust numerical and geometric libraries
crossref: ACM:1999:PFA
pages: 351--359
year: 1999
bibdate: Sat Apr 28 18:58:05 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.04.28 18:58:05 ???
URL: http://www.cs.nyu.edu/exact
acknowledgement: ack-nhfb
rawauthor: V. Karamcheti and C. Li and I. Pechtchanski and C. Yap
rawtitle: A core library for robust numerical and geometric libraries
entry:
@InProceedings{Karamcheti:1999:CLR,
  author =       "V. Karamcheti and C. Li and I. Pechtchanski and C.
                 Yap",
  title =        "A core library for robust numerical and geometric
                 libraries",
  crossref =     "ACM:1999:PFA",
  pages =        "351--359",
  year =         "1999",
  bibdate =      "Sat Apr 28 18:58:05 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.nyu.edu/exact",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kern:1999:FVH
author: Christoph Kern and Mark R. Greenstreet
title: Formal verification in hardware design: a survey
journal: j-TODAES
volume: 4
number: 2
pages: 123--193
month: apr
monthnumber: 4
year: 1999
CODEN: ATASFO
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Fri Jul 27 10:05:33 MDT 2001
bibsource: http://www.acm.org/pubs/toc/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.07.27 10:05:33 MDT
fjournal: ACM Transactions on Design Automation of Electronic Systems (TODAES)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J776
rawauthor: Christoph Kern and Mark R. Greenstreet
rawtitle: Formal verification in hardware design: a survey
URL:
http://www.acm.org/pubs/articles/journals/todaes/1999-4-2/p123-kern/p123-kern.pdf; http://www.acm.org/pubs/citations/journals/todaes/1999-4-2/p123-kern/

abstract:
In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.par There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between -regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.par In order to provide insight into the scope and limitations of currently available techniques, we present a selection of case studies where formal methods were applied to industrial-scale designs, such as microprocessors, floating-point hardware, protocols, memory subsystems, and communications hardware.

keywords:
case studies; formal methods; formal verification; hardware verification; language containment; model checking; survey; theorem proving

subject:
General Literature --- Introductory and Survey (A.1); Hardware --- Integrated Circuits --- Design Aids (B.7.2): bf Verification

rawabstract:
In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.\par There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between -regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.\par In order to provide insight into the scope and limitations of currently available techniques, we present a selection of case studies where formal methods were applied to industrial-scale designs, such as microprocessors, floating-point hardware, protocols, memory subsystems, and communications hardware.

entry:
@Article{Kern:1999:FVH,
  author =       "Christoph Kern and Mark R. Greenstreet",
  title =        "Formal verification in hardware design: a survey",
  journal =      j-TODAES,
  volume =       "4",
  number =       "2",
  pages =        "123--193",
  month =        apr,
  year =         "1999",
  CODEN =        "ATASFO",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Fri Jul 27 10:05:33 MDT 2001",
  bibsource =    "http://www.acm.org/pubs/toc/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/articles/journals/todaes/1999-4-2/p123-kern/p123-kern.pdf;
                 http://www.acm.org/pubs/citations/journals/todaes/1999-4-2/p123-kern/",
  abstract =     "In recent years, formal methods have emerged as an
                 alternative approach to ensuring the quality and
                 correctness of hardware designs, overcoming some of the
                 limitations of traditional validation techniques such
                 as simulation and testing.\par

                 There are two main aspects to the application of formal
                 methods in a design process: the formal framework used
                 to specify desired properties of a design and the
                 verification techniques and tools used to reason about
                 the relationship between a specification and a
                 corresponding implementation. We survey a variety of
                 frameworks and techniques proposed in the literature
                 and applied to actual designs. The specification
                 frameworks we describe include temporal logics,
                 predicate logic, abstraction and refinement, as well as
                 containment between -regular languages. The
                 verification techniques presented include model
                 checking, automata-theoretic techniques, automated
                 theorem proving, and approaches that integrate the
                 above methods.\par

                 In order to provide insight into the scope and
                 limitations of currently available techniques, we
                 present a selection of case studies where formal
                 methods were applied to industrial-scale designs, such
                 as microprocessors, floating-point hardware, protocols,
                 memory subsystems, and communications hardware.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems (TODAES)",
  generalterms = "Design; Verification",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J776",
  keywords =     "case studies; formal methods; formal verification;
                 hardware verification; language containment; model
                 checking; survey; theorem proving",
  subject =      "General Literature --- Introductory and Survey (A.1);
                 Hardware --- Integrated Circuits --- Design Aids
                 (B.7.2): {\bf Verification}",
}


bibtype: inproceedings
filename: fparith.bib
label: Knowles:1999:FA
author: Simon Knowles
title: A Family of Adders
crossref: Koren:1999:ISC
pages: 30--34
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Simon Knowles
rawtitle: A Family of Adders
URL:
http://euler.ecs.umass.edu/paper/final/paper-168.pdf; http://euler.ecs.umass.edu/paper/final/paper-168.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Knowles.pdf

abstract:
Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several examples of adders based on such a formulation have been published, and efficient implementations are numerous. Chief among the known constructions are those of Kogge & Stone and Ladner & Fischer. In this work we show that these are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth. The intermediate structures allow trade-offs between the amount of internal wiring and the fanout of intermediate nodes, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases. Rules for the construction of such adders are given, as are examples of realistic 32b designs implemented in an industrial 0u25 CMOS process.

rawabstract:
Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several examples of adders based on such a formulation have been published, and efficient implementations are numerous. Chief among the known constructions are those of Kogge \& Stone and Ladner \& Fischer. In this work we show that these are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth. The intermediate structures allow trade-offs between the amount of internal wiring and the fanout of intermediate nodes, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases. Rules for the construction of such adders are given, as are examples of realistic 32b designs implemented in an industrial 0u25 CMOS process.

entry:
@InProceedings{Knowles:1999:FA,
  author =       "Simon Knowles",
  title =        "A Family of Adders",
  crossref =     "Koren:1999:ISC",
  pages =        "30--34",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-168.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-168.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Knowles.pdf",
  abstract =     "Binary carry-propagating addition can be efficiently
                 expressed as a prefix computation. Several examples of
                 adders based on such a formulation have been published,
                 and efficient implementations are numerous. Chief among
                 the known constructions are those of Kogge \& Stone and
                 Ladner \& Fischer. In this work we show that these are
                 end cases of a large family of addition structures, all
                 of which share the attractive property of minimum
                 logical depth. The intermediate structures allow
                 trade-offs between the amount of internal wiring and
                 the fanout of intermediate nodes, and can thus usually
                 achieve a more attractive combination of speed and
                 area/power cost than either of the known end-cases.
                 Rules for the construction of such adders are given, as
                 are examples of realistic 32b designs implemented in an
                 industrial 0u25 CMOS process.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Koren:1999:FIS
author: Israel Koren and Peter Kornerup
title: Fourteenth IEEE Symposium on Computer Arithmetic: Foreword
crossref: Koren:1999:ISC
pages: viii--viii
year: 1999
bibdate: Sat Nov 17 21:53:37 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 21:53:37 ???
keywords: ARITH-14
acknowledgement: ack-nhfb
rawauthor: Israel Koren and Peter Kornerup
rawtitle: {Fourteenth IEEE Symposium on Computer Arithmetic}: Foreword
URL:
http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_contents.pdf; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_foreword.pdf; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_preface.pdf

entry:
@InProceedings{Koren:1999:FIS,
  author =       "Israel Koren and Peter Kornerup",
  title =        "{Fourteenth IEEE Symposium on Computer Arithmetic}:
                 Foreword",
  crossref =     "Koren:1999:ISC",
  pages =        "viii--viii",
  year =         "1999",
  bibdate =      "Sat Nov 17 21:53:37 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_contents.pdf;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_foreword.pdf;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_preface.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14",
}


bibtype: misc
filename: fparith.bib
label: Koren:1999:ITS
author: Israel Koren and Peter Kornerup
title: IEEE TC Special Issue on Computer Arithmetic --- May 2000
pages: viii--viii
year: 1999
bibdate: Wed Jan 20 10:00:59 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.01.20 10:00:59 ???
URL: http://www.ecs.umass.edu/ece/koren/sp-issue/
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: Israel Koren and Peter Kornerup
rawtitle: {IEEE TC} Special Issue on Computer Arithmetic --- {May} 2000
entry:
@Misc{Koren:1999:ITS,
  author =       "Israel Koren and Peter Kornerup",
  title =        "{IEEE TC} Special Issue on Computer Arithmetic ---
                 {May} 2000",
  howpublished = "World-Wide Web document.",
  year =         "1999",
  bibdate =      "Wed Jan 20 10:00:59 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ecs.umass.edu/ece/koren/sp-issue/",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:1999:NSC
author: Peter Kornerup
title: Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition
crossref: Koren:1999:ISC
pages: 152--157
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup
rawtitle: Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition
URL:
http://euler.ecs.umass.edu/paper/final/paper-103.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Kornerup.pdf

abstract:
This note presents necessary and sufficient conditions for parallel and constant time conversions from one digit-set into another, and thus also for constant time addition. In the integer domain it is generally believed that such conversion and addition is possible if the target digit-set is redundant and complete. This is also the case when the digit-set is a contiguous set of integers. However, when this is not the case then such conversion and addition in the integer domain is not possible in general, and when more general rings are considered, the same problem may be present.

rawabstract:
This note presents necessary and sufficient conditions for parallel and constant time conversions from one digit-set into another, and thus also for constant time addition. In the integer domain it is generally believed that such conversion and addition is possible if the target digit-set is redundant and complete. This is also the case when the digit-set is a contiguous set of integers. However, when this is not the case then such conversion and addition in the integer domain is not possible in general, and when more general rings are considered, the same problem may be present.

entry:
@InProceedings{Kornerup:1999:NSC,
  author =       "Peter Kornerup",
  title =        "Necessary and Sufficient Conditions for Parallel,
                 Constant Time Conversion and Addition",
  crossref =     "Koren:1999:ISC",
  pages =        "152--157",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-103.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Kornerup.pdf",
  abstract =     "This note presents necessary and sufficient conditions
                 for parallel and constant time conversions from one
                 digit-set into another, and thus also for constant time
                 addition. In the integer domain it is generally
                 believed that such conversion and addition is possible
                 if the target digit-set is redundant and complete. This
                 is also the case when the digit-set is a contiguous set
                 of integers. However, when this is not the case then
                 such conversion and addition in the integer domain is
                 not possible in general, and when more general rings
                 are considered, the same problem may be present.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Krick:1999:AN
author: T. Krick and L. M. Pardo and M. Sombra
title: Arithmetic Nullstellensatze
journal: j-SIGSAM
volume: 33
number: 3
pages: 17--17
month: sep
monthnumber: 9
year: 1999
CODEN: SIGSBZ
ISSN: 0163-5824 (print), 1557-9492 (electronic) OR 01635824 (print), 15579492 (electronic)
ISSNL: 0163-5824 OR 01635824
bibdate: Fri Feb 8 18:27:06 MST 2002
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.08 18:27:06 MST
fjournal: SIGSAM Bulletin
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: T. Krick and L. M. Pardo and M. Sombra
rawtitle: Arithmetic {Nullstellens{\"a}tze}
entry:
@Article{Krick:1999:AN,
  author =       "T. Krick and L. M. Pardo and M. Sombra",
  title =        "Arithmetic {Nullstellens{\"a}tze}",
  journal =      j-SIGSAM,
  volume =       "33",
  number =       "3",
  pages =        "17--17",
  month =        sep,
  year =         "1999",
  CODEN =        "SIGSBZ",
  ISSN =         "0163-5824 (print), 1557-9492 (electronic)",
  ISSN-L =       "0163-5824",
  bibdate =      "Fri Feb 8 18:27:06 MST 2002",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGSAM Bulletin",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Lang:1999:VHR
author: T. Lang and P. Montuschi
title: Very high radix square root with prescaling and rounding and a combined division / square root unit
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 8
pages: 827--841
month: aug
monthnumber: 8
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.795124
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:58 MDT 2011
bibtimestamp: 2011.07.06 08:46:58 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=795124
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. Lang and P. Montuschi
abstract:
An algorithm for square root with prescaling and selection by rounding is developed and combined with a similar scheme for division. Since division is usually more frequent than square root, the main concern of the combined implementation is to maintain the low execution time of division, while accepting a somewhat larger execution time for square root. The algorithm is presented in detail, including the mathematical development of bounds for the first square-root digit and for the scaling factor. The proposed implementation is described, evaluated and compared with other combined div/sqrt units. The comparisons show that the proposed scheme potentially produces a significant speed-up for division, whereas, for square root, the speed-up is small

rawabstract:
An algorithm for square root with prescaling and selection by rounding is developed and combined with a similar scheme for division. Since division is usually more frequent than square root, the main concern of the combined implementation is to maintain the low execution time of division, while accepting a somewhat larger execution time for square root. The algorithm is presented in detail, including the mathematical development of bounds for the first square-root digit and for the scaling factor. The proposed implementation is described, evaluated and compared with other combined div/sqrt units. The comparisons show that the proposed scheme potentially produces a significant speed-up for division, whereas, for square root, the speed-up is small

rawtitle:
Very high radix square root with prescaling and rounding and a combined division\slash square root unit

entry:
@Article{Lang:1999:VHR,
  author =       "T. Lang and P. Montuschi",
  title =        "Very high radix square root with prescaling and
                 rounding and a combined division\slash square root
                 unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "8",
  pages =        "827--841",
  month =        aug,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.795124",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:58 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=795124",
  abstract =     "An algorithm for square root with prescaling and
                 selection by rounding is developed and combined with a
                 similar scheme for division. Since division is usually
                 more frequent than square root, the main concern of the
                 combined implementation is to maintain the low
                 execution time of division, while accepting a somewhat
                 larger execution time for square root. The algorithm is
                 presented in detail, including the mathematical
                 development of bounds for the first square-root digit
                 and for the scaling factor. The proposed implementation
                 is described, evaluated and compared with other
                 combined div/sqrt units. The comparisons show that the
                 proposed scheme potentially produces a significant
                 speed-up for division, whereas, for square root, the
                 speed-up is small",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "An algorithm for square root with prescaling and
                 selection by rounding is developed and combined with a
                 similar scheme for division. Since division is usually
                 more frequent than square root, the main concern of the
                 combined implementation is to \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Langlois:1999:WAL
author: Ph. Langlois and F. Nativel
title: When automatic linear correction of rounding errors is exact
journal: j-C-R-ACAD-SCI-PARIS-SER-I-MATH
volume: 328
pages: 543--548
year: 1999
CODEN: CASMEI
ISSN: 0249-6291 OR 02496291
bibdate: Thu May 27 07:37:54 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.27 07:37:54 ???
note: See erratum, p. 829, in same volume.
fjournal: Comptes Rendus des Seances de l'Academie des Sciences. Serie I. Mathematique
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/1631073X
rawauthor: Ph. Langlois and F. Nativel
rawnote: See erratum, p. 829, in same volume.
rawtitle: When automatic linear correction of rounding errors is exact
entry:
@Article{Langlois:1999:WAL,
  author =       "Ph. Langlois and F. Nativel",
  title =        "When automatic linear correction of rounding errors is
                 exact",
  journal =      j-C-R-ACAD-SCI-PARIS-SER-I-MATH,
  volume =       "328",
  number =       "??",
  pages =        "543--548",
  year =         "1999",
  CODEN =        "CASMEI",
  ISSN =         "0249-6291",
  bibdate =      "Thu May 27 07:37:54 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See erratum, p. 829, in same volume.",
  acknowledgement = ack-nhfb,
  fjournal =     "Comptes Rendus des S{\'e}ances de l'Acad{\'e}mie des
                 Sciences. S{\'e}rie I. Math{\'e}matique",
  journal-URL =  "http://www.sciencedirect.com/science/journal/1631073X",
}


bibtype: article
filename: fparith.bib
label: Lee:1999:EFS
author: Sung-Woo Lee and Hyun-Sung Kim and Jung-Joon Kim and Tae-Geun Kim and Kee-Young Yoo
title: Efficient Fixed-Size Systolic Arrays for the Modular Multiplication
journal: j-LECT-NOTES-COMP-SCI
volume: 1627
pages: 442--??
year: 1999
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Feb 5 11:54:14 MST 2002
bibtimestamp: 2002.02.05 11:54:14 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sung-Woo Lee and Hyun-Sung Kim and Jung-Joon Kim and Tae-Geun Kim and Kee-Young Yoo
rawtitle: Efficient Fixed-Size Systolic Arrays for the Modular Multiplication
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t1627.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/1627/16270442.htm; http://link.springer-ny.com/link/service/series/0558/papers/1627/16270442.pdf

entry:
@Article{Lee:1999:EFS,
  author =       "Sung-Woo Lee and Hyun-Sung Kim and Jung-Joon Kim and
                 Tae-Geun Kim and Kee-Young Yoo",
  title =        "Efficient Fixed-Size Systolic Arrays for the Modular
                 Multiplication",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1627",
  pages =        "442--??",
  year =         "1999",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Feb 5 11:54:14 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t1627.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/1627/16270442.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/1627/16270442.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Lee:1999:NAD
author: Chang-Hyi Lee and Jong-In Lim
title: A New Aspect of Dual Basis for Efficient Field Arithmetic
journal: j-LECT-NOTES-COMP-SCI
volume: 1560
pages: 12--28
year: 1999
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Feb 5 11:53:42 MST 2002
bibtimestamp: 2002.02.05 11:53:42 MST
fjournal: Lecture Notes in Computer Science
keywords: PKC; public key cryptography
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Chang-Hyi Lee and Jong-In Lim
rawtitle: A New Aspect of Dual Basis for Efficient Field Arithmetic
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t1560.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/1560/15600012.htm; http://link.springer-ny.com/link/service/series/0558/papers/1560/15600012.pdf

entry:
@Article{Lee:1999:NAD,
  author =       "Chang-Hyi Lee and Jong-In Lim",
  title =        "A New Aspect of Dual Basis for Efficient Field
                 Arithmetic",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "1560",
  pages =        "12--28",
  year =         "1999",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Feb 5 11:53:42 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t1560.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/1560/15600012.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/1560/15600012.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "PKC; public key cryptography",
}


bibtype: inproceedings
filename: fparith.bib
label: Lee:1999:STS
author: Young-Sang Lee and Jun-Woo Kang and Lee-Sup Kim and Seung-Ho Hwang
booktitle: 6th International Conference on VLSI and CAD: ICVC '99
title: Self-timed shared division and square-root implementation using full redundant signed digit numbers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 541--544
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: Young-Sang Lee and Jun-Woo Kang and Lee-Sup Kim and Seung-Ho Hwang
rawbooktitle: 6th International Conference on {VLSI} and {CAD}: {ICVC '99}
rawtitle: Self-timed shared division and square-root implementation using full redundant signed digit numbers
entry:
@InProceedings{Lee:1999:STS,
  author =       "Young-Sang Lee and Jun-Woo Kang and Lee-Sup Kim and
                 Seung-Ho Hwang",
  booktitle =    "6th International Conference on {VLSI} and {CAD}:
                 {ICVC '99}",
  title =        "Self-timed shared division and square-root
                 implementation using full redundant signed digit
                 numbers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "541--544",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "A radix-$2$ square root implementation for self-timed
                 dividers using redundant signed-digit (RSD) adders is
                 presented. In this method, two self-timed RSD adder
                 stages are used for each result bit selection. A very
                 efficient and simple result bit \ldots{}",
}


bibtype: incollection
filename: fparith.bib
label: Lefevre:1999:ACL
author: V. Lefevre
title: An Algorithm That Computes a Lower Bound on the Distance Between a Segment and $ mathbb Z^2 $
crossref: Csendes:1999:DRC
pages: 203--212
year: 1999
bibdate: Fri Jun 24 12:41:23 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 12:41:23 ???
acknowledgement: ack-nhfb
rawauthor: V. Lef{\`e}vre
rawtitle: An Algorithm That Computes a Lower Bound on the Distance Between a Segment and {$ \mathbb {Z}^2 $}
entry:
@InCollection{Lefevre:1999:ACL,
  author =       "V. Lef{\`e}vre",
  title =        "An Algorithm That Computes a Lower Bound on the
                 Distance Between a Segment and {$ \mathbb {Z}^2 $}",
  crossref =     "Csendes:1999:DRC",
  pages =        "203--212",
  year =         "1999",
  bibdate =      "Fri Jun 24 12:41:23 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lewis:1999:CLN
author: David Lewis
title: Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms
crossref: Koren:1999:ISC
pages: 194--203
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: David Lewis
rawtitle: Complex Logarithmic Number System Arithmetic Using High-Radix Redundant {CORDIC} Algorithms
URL:
http://euler.ecs.umass.edu/paper/final/paper-135.pdf; http://euler.ecs.umass.edu/paper/final/paper-135.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Lewis.pdf

abstract:
This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with approximately the same hardware as a high-radix CORDIC operation. A design example comparable to single precision floating point has been designed and simulated.

rawabstract:
This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with approximately the same hardware as a high-radix CORDIC operation. A design example comparable to single precision floating point has been designed and simulated.

entry:
@InProceedings{Lewis:1999:CLN,
  author =       "David Lewis",
  title =        "Complex Logarithmic Number System Arithmetic Using
                 High-Radix Redundant {CORDIC} Algorithms",
  crossref =     "Koren:1999:ISC",
  pages =        "194--203",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-135.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-135.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Lewis.pdf",
  abstract =     "This paper describes the application of high radix
                 redundant CORDIC algorithms to complex logarithmic
                 number system arithmetic. It shows that a CLNS addition
                 can be performed with approximately the same hardware
                 as a high-radix CORDIC operation. A design example
                 comparable to single precision floating point has been
                 designed and simulated.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Liao:1999:SDR
author: Yuyun Liao and Tom M. Hameenanttila and David B. Roberts
pages: 194--203
day: 23
month: dec
monthnumber: 12
year: 1999
bibdate: Thu Oct 17 12:11:10 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 12:11:10 ???
URL: https://patents.google.com/patent/US6611856B1
acknowledgement: ack-nhfb
howpublished: US Patent 6,611,856B1
rawauthor: Yuyun Liao and Tom M. Hameenanttila and David B. Roberts
abstract:
A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry look-ahead adder functions simultaneously for different operations.

remark:
Patent filed 23 December 1999, priority claimed from British patent GB0407413A of 4 December 2000, granted 26 August 2003 to Intel Corporation, expected expiration 23 December 2019.

rawabstract:
A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry look-ahead adder functions simultaneously for different operations.

entry:
@Misc{Liao:1999:SDR,
  author =       "Yuyun Liao and Tom M. Hameenanttila and David B.
                 Roberts",
  howpublished = "US Patent 6,611,856B1",
  day =          "23",
  month =        dec,
  year =         "1999",
  bibdate =      "Thu Oct 17 12:11:10 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US6611856B1",
  abstract =     "A multiply-accumulate unit, or MAC, may achieve high
                 throughput. The MAC need not use redundant hardware,
                 such as multiple Wallace trees, or pipelining logic,
                 yet may perform Wallace tree and carry look-ahead adder
                 functions simultaneously for different operations.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 23 December 1999, priority claimed from
                 British patent GB0407413A of 4 December 2000, granted
                 26 August 2003 to Intel Corporation, expected
                 expiration 23 December 2019.",
}


bibtype: inproceedings
filename: fparith.bib
label: Liew:1999:SDR
author: T. H. Liew and L.-L. Yang and L. Hanzo
booktitle: VTC 1999 --- Fall. IEEE VTS 50th Vehicular Technology Conference
title: Soft-decision redundant residue number system based error correction coding
volume: 5
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2546--2550
year: 1999
DOI: https://doi.org/10.1109/VETECF.1999.800245
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: T. H. Liew and L.-L. Yang and L. Hanzo
rawbooktitle: {VTC 1999} --- Fall. {IEEE} {VTS 50th} Vehicular Technology Conference
rawtitle: Soft-decision redundant residue number system based error correction coding
entry:
@InProceedings{Liew:1999:SDR,
  author =       "T. H. Liew and L.-L. Yang and L. Hanzo",
  booktitle =    "{VTC 1999} --- Fall. {IEEE} {VTS 50th} Vehicular
                 Technology Conference",
  title =        "Soft-decision redundant residue number system based
                 error correction coding",
  volume =       "5",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2546--2550",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VETECF.1999.800245",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Soft-decision-based redundant residue number system
                 (RRNS)-assisted error control coding is proposed and
                 its performance is evaluated. An RRNS(n,k) code is a
                 maximum-minimum distance block code, exhibiting
                 identical distance properties to Reed- \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Lopez:1999:IPF
author: D. Lopez and J. Llosa and E. Ayguade and M. Valero
title: Impact on performance of fused multiply-add units in aggressive VLIW architectures
crossref: Shiratori:1999:PIC
pages: 22--29
year: 1999
DOI: https://doi.org/10.1109/ICPP.1999.797384
bibdate: Sun Feb 20 09:51:00 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 09:51:00 ???
acknowledgement: ack-nhfb
rawauthor: D. Lopez and J. Llosa and E. Ayguade and M. Valero
rawtitle: Impact on performance of fused multiply-add units in aggressive {VLIW} architectures
abstract:
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the resources offered by the architecture. Several general-purpose superscalar microprocessors have been implemented with multiply-add fused floating-point units, that reduces the latency of the combined operation and the number of resources used. This paper analyses the influence of these two factors in the instruction-level parallelism exploitable from loops executed on a broad set of future aggressive processor configurations. The estimation of implementation costs (area and cycle time) enables a fair comparison of these configurations in terms of final performance and implementation feasibility. The paper performs technological projection for the next years in order to foresee the possible implementable alternatives. From this study we conclude that multiply-add fused units may have a deep impact in raising the performance of future processor architectures with a reasonable increase in cost.

rawabstract:
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the resources offered by the architecture. Several general-purpose superscalar microprocessors have been implemented with multiply-add fused floating-point units, that reduces the latency of the combined operation and the number of resources used. This paper analyses the influence of these two factors in the instruction-level parallelism exploitable from loops executed on a broad set of future aggressive processor configurations. The estimation of implementation costs (area and cycle time) enables a fair comparison of these configurations in terms of final performance and implementation feasibility. The paper performs technological projection for the next years in order to foresee the possible implementable alternatives. From this study we conclude that multiply-add fused units may have a deep impact in raising the performance of future processor architectures with a reasonable increase in cost.

entry:
@InProceedings{Lopez:1999:IPF,
  author =       "D. Lopez and J. Llosa and E. Ayguade and M. Valero",
  title =        "Impact on performance of fused multiply-add units in
                 aggressive {VLIW} architectures",
  crossref =     "Shiratori:1999:PIC",
  pages =        "22--29",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ICPP.1999.797384",
  bibdate =      "Sun Feb 20 09:51:00 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Loops are the main time consuming part of programs
                 based on floating point computations. The performance
                 of the loops is limited either by recurrences in the
                 computation or by the resources offered by the
                 architecture. Several general-purpose superscalar
                 microprocessors have been implemented with multiply-add
                 fused floating-point units, that reduces the latency of
                 the combined operation and the number of resources
                 used. This paper analyses the influence of these two
                 factors in the instruction-level parallelism
                 exploitable from loops executed on a broad set of
                 future aggressive processor configurations. The
                 estimation of implementation costs (area and cycle
                 time) enables a fair comparison of these configurations
                 in terms of final performance and implementation
                 feasibility. The paper performs technological
                 projection for the next years in order to foresee the
                 possible implementable alternatives. From this study we
                 conclude that multiply-add fused units may have a deep
                 impact in raising the performance of future processor
                 architectures with a reasonable increase in cost.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lue:1999:ADE
author: Jeng-Jong J. Lue and Dhananjay S. Phatak
crossref: Koren:1999:ISC
pages: 216--224
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Jeng-Jong J. Lue and Dhananjay S. Phatak
title:
Area $ times $ Delay ($ A cdot T $) Efficient Multipliers Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation

URL:
http://euler.ecs.umass.edu/paper/final/paper-159.pdf; http://euler.ecs.umass.edu/paper/final/paper-159.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Lue.pdf

abstract:
Intermediate Signed Digit (SD) representation can facilitate fast and compact VLSI implementations of partial product accumulation trees. It achieves a reduction ratio of 2:1 at every level and also leads to more regular layouts. Its disadvantage is that the number of bit lines that need to routed can be high. This can lead to a significant area overhead especially at smaller feature sizes where the wire/interconnect area and delay can be dominant.par A Hybrid Signed Digit (HSD) representation lets some of the digits be unsigned bits, thereby reducing the number of bit lines. By arbitrarily varying the positions of and distances between consecutive signed digits, this representation can trade off latency for area and offers a continuum of choices between the two's complement representation on the one hand and fully Signed Digit (FSD or simply SD) representation on the other.par In this paper, we illustrate an $ A cdot T $ (area $ times $ delay) efficient multiplier based on the HSD?1 representation which is one of the many possible HSD formats, wherein every alternate digit is signed and the rest are unsigned (ordinary) bits. It is seen that multipliers based on HSD?1 format require more transistors than those based on FSD format. However, they require fewer bit lines to be routed, which substantially reduces the interconnect area; thereby leading to a reduction in the total VLSI area and a lower $ A cdot T $ product. The design reaffirms that the interconnect area can be significant especially at small feature sizes.

rawabstract:
Intermediate Signed Digit (SD) representation can facilitate fast and compact VLSI implementations of partial product accumulation trees. It achieves a reduction ratio of 2:1 at every level and also leads to more regular layouts. Its disadvantage is that the number of bit lines that need to routed can be high. This can lead to a significant area overhead especially at smaller feature sizes where the wire/interconnect area and delay can be dominant.\par A Hybrid Signed Digit (HSD) representation lets some of the digits be unsigned bits, thereby reducing the number of bit lines. By arbitrarily varying the positions of and distances between consecutive signed digits, this representation can trade off latency for area and offers a continuum of choices between the two's complement representation on the one hand and fully Signed Digit (FSD or simply SD) representation on the other.\par In this paper, we illustrate an $ A \cdot T $ (area $ \times $ delay) efficient multiplier based on the HSD?1 representation which is one of the many possible HSD formats, wherein every alternate digit is signed and the rest are unsigned (ordinary) bits. It is seen that multipliers based on HSD?1 format require more transistors than those based on FSD format. However, they require fewer bit lines to be routed, which substantially reduces the interconnect area; thereby leading to a reduction in the total VLSI area and a lower $ A \cdot T $ product. The design reaffirms that the interconnect area can be significant especially at small feature sizes.

rawtitle:
Area $ \times $ Delay ({$ A \cdot T $}) Efficient Multipliers Based on an Intermediate Hybrid Signed-Digit ({HSD-1}) Representation

entry:
@InProceedings{Lue:1999:ADE,
  author =       "Jeng-Jong J. Lue and Dhananjay S. Phatak",
  title =        "Area $ \times $ Delay ({$ A \cdot T $}) Efficient
                 Multipliers Based on an Intermediate Hybrid
                 Signed-Digit ({HSD-1}) Representation",
  crossref =     "Koren:1999:ISC",
  pages =        "216--224",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-159.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-159.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Lue.pdf",
  abstract =     "Intermediate Signed Digit (SD) representation can
                 facilitate fast and compact VLSI implementations of
                 partial product accumulation trees. It achieves a
                 reduction ratio of 2:1 at every level and also leads to
                 more regular layouts. Its disadvantage is that the
                 number of bit lines that need to routed can be high.
                 This can lead to a significant area overhead especially
                 at smaller feature sizes where the wire/interconnect
                 area and delay can be dominant.\par

                 A Hybrid Signed Digit (HSD) representation lets some of
                 the digits be unsigned bits, thereby reducing the
                 number of bit lines. By arbitrarily varying the
                 positions of and distances between consecutive signed
                 digits, this representation can trade off latency for
                 area and offers a continuum of choices between the
                 two's complement representation on the one hand and
                 fully Signed Digit (FSD or simply SD) representation on
                 the other.\par

                 In this paper, we illustrate an $ A \cdot T $ (area $
                 \times $ delay) efficient multiplier based on the HSD?1
                 representation which is one of the many possible HSD
                 formats, wherein every alternate digit is signed and
                 the rest are unsigned (ordinary) bits. It is seen that
                 multipliers based on HSD?1 format require more
                 transistors than those based on FSD format. However,
                 they require fewer bit lines to be routed, which
                 substantially reduces the interconnect area; thereby
                 leading to a reduction in the total VLSI area and a
                 lower $ A \cdot T $ product. The design reaffirms that
                 the interconnect area can be significant especially at
                 small feature sizes.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Mahesh:1999:IAE
author: M. N. Mahesh and S. Gupta and M. Mehendale
booktitle: Twelfth International Conference on VLSI Design, 1999. Proceedings
title: Improving area efficiency of residue number system based implementation of DSP algorithms
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 340--345
year: 1999
DOI: https://doi.org/10.1109/ICVD.1999.745179
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. N. Mahesh and S. Gupta and M. Mehendale
rawbooktitle: Twelfth International Conference on {VLSI} Design, 1999. Proceedings
rawtitle: Improving area efficiency of residue number system based implementation of {DSP} algorithms
entry:
@InProceedings{Mahesh:1999:IAE,
  author =       "M. N. Mahesh and S. Gupta and M. Mehendale",
  booktitle =    "Twelfth International Conference on {VLSI} Design,
                 1999. Proceedings",
  title =        "Improving area efficiency of residue number system
                 based implementation of {DSP} algorithms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "340--345",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICVD.1999.745179",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue Number System based applications involve
                 modulo-arithmetic which is typically implemented using
                 look-up-tables (LUTs) for a small value of modulus. In
                 this paper we present a data coding technique to
                 minimize the area of these LUTs when \ldots{}",
}


bibtype: article
filename: fparith.bib
label: McCullough:1999:ARS
author: B. D. McCullough
title: Assessing the Reliability of Statistical Software: Part II
journal: j-AMER-STAT
volume: 53
number: 2
pages: 149--159
month: may
monthnumber: 5
year: 1999
CODEN: ASTAAJ
ISSN: 0003-1305 (print), 1537-2731 (electronic) OR 00031305 (print), 15372731 (electronic)
ISSNL: 0003-1305 OR 00031305
bibdate: Fri Jan 27 14:51:25 MST 2012
bibtimestamp: 2012.01.27 14:51:25 MST
URL: http://www.amstat.org/publications/tas/mccull.pdf; http://www.jstor.org/stable/2685736
fjournal: The American Statistician
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/utas20
rawauthor: B. D. McCullough
rawtitle: Assessing the Reliability of Statistical Software: {Part II}
bibsource:
http://www.amstat.org/publications/tas/toc_99.html; http://www.jstor.org/journals/00031305.html; http://www.jstor.org/stable/i326504; https://www.math.utah.edu/pub/tex/bib/amstat1990.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{McCullough:1999:ARS,
  author =       "B. D. McCullough",
  title =        "Assessing the Reliability of Statistical Software:
                 {Part II}",
  journal =      j-AMER-STAT,
  volume =       "53",
  number =       "2",
  pages =        "149--159",
  month =        may,
  year =         "1999",
  CODEN =        "ASTAAJ",
  ISSN =         "0003-1305 (print), 1537-2731 (electronic)",
  ISSN-L =       "0003-1305",
  bibdate =      "Fri Jan 27 14:51:25 MST 2012",
  bibsource =    "http://www.amstat.org/publications/tas/toc_99.html;
                 http://www.jstor.org/journals/00031305.html;
                 http://www.jstor.org/stable/i326504;
                 https://www.math.utah.edu/pub/tex/bib/amstat1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.amstat.org/publications/tas/mccull.pdf;
                 http://www.jstor.org/stable/2685736",
  acknowledgement = ack-nhfb,
  fjournal =     "The American Statistician",
  journal-URL =  "http://www.tandfonline.com/loi/utas20",
}


bibtype: article
filename: fparith.bib
label: McCullough:1999:NRE
author: B. D. McCullough and H. D. Vinod
title: The Numerical Reliability of Econometric Software
journal: j-J-ECON-LIT
volume: 37
number: 2
pages: 633--665
month: jun
monthnumber: 6
year: 1999
CODEN: JECLB3
DOI: https://doi.org/10.1257/jel.37.2.633
ISSN: 0022-0515 (print), 1547-1101 (electronic) OR 00220515 (print), 15471101 (electronic)
ISSNL: 0022-0515 OR 00220515
bibdate: Thu Oct 17 05:56:48 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib
bibtimestamp: 2019.10.17 05:56:48 ???
URL: http://www.jstor.org/stable/2565215; https://www.aeaweb.org/articles?id=10.1257/jel.37.2.633
fjournal: Journal of Economic Literature
acknowledgement: ack-nhfb
journalURL: https://www.aeaweb.org/journals/jel/issues
rawauthor: B. D. McCullough and H. D. Vinod
rawtitle: The Numerical Reliability of Econometric Software
abstract:
Numerous examples show that some econometric software packages contain serious flaws, and that users cannot safely assume that their software is accurate. A brief survey of the fundamentals of computer arithmetic discusses the sources of numerical error and emphasizes that computer arithmetic is not at all like pencil-and-paper arithmetic. Both users and developers of econometrics software should first pay attention to accuracy, and only later consider user-friendliness. Details are provided for assessing the accuracy of basic estimation routines, statistical distributions, and random number generators. More accuracy benchmarks are needed, especially for specialized econometric procedures.

remark:
This paper discusses the effect of both floating-point arithmetic and random-number generators on econometric computations.

rawabstract:
Numerous examples show that some econometric software packages contain serious flaws, and that users cannot safely assume that their software is accurate. A brief survey of the fundamentals of computer arithmetic discusses the sources of numerical error and emphasizes that computer arithmetic is not at all like pencil-and-paper arithmetic. Both users and developers of econometrics software should first pay attention to accuracy, and only later consider user-friendliness. Details are provided for assessing the accuracy of basic estimation routines, statistical distributions, and random number generators. More accuracy benchmarks are needed, especially for specialized econometric procedures.

entry:
@Article{McCullough:1999:NRE,
  author =       "B. D. McCullough and H. D. Vinod",
  title =        "The Numerical Reliability of Econometric Software",
  journal =      j-J-ECON-LIT,
  volume =       "37",
  number =       "2",
  pages =        "633--665",
  month =        jun,
  year =         "1999",
  CODEN =        "JECLB3",
  DOI =          "https://doi.org/10.1257/jel.37.2.633",
  ISSN =         "0022-0515 (print), 1547-1101 (electronic)",
  ISSN-L =       "0022-0515",
  bibdate =      "Thu Oct 17 05:56:48 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  URL =          "http://www.jstor.org/stable/2565215;
                 https://www.aeaweb.org/articles?id=10.1257/jel.37.2.633",
  abstract =     "Numerous examples show that some econometric software
                 packages contain serious flaws, and that users cannot
                 safely assume that their software is accurate. A brief
                 survey of the fundamentals of computer arithmetic
                 discusses the sources of numerical error and emphasizes
                 that computer arithmetic is not at all like
                 pencil-and-paper arithmetic. Both users and developers
                 of econometrics software should first pay attention to
                 accuracy, and only later consider user-friendliness.
                 Details are provided for assessing the accuracy of
                 basic estimation routines, statistical distributions,
                 and random number generators. More accuracy benchmarks
                 are needed, especially for specialized econometric
                 procedures.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Economic Literature",
  journal-URL =  "https://www.aeaweb.org/journals/jel/issues",
  remark =       "This paper discusses the effect of both floating-point
                 arithmetic and random-number generators on econometric
                 computations.",
}


bibtype: inproceedings
filename: fparith.bib
label: McInerney:1999:HMC
author: S. McInerney and R. B. Reilly
title: Hybrid multiplier / CORDIC unit for online handwriting recognition
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1909--1912 (vol. 4)
year: 1999
DOI: https://doi.org/10.1109/ICASSP.1999.758297
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: S. McInerney and R. B. Reilly
rawtitle: Hybrid multiplier\slash {CORDIC} unit for online handwriting recognition
booktitle:
1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No. 99CH36258)

keywords:
Acceleration; Arithmetic; Character recognition; Digital signal processing; Euclidean distance; Feature extraction; Handwriting recognition; Hardware; Iterative algorithms; Personal digital assistants

rawbooktitle:
{1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No. 99CH36258)}

entry:
@InProceedings{McInerney:1999:HMC,
  author =       "S. McInerney and R. B. Reilly",
  booktitle =    "{1999 IEEE International Conference on Acoustics,
                 Speech, and Signal Processing. Proceedings. ICASSP99
                 (Cat. No. 99CH36258)}",
  title =        "Hybrid multiplier\slash {CORDIC} unit for online
                 handwriting recognition",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1909--1912 (vol. 4)",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/ICASSP.1999.758297",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; Arithmetic; Character recognition;
                 Digital signal processing; Euclidean distance; Feature
                 extraction; Handwriting recognition; Hardware;
                 Iterative algorithms; Personal digital assistants",
}


bibtype: inproceedings
filename: fparith.bib
label: Montuschi:1999:BVH
author: Paolo Montuschi and Tomas Lang
title: Boosting Very High Radix Division with Prescaling and Selection by Rounding
crossref: Koren:1999:ISC
pages: 52--59
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Paolo Montuschi and Tom{\'a}s Lang
rawtitle: Boosting Very High Radix Division with Prescaling and Selection by Rounding
URL:
http://euler.ecs.umass.edu/paper/final/paper-150.pdf; http://euler.ecs.umass.edu/paper/final/paper-150.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Montuschi.pdf

abstract:
An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists in increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor nor the delay of an iteration. As a consequence, for some values of the effective radix, it permits an implementation with a smaller area and the same execution time than the original scheme. Estimations are given for 54-bit and 114-bit quotients.

rawabstract:
An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists in increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor nor the delay of an iteration. As a consequence, for some values of the effective radix, it permits an implementation with a smaller area and the same execution time than the original scheme. Estimations are given for 54-bit and 114-bit quotients.

entry:
@InProceedings{Montuschi:1999:BVH,
  author =       "Paolo Montuschi and Tom{\'a}s Lang",
  title =        "Boosting Very High Radix Division with Prescaling and
                 Selection by Rounding",
  crossref =     "Koren:1999:ISC",
  pages =        "52--59",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-150.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-150.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Montuschi.pdf",
  abstract =     "An extension of the very-high radix division with
                 prescaling and selection by rounding is presented. This
                 extension consists in increasing the effective radix of
                 the implementation by obtaining a few additional bits
                 of the quotient per iteration, without increasing the
                 complexity of the unit to obtain the prescaling factor
                 nor the delay of an iteration. As a consequence, for
                 some values of the effective radix, it permits an
                 implementation with a smaller area and the same
                 execution time than the original scheme. Estimations
                 are given for 54-bit and 114-bit quotients.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Muller:1999:FRT
author: Jean-Michel Muller
title: A Few Results on Table-Based Methods
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 279--288
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: Jean-Michel Muller
rawtitle: A Few Results on Table-Based Methods
entry:
@Article{Muller:1999:FRT,
  author =       "Jean-Michel Muller",
  title =        "A Few Results on Table-Based Methods",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "279--288",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: article
filename: fparith.bib
label: Muroi:1999:ESR
author: Kazuo Muroi
title: Extraction of square roots in Babylonian mathematics
journal: j-HIST-SCI-2
volume: 9
number: 2
pages: 127--133
month: nov
monthnumber: 11
year: 1999
CODEN: HISCDU
ISSN: 0285-4821 OR 02854821
ISSNL: 0285-4821 OR 02854821
MRclass: 01A17
MRnumber: 1762167
MRreviewer: Bruno Poizat
bibdate: Sat Oct 6 17:22:25 2018
bibtimestamp: 2018.10.06 17:22:25 ???
acknowledgement: ack-nhfb
journalURL: http://hssj.info/
rawauthor: Kazuo Muroi
rawtitle: Extraction of square roots in {Babylonian} mathematics
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histscijpn.bib

fjournal:
Historia Scientiarum. Second Series. International Journal of the History of Science Society of Japan

entry:
@Article{Muroi:1999:ESR,
  author =       "Kazuo Muroi",
  title =        "Extraction of square roots in {Babylonian}
                 mathematics",
  journal =      j-HIST-SCI-2,
  volume =       "9",
  number =       "2",
  pages =        "127--133",
  month =        nov,
  year =         "1999",
  CODEN =        "HISCDU",
  ISSN =         "0285-4821",
  ISSN-L =       "0285-4821",
  MRclass =      "01A17",
  MRnumber =     "1762167",
  MRreviewer =   "Bruno Poizat",
  bibdate =      "Sat Oct 6 17:22:25 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histscijpn.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Scientiarum. Second Series. International
                 Journal of the History of Science Society of Japan",
  journal-URL =  "http://hssj.info/",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:1999:LPDa
author: Alberto Nannarelli and Tomas Lang
title: Low-Power Division: Comparison among Implementations of Radix $4$, $8$ and $ 16 $
crossref: Koren:1999:ISC
pages: 60--69
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli and Tomas Lang
rawtitle: Low-Power Division: Comparison among Implementations of Radix $4$, $8$ and $ 16 $
URL:
http://euler.ecs.umass.edu/paper/final/paper-158.pdf; http://euler.ecs.umass.edu/paper/final/paper-158.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Nannarelli.pdf

abstract:
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this paper we explore the relation between the radix and the energy dissipated. Previous work has been done on radix-4 and radix-8 division. Here we extend this study to a radix-16 scheme with two overlapped radix-4 stages and compare the latency, area, and energy of the three implementations.par Results show that by applying the low-power techniques the energy dissipation is reduced from 30% to 40%, with respect to the standard implementation. An additional 20% reduction can be obtained using a dual voltage. Moreover, the energy dissipated to complete the division is roughly the same for the three radices. However, the power dissipation, proportional to the average current, increases with the radix. If reducing the energy is the priority, for the same latency radix-16 with dual voltage produces the smallest energy dissipation.

rawabstract:
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this paper we explore the relation between the radix and the energy dissipated. Previous work has been done on radix-4 and radix-8 division. Here we extend this study to a radix-16 scheme with two overlapped radix-4 stages and compare the latency, area, and energy of the three implementations.\par Results show that by applying the low-power techniques the energy dissipation is reduced from 30\% to 40\%, with respect to the standard implementation. An additional 20\% reduction can be obtained using a dual voltage. Moreover, the energy dissipated to complete the division is roughly the same for the three radices. However, the power dissipation, proportional to the average current, increases with the radix. If reducing the energy is the priority, for the same latency radix-16 with dual voltage produces the smallest energy dissipation.

entry:
@InProceedings{Nannarelli:1999:LPDa,
  author =       "Alberto Nannarelli and Tomas Lang",
  title =        "Low-Power Division: Comparison among Implementations
                 of Radix $4$, $8$ and $ 16 $",
  crossref =     "Koren:1999:ISC",
  pages =        "60--69",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-158.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-158.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Nannarelli.pdf",
  abstract =     "Although division is less frequent than addition and
                 multiplication, because of its longer latency it
                 dissipates a substantial part of the energy in
                 floating-point units. In this paper we explore the
                 relation between the radix and the energy dissipated.
                 Previous work has been done on radix-4 and radix-8
                 division. Here we extend this study to a radix-16
                 scheme with two overlapped radix-4 stages and compare
                 the latency, area, and energy of the three
                 implementations.\par

                 Results show that by applying the low-power techniques
                 the energy dissipation is reduced from 30\% to 40\%,
                 with respect to the standard implementation. An
                 additional 20\% reduction can be obtained using a dual
                 voltage. Moreover, the energy dissipated to complete
                 the division is roughly the same for the three radices.
                 However, the power dissipation, proportional to the
                 average current, increases with the radix. If reducing
                 the energy is the priority, for the same latency
                 radix-16 with dual voltage produces the smallest energy
                 dissipation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Nannarelli:1999:LPDb
author: A. Nannarelli and T. Lang
title: Low-Power Divider
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 1
pages: 2--14
month: jan
monthnumber: 1
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.743407
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:56 MDT 2011
bibtimestamp: 2011.07.06 08:46:56 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=743407
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Nannarelli and T. Lang
rawtitle: Low-Power Divider
entry:
@Article{Nannarelli:1999:LPDb,
  author =       "A. Nannarelli and T. Lang",
  title =        "Low-Power Divider",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "1",
  pages =        "2--14",
  month =        jan,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.743407",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=743407",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:1999:LPR
author: Alberto Nannarelli and Tomas Lang
booktitle: (ICCD '99) International Conference on Computer Design
title: Low-power radix-$4$ combined division and square root
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 236--242
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli and Tomas Lang
rawbooktitle: ({ICCD '99}) International Conference on Computer Design
rawtitle: Low-power radix-$4$ combined division and square root
entry:
@InProceedings{Nannarelli:1999:LPR,
  author =       "Alberto Nannarelli and Tomas Lang",
  booktitle =    "({ICCD '99}) International Conference on Computer
                 Design",
  title =        "Low-power radix-$4$ combined division and square
                 root",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "236--242",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Because of the similarities in the algorithm it is
                 quite common to implement division and square root in
                 the same unit. The purpose of this work is to implement
                 a low-power combined radix-$4$ division and square root
                 floating-point double precision \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Nedialkov:1999:IHO
author: N. S. Nedialkov and K. R. Jackson
journal: j-RELIABLE-COMPUTING
volume: 5
number: 3
pages: 289--310
year: 1999
CODEN: RCOMF8
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Mon May 20 06:37:48 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:37:48 MDT
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: N. S. Nedialkov and K. R. Jackson
title:
An Interval Hermite-Obreschkoff Method for Computing Rigorous Bounds on the Solution of an Initial Value Problem for an Ordinary Differential Equation

rawtitle:
An Interval Hermite-Obreschkoff Method for Computing Rigorous Bounds on the Solution of an Initial Value Problem for an Ordinary Differential Equation

entry:
@Article{Nedialkov:1999:IHO,
  author =       "N. S. Nedialkov and K. R. Jackson",
  title =        "An Interval Hermite-Obreschkoff Method for Computing
                 Rigorous Bounds on the Solution of an Initial Value
                 Problem for an Ordinary Differential Equation",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "5",
  number =       "3",
  pages =        "289--310",
  year =         "1999",
  CODEN =        "RCOMF8",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Mon May 20 06:37:48 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
  remark =       "Papers from Scientific computing, computer arithmetic
                 and validated numerics (SCAN '98), September 1998,
                 Budapest, Hungary.",
}


bibtype: inproceedings
filename: fparith.bib
label: Northrop:1999:GM
title: 600MHz G5 S/390 Microprocessor
crossref: Wuorinen:1999:IIS
pages: ??--??
year: 1999
bibdate: Mon Jan 08 08:40:27 2001
bibsource: http://www.sscs.org/digests/1999/DATA/05_2.pdf; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.01.08 08:40:27 ???
acknowledgement: ack-nhfb
rawtitle: {600MHz G5 S/390} Microprocessor
author:
G. Northrop and R. Averill and K. Barkley and S. Carey and Y. Chan and Y. H. Chan and M. Check and D. Hoffman and W. Huott and B. Krumm and C. Krygowski and J. Liptay and M. Mayo and T. McNamara and T. McPherson and E. Schwarz and L. Sigal and T. Slegel and C. Webb and D. Webber and P. Williams

rawauthor:
G. Northrop and R. Averill and K. Barkley and S. Carey and Y. Chan and Y. H. Chan and M. Check and D. Hoffman and W. Huott and B. Krumm and C. Krygowski and J. Liptay and M. Mayo and T. McNamara and T. McPherson and E. Schwarz and L. Sigal and T. Slegel and C. Webb and D. Webber and P. Williams

entry:
@InProceedings{Northrop:1999:GM,
  author =       "G. Northrop and R. Averill and K. Barkley and S. Carey
                 and Y. Chan and Y. H. Chan and M. Check and D. Hoffman
                 and W. Huott and B. Krumm and C. Krygowski and J.
                 Liptay and M. Mayo and T. McNamara and T. McPherson and
                 E. Schwarz and L. Sigal and T. Slegel and C. Webb and
                 D. Webber and P. Williams",
  title =        "{600MHz G5 S/390} Microprocessor",
  crossref =     "Wuorinen:1999:IIS",
  pages =        "??--??",
  year =         "1999",
  bibdate =      "Mon Jan 08 08:40:27 2001",
  bibsource =    "http://www.sscs.org/digests/1999/DATA/05_2.pdf;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  pagecount =    "9",
}


bibtype: inproceedings
filename: fparith.bib
label: Oberman:1999:FPD
author: Stuart F. Oberman
crossref: Koren:1999:ISC
pages: 106--115
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Stuart F. Oberman
title:
Floating point division and square root algorithms and implementation in the AMD-K7TM microprocessor

URL:
http://euler.ecs.umass.edu/paper/final/paper-139.pdf; http://euler.ecs.umass.edu/paper/final/paper-139.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Oberman.pdf

abstract:
This paper presents the AMD-K7 IEEE 754 and x87 compliant floating point division and square root algorithms and implementation. The AMD-K7 processor employs an iterative implementation of a series expansion to converge quadratically to the quotient and square root. Highly accurate initial approximations and a high performance shared floating point multiplier assist in achieving low division and square root latencies at high operating frequencies. A novel time-sharing technique allows independent floating point multiplication operations to proceed while division or square root computation is in progress. Exact IEEE 754 rounding for all rounding modes and target precisions has been verified by conventional directed and random testing procedures, along with the formulation of a mechanically-checked formal proof using the ACL2 theorem prover.

rawabstract:
This paper presents the AMD-K7 IEEE 754 and x87 compliant floating point division and square root algorithms and implementation. The AMD-K7 processor employs an iterative implementation of a series expansion to converge quadratically to the quotient and square root. Highly accurate initial approximations and a high performance shared floating point multiplier assist in achieving low division and square root latencies at high operating frequencies. A novel time-sharing technique allows independent floating point multiplication operations to proceed while division or square root computation is in progress. Exact IEEE 754 rounding for all rounding modes and target precisions has been verified by conventional directed and random testing procedures, along with the formulation of a mechanically-checked formal proof using the ACL2 theorem prover.

rawtitle:
Floating point division and square root algorithms and implementation in the {AMD-K7{\TM}} microprocessor

entry:
@InProceedings{Oberman:1999:FPD,
  author =       "Stuart F. Oberman",
  title =        "Floating point division and square root algorithms and
                 implementation in the {AMD-K7{\TM}} microprocessor",
  crossref =     "Koren:1999:ISC",
  pages =        "106--115",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-139.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-139.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Oberman.pdf",
  abstract =     "This paper presents the AMD-K7 IEEE 754 and x87
                 compliant floating point division and square root
                 algorithms and implementation. The AMD-K7 processor
                 employs an iterative implementation of a series
                 expansion to converge quadratically to the quotient and
                 square root. Highly accurate initial approximations and
                 a high performance shared floating point multiplier
                 assist in achieving low division and square root
                 latencies at high operating frequencies. A novel
                 time-sharing technique allows independent floating
                 point multiplication operations to proceed while
                 division or square root computation is in progress.
                 Exact IEEE 754 rounding for all rounding modes and
                 target precisions has been verified by conventional
                 directed and random testing procedures, along with the
                 formulation of a mechanically-checked formal proof
                 using the ACL2 theorem prover.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
  summary =      "This paper presents the AMD-K7 IEEE 754 and $\times$87
                 compliant floating point division and square root
                 algorithms and implementation. The AMD-K7 processor
                 employs an iterative implementation of a series
                 expansion to converge quadratically to the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: OLeary:1999:FVI
author: John O'Leary and Xudong Zhao and Rob Gerth and Carl-Johan H. Seger
title: Formally Verifying IEEE Compliance of Floating-Point Hardware
journal: j-INTEL-TECH-J
volume: Q1
pages: 10
day: 17
month: feb
monthnumber: 2
year: 1999
bibdate: Fri Jun 01 06:02:08 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.01 06:02:08 ???
acknowledgement: ack-nhfb
rawauthor: John O'Leary and Xudong Zhao and Rob Gerth and Carl-Johan H. Seger
rawtitle: Formally Verifying {IEEE} Compliance of Floating-Point Hardware
URL:
http://developer.intel.com/technology/itj/q11999/articles/art_5.htm; http://developer.intel.com/technology/itj/q11999/pdf/floating_point.pdf

entry:
@Article{OLeary:1999:FVI,
  author =       "John O'Leary and Xudong Zhao and Rob Gerth and
                 Carl-Johan H. Seger",
  title =        "Formally Verifying {IEEE} Compliance of Floating-Point
                 Hardware",
  journal =      j-INTEL-TECH-J,
  volume =       "Q1",
  pages =        "10",
  day =          "17",
  month =        feb,
  year =         "1999",
  bibdate =      "Fri Jun 01 06:02:08 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://developer.intel.com/technology/itj/q11999/articles/art_5.htm;
                 http://developer.intel.com/technology/itj/q11999/pdf/floating_point.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Paar:1999:FAP
author: C. Paar and P. Fleischmann and P. Soria-Rodriguez
title: Fast arithmetic for public-key algorithms in Galois fields with composite exponents
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 10
pages: 1025--1034
month: oct
monthnumber: 10
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.805153
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:46:59 MDT 2011
bibtimestamp: 2011.07.06 08:46:59 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=805153
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. Paar and P. Fleischmann and P. Soria-Rodriguez
rawtitle: Fast arithmetic for public-key algorithms in {Galois} fields with composite exponents
entry:
@Article{Paar:1999:FAP,
  author =       "C. Paar and P. Fleischmann and P. Soria-Rodriguez",
  title =        "Fast arithmetic for public-key algorithms in {Galois}
                 fields with composite exponents",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "10",
  pages =        "1025--1034",
  month =        oct,
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.805153",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:46:59 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=805153",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Paliouras:1999:MAR
author: V. Paliouras and T. Stouraitis
title: Multifunction Architectures for RNS Processors
journal: j-IEEE-TRANS-CIRCUITS-SYST
volume: 46
number: 8
pages: 1041--1054
month: aug
monthnumber: 8
year: 1999
CODEN: ICSYBT
ISSN: 0098-4094 (print), 1558-1276 (electronic) OR 00984094 (print), 15581276 (electronic)
ISSNL: 0098-4094 OR 00984094
bibdate: Fri Jun 24 18:26:56 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 18:26:56 ???
fjournal: IEEE Transactions on Circuits and Systems
keywords: Residue Number System (RNS)
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawtitle: Multifunction Architectures for {RNS} Processors
entry:
@Article{Paliouras:1999:MAR,
  author =       "V. Paliouras and T. Stouraitis",
  title =        "Multifunction Architectures for {RNS} Processors",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST,
  volume =       "46",
  number =       "8",
  pages =        "1041--1054",
  month =        aug,
  year =         "1999",
  CODEN =        "ICSYBT",
  ISSN =         "0098-4094 (print), 1558-1276 (electronic)",
  ISSN-L =       "0098-4094",
  bibdate =      "Fri Jun 24 18:26:56 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems",
  keywords =     "Residue Number System (RNS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:1999:NHR
author: V. Paliouras and T. Stouraitis
title: Novel high-radix residue number system multipliers and adders
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 451--454
year: 1999
DOI: https://doi.org/10.1109/ISCAS.1999.777911
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawtitle: Novel high-radix residue number system multipliers and adders
booktitle:
ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 2 June 1999

rawbooktitle:
{ISCAS '99}. Proceedings of the 1999 {IEEE} International Symposium on Circuits and Systems, 2 June 1999

entry:
@InProceedings{Paliouras:1999:NHR,
  author =       "V. Paliouras and T. Stouraitis",
  booktitle =    "{ISCAS '99}. Proceedings of the 1999 {IEEE}
                 International Symposium on Circuits and Systems, 2 June
                 1999",
  title =        "Novel high-radix residue number system multipliers and
                 adders",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "451--454",
  year =         "1999",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1999.777911",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Radix-r modulo r n multipliers and adders are
                 introduced in this paper. The proposed architectures
                 are shown to require several times less area than
                 previously reported architectures, for particular
                 moduli of operation. The proposed \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parhami:1999:ALT
author: B. Parhami
booktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
title: Analysis of the lookup table size for square-rooting
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1327--1330
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: B. Parhami
rawbooktitle: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999
rawtitle: Analysis of the lookup table size for square-rooting
entry:
@InProceedings{Parhami:1999:ALT,
  author =       "B. Parhami",
  booktitle =    "Conference Record of the Thirty-Third Asilomar
                 Conference on Signals, Systems, and Computers, 1999",
  title =        "Analysis of the lookup table size for square-rooting",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1327--1330",
  year =         "1999",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Convergence methods are widely used for division,
                 reciprocation, and square-rooting. With such methods,
                 it is common to use an initial table lookup step for
                 obtaining an approximate result that leads to faster
                 convergence. In the case of division \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Park:1999:FPM
author: W.-C. Park and T.-D. Han and S.-D. Kim and S.-B. Yang
title: A floating point multiplier performing IEEE rounding and addition in parallel
journal: j-J-SYST-ARCH
volume: 45
number: 14
pages: 1195--1207
month: jul
monthnumber: 7
year: 1999
CODEN: JSARFB
ISSN: 1383-7621 (print), 1873-6165 (electronic) OR 13837621 (print), 18736165 (electronic)
ISSNL: 1383-7621 OR 13837621
bibdate: Fri Nov 8 05:39:32 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Ingenta database
bibtimestamp: 2002.11.08 05:39:32 MST
fjournal: Journal of Systems Architecture
acknowledgement: ack-nhfb
rawauthor: W.-C. Park and T.-D. Han and S.-D. Kim and S.-B. Yang
rawtitle: A floating point multiplier performing {IEEE} rounding and addition in parallel
entry:
@Article{Park:1999:FPM,
  author =       "W.-C. Park and T.-D. Han and S.-D. Kim and S.-B.
                 Yang",
  title =        "A floating point multiplier performing {IEEE} rounding
                 and addition in parallel",
  journal =      j-J-SYST-ARCH,
  volume =       "45",
  number =       "14",
  pages =        "1195--1207",
  month =        jul,
  year =         "1999",
  CODEN =        "JSARFB",
  ISSN =         "1383-7621 (print), 1873-6165 (electronic)",
  ISSN-L =       "1383-7621",
  bibdate =      "Fri Nov 8 05:39:32 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Ingenta database",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Systems Architecture",
  pagecount =    "13",
}


bibtype: misc
filename: fparith.bib
label: Parker:1999:SPA
author: D. Stott Parker
title: A semi-portable ANSI C implementation of Monte Carlo floating-point arithmetic
pages: 1195--1207
year: 1999
bibdate: Mon Aug 25 15:08:02 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.08.25 15:08:02 ???
URL: http://www.cs.ucla.edu/~stott/mca/MCAdemo.c
acknowledgement: ack-nhfb
howpublished: World-Wide Web document.
rawauthor: D. Stott Parker
rawtitle: A semi-portable {ANSI} {C} implementation of {Monte Carlo} floating-point arithmetic
entry:
@Misc{Parker:1999:SPA,
  author =       "D. Stott Parker",
  title =        "A semi-portable {ANSI} {C} implementation of {Monte
                 Carlo} floating-point arithmetic",
  howpublished = "World-Wide Web document.",
  year =         "1999",
  bibdate =      "Mon Aug 25 15:08:02 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.ucla.edu/~stott/mca/MCAdemo.c",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Parks:1999:NTT
author: Michael Parks
title: Number-Theoretic Test Generation for Directed Rounding
crossref: Koren:1999:ISC
pages: 241--249
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic; correct rounding; floating-point arithmetic; floating-point testing
acknowledgement: ack-nhfb
rawauthor: Michael Parks
rawtitle: Number-Theoretic Test Generation for Directed Rounding
URL:
http://euler.ecs.umass.edu/paper/final/paper-131.pdf; http://euler.ecs.umass.edu/paper/final/paper-131.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Parks.pdf

abstract:
We present methods to generate systematically the hardest test cases for multiplication, division, and square root subject to directed rounding, essentially extending previous work on number-theoretic floating-point testing to rounding modes other than to-nearest. The algorithms focus upon the rounding boundaries of the modes truncate, to-minus-infinity, and to-infinity, and programs based on them require little beyond exact arithmetic in the working precision to create billions of edge cases. We will show that the amount of work required to calculate trial multiplicands pays off in the form of free extra tests due to an interconnection among the operations considered herein. Although these tests do not replace proofs of correctness, they can be used to gain a high degree of confidence that the accuracy requirements as mandated by IEEE Standard 754 have been satisfied.

rawabstract:
We present methods to generate systematically the hardest test cases for multiplication, division, and square root subject to directed rounding, essentially extending previous work on number-theoretic floating-point testing to rounding modes other than to-nearest. The algorithms focus upon the rounding boundaries of the modes truncate, to-minus-infinity, and to-infinity, and programs based on them require little beyond exact arithmetic in the working precision to create billions of edge cases. We will show that the amount of work required to calculate trial multiplicands pays off in the form of free extra tests due to an interconnection among the operations considered herein. Although these tests do not replace proofs of correctness, they can be used to gain a high degree of confidence that the accuracy requirements as mandated by IEEE Standard 754 have been satisfied.

entry:
@InProceedings{Parks:1999:NTT,
  author =       "Michael Parks",
  title =        "Number-Theoretic Test Generation for Directed
                 Rounding",
  crossref =     "Koren:1999:ISC",
  pages =        "241--249",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-131.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-131.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Parks.pdf",
  abstract =     "We present methods to generate systematically the
                 hardest test cases for multiplication, division, and
                 square root subject to directed rounding, essentially
                 extending previous work on number-theoretic
                 floating-point testing to rounding modes other than
                 to-nearest. The algorithms focus upon the rounding
                 boundaries of the modes truncate, to-minus-infinity,
                 and to-infinity, and programs based on them require
                 little beyond exact arithmetic in the working precision
                 to create billions of edge cases. We will show that the
                 amount of work required to calculate trial
                 multiplicands pays off in the form of free extra tests
                 due to an interconnection among the operations
                 considered herein. Although these tests do not replace
                 proofs of correctness, they can be used to gain a high
                 degree of confidence that the accuracy requirements as
                 mandated by IEEE Standard 754 have been satisfied.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic; correct rounding;
                 floating-point arithmetic; floating-point testing",
  summary =      "We present methods to generate systematically the
                 hardest test cases for multiplication, division, and
                 square root subject to directed rounding, essentially
                 extending previous work on number-theoretic floating
                 point testing to rounding modes other \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Phatak:1999:IVE
author: Dhananjay S. Phatak and I. Koren
crossref: Koren:1999:ISC
pages: 22--29
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Dhananjay S. Phatak and I. Koren
title:
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition

URL:
http://euler.ecs.umass.edu/paper/final/paper-149.pdf; http://euler.ecs.umass.edu/paper/final/paper-149.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Phatak.pdf

abstract:
In two operand addition, bit-wise intermediate variables such as the ``propagate'' and ``generate'' terms are defined / evaluated first. Basic carry propagation recursion is then expressed in terms of these variables and is ``unrolled'' to obtain a tree structure for fast execution. In CMOS VLSI technology, multiplexors are fast and efficient to implement. Hence, we investigate in this paper all possible two-bit encodings for the intermediate variables and identify the ones that enable multiplexor-based implementations. Some of these encodings enable further simplification of the multiplexor-based realizations. Our analysis also shows that adopting an intermediate signed-digit representation simply amounts to selecting one of the possible encodings. Thus, there is no inherent advantage to the use of intermediate signed-digit representations in a two operand addition. Finally, we extend our analysis to the generalized look-ahead-recursions proposed by Doran.

rawabstract:
In two operand addition, bit-wise intermediate variables such as the ``propagate'' and ``generate'' terms are defined \slash evaluated first. Basic carry propagation recursion is then expressed in terms of these variables and is ``unrolled'' to obtain a tree structure for fast execution. In CMOS VLSI technology, multiplexors are fast and efficient to implement. Hence, we investigate in this paper all possible two-bit encodings for the intermediate variables and identify the ones that enable multiplexor-based implementations. Some of these encodings enable further simplification of the multiplexor-based realizations. Our analysis also shows that adopting an intermediate signed-digit representation simply amounts to selecting one of the possible encodings. Thus, there is no inherent advantage to the use of intermediate signed-digit representations in a two operand addition. Finally, we extend our analysis to the generalized look-ahead-recursions proposed by Doran.

rawtitle:
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition

entry:
@InProceedings{Phatak:1999:IVE,
  author =       "Dhananjay S. Phatak and I. Koren",
  title =        "Intermediate Variable Encodings that Enable
                 Multiplexor-Based Implementations of Two Operand
                 Addition",
  crossref =     "Koren:1999:ISC",
  pages =        "22--29",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-149.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-149.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Phatak.pdf",
  abstract =     "In two operand addition, bit-wise intermediate
                 variables such as the ``propagate'' and ``generate''
                 terms are defined \slash evaluated first. Basic carry
                 propagation recursion is then expressed in terms of
                 these variables and is ``unrolled'' to obtain a tree
                 structure for fast execution. In CMOS VLSI technology,
                 multiplexors are fast and efficient to implement.
                 Hence, we investigate in this paper all possible
                 two-bit encodings for the intermediate variables and
                 identify the ones that enable multiplexor-based
                 implementations. Some of these encodings enable further
                 simplification of the multiplexor-based realizations.
                 Our analysis also shows that adopting an intermediate
                 signed-digit representation simply amounts to selecting
                 one of the possible encodings. Thus, there is no
                 inherent advantage to the use of intermediate
                 signed-digit representations in a two operand addition.
                 Finally, we extend our analysis to the generalized
                 look-ahead-recursions proposed by Doran.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Ralev:1999:RBF
author: K. R. Ralev and P. H. Bauer
title: Realization of block floating-point digital filters and application to block implementations
journal: j-IEEE-TRANS-SIG-PROC
volume: 47
number: 4
pages: 1076--1086
month: apr
monthnumber: 4
year: 1999
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: K. R. Ralev and P. H. Bauer
rawtitle: Realization of block floating-point digital filters and application to block implementations
entry:
@Article{Ralev:1999:RBF,
  author =       "K. R. Ralev and P. H. Bauer",
  title =        "Realization of block floating-point digital filters
                 and application to block implementations",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "47",
  number =       "4",
  pages =        "1076--1086",
  month =        apr,
  year =         "1999",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "Realization issues of block floating-point (BFP)
                 filters such as complexity, roundoff noise, and absence
                 of limit cycles are analyzed. Several new results are
                 established. Under certain conditions, BFP filters
                 perform better than fixed-point filters \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ruess:1999:MVS
author: Harald Ruess and Natarajan Shankar and Mandayam K. Srivas
title: Modular Verification of SRT Division
journal: j-FORM-METHODS-SYST-DES
volume: 14
number: 1
pages: 45--73
month: jan
monthnumber: 1
year: 1999
CODEN: FMSDE6
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Sat Jun 02 09:22:39 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 09:22:39 ???
note: Special issue on arithmetic circuits.
URL: http://www.wkap.nl/jrnltoc.htm/0925-9856; http://www.wkap.nl/oasis.htm/194807
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: Harald Ruess and Natarajan Shankar and Mandayam K. Srivas
rawnote: Special issue on arithmetic circuits.
rawtitle: Modular Verification of {SRT} Division
entry:
@Article{Ruess:1999:MVS,
  author =       "Harald Ruess and Natarajan Shankar and Mandayam K.
                 Srivas",
  title =        "Modular Verification of {SRT} Division",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "14",
  number =       "1",
  pages =        "45--73",
  month =        jan,
  year =         "1999",
  CODEN =        "FMSDE6",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Sat Jun 02 09:22:39 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special issue on arithmetic circuits.",
  URL =          "http://www.wkap.nl/jrnltoc.htm/0925-9856;
                 http://www.wkap.nl/oasis.htm/194807",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: article
filename: fparith.bib
label: Rugina:1999:APD
author: Radu Rugina and Martin Rinard
title: Automatic parallelization of divide and conquer algorithms
journal: j-SIGPLAN
volume: 34
number: 8
pages: 72--83
month: aug
monthnumber: 8
year: 1999
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:18:06 MST 2003
bibtimestamp: 2003.12.14 09:18:06 MST
URL: http://www.acm.org/pubs/citations/proceedings/ppopp/301104/p72-rugina/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Radu Rugina and Martin Rinard
rawtitle: Automatic parallelization of divide and conquer algorithms
bibsource:
http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/ppopp/301104/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Rugina:1999:APD,
  author =       "Radu Rugina and Martin Rinard",
  title =        "Automatic parallelization of divide and conquer
                 algorithms",
  journal =      j-SIGPLAN,
  volume =       "34",
  number =       "8",
  pages =        "72--83",
  month =        aug,
  year =         "1999",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:18:06 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/ppopp/301104/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org/pubs/citations/proceedings/ppopp/301104/p72-rugina/",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: inproceedings
filename: fparith.bib
label: Rump:1999:IIL
author: Siegfried M. Rump
title: INTLAB--INTerval LABoratory
crossref: Csendes:1999:DRC
pages: 77--104
year: 1999
bibdate: Tue Nov 22 06:39:33 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.22 06:39:33 ???
keywords: accurate floating-point summation; interval arithmetic
acknowledgement: ack-nhfb
rawauthor: Siegfried M. Rump
rawtitle: {INTLAB--INTerval LABoratory}
entry:
@InProceedings{Rump:1999:IIL,
  author =       "Siegfried M. Rump",
  title =        "{INTLAB--INTerval LABoratory}",
  crossref =     "Csendes:1999:DRC",
  pages =        "77--104",
  year =         "1999",
  bibdate =      "Tue Nov 22 06:39:33 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; interval
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: Russinoff:1999:MCP
author: David M. Russinoff
title: A mechanically checked proof of correctness of the AMD K5 floating point square root microcode
journal: j-FORM-METHODS-SYST-DES
volume: 14
number: 1
pages: 75--125
month: jan
monthnumber: 1
year: 1999
CODEN: FMSDE6
DOI: https://doi.org/10.1023/A:1008669628911
ISSN: 0925-9856 (print), 1572-8102 (electronic) OR 09259856 (print), 15728102 (electronic)
ISSNL: 0925-9856 OR 09259856
bibdate: Sat Jun 02 07:51:51 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 07:51:51 ???
note: Special issue on arithmetic circuits.
fjournal: Formal Methods in System Design
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/fmsd
rawauthor: David M. Russinoff
rawnote: Special issue on arithmetic circuits.
rawtitle: A mechanically checked proof of correctness of the {AMD K5} floating point square root microcode
URL:
http://www.wkap.nl/jrnltoc.htm/0925-9856; http://www.wkap.nl/oasis.htm/194808; https://dl.acm.org/doi/abs/10.1023/A:1008669628911

abstract:
We present a rigorous mathematical proof of the correctness of the floating point square root instruction of the AMD K5 microprocessor. The instruction is represented as a program in a formal language that was designed for this purpose, based on the K5 microcode and the architecture of its FPU. We prove a statement of its correctness that corresponds directly with the IEEE Standard. We also derive an equivalent formulation, expressed in terms of rational arithmetic, which has been encoded as a formula in the ACL2 logic and mechanically verified with the ACL2 prover. Finally, we describe a microcode modification that was implemented as a result of this analysis in order to ensure the correctness of the instruction.

rawabstract:
We present a rigorous mathematical proof of the correctness of the floating point square root instruction of the AMD K5 microprocessor. The instruction is represented as a program in a formal language that was designed for this purpose, based on the K5 microcode and the architecture of its FPU. We prove a statement of its correctness that corresponds directly with the IEEE Standard. We also derive an equivalent formulation, expressed in terms of rational arithmetic, which has been encoded as a formula in the ACL2 logic and mechanically verified with the ACL2 prover. Finally, we describe a microcode modification that was implemented as a result of this analysis in order to ensure the correctness of the instruction.

entry:
@Article{Russinoff:1999:MCP,
  author =       "David M. Russinoff",
  title =        "A mechanically checked proof of correctness of the
                 {AMD K5} floating point square root microcode",
  journal =      j-FORM-METHODS-SYST-DES,
  volume =       "14",
  number =       "1",
  pages =        "75--125",
  month =        jan,
  year =         "1999",
  CODEN =        "FMSDE6",
  DOI =          "https://doi.org/10.1023/A:1008669628911",
  ISSN =         "0925-9856 (print), 1572-8102 (electronic)",
  ISSN-L =       "0925-9856",
  bibdate =      "Sat Jun 02 07:51:51 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special issue on arithmetic circuits.",
  URL =          "http://www.wkap.nl/jrnltoc.htm/0925-9856;
                 http://www.wkap.nl/oasis.htm/194808;
                 https://dl.acm.org/doi/abs/10.1023/A:1008669628911",
  abstract =     "We present a rigorous mathematical proof of the
                 correctness of the floating point square root
                 instruction of the AMD K5 microprocessor. The
                 instruction is represented as a program in a formal
                 language that was designed for this purpose, based on
                 the K5 microcode and the architecture of its FPU. We
                 prove a statement of its correctness that corresponds
                 directly with the IEEE Standard. We also derive an
                 equivalent formulation, expressed in terms of rational
                 arithmetic, which has been encoded as a formula in the
                 ACL2 logic and mechanically verified with the ACL2
                 prover. Finally, we describe a microcode modification
                 that was implemented as a result of this analysis in
                 order to ensure the correctness of the instruction.",
  acknowledgement = ack-nhfb,
  fjournal =     "Formal Methods in System Design",
  journal-URL =  "https://dl.acm.org/loi/fmsd",
}


bibtype: inproceedings
filename: fparith.bib
label: Saed:1999:ASA
author: Aryan Saed and Majid Ahmadi and Graham A. Jullien
title: Arithmetic with Signed Analog Digits
crossref: Koren:1999:ISC
pages: 134--141
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Aryan Saed and Majid Ahmadi and Graham A. Jullien
rawtitle: Arithmetic with Signed Analog Digits
URL:
http://euler.ecs.umass.edu/paper/final/paper-140.pdf; http://euler.ecs.umass.edu/paper/final/paper-140.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Saed.pdf

abstract:
This paper presents mathematical foundations of the Overlap Resolution Number System (ORNS) which is based on signed Continuous Valued Digits (CVD's). ORNS is a redundant Number System employing residue arithmetic. In contrast to the implementation of arithmetic by binary or multiple-valued logic circuits, arithmetic operations in this novel number system are performed by analog digit manipulation circuitry. The redundancy in an ensemble of Continuous Valued Digits that comprises a number provides tolerance to implementation imprecisions. Processing with these analog digits is performed by carry-free arithmetic structures with systematic circuit level redundancy.

rawabstract:
This paper presents mathematical foundations of the Overlap Resolution Number System (ORNS) which is based on signed Continuous Valued Digits (CVD's). ORNS is a redundant Number System employing residue arithmetic. In contrast to the implementation of arithmetic by binary or multiple-valued logic circuits, arithmetic operations in this novel number system are performed by analog digit manipulation circuitry. The redundancy in an ensemble of Continuous Valued Digits that comprises a number provides tolerance to implementation imprecisions. Processing with these analog digits is performed by carry-free arithmetic structures with systematic circuit level redundancy.

entry:
@InProceedings{Saed:1999:ASA,
  author =       "Aryan Saed and Majid Ahmadi and Graham A. Jullien",
  title =        "Arithmetic with Signed Analog Digits",
  crossref =     "Koren:1999:ISC",
  pages =        "134--141",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-140.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-140.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Saed.pdf",
  abstract =     "This paper presents mathematical foundations of the
                 Overlap Resolution Number System (ORNS) which is based
                 on signed Continuous Valued Digits (CVD's). ORNS is a
                 redundant Number System employing residue arithmetic.
                 In contrast to the implementation of arithmetic by
                 binary or multiple-valued logic circuits, arithmetic
                 operations in this novel number system are performed by
                 analog digit manipulation circuitry. The redundancy in
                 an ensemble of Continuous Valued Digits that comprises
                 a number provides tolerance to implementation
                 imprecisions. Processing with these analog digits is
                 performed by carry-free arithmetic structures with
                 systematic circuit level redundancy.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: SanGregory:1999:FLP
author: Samuel L. SanGregory and Charles Brothers and David Gallagher and Raymond Siferd
editor: IEEE
title: A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 388--391
year: 1999
DOI: https://doi.org/10.1109/MWSCAS.1999.867287
LCCN: TK3226 .M531 42nd 1999
bibdate: Wed Dec 20 07:16:14 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:16:14 ???
URL: https://digitalcommons.cedarville.edu/engineering_and_computer_science_presentations/13
acknowledgement: ack-nhfb
bookpages: xl + 1150 (two volumes)
rawauthor: Samuel L. SanGregory and Charles Brothers and David Gallagher and Raymond Siferd
raweditor: {IEEE}
rawtitle: A Fast, Low-Power Logarithm Approximation with {CMOS VLSI} Implementation
booktitle:
Proceedings of 1999 Midwest Symposium on Circuits and Systems: August 8--12, 1999, Corbett Center, New Mexico State University, Las Cruces, New Mexico

ISBN:
0-7803-5491-5 (softbound), 0-7803-5492-3 (casebound), 0-7803-5493-1 (microfiche) OR 0780354915 (softbound), 0780354923 (casebound), 0780354931 (microfiche)

ISBN13:
978-0-7803-5491-3 (softbound), 978-0-7803-5492-0 (casebound), 978-0-7803-5493-7 (microfiche) OR 9780780354913 (softbound), 9780780354920 (casebound), 9780780354937 (microfiche)

abstract:
A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2 and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented, a ROM of only $ N times log _2 (N) $ bits is used to convert $N$ bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25.

rawabstract:
A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2 and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented, a ROM of only $ N \times \log_2 (N) $ bits is used to convert $N$ bit integers. The maximum error of the approximation is 1.5\% when the input value is 3, and decays exponentially to less than 0.5\% for input values greater than 25.

rawbooktitle:
{Proceedings of 1999 Midwest Symposium on Circuits and Systems: August 8--12, 1999, Corbett Center, New Mexico State University, Las Cruces, New Mexico}

entry:
@InProceedings{SanGregory:1999:FLP,
  author =       "Samuel L. SanGregory and Charles Brothers and David
                 Gallagher and Raymond Siferd",
  editor =       "{IEEE}",
  booktitle =    "{Proceedings of 1999 Midwest Symposium on Circuits and
                 Systems: August 8--12, 1999, Corbett Center, New Mexico
                 State University, Las Cruces, New Mexico}",
  title =        "A Fast, Low-Power Logarithm Approximation with {CMOS
                 VLSI} Implementation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xl + 1150 (two volumes)",
  pages =        "388--391",
  year =         "1999",
  DOI =          "https://doi.org/10.1109/MWSCAS.1999.867287",
  ISBN =         "0-7803-5491-5 (softbound), 0-7803-5492-3 (casebound),
                 0-7803-5493-1 (microfiche)",
  ISBN-13 =      "978-0-7803-5491-3 (softbound), 978-0-7803-5492-0
                 (casebound), 978-0-7803-5493-7 (microfiche)",
  LCCN =         "TK3226 .M531 42nd 1999",
  bibdate =      "Wed Dec 20 07:16:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://digitalcommons.cedarville.edu/engineering_and_computer_science_presentations/13",
  abstract =     "A new technique and CMOS VLSI implementation for
                 computing approximate logarithms (base 2 and 10) for
                 binary integers is presented. The approximation is
                 performed using only combinational logic and requires
                 no multiplications. Additionally, as implemented, a ROM
                 of only $ N \times \log_2 (N) $ bits is used to convert
                 $N$ bit integers. The maximum error of the
                 approximation is 1.5\% when the input value is 3, and
                 decays exponentially to less than 0.5\% for input
                 values greater than 25.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Scherer:1999:OTW
title: An Out-of-Order Three-Way Superscalar Multimedia Floating-Point Unit
crossref: Wuorinen:1999:IIS
pages: ??--??
year: 1999
bibdate: Mon Jan 08 08:35:15 2001
bibsource: http://www.sscs.org/digests/1999/DATA/05_5.pdf; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.01.08 08:35:15 ???
keywords: AMD-K7 floating-point unit
acknowledgement: ack-nhfb
rawtitle: An Out-of-Order Three-Way Superscalar Multimedia Floating-Point Unit
author:
Alisa Scherer and Michael Golden and Norbert Juffa and Stephan Meier and Stuart Oberman and Hamid Partovi and Fred Weber

remark:
The AMD-K7 floating-point unit is implemented as an out-of-order coprocessor responsible for executing all x86 FPU, MMX, and AMD 3DNow! instructions.

rawauthor:
Alisa Scherer and Michael Golden and Norbert Juffa and Stephan Meier and Stuart Oberman and Hamid Partovi and Fred Weber

entry:
@InProceedings{Scherer:1999:OTW,
  author =       "Alisa Scherer and Michael Golden and Norbert Juffa and
                 Stephan Meier and Stuart Oberman and Hamid Partovi and
                 Fred Weber",
  title =        "An Out-of-Order Three-Way Superscalar Multimedia
                 Floating-Point Unit",
  crossref =     "Wuorinen:1999:IIS",
  pages =        "??--??",
  year =         "1999",
  bibdate =      "Mon Jan 08 08:35:15 2001",
  bibsource =    "http://www.sscs.org/digests/1999/DATA/05_5.pdf;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AMD-K7 floating-point unit",
  pagecount =    "10",
  remark =       "The AMD-K7 floating-point unit is implemented as an
                 out-of-order coprocessor responsible for executing all
                 x86 FPU, MMX, and AMD 3DNow! instructions.",
}


bibtype: inproceedings
filename: fparith.bib
label: Schmookler:1999:LPH
title: A Low-Power, High-Speed Implementation of a PowerPC[TM] Microprocessor Vector Extension
crossref: Koren:1999:ISC
pages: 12--21
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawtitle: A Low-Power, High-Speed Implementation of a {PowerPC[TM]} Microprocessor Vector Extension
author:
Martin S. Schmookler and Michael Putrino and Charles Roth and Mukesh Sharma and Anh Mather and Jon Tyler and Huy Van Nguyen and Mydung N. Pham and Jeff Lent

URL:
http://euler.ecs.umass.edu/paper/final/paper-145.pdf; http://euler.ecs.umass.edu/paper/final/paper-145.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schmookler.pdf

abstract:
The AltiVecTM technology is an extension to the PowerPC architectureTM which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low cost, low power processor based on the acclaimed PowerPC 750TM microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

rawabstract:
The AltiVec{\TM} technology is an extension to the PowerPC architecture{\TM} which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low cost, low power processor based on the acclaimed PowerPC 750{\TM} microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

rawauthor:
Martin S. Schmookler and Michael Putrino and Charles Roth and Mukesh Sharma and Anh Mather and Jon Tyler and Huy Van Nguyen and Mydung N. Pham and Jeff Lent

entry:
@InProceedings{Schmookler:1999:LPH,
  author =       "Martin S. Schmookler and Michael Putrino and Charles
                 Roth and Mukesh Sharma and Anh Mather and Jon Tyler and
                 Huy Van Nguyen and Mydung N. Pham and Jeff Lent",
  title =        "A Low-Power, High-Speed Implementation of a
                 {PowerPC[TM]} Microprocessor Vector Extension",
  crossref =     "Koren:1999:ISC",
  pages =        "12--21",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-145.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-145.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schmookler.pdf",
  abstract =     "The AltiVec{\TM} technology is an extension to the
                 PowerPC architecture{\TM} which provides new
                 computational and storage operations for handling
                 vectors of various data lengths and data types. The
                 first implementation using this technology is a low
                 cost, low power processor based on the acclaimed
                 PowerPC 750{\TM} microprocessor. This paper describes
                 the microarchitecture and design of the vector
                 arithmetic unit of this implementation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Schulte:1999:AEF
author: M. Schulte and J. Stine
title: Approximating Elementary Functions with Symmetric Bipartite Tables
journal: j-IEEE-TRANS-COMPUT
volume: 48
number: 8
pages: 842--847
year: 1999
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.795125
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 20:20:58 2005
bibtimestamp: 2005.06.24 20:20:58 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-10.pdf
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Schulte and J. Stine
rawtitle: Approximating Elementary Functions with Symmetric Bipartite Tables
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

entry:
@Article{Schulte:1999:AEF,
  author =       "M. Schulte and J. Stine",
  title =        "Approximating Elementary Functions with Symmetric
                 Bipartite Tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "48",
  number =       "8",
  pages =        "842--847",
  year =         "1999",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.795125",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 20:20:58 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-10.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:CSI
author: M. J. Schulte and A. Akkas and V. Zelov and J. C. Burley
title: Compiler Support for Interval Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1189--1193
year: 1999
bibdate: Fri Jun 11 05:44:37 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.06.11 05:44:37 ???
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and A. Akkas and V. Zelov and J. C. Burley
rawtitle: Compiler Support for Interval Arithmetic
booktitle:
Proceedings of 16th IEEE Instrumentation and Measurement Technology Conference, Venice, Italy, May, 1999

URL:
http://home.ku.edu.tr/~ahakkas/publications/comp-supp.pdf; http://mesa.ece.wisc.edu/publications/cp_1999-04.pdf

rawbooktitle:
Proceedings of {16th IEEE Instrumentation and Measurement Technology Conference, Venice, Italy, May, 1999}

entry:
@InProceedings{Schulte:1999:CSI,
  author =       "M. J. Schulte and A. Akkas and V. Zelov and J. C.
                 Burley",
  booktitle =    "Proceedings of {16th IEEE Instrumentation and
                 Measurement Technology Conference, Venice, Italy, May,
                 1999}",
  title =        "Compiler Support for Interval Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1189--1193",
  year =         "1999",
  bibdate =      "Fri Jun 11 05:44:37 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home.ku.edu.tr/~ahakkas/publications/comp-supp.pdf;
                 http://mesa.ece.wisc.edu/publications/cp_1999-04.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:ESO
author: M. J. Schulte and K. E. Wires
title: Efficient Second Order Approximations for Reciprocals and Square Roots
crossref: Luk:1999:PSA
volume: 3807
pages: 10--18
year: 1999
bibdate: Sun Mar 04 11:10:48 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:10:48 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-05.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and K. E. Wires
rawtitle: Efficient Second Order Approximations for Reciprocals and Square Roots
entry:
@InProceedings{Schulte:1999:ESO,
  author =       "M. J. Schulte and K. E. Wires",
  title =        "Efficient Second Order Approximations for Reciprocals
                 and Square Roots",
  crossref =     "Luk:1999:PSA",
  volume =       "3807",
  pages =        "10--18",
  year =         "1999",
  bibdate =      "Sun Mar 04 11:10:48 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-05.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:HSI
author: Michael J. Schulte and Kent E. Wires
title: High-Speed Inverse Square Roots
crossref: Koren:1999:ISC
pages: 124--131
year: 1999
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Michael J. Schulte and Kent E. Wires
rawtitle: High-Speed Inverse Square Roots
URL:
http://euler.ecs.umass.edu/paper/final/paper-109.pdf; http://euler.ecs.umass.edu/paper/final/paper-109.ps; http://mesa.ece.wisc.edu/publications/cp_1999-03.pdf; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schulte.pdf

abstract:
Inverse square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents a high-speed method for computing inverse square roots. This method uses a table lookup, operand modification, and multiplication to obtain an initial approximation to the inverse square root. This is followed by a modified Newton--Raphson iteration, consisting of one square, one multiply-complement, and one multiply-add operation. The initial approximation and Newton--Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. Application of this method is illustrated through the design of an inverse square root unit for operands in the IEEE single precision format. An implementation of this unit with a 4-layer metal, 2.5 Volt, 0.25 micron CMOS standard cell library has a cycle time of 6.7 ns, an area of 0.41 mm$^2$, a latency of five cycles, and a throughput of one result per cycle.

rawabstract:
Inverse square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents a high-speed method for computing inverse square roots. This method uses a table lookup, operand modification, and multiplication to obtain an initial approximation to the inverse square root. This is followed by a modified Newton--Raphson iteration, consisting of one square, one multiply-complement, and one multiply-add operation. The initial approximation and Newton--Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. Application of this method is illustrated through the design of an inverse square root unit for operands in the IEEE single precision format. An implementation of this unit with a 4-layer metal, 2.5 Volt, 0.25 micron CMOS standard cell library has a cycle time of 6.7 ns, an area of 0.41 mm$^2$, a latency of five cycles, and a throughput of one result per cycle.

entry:
@InProceedings{Schulte:1999:HSI,
  author =       "Michael J. Schulte and Kent E. Wires",
  title =        "High-Speed Inverse Square Roots",
  crossref =     "Koren:1999:ISC",
  pages =        "124--131",
  year =         "1999",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://euler.ecs.umass.edu/paper/final/paper-109.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-109.ps;
                 http://mesa.ece.wisc.edu/publications/cp_1999-03.pdf;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schulte.pdf",
  abstract =     "Inverse square roots are used in several digital
                 signal processing, multimedia, and scientific computing
                 applications. This paper presents a high-speed method
                 for computing inverse square roots. This method uses a
                 table lookup, operand modification, and multiplication
                 to obtain an initial approximation to the inverse
                 square root. This is followed by a modified
                 Newton--Raphson iteration, consisting of one square,
                 one multiply-complement, and one multiply-add
                 operation. The initial approximation and
                 Newton--Raphson iteration employ specialized hardware
                 to reduce the delay, area, and power dissipation.
                 Application of this method is illustrated through the
                 design of an inverse square root unit for operands in
                 the IEEE single precision format. An implementation of
                 this unit with a 4-layer metal, 2.5 Volt, 0.25 micron
                 CMOS standard cell library has a cycle time of 6.7 ns,
                 an area of 0.41 mm$^2$, a latency of five cycles, and a
                 throughput of one result per cycle.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
  summary =      "Inverse square roots are used in several digital
                 signal processing, multimedia, and scientific computing
                 applications. This paper presents a high-speed method
                 for computing inverse square roots. This method uses a
                 table lookup, operand modification, \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:IEG
author: M. J. Schulte and V. A. Zelov and A. Akkas and J. C. Burley
title: The interval-enhanced GNU Fortran compiler
crossref: Csendes:1999:DRC
pages: 311--322
year: 1999
bibdate: Wed Jan 29 16:56:25 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.01.29 16:56:25 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-12.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and V. A. Zelov and A. Akkas and J. C. Burley
rawtitle: The interval-enhanced {GNU Fortran} compiler
remark:
From cite Steele:2004:RHP: ``A recent extension of the GNU Fortran compiler makes use of accurate conversion techniques.''

entry:
@InProceedings{Schulte:1999:IEG,
  author =       "M. J. Schulte and V. A. Zelov and A. Akkas and J. C.
                 Burley",
  title =        "The interval-enhanced {GNU Fortran} compiler",
  crossref =     "Csendes:1999:DRC",
  pages =        "311--322",
  year =         "1999",
  bibdate =      "Wed Jan 29 16:56:25 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-12.pdf",
  acknowledgement = ack-nhfb,
  remark =       "From \cite{Steele:2004:RHP}: ``A recent extension of
                 the GNU Fortran compiler makes use of accurate
                 conversion techniques.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1999:RPD
author: M. J. Schulte and J. G. Jansen and J. E. Stine
title: Reduced Power Dissipation Through Truncated Multiplication
crossref: Piuri:1999:IAV
pages: 61--69
year: 1999
bibdate: Sun Mar 04 11:16:43 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 11:16:43 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1999-01.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and J. G. Jansen and J. E. Stine
rawtitle: Reduced Power Dissipation Through Truncated Multiplication
entry:
@InProceedings{Schulte:1999:RPD,
  author =       "M. J. Schulte and J. G. Jansen and J. E. Stine",
  title =        "Reduced Power Dissipation Through Truncated
                 Multiplication",
  crossref =     "Piuri:1999:IAV",
  pages =        "61--69",
  year =         "1999",
  bibdate =      "Sun Mar 04 11:16:43 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1999-01.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schwarz:1999:GFPa
author: Eric M. Schwarz and Ronald M. Smith and Christopher A. Krygowski
title: The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
crossref: Koren:1999:ISC
pages: 258--265
year: 1999
bibdate: Mon Feb 7 07:28:26 MST 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.02.07 07:28:26 MST
keywords: ARITH-14; computer arithmetic
acknowledgement: ack-nhfb
rawauthor: Eric M. Schwarz and Ronald M. Smith and Christopher A. Krygowski
rawtitle: The {S/390 G5} Floating Point Unit Supporting Hex and Binary Architectures
URL:
http://computer.org/proceedings/arith/0116/0116toc.htm; http://euler.ecs.umass.edu/paper/final/paper-112.pdf; http://euler.ecs.umass.edu/paper/final/paper-112.ps; http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schwarz.pdf

abstract:
The first high performance floating point unit to support both IBM 360 hexadecimal based floating point architecture and the IEEE 754 Standard binary floating point architecture is described. The S/390 G5 floating point unit supports the new S/390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This floating point unit is part of the microprocessor chip on the S/390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S/390 G5 represents the current state of the art in CISC processor design. This paper describes the S/390 architecture enhancements, the internal format of the FPU, and the modifications to the FPU dataflow.

rawabstract:
The first high performance floating point unit to support both IBM 360 hexadecimal based floating point architecture and the IEEE 754 Standard binary floating point architecture is described. The S/390 G5 floating point unit supports the new S/390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This floating point unit is part of the microprocessor chip on the S/390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S/390 G5 represents the current state of the art in CISC processor design. This paper describes the S/390 architecture enhancements, the internal format of the FPU, and the modifications to the FPU dataflow.

entry:
@InProceedings{Schwarz:1999:GFPa,
  author =       "Eric M. Schwarz and Ronald M. Smith and Christopher A.
                 Krygowski",
  title =        "The {S/390 G5} Floating Point Unit Supporting Hex and
                 Binary Architectures",
  crossref =     "Koren:1999:ISC",
  pages =        "258--265",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://computer.org/proceedings/arith/0116/0116toc.htm;
                 http://euler.ecs.umass.edu/paper/final/paper-112.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-112.ps;
                 http://www.acsel-lab.com/arithmetic/arith14/papers/ARITH14_Schwarz.pdf",
  abstract =     "The first high performance floating point unit to
                 support both IBM 360 hexadecimal based floating point
                 architecture and the IEEE 754 Standard binary floating
                 point architecture is described. The S/390 G5 floating
                 point unit supports the new S/390 architecture which
                 includes hexadecimal based short, long, and extended
                 precision formats and IEEE 754 standard single, double,
                 and quad formats. This floating point unit is part of
                 the microprocessor chip on the S/390 G5 mainframe
                 computer introduced in 1998 and generally available at
                 500 MHz speeds. The S/390 G5 represents the current
                 state of the art in CISC processor design. This paper
                 describes the S/390 architecture enhancements, the
                 internal format of the FPU, and the modifications to
                 the FPU dataflow.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-14; computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Schwarz:1999:GFPb
author: E. M. Schwarz and C. A. Krygowski
title: The S/390 G5 floating-point unit
journal: j-IBM-JRD
volume: 43
number: 5/6
pages: 707--721
month: sep
monthnumber: 9
year: 1999
CODEN: IBMJAE
DOI: https://doi.org/10.1147/rd.435.0707
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Apr 19 18:58:23 MDT 2000
bibtimestamp: 2000.04.19 18:58:23 MDT
URL: http://www.research.ibm.com/journal/rd/435/schwarz.html
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: E. M. Schwarz and C. A. Krygowski
rawtitle: The {S/390 G5} floating-point unit
entry:
@Article{Schwarz:1999:GFPb,
  author =       "E. M. Schwarz and C. A. Krygowski",
  title =        "The {S/390 G5} floating-point unit",
  journal =      j-IBM-JRD,
  volume =       "43",
  number =       "5/6",
  pages =        "707--721",
  month =        sep # "\slash " # nov,
  year =         "1999",
  CODEN =        "IBMJAE",
  DOI =          "https://doi.org/10.1147/rd.435.0707",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Apr 19 18:58:23 MDT 2000",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ibmjrd.bib",
  URL =          "http://www.research.ibm.com/journal/rd/435/schwarz.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}


