# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Meloni:2022:AAP
author: Nicolas Meloni
title: An Alternative Approach to Polynomial Modular Number System Internal Reduction
crossref: IEEE:2022:ISC
pages: 85--85
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00024
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
keywords: ARITH 2022; ARITH-29
acknowledgement: ack-nhfb
rawauthor: Nicolas Meloni
rawtitle: An Alternative Approach to Polynomial Modular Number System Internal Reduction
entry:
@InProceedings{Meloni:2022:AAP,
  author =       "Nicolas Meloni",
  title =        "An Alternative Approach to Polynomial Modular Number
                 System Internal Reduction",
  crossref =     "IEEE:2022:ISC",
  pages =        "85--85",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00024",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2022; ARITH-29",
}


bibtype: article
filename: fparith.bib
label: Micikevicius:2022:FFD
title: FP8 Formats for Deep Learning
journal: arXiv.org
pages: 1--9
year: 2022
bibdate: Wed Aug 7 16:23:07 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 16:23:07 ???
URL: https://arxiv.org/abs/2209.05433
acknowledgement: ack-nhfb
rawtitle: {FP8} Formats for Deep Learning
author:
Paulius Micikevicius and Dusan Stosic and Neil Burgess and Marius Cornea and Pradeep Dubey and Richard Grisenthwaite and Sangwon Ha and Alexander Heinecke and Patrick Judd and John Kamalu and Naveen Mellempudi and Stuart Oberman and Mohammad Shoeybi and Michael Siu and Hao Wu

abstract:
FP8 is a natural progression for accelerating deep learning training inference beyond the 16-bit formats common in modern processors. In this paper we propose an 8-bit floating point (FP8) binary interchange format consisting of two encodings - E4M3 (4-bit exponent and 3-bit mantissa) and E5M2 (5-bit exponent and 2-bit mantissa). While E5M2 follows IEEE 754 conventions for representation of special values, E4M3's dynamic range is extended by not representing infinities and having only one mantissa bit-pattern for NaNs. We demonstrate the efficacy of the FP8 format on a variety of image and language tasks, effectively matching the result quality achieved by 16-bit training sessions. Our study covers the main modern neural network architectures - CNNs, RNNs, and Transformer-based models, leaving all the hyperparameters unchanged from the 16-bit baseline training sessions. Our training experiments include large, up to 175B parameter, language models. We also examine FP8 post-training-quantization of language models trained using 16-bit formats that resisted fixed point int8 quantization.

rawabstract:
FP8 is a natural progression for accelerating deep learning training inference beyond the 16-bit formats common in modern processors. In this paper we propose an 8-bit floating point (FP8) binary interchange format consisting of two encodings - E4M3 (4-bit exponent and 3-bit mantissa) and E5M2 (5-bit exponent and 2-bit mantissa). While E5M2 follows IEEE 754 conventions for representation of special values, E4M3's dynamic range is extended by not representing infinities and having only one mantissa bit-pattern for NaNs. We demonstrate the efficacy of the FP8 format on a variety of image and language tasks, effectively matching the result quality achieved by 16-bit training sessions. Our study covers the main modern neural network architectures - CNNs, RNNs, and Transformer-based models, leaving all the hyperparameters unchanged from the 16-bit baseline training sessions. Our training experiments include large, up to 175B parameter, language models. We also examine FP8 post-training-quantization of language models trained using 16-bit formats that resisted fixed point int8 quantization.

rawauthor:
Paulius Micikevicius and Dusan Stosic and Neil Burgess and Marius Cornea and Pradeep Dubey and Richard Grisenthwaite and Sangwon Ha and Alexander Heinecke and Patrick Judd and John Kamalu and Naveen Mellempudi and Stuart Oberman and Mohammad Shoeybi and Michael Siu and Hao Wu

entry:
@Article{Micikevicius:2022:FFD,
  author =       "Paulius Micikevicius and Dusan Stosic and Neil Burgess
                 and Marius Cornea and Pradeep Dubey and Richard
                 Grisenthwaite and Sangwon Ha and Alexander Heinecke and
                 Patrick Judd and John Kamalu and Naveen Mellempudi and
                 Stuart Oberman and Mohammad Shoeybi and Michael Siu and
                 Hao Wu",
  title =        "{FP8} Formats for Deep Learning",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--9",
  year =         "2022",
  bibdate =      "Wed Aug 7 16:23:07 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/2209.05433",
  abstract =     "FP8 is a natural progression for accelerating deep
                 learning training inference beyond the 16-bit formats
                 common in modern processors. In this paper we propose
                 an 8-bit floating point (FP8) binary interchange format
                 consisting of two encodings - E4M3 (4-bit exponent and
                 3-bit mantissa) and E5M2 (5-bit exponent and 2-bit
                 mantissa). While E5M2 follows IEEE 754 conventions for
                 representation of special values, E4M3's dynamic range
                 is extended by not representing infinities and having
                 only one mantissa bit-pattern for NaNs. We demonstrate
                 the efficacy of the FP8 format on a variety of image
                 and language tasks, effectively matching the result
                 quality achieved by 16-bit training sessions. Our study
                 covers the main modern neural network architectures -
                 CNNs, RNNs, and Transformer-based models, leaving all
                 the hyperparameters unchanged from the 16-bit baseline
                 training sessions. Our training experiments include
                 large, up to 175B parameter, language models. We also
                 examine FP8 post-training-quantization of language
                 models trained using 16-bit formats that resisted fixed
                 point int8 quantization.",
  acknowledgement = ack-nhfb,
  archiveprefix = "arXiv",
  eprint =       "2209.05433",
  primaryclass = "cs.LG",
}


bibtype: inproceedings
filename: fparith.bib
label: Monniaux:2022:FVB
author: David Monniaux and Alice Pain
title: Formally verified 32- and 64-bit integer division using double-precision floating-point arithmetic
crossref: IEEE:2022:ISC
pages: 128--132
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00032
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
URL: https://hal.science/hal-03722203/
keywords: ARITH 2022; ARITH-29
acknowledgement: ack-nhfb
rawauthor: David Monniaux and Alice Pain
rawtitle: Formally verified 32- and 64-bit integer division using double-precision floating-point arithmetic
abstract:
Some recent processors are not equipped with an integer division unit. Compilers then implement division by a call to a special function supplied by the processor designers, which implements division by a loop producing one bit of quotient per iteration. This hinders compiler optimizations and results in non-constant time computation, which is a problem in some applications. We advocate instead using the processor's floating-point unit, and propose code that the compiler can easily interleave with other computations. We fully proved the correctness of our algorithm, which mixes floating-point and fixed-bitwidth integer computations, using the Coq proof assistant and successfully integrated it into the CompCert formally verified compiler.

rawabstract:
Some recent processors are not equipped with an integer division unit. Compilers then implement division by a call to a special function supplied by the processor designers, which implements division by a loop producing one bit of quotient per iteration. This hinders compiler optimizations and results in non-constant time computation, which is a problem in some applications. We advocate instead using the processor's floating-point unit, and propose code that the compiler can easily interleave with other computations. We fully proved the correctness of our algorithm, which mixes floating-point and fixed-bitwidth integer computations, using the Coq proof assistant and successfully integrated it into the CompCert formally verified compiler.

entry:
@InProceedings{Monniaux:2022:FVB,
  author =       "David Monniaux and Alice Pain",
  title =        "Formally verified 32- and 64-bit integer division
                 using double-precision floating-point arithmetic",
  crossref =     "IEEE:2022:ISC",
  pages =        "128--132",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00032",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-03722203/",
  abstract =     "Some recent processors are not equipped with an
                 integer division unit. Compilers then implement
                 division by a call to a special function supplied by
                 the processor designers, which implements division by a
                 loop producing one bit of quotient per iteration. This
                 hinders compiler optimizations and results in
                 non-constant time computation, which is a problem in
                 some applications. We advocate instead using the
                 processor's floating-point unit, and propose code that
                 the compiler can easily interleave with other
                 computations. We fully proved the correctness of our
                 algorithm, which mixes floating-point and
                 fixed-bitwidth integer computations, using the Coq
                 proof assistant and successfully integrated it into the
                 CompCert formally verified compiler.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2022; ARITH-29",
}


bibtype: article
filename: fparith.bib
label: Montuschi:2022:CAC
author: Paolo Montuschi and Jean-Michel Muller and Florent de Dinechin
title: Computer Arithmetic: Continuing a Long and Steady Emergence
journal: j-COMPUTER
volume: 55
number: 10
pages: 4--6
month: oct
monthnumber: 10
year: 2022
CODEN: CPTRB4
DOI: https://doi.org/10.1109/MC.2022.3193206
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Thu Oct 27 08:20:29 2022
bibtimestamp: 2022.10.27 08:20:29 ???
fjournal: Computer
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: Paolo Montuschi and Jean-Michel Muller and Florent de Dinechin
rawtitle: Computer Arithmetic: Continuing a Long and Steady Emergence
bibsource:
https://www.math.utah.edu/pub/tex/bib/computer2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Montuschi:2022:CAC,
  author =       "Paolo Montuschi and Jean-Michel Muller and Florent de
                 Dinechin",
  title =        "Computer Arithmetic: Continuing a Long and Steady
                 Emergence",
  journal =      j-COMPUTER,
  volume =       "55",
  number =       "10",
  pages =        "4--6",
  month =        oct,
  year =         "2022",
  CODEN =        "CPTRB4",
  DOI =          "https://doi.org/10.1109/MC.2022.3193206",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Thu Oct 27 08:20:29 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computer2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
}


bibtype: article
filename: fparith.bib
label: Muller:2022:FDW
author: Jean-Michel Muller and Laurence Rideau
journal: j-TOMS
volume: 48
number: 1
pages: 9:1--9:24
month: mar
monthnumber: 3
year: 2022
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3484514
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Thu Feb 17 08:00:57 MST 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2022.02.17 08:00:57 MST
URL: https://dl.acm.org/doi/10.1145/3484514
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 9
journalURL: https://dl.acm.org/loi/toms
rawauthor: Jean-Michel Muller and Laurence Rideau
title:
Formalization of Double-Word Arithmetic, and Comments on ``Tight and Rigorous Error Bounds for Basic Building Blocks of Double-Word Arithmetic''

abstract:
Recently, a complete set of algorithms for manipulating double-word numbers (some classical, some new) was analyzed [16]. We have formally proven all the theorems given in that article, using the Coq proof assistant. The formal proof work led us to: (i) locate mistakes in some of the original paper proofs (mistakes that, however, do not hinder the validity of the algorithms), (ii) significantly improve some error bounds, and (iii) generalize some results by showing that they are still valid if we slightly change the rounding mode. The consequence is that the algorithms presented in [16] can be used with high confidence, and that some of them are even more accurate than what was believed before. This illustrates what formal proof can bring to computer arithmetic: beyond mere (yet extremely useful) verification, correction, and consolidation of already known results, it can help to find new properties. All our formal proofs are freely available.

rawabstract:
Recently, a complete set of algorithms for manipulating double-word numbers (some classical, some new) was analyzed [16]. We have formally proven all the theorems given in that article, using the Coq proof assistant. The formal proof work led us to: (i) locate mistakes in some of the original paper proofs (mistakes that, however, do not hinder the validity of the algorithms), (ii) significantly improve some error bounds, and (iii) generalize some results by showing that they are still valid if we slightly change the rounding mode. The consequence is that the algorithms presented in [16] can be used with high confidence, and that some of them are even more accurate than what was believed before. This illustrates what formal proof can bring to computer arithmetic: beyond mere (yet extremely useful) verification, correction, and consolidation of already known results, it can help to find new properties. All our formal proofs are freely available.

rawtitle:
Formalization of Double-Word Arithmetic, and Comments on {``Tight and Rigorous Error Bounds for Basic Building Blocks of Double-Word Arithmetic''}

entry:
@Article{Muller:2022:FDW,
  author =       "Jean-Michel Muller and Laurence Rideau",
  title =        "Formalization of Double-Word Arithmetic, and Comments
                 on {``Tight and Rigorous Error Bounds for Basic
                 Building Blocks of Double-Word Arithmetic''}",
  journal =      j-TOMS,
  volume =       "48",
  number =       "1",
  pages =        "9:1--9:24",
  month =        mar,
  year =         "2022",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3484514",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Thu Feb 17 08:00:57 MST 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3484514",
  abstract =     "Recently, a complete set of algorithms for
                 manipulating double-word numbers (some classical, some
                 new) was analyzed [16]. We have formally proven all the
                 theorems given in that article, using the Coq proof
                 assistant. The formal proof work led us to: (i) locate
                 mistakes in some of the original paper proofs (mistakes
                 that, however, do not hinder the validity of the
                 algorithms), (ii) significantly improve some error
                 bounds, and (iii) generalize some results by showing
                 that they are still valid if we slightly change the
                 rounding mode. The consequence is that the algorithms
                 presented in [16] can be used with high confidence, and
                 that some of them are even more accurate than what was
                 believed before. This illustrates what formal proof can
                 bring to computer arithmetic: beyond mere (yet
                 extremely useful) verification, correction, and
                 consolidation of already known results, it can help to
                 find new properties. All our formal proofs are freely
                 available.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2022:CDD
author: Raul Murillo and David Mallasen and Alberto A. Del Barrio and Guillermo Botella
title: Comparing Different Decodings for Posit Arithmetic
crossref: Gustafson:2022:NGA
pages: 84--99
year: 2022
DOI: https://doi.org/10.1007/978-3-031-09779-9_6
bibdate: Fri Dec 15 07:04:06 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:04:06 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Raul Murillo and David Mallas{\'e}n and Alberto A. {Del Barrio} and Guillermo Botella
rawtitle: Comparing Different Decodings for Posit Arithmetic
entry:
@InProceedings{Murillo:2022:CDD,
  author =       "Raul Murillo and David Mallas{\'e}n and Alberto A.
                 {Del Barrio} and Guillermo Botella",
  title =        "Comparing Different Decodings for Posit Arithmetic",
  crossref =     "Gustafson:2022:NGA",
  pages =        "84--99",
  year =         "2022",
  DOI =          "https://doi.org/10.1007/978-3-031-09779-9_6",
  bibdate =      "Fri Dec 15 07:04:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Murillo:2022:PPL
title: PLAM: a Posit Logarithm-Approximate Multiplier
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 4
pages: 2079--2085
month: oct
monthnumber: 10
year: 2022
DOI: https://doi.org/10.1109/TETC.2021.3109127
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawtitle: {PLAM}: a Posit Logarithm-Approximate Multiplier
author:
Raul Murillo and Alberto A. Del Barrio and Guillermo Botella and Min Soo Kim and HyunJin Kim and Nader Bagherzadeh

abstract:
The PositTM Number System was introduced in 2017 as a replacement for floating-point numbers. Since then, the community has explored its application in several areas, such as deep learning, and produced some unit designs which are still far from being competitive with their floating-point counterparts. This article proposes a Posit Logarithm-Approximate Multiplication (PLAM) scheme to significantly reduce the complexity of posit multipliers, one of the most power-hungry arithmetic units. The impact of this approach is evaluated in deep neural network inference, where there are no significant accuracy drops. Compared with state-of-the-art posit multipliers, experiments show that the proposed technique reduces the area, power, and delay of 32-bit hardware multipliers up to 72.86%, 81.79%, and 17.01%, respectively.

rawabstract:
The Posit{\TM} Number System was introduced in 2017 as a replacement for floating-point numbers. Since then, the community has explored its application in several areas, such as deep learning, and produced some unit designs which are still far from being competitive with their floating-point counterparts. This article proposes a Posit Logarithm-Approximate Multiplication (PLAM) scheme to significantly reduce the complexity of posit multipliers, one of the most power-hungry arithmetic units. The impact of this approach is evaluated in deep neural network inference, where there are no significant accuracy drops. Compared with state-of-the-art posit multipliers, experiments show that the proposed technique reduces the area, power, and delay of 32-bit hardware multipliers up to 72.86\%, 81.79\%, and 17.01\%, respectively.

rawauthor:
Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella and Min Soo Kim and HyunJin Kim and Nader Bagherzadeh

entry:
@Article{Murillo:2022:PPL,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella and Min Soo Kim and HyunJin Kim and Nader
                 Bagherzadeh",
  title =        "{PLAM}: a Posit Logarithm-Approximate Multiplier",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "4",
  pages =        "2079--2085",
  month =        oct # "\slash " # dec,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2021.3109127",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "The Posit{\TM} Number System was introduced in 2017 as
                 a replacement for floating-point numbers. Since then,
                 the community has explored its application in several
                 areas, such as deep learning, and produced some unit
                 designs which are still far from being competitive with
                 their floating-point counterparts. This article
                 proposes a Posit Logarithm-Approximate Multiplication
                 (PLAM) scheme to significantly reduce the complexity of
                 posit multipliers, one of the most power-hungry
                 arithmetic units. The impact of this approach is
                 evaluated in deep neural network inference, where there
                 are no significant accuracy drops. Compared with
                 state-of-the-art posit multipliers, experiments show
                 that the proposed technique reduces the area, power,
                 and delay of 32-bit hardware multipliers up to 72.86\%,
                 81.79\%, and 17.01\%, respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: article
filename: fparith.bib
label: Nath:2022:KVM
author: Kaushik Nath and Palash Sarkar
title: Kummer versus Montgomery Face-off over Prime Order Fields
journal: j-TOMS
volume: 48
number: 2
pages: 13:1--13:28
month: jun
monthnumber: 6
year: 2022
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3503536
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Jul 20 07:04:17 MDT 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2022.07.20 07:04:17 MDT
URL: https://dl.acm.org/doi/10.1145/3503536
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 13
journalURL: https://dl.acm.org/loi/toms
rawauthor: Kaushik Nath and Palash Sarkar
rawtitle: {Kummer} versus {Montgomery} Face-off over Prime Order Fields
abstract:
This paper makes a comprehensive comparison of the efficiencies of vectorized implementations of Kummer lines and Montgomery curves at various security levels. For the comparison, nine Kummer lines are considered, out of which eight are new, and new assembly implementations of all nine Kummer lines have been made. Seven previously proposed Montgomery curves are considered and new vectorized assembly implementations have been made for three of them. Our comparisons show that for all security levels, Kummer lines are consistently faster than Montgomery curves, though the speed-up gap is not much.

rawabstract:
This paper makes a comprehensive comparison of the efficiencies of vectorized implementations of Kummer lines and Montgomery curves at various security levels. For the comparison, nine Kummer lines are considered, out of which eight are new, and new assembly implementations of all nine Kummer lines have been made. Seven previously proposed Montgomery curves are considered and new vectorized assembly implementations have been made for three of them. Our comparisons show that for all security levels, Kummer lines are consistently faster than Montgomery curves, though the speed-up gap is not much.

entry:
@Article{Nath:2022:KVM,
  author =       "Kaushik Nath and Palash Sarkar",
  title =        "{Kummer} versus {Montgomery} Face-off over Prime Order
                 Fields",
  journal =      j-TOMS,
  volume =       "48",
  number =       "2",
  pages =        "13:1--13:28",
  month =        jun,
  year =         "2022",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3503536",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Jul 20 07:04:17 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3503536",
  abstract =     "This paper makes a comprehensive comparison of the
                 efficiencies of vectorized implementations of Kummer
                 lines and Montgomery curves at various security levels.
                 For the comparison, nine Kummer lines are considered,
                 out of which eight are new, and new assembly
                 implementations of all nine Kummer lines have been
                 made. Seven previously proposed Montgomery curves are
                 considered and new vectorized assembly implementations
                 have been made for three of them. Our comparisons show
                 that for all security levels, Kummer lines are
                 consistently faster than Montgomery curves, though the
                 speed-up gap is not much.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Nezhadi:2022:SFP
author: Ali Nezhadi and Shaahin Angizi and Arman Roohi
booktitle: 2022 21st IEEE International Conference on Machine Learning and Applications (ICMLA)
title: semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 837--842
year: 2022
DOI: https://doi.org/10.1109/ICMLA55696.2022.00139
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Ali Nezhadi and Shaahin Angizi and Arman Roohi
rawbooktitle: {2022 21st IEEE International Conference on Machine Learning and Applications (ICMLA)}
rawtitle: {semiMul}: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training
keywords:
Approximate Computing; Computer architecture; Costs; Deep learning; Graphics processing units; Machine Learning; Neural networks; Neural Networks; Power demand; Training

entry:
@InProceedings{Nezhadi:2022:SFP,
  author =       "Ali Nezhadi and Shaahin Angizi and Arman Roohi",
  booktitle =    "{2022 21st IEEE International Conference on Machine
                 Learning and Applications (ICMLA)}",
  title =        "{semiMul}: Floating-Point Free Implementations for
                 Efficient and Accurate Neural Network Training",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "837--842",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICMLA55696.2022.00139",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Approximate Computing; Computer architecture; Costs;
                 Deep learning; Graphics processing units; Machine
                 Learning; Neural networks; Neural Networks; Power
                 demand; Training",
}


bibtype: article
filename: fparith.bib
label: Noune:2022:BNF
author: B. Noune and P. Jones and D. Justus and D. Masters and C. Luschi
title: 8-bit numerical formats for deep neural networks
journal: arXiv.org
pages: 1--30
year: 2022
bibdate: Thu Nov 30 05:46:05 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.30 05:46:05 ???
URL: https://arxiv.org/abs/2206.02915
acknowledgement: ack-nhfb
rawauthor: B. Noune and P. Jones and D. Justus and D. Masters and C. Luschi
rawtitle: 8-bit numerical formats for deep neural networks
abstract:
Given the current trend of increasing size and complexity of machine learning architectures, it has become of critical importance to identify new approaches to improve the computational efficiency of model training. In this context, we address the advantages of floating-point over fixed-point representation, and present an in-depth study on the use of 8-bit floating-point number formats for activations, weights, and gradients for both training and inference. We explore the effect of different bit-widths for exponents and significands and different exponent biases. The experimental results demonstrate that a suitable choice of these low-precision formats enables faster training and reduced power consumption without any degradation in accuracy for a range of deep learning models for image classification and language processing.

rawabstract:
Given the current trend of increasing size and complexity of machine learning architectures, it has become of critical importance to identify new approaches to improve the computational efficiency of model training. In this context, we address the advantages of floating-point over fixed-point representation, and present an in-depth study on the use of 8-bit floating-point number formats for activations, weights, and gradients for both training and inference. We explore the effect of different bit-widths for exponents and significands and different exponent biases. The experimental results demonstrate that a suitable choice of these low-precision formats enables faster training and reduced power consumption without any degradation in accuracy for a range of deep learning models for image classification and language processing.

entry:
@Article{Noune:2022:BNF,
  author =       "B. Noune and P. Jones and D. Justus and D. Masters and
                 C. Luschi",
  title =        "8-bit numerical formats for deep neural networks",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--30",
  year =         "2022",
  bibdate =      "Thu Nov 30 05:46:05 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/2206.02915",
  abstract =     "Given the current trend of increasing size and
                 complexity of machine learning architectures, it has
                 become of critical importance to identify new
                 approaches to improve the computational efficiency of
                 model training. In this context, we address the
                 advantages of floating-point over fixed-point
                 representation, and present an in-depth study on the
                 use of 8-bit floating-point number formats for
                 activations, weights, and gradients for both training
                 and inference. We explore the effect of different
                 bit-widths for exponents and significands and different
                 exponent biases. The experimental results demonstrate
                 that a suitable choice of these low-precision formats
                 enables faster training and reduced power consumption
                 without any degradation in accuracy for a range of deep
                 learning models for image classification and language
                 processing.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Nunez-Yanez:2022:FAD
author: Jose Nunez-Yanez
title: Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite
journal: j-IEEE-MICRO
volume: 42
number: 6
pages: 55--66
month: nov
monthnumber: 11
year: 2022
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2022.3196705
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Thu Nov 03 05:37:10 2022
bibtimestamp: 2022.11.03 05:37:10 ???
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: Jose Nunez-Yanez
rawtitle: Fused Architecture for Dense and Sparse Matrix Processing in {TensorFlow Lite}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib

entry:
@Article{Nunez-Yanez:2022:FAD,
  author =       "Jose Nunez-Yanez",
  title =        "Fused Architecture for Dense and Sparse Matrix
                 Processing in {TensorFlow Lite}",
  journal =      j-IEEE-MICRO,
  volume =       "42",
  number =       "6",
  pages =        "55--66",
  month =        nov # "\slash " # dec,
  year =         "2022",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2022.3196705",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Nov 03 05:37:10 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: article
filename: fparith.bib
label: Oaks:2022:ZNM
author: Jeffrey Oaks
title: Zero and nothing in medieval Arabic arithmetic
journal: j-BRITISH-J-HIST-MATH
volume: 37
number: 3
pages: 179--211
year: 2022
DOI: https://doi.org/10.1080/26375451.2022.2115745
ISSN: 1749-8430 (print), 1749-8341 (electronic) OR 17498430 (print), 17498341 (electronic)
ISSNL: 1749-8341 OR 17498341
bibdate: Tue Feb 28 07:20:03 MST 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/bshm.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.02.28 07:20:03 MST
URL: http://www.tandfonline.com/doi/full/10.1080/26375451.2022.2115745
fjournal: BSHM Bulletin: Journal of the British Society for the History of Mathematics
acknowledgement: ack-nhfb
ajournal: BSHM Bull.
journalURL: http://www.tandfonline.com/loi/tbsh20
onlinedate: 25 Sep 2022
rawauthor: Jeffrey Oaks
rawtitle: Zero and nothing in medieval {Arabic} arithmetic
abstract:
Whether explaining calculations with decimal or sexagesimal notation, arithmetic books composed in Arabic beginning in the ninth century CE consistently describe the zero (sifr) as a sign indicating an empty place where there is no number. And yet we find that some arithmeticians explicitly performed operations on this zero. To understand how the zero was conceived and manipulated in medieval Arabic texts we first address the way that numbers themselves were conceived and how `nothing' entered into arithmetical problem-solving. From there we examine arithmetic books for their treatment of zero. We find that there is no inconsistency in operating on what is literally nothing, and thus there was no motive for arithmeticians to regard zero as a number.

rawabstract:
Whether explaining calculations with decimal or sexagesimal notation, arithmetic books composed in Arabic beginning in the ninth century CE consistently describe the zero ({\d{s}}ifr) as a sign indicating an empty place where there is no number. And yet we find that some arithmeticians explicitly performed operations on this zero. To understand how the zero was conceived and manipulated in medieval Arabic texts we first address the way that numbers themselves were conceived and how `nothing' entered into arithmetical problem-solving. From there we examine arithmetic books for their treatment of zero. We find that there is no inconsistency in operating on what is literally nothing, and thus there was no motive for arithmeticians to regard zero as a number.

entry:
@Article{Oaks:2022:ZNM,
  author =       "Jeffrey Oaks",
  title =        "Zero and nothing in medieval {Arabic} arithmetic",
  journal =      j-BRITISH-J-HIST-MATH,
  volume =       "37",
  number =       "3",
  pages =        "179--211",
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1080/26375451.2022.2115745",
  ISSN =         "1749-8430 (print), 1749-8341 (electronic)",
  ISSN-L =       "1749-8341",
  bibdate =      "Tue Feb 28 07:20:03 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bshm.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.tandfonline.com/doi/full/10.1080/26375451.2022.2115745",
  abstract =     "Whether explaining calculations with decimal or
                 sexagesimal notation, arithmetic books composed in
                 Arabic beginning in the ninth century CE consistently
                 describe the zero ({\d{s}}ifr) as a sign indicating an
                 empty place where there is no number. And yet we find
                 that some arithmeticians explicitly performed
                 operations on this zero. To understand how the zero was
                 conceived and manipulated in medieval Arabic texts we
                 first address the way that numbers themselves were
                 conceived and how `nothing' entered into arithmetical
                 problem-solving. From there we examine arithmetic books
                 for their treatment of zero. We find that there is no
                 inconsistency in operating on what is literally
                 nothing, and thus there was no motive for
                 arithmeticians to regard zero as a number.",
  acknowledgement = ack-nhfb,
  ajournal =     "BSHM Bull.",
  fjournal =     "BSHM Bulletin: Journal of the British Society for the
                 History of Mathematics",
  journal-URL =  "http://www.tandfonline.com/loi/tbsh20",
  onlinedate =   "25 Sep 2022",
}


bibtype: article
filename: fparith.bib
label: Oberman:2022:GES
author: Stuart Oberman and Leonel Sousa and Bogdan Pasca and Alberto Nannarelli
title: Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 3
pages: 1239--1240
month: jul
monthnumber: 7
year: 2022
DOI: https://doi.org/10.1109/TETC.2022.3195414
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Stuart Oberman and Leonel Sousa and Bogdan Pasca and Alberto Nannarelli
rawtitle: Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic
entry:
@Article{Oberman:2022:GES,
  author =       "Stuart Oberman and Leonel Sousa and Bogdan Pasca and
                 Alberto Nannarelli",
  title =        "Guest Editorial: Special Section on Emerging and
                 Impacting Trends on Computer Arithmetic",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "3",
  pages =        "1239--1240",
  month =        jul # "\slash " # sep,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2022.3195414",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:2022:EPA
author: Hyun Woo Oh and Won Sik Jeong and Seung Eun Lee
editor: IEEE
booktitle: 2022 19th International SoC Design Conference (ISOCC)
title: Evaluation of Posit Arithmetic on Machine Learning based on Approximate Exponential Functions
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 358--359
year: 2022
DOI: https://doi.org/10.1109/ISOCC56007.2022.10031524
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Hyun Woo Oh and Won Sik Jeong and Seung Eun Lee
rawbooktitle: {2022 19th International SoC Design Conference (ISOCC)}
raweditor: {IEEE}
rawtitle: Evaluation of Posit Arithmetic on Machine Learning based on Approximate Exponential Functions
entry:
@InProceedings{Oh:2022:EPA,
  author =       "Hyun Woo Oh and Won Sik Jeong and Seung Eun Lee",
  editor =       "{IEEE}",
  booktitle =    "{2022 19th International SoC Design Conference
                 (ISOCC)}",
  title =        "Evaluation of Posit Arithmetic on Machine Learning
                 based on Approximate Exponential Functions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "358--359",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISOCC56007.2022.10031524",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ollivier:2022:PRB
journal: j-IEEE-MICRO
volume: 42
number: 6
pages: 9--16
month: nov
monthnumber: 11
year: 2022
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2022.3195761
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Thu Nov 03 05:37:10 2022
bibtimestamp: 2022.11.03 05:37:10 ???
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
author:
Sebastien Ollivier and Xinyi Zhang and Yue Tang and Chayanika Choudhuri and Jingtong Hu and Alex K. Jones

title:
Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib

rawauthor:
S{\'e}bastien Ollivier and Xinyi Zhang and Yue Tang and Chayanika Choudhuri and Jingtong Hu and Alex K. Jones

rawtitle:
Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge

entry:
@Article{Ollivier:2022:PRB,
  author =       "S{\'e}bastien Ollivier and Xinyi Zhang and Yue Tang
                 and Chayanika Choudhuri and Jingtong Hu and Alex K.
                 Jones",
  title =        "Pod-racing: bulk-bitwise to floating-point compute in
                 racetrack memory for machine learning at the edge",
  journal =      j-IEEE-MICRO,
  volume =       "42",
  number =       "6",
  pages =        "9--16",
  month =        nov # "\slash " # dec,
  year =         "2022",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2022.3195761",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Nov 03 05:37:10 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: inproceedings
filename: fparith.bib
label: Omtzigt:2022:URR
author: E. Theodore L. Omtzigt and James Quinlan
title: Universal: Reliable, Reproducible, and Energy-Efficient Numerics
crossref: Gustafson:2022:NGA
pages: 100--116
year: 2022
DOI: https://doi.org/10.1007/978-3-031-09779-9_7
bibdate: Fri Dec 15 07:04:06 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:04:06 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: E. Theodore L. Omtzigt and James Quinlan
rawtitle: Universal: Reliable, Reproducible, and Energy-Efficient Numerics
entry:
@InProceedings{Omtzigt:2022:URR,
  author =       "E. Theodore L. Omtzigt and James Quinlan",
  title =        "Universal: Reliable, Reproducible, and
                 Energy-Efficient Numerics",
  crossref =     "Gustafson:2022:NGA",
  pages =        "100--116",
  year =         "2022",
  DOI =          "https://doi.org/10.1007/978-3-031-09779-9_7",
  bibdate =      "Fri Dec 15 07:04:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Osorio:2022:BFA
author: John Osorio and Adria Armejach and Eric Petit and Greg Henry and Marc Casas
title: A BF16 FMA is All You Need for DNN Training
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 3
pages: 1302--1314
year: 2022
DOI: https://doi.org/10.1109/TETC.2022.3187770
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: John Osorio and Adri{\`a} Armejach and Eric Petit and Greg Henry and Marc Casas
rawtitle: A {BF16 FMA} is All You Need for {DNN} Training
keywords:
Arithmetic; BF16; Compounds; Computational modeling; computer arithmetic; emulation; FMA Operators; FP32; Hardware; hardware; machine learning; Neural nets; Proposals; reduced precision; Silicon; swamping; Training

entry:
@Article{Osorio:2022:BFA,
  author =       "John Osorio and Adri{\`a} Armejach and Eric Petit and
                 Greg Henry and Marc Casas",
  title =        "A {BF16 FMA} is All You Need for {DNN} Training",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "3",
  pages =        "1302--1314",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2022.3187770",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
  keywords =     "Arithmetic; BF16; Compounds; Computational modeling;
                 computer arithmetic; emulation; FMA Operators; FP32;
                 Hardware; hardware; machine learning; Neural nets;
                 Proposals; reduced precision; Silicon; swamping;
                 Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Osorio:2022:FFA
author: John Osorio and Adria Armejach and Eric Petit and Greg Henry and Marc Casas
booktitle: 2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
title: FASE: a Fast, Accurate and Seamless Emulator for Custom Numerical Formats
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 144--146
year: 2022
DOI: https://doi.org/10.1109/ISPASS55109.2022.00017
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: John Osorio and Adri{\`a} Armejach and Eric Petit and Greg Henry and Marc Casas
rawbooktitle: {2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}
rawtitle: {FASE}: a Fast, Accurate and Seamless Emulator for Custom Numerical Formats
keywords:
BFloat16; Binary Analysis Tool; Codes; Deep learning; DNN; Emulation; FASE (FAST, ACCURATE, AND SEAMLESS EMULATOR); FP32; LOW PRECISION; NEURAL NETWORKS; POWER DEMAND; SOFTWARE; TRAINING

entry:
@InProceedings{Osorio:2022:FFA,
  author =       "John Osorio and Adri{\`a} Armejach and Eric Petit and
                 Greg Henry and Marc Casas",
  booktitle =    "{2022 IEEE International Symposium on Performance
                 Analysis of Systems and Software (ISPASS)}",
  title =        "{FASE}: a Fast, Accurate and Seamless Emulator for
                 Custom Numerical Formats",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "144--146",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISPASS55109.2022.00017",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "BFloat16; Binary Analysis Tool; Codes; Deep learning;
                 DNN; Emulation; FASE (FAST, ACCURATE, AND SEAMLESS
                 EMULATOR); FP32; LOW PRECISION; NEURAL NETWORKS; POWER
                 DEMAND; SOFTWARE; TRAINING",
}


bibtype: article
filename: fparith.bib
label: Park:2022:NNT
author: Jeongwoo Park and Sunwoo Lee and Dongsuk Jeon
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 57
number: 3
pages: 965--977
year: 2022
CODEN: IJSCBC
DOI: https://doi.org/10.1109/JSSC.2021.3103603
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawauthor: Jeongwoo Park and Sunwoo Lee and Dongsuk Jeon
title:
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees

keywords:
Computational efficiency; Computational modeling; Degradation; digital integrated circuits; Hardware; learning systems; neural network accelerators; Neural networks; Task analysis; Tensors; Training; very large-scale integration

rawtitle:
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees

entry:
@Article{Park:2022:NNT,
  author =       "Jeongwoo Park and Sunwoo Lee and Dongsuk Jeon",
  title =        "A Neural Network Training Processor With 8-Bit Shared
                 Exponent Bias Floating Point and Multiple-Way Fused
                 Multiply-Add Trees",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "57",
  number =       "3",
  pages =        "965--977",
  year =         "2022",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2021.3103603",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "Computational efficiency; Computational modeling;
                 Degradation; digital integrated circuits; Hardware;
                 learning systems; neural network accelerators; Neural
                 networks; Task analysis; Tensors; Training; very
                 large-scale integration",
}


bibtype: article
filename: fparith.bib
label: Park:2022:RCR
author: Kangkyu Park and Seungkyu Choi and Yeongjae Choi and Lee-Sup Kim
journal: j-IEEE-TRANS-COMPUT
volume: 71
number: 4
pages: 795--808
month: apr
monthnumber: 4
year: 2022
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2021.3063269
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Mar 17 06:38:17 2022
bibtimestamp: 2022.03.17 06:38:17 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Kangkyu Park and Seungkyu Choi and Yeongjae Choi and Lee-Sup Kim
title:
Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks

rawtitle:
Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks

entry:
@Article{Park:2022:RCR,
  author =       "Kangkyu Park and Seungkyu Choi and Yeongjae Choi and
                 Lee-Sup Kim",
  title =        "Rare Computing: Removing Redundant Multiplications
                 From Sparse and Repetitive Data in Deep Neural
                 Networks",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "4",
  pages =        "795--808",
  month =        apr,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2021.3063269",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Mar 17 06:38:17 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Patel:2022:LPG
author: Pragnesh Patel and Aman Arora and Earl Swartzlander and Lizy John
booktitle: 2022 23rd International Symposium on Quality Electronic Design (ISQED)
title: LogGen: a Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--7
year: 2022
DOI: https://doi.org/10.1109/ISQED54688.2022.9806139
bibdate: Wed Oct 1 06:40:18 2025
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Pragnesh Patel and Aman Arora and Earl Swartzlander and Lizy John
rawbooktitle: {2022 23rd International Symposium on Quality Electronic Design (ISQED)}
rawtitle: {LogGen}: a Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning
keywords:
ASIC; Deep learning; Deep Learning Hardware; Delays; Digital signal processing; Floating-point Arithmetic; FPGA; Generator; Generators; Logarithm; Measurement; Memory management; Pipelines; Tools

entry:
@InProceedings{Patel:2022:LPG,
  author =       "Pragnesh Patel and Aman Arora and Earl Swartzlander
                 and Lizy John",
  booktitle =    "{2022 23rd International Symposium on Quality
                 Electronic Design (ISQED)}",
  title =        "{LogGen}: a Parameterized Generator for Designing
                 Floating-Point Logarithm Units for Deep Learning",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISQED54688.2022.9806139",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ASIC; Deep learning; Deep Learning Hardware; Delays;
                 Digital signal processing; Floating-point Arithmetic;
                 FPGA; Generator; Generators; Logarithm; Measurement;
                 Memory management; Pipelines; Tools",
}


bibtype: article
filename: fparith.bib
label: Peng:2022:DNN
title: A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System
journal: j-JETC
volume: 18
number: 4
pages: 81:1--81:??
month: oct
monthnumber: 10
year: 2022
DOI: https://doi.org/10.1145/3550273
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Sat Oct 29 07:30:43 MDT 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jetc.bib
bibtimestamp: 2022.10.29 07:30:43 MDT
URL: https://dl.acm.org/doi/10.1145/3550273
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
acknowledgement: ack-nhfb
articleno: 81
journalURL: https://dl.acm.org/loi/jetc
rawtitle: A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System
author:
Jiaxin Peng and Yousra Alkabani and Krunal Puri and Xiaoxuan Ma and Volker Sorger and Tarek El-Ghazawi

abstract:
The acceleration of Deep Neural Networks (DNNs) has attracted much attention in research. Many critical real-time applications benefit from DNN accelerators but are limited by their compute-intensive nature. This work introduces an accelerator for ldots 

rawabstract:
The acceleration of Deep Neural Networks (DNNs) has attracted much attention in research. Many critical real-time applications benefit from DNN accelerators but are limited by their compute-intensive nature. This work introduces an accelerator for \ldots{}

rawauthor:
Jiaxin Peng and Yousra Alkabani and Krunal Puri and Xiaoxuan Ma and Volker Sorger and Tarek El-Ghazawi

entry:
@Article{Peng:2022:DNN,
  author =       "Jiaxin Peng and Yousra Alkabani and Krunal Puri and
                 Xiaoxuan Ma and Volker Sorger and Tarek El-Ghazawi",
  title =        "A Deep Neural Network Accelerator using Residue
                 Arithmetic in a Hybrid Optoelectronic System",
  journal =      j-JETC,
  volume =       "18",
  number =       "4",
  pages =        "81:1--81:??",
  month =        oct,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3550273",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Oct 29 07:30:43 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3550273",
  abstract =     "The acceleration of Deep Neural Networks (DNNs) has
                 attracted much attention in research. Many critical
                 real-time applications benefit from DNN accelerators
                 but are limited by their compute-intensive nature. This
                 work introduces an accelerator for \ldots{}",
  acknowledgement = ack-nhfb,
  articleno =    "81",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "https://dl.acm.org/loi/jetc",
}


bibtype: inproceedings
filename: fparith.bib
label: Puntsri:2022:RAG
title: Reconfigurable AWGN Generator Using Box--Muller Method with CORDIC-based Square Root Calculation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2022
DOI: https://doi.org/10.1109/ITC-CSCC55581.2022.9894924
bibdate: Mon Oct 27 10:32:44 2025
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
author:
Kidsananapong Puntsri and Bussakorn Bunsri and Yaowarat Pittayang and Tanatip Bubpawan and Wuttichai Partipralam and Watid Phakphisut

booktitle:
2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)

keywords:
Box--Muller Method; CODIC method; Gaussian Noise Generator; Generators; Noise generators; Parity check codes; Polar codes; Real-time systems; Registers; Table lookup

rawauthor:
Kidsananapong Puntsri and Bussakorn Bunsri and Yaowarat Pittayang and Tanatip Bubpawan and Wuttichai Partipralam and Watid Phakphisut

rawbooktitle:
{2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)}

rawtitle:
Reconfigurable {AWGN} Generator Using {Box--Muller} Method with {CORDIC}-based Square Root Calculation

entry:
@InProceedings{Puntsri:2022:RAG,
  author =       "Kidsananapong Puntsri and Bussakorn Bunsri and
                 Yaowarat Pittayang and Tanatip Bubpawan and Wuttichai
                 Partipralam and Watid Phakphisut",
  booktitle =    "{2022 37th International Technical Conference on
                 Circuits/Systems, Computers and Communications
                 (ITC-CSCC)}",
  title =        "Reconfigurable {AWGN} Generator Using {Box--Muller}
                 Method with {CORDIC}-based Square Root Calculation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ITC-CSCC55581.2022.9894924",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Box--Muller Method; CODIC method; Gaussian Noise
                 Generator; Generators; Noise generators; Parity check
                 codes; Polar codes; Real-time systems; Registers; Table
                 lookup",
}


bibtype: techreport
filename: fparith.bib
label: PWG:2022:SPA
author: Posit Working Group
title: Standard for PositTM Arithmetic (2022)
type: Report
institution: National Supercomputing Centre (NSCC)
address: Singapore
pages: 12
day: 2
month: mar
monthnumber: 3
year: 2022
bibdate: Fri Dec 15 11:16:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:16:55 ???
URL: https://posithub.org/docs/posit_standard-2.pdf
acknowledgement: ack-nhfb
rawauthor: {Posit Working Group}
rawtitle: Standard for Posit{\TM} Arithmetic (2022)
entry:
@TechReport{PWG:2022:SPA,
  author =       "{Posit Working Group}",
  title =        "Standard for Posit{\TM} Arithmetic (2022)",
  type =         "Report",
  institution =  "National Supercomputing Centre (NSCC)",
  address =      "Singapore",
  pages =        "12",
  day =          "2",
  month =        mar,
  year =         "2022",
  bibdate =      "Fri Dec 15 11:16:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://posithub.org/docs/posit_standard-2.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Ramachandran:2022:PCP
author: Akshat Ramachandran and John Gustafson and Anusua Roy and Rizwan Ahmed Ansari and Rohin Daruwala
editor: IEEE
booktitle: 2022 25th Euromicro Conference on Digital System Design (DSD)
title: PositIV: a Configurable Posit Processor Architecture for Image and Video Processing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 93--100
year: 2022
DOI: https://doi.org/10.1109/DSD57027.2022.00022
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Akshat Ramachandran and John Gustafson and Anusua Roy and Rizwan Ahmed Ansari and Rohin Daruwala
rawbooktitle: {2022 25th Euromicro Conference on Digital System Design (DSD)}
raweditor: {IEEE}
rawtitle: {PositIV}: a Configurable Posit Processor Architecture for Image and Video Processing
entry:
@InProceedings{Ramachandran:2022:PCP,
  author =       "Akshat Ramachandran and John Gustafson and Anusua Roy
                 and Rizwan Ahmed Ansari and Rohin Daruwala",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{PositIV}: a Configurable Posit Processor Architecture
                 for Image and Video Processing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "93--100",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00022",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Roy:2022:AAC
author: Avishek Sinha Roy and Hardik Agrawal and Anindya Sundar Dhar
title: ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 4
pages: 2072--2078
month: oct
monthnumber: 10
year: 2022
DOI: https://doi.org/10.1109/TETC.2021.3107509
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Avishek Sinha Roy and Hardik Agrawal and Anindya Sundar Dhar
rawtitle: {ACBAM}-Accuracy-Configurable Sign Inclusive Broken Array {Booth} Multiplier Design
entry:
@Article{Roy:2022:AAC,
  author =       "Avishek Sinha Roy and Hardik Agrawal and Anindya
                 Sundar Dhar",
  title =        "{ACBAM}-Accuracy-Configurable Sign Inclusive Broken
                 Array {Booth} Multiplier Design",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "4",
  pages =        "2072--2078",
  month =        oct # "\slash " # dec,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2021.3107509",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Russinoff:2022:FVC
crossref: IEEE:2022:ISC
pages: 120--126
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00030
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
keywords: ARITH 2022; ARITH-29
acknowledgement: ack-nhfb
author:
David Russinoff and Javier Bruguera and Cuong Chau and Mayank Manjrekar and Nicholas Pfister and Harsha Valsaraju

title:
Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking

rawauthor:
David Russinoff and Javier Bruguera and Cuong Chau and Mayank Manjrekar and Nicholas Pfister and Harsha Valsaraju

rawtitle:
Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking

entry:
@InProceedings{Russinoff:2022:FVC,
  author =       "David Russinoff and Javier Bruguera and Cuong Chau and
                 Mayank Manjrekar and Nicholas Pfister and Harsha
                 Valsaraju",
  title =        "Formal Verification of a Chained Multiply-Add Design:
                 Combining Theorem Proving and Equivalence Checking",
  crossref =     "IEEE:2022:ISC",
  pages =        "120--126",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00030",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2022; ARITH-29",
}


bibtype: inproceedings
filename: fparith.bib
label: S:2022:IRP
author: Sathyavathi N S and Augusta Sophy Beulet P
editor: IEEE
title: Implementation of Regime-5 Posit adder
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1040--1043
year: 2022
DOI: https://doi.org/10.1109/ICICICT54557.2022.9917949
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Sathyavathi N S and Augusta Sophy Beulet P
raweditor: {IEEE}
rawtitle: Implementation of {Regime-5} Posit adder
booktitle:
2022 Third International Conference on Intelligent Computing Instrumentation and Control Technologies (ICICICT)

rawbooktitle:
{2022 Third International Conference on Intelligent Computing Instrumentation and Control Technologies (ICICICT)}

entry:
@InProceedings{S:2022:IRP,
  author =       "Sathyavathi N S and Augusta Sophy Beulet P",
  editor =       "{IEEE}",
  booktitle =    "{2022 Third International Conference on Intelligent
                 Computing Instrumentation and Control Technologies
                 (ICICICT)}",
  title =        "Implementation of {Regime-5} Posit adder",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1040--1043",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICICICT54557.2022.9917949",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sadeghimanesh:2022:SSN
author: AmirHosein Sadeghimanesh and Matthew England
title: An SMT solver for non-linear real arithmetic inside Maple
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 56
number: 2
pages: 76--79
month: jun
monthnumber: 6
year: 2022
DOI: https://doi.org/10.1145/3572867.3572880
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Mon Aug 21 16:58:02 MDT 2023
bibtimestamp: 2023.08.21 16:58:02 MDT
URL: https://dl.acm.org/doi/10.1145/3572867.3572880
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
ajournal: ACM Commun. Computer Algebr.
journalURL: https://dl.acm.org/loi/sigsam-cca
rawauthor: AmirHosein Sadeghimanesh and Matthew England
rawtitle: An {SMT} solver for non-linear real arithmetic inside {Maple}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/maple-extract.bib; https://www.math.utah.edu/pub/tex/bib/sigsam.bib

abstract:
We report on work-in-progress to create an SMT-solver inside Maple for non-linear real arithmetic (NRA). We give background information on the algorithm being implemented: cylindrical algebraic coverings as a theory solver in the lazy SMT paradigm. We then present some new work on the identification of minimal conflicting cores from the coverings.

rawabstract:
We report on work-in-progress to create an SMT-solver inside Maple for non-linear real arithmetic (NRA). We give background information on the algorithm being implemented: cylindrical algebraic coverings as a theory solver in the lazy SMT paradigm. We then present some new work on the identification of minimal conflicting cores from the coverings.

entry:
@Article{Sadeghimanesh:2022:SSN,
  author =       "AmirHosein Sadeghimanesh and Matthew England",
  title =        "An {SMT} solver for non-linear real arithmetic inside
                 {Maple}",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "56",
  number =       "2",
  pages =        "76--79",
  month =        jun,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3572867.3572880",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Mon Aug 21 16:58:02 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/maple-extract.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3572867.3572880",
  abstract =     "We report on work-in-progress to create an SMT-solver
                 inside Maple for non-linear real arithmetic (NRA). We
                 give background information on the algorithm being
                 implemented: cylindrical algebraic coverings as a
                 theory solver in the lazy SMT paradigm. We then present
                 some new work on the identification of minimal
                 conflicting cores from the coverings.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Commun. Computer Algebr.",
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "https://dl.acm.org/loi/sigsam-cca",
}


bibtype: inproceedings
filename: fparith.bib
label: Safieh:2022:ERA
author: Malek Safieh and Fabrizio De Santis
title: Efficient Reduction Algorithms for Special Gaussian Integer Moduli
crossref: IEEE:2022:ISC
pages: 111--119
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00029
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
keywords: ARITH 2022; ARITH-29
acknowledgement: ack-nhfb
rawauthor: Malek Safieh and Fabrizio {De Santis}
rawtitle: Efficient Reduction Algorithms for Special {Gaussian} Integer Moduli
entry:
@InProceedings{Safieh:2022:ERA,
  author =       "Malek Safieh and Fabrizio {De Santis}",
  title =        "Efficient Reduction Algorithms for Special {Gaussian}
                 Integer Moduli",
  crossref =     "IEEE:2022:ISC",
  pages =        "111--119",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00029",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2022; ARITH-29",
}


bibtype: article
filename: fparith.bib
label: Schober:2022:HAM
author: Peter Schober and M. Hassan Najafi and Nima TaheriNejad
title: High-Accuracy Multiply-Accumulate (MAC) Technique for Unary Stochastic Computing
journal: j-IEEE-TRANS-COMPUT
volume: 71
number: 6
pages: 1425--1439
month: jun
monthnumber: 6
year: 2022
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2021.3087027
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed May 25 09:41:19 2022
bibtimestamp: 2022.05.25 09:41:19 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter Schober and M. Hassan Najafi and Nima TaheriNejad
rawtitle: High-Accuracy Multiply-Accumulate ({MAC}) Technique for Unary Stochastic Computing
entry:
@Article{Schober:2022:HAM,
  author =       "Peter Schober and M. Hassan Najafi and Nima
                 TaheriNejad",
  title =        "High-Accuracy Multiply-Accumulate ({MAC}) Technique
                 for Unary Stochastic Computing",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "6",
  pages =        "1425--1439",
  month =        jun,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2021.3087027",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed May 25 09:41:19 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Seidel:2022:EFP
title: Efficient Floating Point Arithmetic for Quantum Computers
journal: j-IEEE-ACCESS
volume: 10
pages: 72400--72415
year: 2022
DOI: https://doi.org/10.1109/ACCESS.2022.3188251
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawtitle: Efficient Floating Point Arithmetic for Quantum Computers
author:
Raphael Seidel and Nikolay Tcholtchev and Sebastian Bock and Colin Kai-Uwe Becker and Manfred Hauswirth

keywords:
Adders; Arithmetic; Computers; floating point arithmetic; Logic gates; Quantum arithmetic; quantum computing; Quantum computing; Qubit; Registers

rawauthor:
Raphael Seidel and Nikolay Tcholtchev and Sebastian Bock and Colin Kai-Uwe Becker and Manfred Hauswirth

entry:
@Article{Seidel:2022:EFP,
  author =       "Raphael Seidel and Nikolay Tcholtchev and Sebastian
                 Bock and Colin Kai-Uwe Becker and Manfred Hauswirth",
  title =        "Efficient Floating Point Arithmetic for Quantum
                 Computers",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  pages =        "72400--72415",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3188251",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Adders; Arithmetic; Computers; floating point
                 arithmetic; Logic gates; Quantum arithmetic; quantum
                 computing; Quantum computing; Qubit; Registers",
}


bibtype: article
filename: fparith.bib
label: Shah:2022:DDP
title: DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 57
number: 8
pages: 2586--2596
year: 2022
CODEN: IJSCBC
DOI: https://doi.org/10.1109/JSSC.2021.3134897
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: {DPU}: {DAG} Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm
author:
Nimish Shah and Laura Isabel Galindez Olascoaga and Shirui Zhao and Wannes Meert and Marian Verhelst

entry:
@Article{Shah:2022:DDP,
  author =       "Nimish Shah and Laura Isabel Galindez Olascoaga and
                 Shirui Zhao and Wannes Meert and Marian Verhelst",
  title =        "{DPU}: {DAG} Processing Unit for Irregular Graphs With
                 Precision-Scalable Posit Arithmetic in 28 nm",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "57",
  number =       "8",
  pages =        "2586--2596",
  year =         "2022",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2021.3134897",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}


bibtype: inproceedings
filename: fparith.bib
label: Sibidanov:2022:CMP
author: Alexei Sibidanov and Paul Zimmermann and Stephane Glondu
title: The CORE-MATH Project
crossref: IEEE:2022:ISC
pages: 26--34
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00014
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
keywords: ARITH-29; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Alexei Sibidanov and Paul Zimmermann and St{\'e}phane Glondu
rawtitle: The {CORE-MATH} Project
abstract:
The CORE-MATH project aims at providing open-source mathematical functions with correct rounding that can be integrated into current mathematical libraries. This article demonstrates the CORE-MATH methodology on two functions: the binary32 power function (powf) and the binary64 cube root function (cbrt). CORE-MATH already provides a full set of correctly rounded C99 functions for single precision (binary32). These functions provide similar or in some cases up to threefold speedups with respect to the GNU libc mathematic library, which is not correctly rounded. This work offers a prospect of the mandatory requirement of correct rounding for mathematical functions in the next revision of the IEEE-754 standard.

rawabstract:
The CORE-MATH project aims at providing open-source mathematical functions with correct rounding that can be integrated into current mathematical libraries. This article demonstrates the CORE-MATH methodology on two functions: the binary32 power function (powf) and the binary64 cube root function (cbrt). CORE-MATH already provides a full set of correctly rounded C99 functions for single precision (binary32). These functions provide similar or in some cases up to threefold speedups with respect to the GNU libc mathematic library, which is not correctly rounded. This work offers a prospect of the mandatory requirement of correct rounding for mathematical functions in the next revision of the IEEE-754 standard.

entry:
@InProceedings{Sibidanov:2022:CMP,
  author =       "Alexei Sibidanov and Paul Zimmermann and St{\'e}phane
                 Glondu",
  title =        "The {CORE-MATH} Project",
  crossref =     "IEEE:2022:ISC",
  pages =        "26--34",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00014",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The CORE-MATH project aims at providing open-source
                 mathematical functions with correct rounding that can
                 be integrated into current mathematical libraries. This
                 article demonstrates the CORE-MATH methodology on two
                 functions: the binary32 power function (powf) and the
                 binary64 cube root function (cbrt). CORE-MATH already
                 provides a full set of correctly rounded C99 functions
                 for single precision (binary32). These functions
                 provide similar or in some cases up to threefold
                 speedups with respect to the GNU libc mathematic
                 library, which is not correctly rounded. This work
                 offers a prospect of the mandatory requirement of
                 correct rounding for mathematical functions in the next
                 revision of the IEEE-754 standard.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-29; correct rounding; floating-point
                 arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Siddamshetty:2022:EHA
author: Susheel Ujwal Siddamshetty and Srinivas Boppu and Debapratim Ghosh
editor: IEEE
booktitle: 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
title: Efficient Hardware Architecture for Posit Addition / Subtraction
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 387--394
year: 2022
DOI: https://doi.org/10.1109/MCSoC57363.2022.00068
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Susheel Ujwal Siddamshetty and Srinivas Boppu and Debapratim Ghosh
rawbooktitle: {2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)}
raweditor: {IEEE}
rawtitle: Efficient Hardware Architecture for Posit Addition\slash Subtraction
entry:
@InProceedings{Siddamshetty:2022:EHA,
  author =       "Susheel Ujwal Siddamshetty and Srinivas Boppu and
                 Debapratim Ghosh",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 15th International Symposium on Embedded
                 Multicore/Many-core Systems-on-Chip (MCSoC)}",
  title =        "Efficient Hardware Architecture for Posit
                 Addition\slash Subtraction",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "387--394",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MCSoC57363.2022.00068",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Sohn:2022:EFP
author: Jongwook Sohn and David K. Dean and Eric Quintana and Wing Shek Wong
title: Enhanced Floating-Point Adder with Full Denormal Support
crossref: IEEE:2022:ISC
pages: 01--08
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00015
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
keywords: ARITH 2022; ARITH-29
acknowledgement: ack-nhfb
rawauthor: Jongwook Sohn and David K. Dean and Eric Quintana and Wing Shek Wong
rawtitle: Enhanced Floating-Point Adder with Full Denormal Support
entry:
@InProceedings{Sohn:2022:EFP,
  author =       "Jongwook Sohn and David K. Dean and Eric Quintana and
                 Wing Shek Wong",
  title =        "Enhanced Floating-Point Adder with Full Denormal
                 Support",
  crossref =     "IEEE:2022:ISC",
  pages =        "01--08",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00015",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2022; ARITH-29",
}


bibtype: misc
filename: fparith.bib
label: Spiridonov:2022:ABE
author: Iouri Spiridonov
title: Arithmetic of binary equivalents of decimal numbers
pages: 01--08
day: 23
month: nov
monthnumber: 11
year: 2022
DOI: https://doi.org/10.36227/techrxiv.19294511.v4
bibdate: Fri Sep 29 14:24:39 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 14:24:39 ???
acknowledgement: ack-nhfb
howpublished: TechRxiv preprint.
rawauthor: Iouri Spiridonov
rawtitle: Arithmetic of binary equivalents of decimal numbers
URL:
https://www.techrxiv.org/articles/preprint/The_arithmetic_of_binary_equivalents_of_decimal_numbers/19294511

abstract:
Within the framework of the concept of decimal calculations proposed in the article using binary arithmetic, a theory of binary equivalents of decimal floating-point numbers has been developed. According to this theory, basic decimal arithmetic operations on finite decimal numbers are performed with decimal precision by a binary processor according to the rules of binary arithmetic on the binary equivalents of decimal numbers. These calculation results are entirely consistent with the classical decimal finite number arithmetic and do not require the use of test programs. The identity of calculation results in decimal and binary equivalent arithmetics guarantees the repeatability of results on any platform. The article shows that implementing binary equivalents arithmetic with an acceptable decimal calculation error requires significantly fewer bits of binary processor registers than in modern computers. Because of the uniqueness of binary decimal equivalents, the difference between equal, properly rounded binary decimal equivalents is strictly zero. The presence of an explicit zero in the arithmetic of binary equivalents of decimal numbers makes it possible to implement a bitwise comparison of such numbers and introduce the concept of an infinitesimal number when the significand of a floating-point number is equal to zero.

rawabstract:
Within the framework of the concept of decimal calculations proposed in the article using binary arithmetic, a theory of binary equivalents of decimal floating-point numbers has been developed. According to this theory, basic decimal arithmetic operations on finite decimal numbers are performed with decimal precision by a binary processor according to the rules of binary arithmetic on the binary equivalents of decimal numbers. These calculation results are entirely consistent with the classical decimal finite number arithmetic and do not require the use of test programs. The identity of calculation results in decimal and binary equivalent arithmetics guarantees the repeatability of results on any platform. The article shows that implementing binary equivalents arithmetic with an acceptable decimal calculation error requires significantly fewer bits of binary processor registers than in modern computers. Because of the uniqueness of binary decimal equivalents, the difference between equal, properly rounded binary decimal equivalents is strictly zero. The presence of an explicit zero in the arithmetic of binary equivalents of decimal numbers makes it possible to implement a bitwise comparison of such numbers and introduce the concept of an infinitesimal number when the significand of a floating-point number is equal to zero.

entry:
@Misc{Spiridonov:2022:ABE,
  author =       "Iouri Spiridonov",
  title =        "Arithmetic of binary equivalents of decimal numbers",
  howpublished = "TechRxiv preprint.",
  day =          "23",
  month =        nov,
  year =         "2022",
  DOI =          "https://doi.org/10.36227/techrxiv.19294511.v4",
  bibdate =      "Fri Sep 29 14:24:39 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.techrxiv.org/articles/preprint/The_arithmetic_of_binary_equivalents_of_decimal_numbers/19294511",
  abstract =     "Within the framework of the concept of decimal
                 calculations proposed in the article using binary
                 arithmetic, a theory of binary equivalents of decimal
                 floating-point numbers has been developed. According to
                 this theory, basic decimal arithmetic operations on
                 finite decimal numbers are performed with decimal
                 precision by a binary processor according to the rules
                 of binary arithmetic on the binary equivalents of
                 decimal numbers. These calculation results are entirely
                 consistent with the classical decimal finite number
                 arithmetic and do not require the use of test programs.
                 The identity of calculation results in decimal and
                 binary equivalent arithmetics guarantees the
                 repeatability of results on any platform. The article
                 shows that implementing binary equivalents arithmetic
                 with an acceptable decimal calculation error requires
                 significantly fewer bits of binary processor registers
                 than in modern computers. Because of the uniqueness of
                 binary decimal equivalents, the difference between
                 equal, properly rounded binary decimal equivalents is
                 strictly zero. The presence of an explicit zero in the
                 arithmetic of binary equivalents of decimal numbers
                 makes it possible to implement a bitwise comparison of
                 such numbers and introduce the concept of an
                 infinitesimal number when the significand of a
                 floating-point number is equal to zero.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Sravya:2022:HPN
author: Alapati Madhu Sravya and N. Swetha and Asisa Kumar Panigrahy
editor: IEEE
booktitle: 2022 3rd International Conference for Emerging Technology (INCET)
title: Hardware Posit Numeration System primarily based on Arithmetic Operations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--8
year: 2022
DOI: https://doi.org/10.1109/INCET54531.2022.9825011
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Alapati Madhu Sravya and N. Swetha and Asisa Kumar Panigrahy
rawbooktitle: {2022 3rd International Conference for Emerging Technology (INCET)}
raweditor: {IEEE}
rawtitle: Hardware Posit Numeration System primarily based on Arithmetic Operations
entry:
@InProceedings{Sravya:2022:HPN,
  author =       "Alapati Madhu Sravya and N. Swetha and Asisa Kumar
                 Panigrahy",
  editor =       "{IEEE}",
  booktitle =    "{2022 3rd International Conference for Emerging
                 Technology (INCET)}",
  title =        "Hardware Posit Numeration System primarily based on
                 Arithmetic Operations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/INCET54531.2022.9825011",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Srivastava:2022:FSC
author: Nitish Srivastava and Gai Liu and Yi-Hsiang Lai and Zhiru Zhang
booktitle: Handbook of Computer Architecture
title: FPGA-Specific Compilers
publisher: Springer Nature
address: Singapore
pages: 1--37
year: 2022
DOI: https://doi.org/10.1007/978-981-15-6401-7_25-1
ISBN: 981-15-6401-9 OR 9811564019
ISBN13: 978-981-15-6401-7 OR 9789811564017
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nitish Srivastava and Gai Liu and Yi-Hsiang Lai and Zhiru Zhang
rawbooktitle: Handbook of Computer Architecture
rawtitle: {FPGA}-Specific Compilers
entry:
@InProceedings{Srivastava:2022:FSC,
  author =       "Nitish Srivastava and Gai Liu and Yi-Hsiang Lai and
                 Zhiru Zhang",
  booktitle =    "Handbook of Computer Architecture",
  title =        "{FPGA}-Specific Compilers",
  publisher =    "Springer Nature",
  address =      "Singapore",
  pages =        "1--37",
  year =         "2022",
  DOI =          "https://doi.org/10.1007/978-981-15-6401-7_25-1",
  ISBN =         "981-15-6401-9",
  ISBN-13 =      "978-981-15-6401-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: book
filename: fparith.bib
label: Strickland:2022:LBI
author: Lloyd Strickland and Harry R. Lewis
title: Leibniz on Binary: The Invention of Computer Arithmetic
publisher: MIT Press
address: Wheaton, MA, USA
pages: 413
year: 2022
ISBN: 0-262-37212-6 (e-book), 0-262-54434-2 OR 0262372126 (ebook), 0262544342
ISBN13: 978-0-262-37212-1 (e-book), 978-0-262-54434-4 OR 9780262372121 (ebook), 9780262544344
LCCN: QA141.4
bibdate: Fri Mar 17 08:38:41 MDT 2023
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.03.17 08:38:41 MDT
acknowledgement: ack-nhfb
subjectdates: 1646--1716
rawauthor: Lloyd Strickland and Harry R. Lewis
rawtitle: {Leibniz} on Binary: The Invention of Computer Arithmetic
subject:
Leibniz, Gottfried Wilhelm, Freiherr von; Translations into English; Mathematics, German; Binary system (Mathematics); History

TOC:
Intro Title Page Copyright Page Dedication Epigraph Table of Contents List of Figures Abbreviations Preface Acknowledgments Introduction 1. Notes on Algebra, Arithmetic, and Geometric Series (October 1674) 2. The Series of All Numbers, and on Binary Progression (before 15/25 March 1679) 3. Binary Progression (before 15/25 March 1679) 4. Geometric Progressions and Positional Notation (before 15/25 March 1679) 5. Binary Arithmetic Machine (before 15/25 March 1679) 6. On the Binary Progression (15/25 March 1679)7. Attempted Expression of the Circle in Binary Progression (c. 1679) 8. Sedecimal Progression (1679) 9. Binary Progression Is for Theory, Sedecimal for Practice (c. 1679) 10. On the Organon or Great Art of Thinking (first half [?] of 1679) 11. Binary Ancestral Calculations (early 1680s [?]) 12. Sedecimal on an Envelope (c. 1682--1685) 13. Remarks on Weigel (1694--mid-March 1695) 14. Leibniz to Duke Rudolph August (7/17--8/18 May 1696)15. A Wonderful Expression of All Numbers by 1 and 0 Representing the Origin of Things from God and Nothing, or the Mystery of Creation (7/17 May 1696) 16. Wonderful Origin of All Numbers from 1 and 0, Which Serves as a Beautiful Representation of the Mystery of Creation, since Everything Arises from God and Nothing Else (8/18 May 1696) 17. Leibniz to Duke Rudolph August (2/12 January 1697) 18. Duke Rudolph August to Johann Urban Muller (5/15 January 1697) 19. Leibniz to Claudio Filippo Grimaldi (mid-January-early February 1697) 20. Periods (May 1698--first half of January 1701)21. Leibniz to Philippe Naude (15 January 1701) 22. Leibniz to Joachim Bouvet (15 February 1701) 23. Essay on a New Science of Numbers (26 February 1701) 24. Binary Addition (spring-summer 1701 [?]) 25. Periods in Binary (spring-fall 1701) 26. Periods and Powers (mid-to-late June 1701 [?]) 27. Demonstration That Columns of Sequences Exhibiting Powers of Arithmetic Progressions, or Numbers Composed from These, Are Periodic (November 1701) 28. Joachim Bouvet to Leibniz (4 November 1701) 29. Leibniz to Bouvet (early April [?] 1703)30. Explanation of Binary Arithmetic, Which Uses Only the Digits 0 and 1, with Some Remarks on Its Usefulness, and on the Light It Throws on the Ancient Chinese Figures of Fuxi (7 April 1703) 31. Leibniz to Cesar Caze (23 June 1705) 32. On Binary (late June 1705) Bibliography Index

rawTOC:
Intro \\ Title Page \\ Copyright Page \\ Dedication \\ Epigraph \\ Table of Contents \\ List of Figures \\ Abbreviations \\ Preface \\ Acknowledgments \\ Introduction \\ 1. Notes on Algebra, Arithmetic, and Geometric Series (October 1674) \\ 2. The Series of All Numbers, and on Binary Progression (before 15/25 March 1679) \\ 3. Binary Progression (before 15/25 March 1679) \\ 4. Geometric Progressions and Positional Notation (before 15/25 March 1679) \\ 5. Binary Arithmetic Machine (before 15/25 March 1679) \\ 6. On the Binary Progression (15/25 March 1679)7. Attempted Expression of the Circle in Binary Progression (c. 1679) \\ 8. Sedecimal Progression (1679) \\ 9. Binary Progression Is for Theory, Sedecimal for Practice (c. 1679) \\ 10. On the Organon or Great Art of Thinking (first half [?] of 1679) \\ 11. Binary Ancestral Calculations (early 1680s [?]) \\ 12. Sedecimal on an Envelope (c. 1682--1685) \\ 13. Remarks on Weigel (1694--mid-March 1695) \\ 14. Leibniz to Duke Rudolph August (7/17--8/18 May 1696)15. A Wonderful Expression of All Numbers by 1 and 0 Representing the Origin of Things from God and Nothing, or the Mystery of Creation (7/17 May 1696) \\ 16. Wonderful Origin of All Numbers from 1 and 0, Which Serves as a Beautiful Representation of the Mystery of Creation, since Everything Arises from God and Nothing Else (8/18 May 1696) \\ 17. Leibniz to Duke Rudolph August (2/12 January 1697) \\ 18. Duke Rudolph August to Johann Urban M{\"u}ller (5/15 January 1697) \\ 19. Leibniz to Claudio Filippo Grimaldi (mid-January-early February 1697) \\ 20. Periods (May 1698--first half of January 1701)21. Leibniz to Philippe Naud{\'e} (15 January 1701) \\ 22. Leibniz to Joachim Bouvet (15 February 1701) \\ 23. Essay on a New Science of Numbers (26 February 1701) \\ 24. Binary Addition (spring-summer 1701 [?]) \\ 25. Periods in Binary (spring-fall 1701) \\ 26. Periods and Powers (mid-to-late June 1701 [?]) \\ 27. Demonstration That Columns of Sequences Exhibiting Powers of Arithmetic Progressions, or Numbers Composed from These, Are Periodic (November 1701) \\ 28. Joachim Bouvet to Leibniz (4 November 1701) \\ 29. Leibniz to Bouvet (early April [?] 1703)30. Explanation of Binary Arithmetic, Which Uses Only the Digits 0 and 1, with Some Remarks on Its Usefulness, and on the Light It Throws on the Ancient Chinese Figures of Fuxi (7 April 1703) \\ 31. Leibniz to C{\'e}sar Caze (23 June 1705) \\ 32. On Binary (late June 1705) \\ Bibliography \\ Index

entry:
@Book{Strickland:2022:LBI,
  author =       "Lloyd Strickland and Harry R. Lewis",
  title =        "{Leibniz} on Binary: The Invention of Computer
                 Arithmetic",
  publisher =    "MIT Press",
  address =      "Wheaton, MA, USA",
  pages =        "413",
  year =         "2022",
  ISBN =         "0-262-37212-6 (e-book), 0-262-54434-2",
  ISBN-13 =      "978-0-262-37212-1 (e-book), 978-0-262-54434-4",
  LCCN =         "QA141.4",
  bibdate =      "Fri Mar 17 08:38:41 MDT 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  subject =      "Leibniz, Gottfried Wilhelm, Freiherr von; Translations
                 into English; Mathematics, German; Binary system
                 (Mathematics); History",
  subject-dates = "1646--1716",
  tableofcontents = "Intro \\
                 Title Page \\
                 Copyright Page \\
                 Dedication \\
                 Epigraph \\
                 Table of Contents \\
                 List of Figures \\
                 Abbreviations \\
                 Preface \\
                 Acknowledgments \\
                 Introduction \\
                 1. Notes on Algebra, Arithmetic, and Geometric Series
                 (October 1674) \\
                 2. The Series of All Numbers, and on Binary Progression
                 (before 15/25 March 1679) \\
                 3. Binary Progression (before 15/25 March 1679) \\
                 4. Geometric Progressions and Positional Notation
                 (before 15/25 March 1679) \\
                 5. Binary Arithmetic Machine (before 15/25 March 1679)
                 \\
                 6. On the Binary Progression (15/25 March 1679)7.
                 Attempted Expression of the Circle in Binary
                 Progression (c. 1679) \\
                 8. Sedecimal Progression (1679) \\
                 9. Binary Progression Is for Theory, Sedecimal for
                 Practice (c. 1679) \\
                 10. On the Organon or Great Art of Thinking (first half
                 [?] of 1679) \\
                 11. Binary Ancestral Calculations (early 1680s [?]) \\
                 12. Sedecimal on an Envelope (c. 1682--1685) \\
                 13. Remarks on Weigel (1694--mid-March 1695) \\
                 14. Leibniz to Duke Rudolph August (7/17--8/18 May
                 1696)15. A Wonderful Expression of All Numbers by 1 and
                 0 Representing the Origin of Things from God and
                 Nothing, or the Mystery of Creation (7/17 May 1696) \\
                 16. Wonderful Origin of All Numbers from 1 and 0, Which
                 Serves as a Beautiful Representation of the Mystery of
                 Creation, since Everything Arises from God and Nothing
                 Else (8/18 May 1696) \\
                 17. Leibniz to Duke Rudolph August (2/12 January 1697)
                 \\
                 18. Duke Rudolph August to Johann Urban M{\"u}ller
                 (5/15 January 1697) \\
                 19. Leibniz to Claudio Filippo Grimaldi
                 (mid-January-early February 1697) \\
                 20. Periods (May 1698--first half of January 1701)21.
                 Leibniz to Philippe Naud{\'e} (15 January 1701) \\
                 22. Leibniz to Joachim Bouvet (15 February 1701) \\
                 23. Essay on a New Science of Numbers (26 February
                 1701) \\
                 24. Binary Addition (spring-summer 1701 [?]) \\
                 25. Periods in Binary (spring-fall 1701) \\
                 26. Periods and Powers (mid-to-late June 1701 [?]) \\
                 27. Demonstration That Columns of Sequences Exhibiting
                 Powers of Arithmetic Progressions, or Numbers Composed
                 from These, Are Periodic (November 1701) \\
                 28. Joachim Bouvet to Leibniz (4 November 1701) \\
                 29. Leibniz to Bouvet (early April [?] 1703)30.
                 Explanation of Binary Arithmetic, Which Uses Only the
                 Digits 0 and 1, with Some Remarks on Its Usefulness,
                 and on the Light It Throws on the Ancient Chinese
                 Figures of Fuxi (7 April 1703) \\
                 31. Leibniz to C{\'e}sar Caze (23 June 1705) \\
                 32. On Binary (late June 1705) \\
                 Bibliography \\
                 Index",
}


bibtype: article
filename: fparith.bib
label: Tan:2022:SRT
author: Bryan Tan and Benjamin Mariano and Shuvendu K. Lahiri and Isil Dillig and Yu Feng
title: SolType: refinement types for arithmetic overflow in Solidity
journal: j-PACMPL
volume: 6
number: POPL
pages: 4:1--4:29
month: jan
monthnumber: 1
year: 2022
DOI: https://doi.org/10.1145/3498665
ISSN: 2475-1421 (electronic) OR 24751421 (electronic)
ISSNL: 2475-1421 OR 24751421
bibdate: Thu May 26 06:32:48 MDT 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2022.05.26 06:32:48 MDT
URL: https://dl.acm.org/doi/10.1145/3498665
fjournal: Proceedings of the ACM on Programming Languages (PACMPL)
acknowledgement: ack-nhfb
articleno: 4
journalURL: https://dl.acm.org/loi/pacmpl
rawauthor: Bryan Tan and Benjamin Mariano and Shuvendu K. Lahiri and Isil Dillig and Yu Feng
rawtitle: {SolType}: refinement types for arithmetic overflow in {Solidity}
abstract:
As smart contracts gain adoption in financial transactions, it becomes increasingly important to ensure that they are free of bugs and security vulnerabilities. Of particular relevance in this context are arithmetic overflow bugs, as integers are often used to represent financial assets like account balances. Motivated by this observation, this paper presents SolType, a refinement type system for Solidity that can be used to prevent arithmetic over- and under-flows in smart contracts. SolType allows developers to add refinement type annotations and uses them to prove that arithmetic operations do not lead to over- and under-flows. SolType incorporates a rich vocabulary of refinement terms that allow expressing relationships between integer values and aggregate properties of complex data structures. Furthermore, our implementation, called Solid, incorporates a type inference engine and can automatically infer useful type annotations, including non-trivial contract invariants.par To evaluate the usefulness of our type system, we use Solid to prove arithmetic safety of a total of 120 smart contracts. When used in its fully automated mode (i.e., using Solid's type inference capabilities), Solid is able to eliminate 86.3% of redundant runtime checks used to guard against overflows. We also compare Solid against a state-of-the-art arithmetic safety verifier called VeriSmart and show that Solid has a significantly lower false positive rate, while being significantly faster in terms of verification time.

rawabstract:
As smart contracts gain adoption in financial transactions, it becomes increasingly important to ensure that they are free of bugs and security vulnerabilities. Of particular relevance in this context are arithmetic overflow bugs, as integers are often used to represent financial assets like account balances. Motivated by this observation, this paper presents SolType, a refinement type system for Solidity that can be used to prevent arithmetic over- and under-flows in smart contracts. SolType allows developers to add refinement type annotations and uses them to prove that arithmetic operations do not lead to over- and under-flows. SolType incorporates a rich vocabulary of refinement terms that allow expressing relationships between integer values and aggregate properties of complex data structures. Furthermore, our implementation, called Solid, incorporates a type inference engine and can automatically infer useful type annotations, including non-trivial contract invariants.\par To evaluate the usefulness of our type system, we use Solid to prove arithmetic safety of a total of 120 smart contracts. When used in its fully automated mode (i.e., using Solid's type inference capabilities), Solid is able to eliminate 86.3\% of redundant runtime checks used to guard against overflows. We also compare Solid against a state-of-the-art arithmetic safety verifier called VeriSmart and show that Solid has a significantly lower false positive rate, while being significantly faster in terms of verification time.

entry:
@Article{Tan:2022:SRT,
  author =       "Bryan Tan and Benjamin Mariano and Shuvendu K. Lahiri
                 and Isil Dillig and Yu Feng",
  title =        "{SolType}: refinement types for arithmetic overflow in
                 {Solidity}",
  journal =      j-PACMPL,
  volume =       "6",
  number =       "POPL",
  pages =        "4:1--4:29",
  month =        jan,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3498665",
  ISSN =         "2475-1421 (electronic)",
  ISSN-L =       "2475-1421",
  bibdate =      "Thu May 26 06:32:48 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3498665",
  abstract =     "As smart contracts gain adoption in financial
                 transactions, it becomes increasingly important to
                 ensure that they are free of bugs and security
                 vulnerabilities. Of particular relevance in this
                 context are arithmetic overflow bugs, as integers are
                 often used to represent financial assets like account
                 balances. Motivated by this observation, this paper
                 presents SolType, a refinement type system for Solidity
                 that can be used to prevent arithmetic over- and
                 under-flows in smart contracts. SolType allows
                 developers to add refinement type annotations and uses
                 them to prove that arithmetic operations do not lead to
                 over- and under-flows. SolType incorporates a rich
                 vocabulary of refinement terms that allow expressing
                 relationships between integer values and aggregate
                 properties of complex data structures. Furthermore, our
                 implementation, called Solid, incorporates a type
                 inference engine and can automatically infer useful
                 type annotations, including non-trivial contract
                 invariants.\par

                 To evaluate the usefulness of our type system, we use
                 Solid to prove arithmetic safety of a total of 120
                 smart contracts. When used in its fully automated mode
                 (i.e., using Solid's type inference capabilities),
                 Solid is able to eliminate 86.3\% of redundant runtime
                 checks used to guard against overflows. We also compare
                 Solid against a state-of-the-art arithmetic safety
                 verifier called VeriSmart and show that Solid has a
                 significantly lower false positive rate, while being
                 significantly faster in terms of verification time.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "Proceedings of the ACM on Programming Languages
                 (PACMPL)",
  journal-URL =  "https://dl.acm.org/loi/pacmpl",
}


bibtype: inproceedings
filename: fparith.bib
label: Tatar:2022:PEL
author: Guner Tatar and Salih Bayar and Ihsan Cicek
booktitle: 2022 International Conference on Innovations in Intelligent SysTems and Applications (INISTA)
title: Performance Evaluation of Low-Precision Quantized LeNet and ConvNet Neural Networks
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2022
DOI: https://doi.org/10.1109/INISTA55318.2022.9894261
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Guner Tatar and Salih Bayar and Ihsan Cicek
rawbooktitle: {2022 International Conference on Innovations in Intelligent SysTems and Applications (INISTA)}
rawtitle: Performance Evaluation of Low-Precision Quantized {LeNet} and {ConvNet} Neural Networks
keywords:
Computational modeling; ConvNet; Convolutional neural networks; Fixed point arithmetic; Floating point arithmetic; FPGA; Hardware accelerators; LeNet; Neural networks; Performance evaluation; Power demand; Quantization (signal); Quantized neural networks; Technological innovation; Training

entry:
@InProceedings{Tatar:2022:PEL,
  author =       "Guner Tatar and Salih Bayar and Ihsan Cicek",
  booktitle =    "{2022 International Conference on Innovations in
                 Intelligent SysTems and Applications (INISTA)}",
  title =        "Performance Evaluation of Low-Precision Quantized
                 {LeNet} and {ConvNet} Neural Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/INISTA55318.2022.9894261",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computational modeling; ConvNet; Convolutional neural
                 networks; Fixed point arithmetic; Floating point
                 arithmetic; FPGA; Hardware accelerators; LeNet; Neural
                 networks; Performance evaluation; Power demand;
                 Quantization (signal); Quantized neural networks;
                 Technological innovation; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Tortorella:2022:RCF
author: Yvan Tortorella and Luca Bertaccini and Davide Rossi and Luca Benini and Francesco Conti
editor: IEEE
booktitle: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1099--1102
year: 2022
DOI: https://doi.org/10.23919/DATE54114.2022.9774759
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Yvan Tortorella and Luca Bertaccini and Davide Rossi and Luca Benini and Francesco Conti
rawbooktitle: {2022 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
raweditor: {IEEE}
title:
RedMulE: a Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs

rawtitle:
{RedMulE}: a Compact {FP16} Matrix-Multiplication Accelerator for Adaptive Deep Learning on {RISC-V}-Based Ultra-Low-Power {SoCs}

entry:
@InProceedings{Tortorella:2022:RCF,
  author =       "Yvan Tortorella and Luca Bertaccini and Davide Rossi
                 and Luca Benini and Francesco Conti",
  editor =       "{IEEE}",
  booktitle =    "{2022 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{RedMulE}: a Compact {FP16} Matrix-Multiplication
                 Accelerator for Adaptive Deep Learning on
                 {RISC-V}-Based Ultra-Low-Power {SoCs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1099--1102",
  year =         "2022",
  DOI =          "https://doi.org/10.23919/DATE54114.2022.9774759",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Venkataramanaiah:2022:BFP
booktitle: ESSCIRC 2022 --- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 89--92
year: 2022
DOI: https://doi.org/10.1109/ESSCIRC55480.2022.9911359
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {ESSCIRC 2022 --- IEEE 48th European Solid State Circuits Conference (ESSCIRC)}
author:
Shreyas Kolala Venkataramanaiah and Jian Meng and Han-Sok Suh and Injune Yeo and Jyotishman Saikia and Sai Kiran Cherupally and Yichi Zhang and Zhiru Zhang and Jae-sun Seo

title:
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation / Weight Sparsification

keywords:
Convolutional neural networks; deep neural network training; Energy efficiency; Europe; hardware accelerator; Neural networks; Prototypes; structured sparsity; Tensors; Topology; Training

rawauthor:
Shreyas Kolala Venkataramanaiah and Jian Meng and Han-Sok Suh and Injune Yeo and Jyotishman Saikia and Sai Kiran Cherupally and Yichi Zhang and Zhiru Zhang and Jae-sun Seo

rawtitle:
A 28nm 8-bit Floating-Point {Tensor Core} based {CNN} Training Processor with Dynamic Activation\slash Weight Sparsification

entry:
@InProceedings{Venkataramanaiah:2022:BFP,
  author =       "Shreyas Kolala Venkataramanaiah and Jian Meng and
                 Han-Sok Suh and Injune Yeo and Jyotishman Saikia and
                 Sai Kiran Cherupally and Yichi Zhang and Zhiru Zhang
                 and Jae-sun Seo",
  booktitle =    "{ESSCIRC 2022 --- IEEE 48th European Solid State
                 Circuits Conference (ESSCIRC)}",
  title =        "A 28nm 8-bit Floating-Point {Tensor Core} based {CNN}
                 Training Processor with Dynamic Activation\slash Weight
                 Sparsification",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "89--92",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ESSCIRC55480.2022.9911359",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Convolutional neural networks; deep neural network
                 training; Energy efficiency; Europe; hardware
                 accelerator; Neural networks; Prototypes; structured
                 sparsity; Tensors; Topology; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Verma:2022:RVC
author: Anu Verma and Priyamvada Sharma and Bishnu Prasad Das
editor: IEEE
booktitle: 2022 25th Euromicro Conference on Digital System Design (DSD)
title: RISC-V Core with Approximate Multiplier for Error-Tolerant Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 239--246
year: 2022
DOI: https://doi.org/10.1109/DSD57027.2022.00040
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Anu Verma and Priyamvada Sharma and Bishnu Prasad Das
rawbooktitle: {2022 25th Euromicro Conference on Digital System Design (DSD)}
raweditor: {IEEE}
rawtitle: {RISC-V} Core with Approximate Multiplier for Error-Tolerant Applications
entry:
@InProceedings{Verma:2022:RVC,
  author =       "Anu Verma and Priyamvada Sharma and Bishnu Prasad
                 Das",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{RISC-V} Core with Approximate Multiplier for
                 Error-Tolerant Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "239--246",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00040",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Walia:2022:FLP
author: Sumit Walia and Bachu Varun Tej and Arpita Kabra and Joydeep Devnath and Joycee Mekie
title: Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation
journal: j-IEEE-TRANS-VLSI-SYST
volume: 30
number: 1
pages: 108--111
year: 2022
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2021.3131609
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Sumit Walia and Bachu Varun Tej and Arpita Kabra and Joydeep Devnath and Joycee Mekie
rawtitle: Fast and Low-Power Quantized Fixed Posit High-Accuracy {DNN} Implementation
entry:
@Article{Walia:2022:FLP,
  author =       "Sumit Walia and Bachu Varun Tej and Arpita Kabra and
                 Joydeep Devnath and Joycee Mekie",
  title =        "Fast and Low-Power Quantized Fixed Posit High-Accuracy
                 {DNN} Implementation",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "30",
  number =       "1",
  pages =        "108--111",
  year =         "2022",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2021.3131609",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2022:ARE
author: Luming Wang and Defeng Chen and Dongliang Wang and Chao Wang
volume: 5
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 990--995
year: 2022
DOI: https://doi.org/10.1109/IMCEC55388.2022.10019890
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Luming Wang and Defeng Chen and Dongliang Wang and Chao Wang
booktitle:
2022 IEEE 5th Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC)

title:
Acceleration of radar echo coherent accumulation system based on half-precision format and tensor core

keywords:
Batch production systems; coherent accumulation system; GPU; half precision; Life estimation; Process control; Radar; Radar detection; Spaceborne radar; tensor core; Tensors

rawbooktitle:
{2022 IEEE 5th Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC)}

rawtitle:
Acceleration of radar echo coherent accumulation system based on half-precision format and tensor core

entry:
@InProceedings{Wang:2022:ARE,
  author =       "Luming Wang and Defeng Chen and Dongliang Wang and
                 Chao Wang",
  booktitle =    "{2022 IEEE 5th Advanced Information Management,
                 Communicates, Electronic and Automation Control
                 Conference (IMCEC)}",
  title =        "Acceleration of radar echo coherent accumulation
                 system based on half-precision format and tensor core",
  volume =       "5",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "990--995",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IMCEC55388.2022.10019890",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Batch production systems; coherent accumulation
                 system; GPU; half precision; Life estimation; Process
                 control; Radar; Radar detection; Spaceborne radar;
                 tensor core; Tensors",
}


bibtype: article
filename: fparith.bib
label: Wang:2022:PNE
author: Yang Wang and Dazheng Deng and Leibo Liu and Shaojun Wei and Shouyi Yin
journal: j-IEEE-TRANS-CIRCUITS-SYST-1
volume: 69
number: 10
pages: 4042--4055
year: 2022
DOI: https://doi.org/10.1109/TCSI.2022.3184115
ISSN: 1549-8328 (print), 1558-0806 (electronic) OR 15498328 (print), 15580806 (electronic)
ISSNL: 1549-8328 OR 15498328
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Circuits and Systems I: Regular Papers
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
rawauthor: Yang Wang and Dazheng Deng and Leibo Liu and Shaojun Wei and Shouyi Yin
title:
PL-NPU: an Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing

rawtitle:
{PL-NPU}: an Energy-Efficient Edge-Device {DNN} Training Processor With Posit-Based Logarithm-Domain Computing

entry:
@Article{Wang:2022:PNE,
  author =       "Yang Wang and Dazheng Deng and Leibo Liu and Shaojun
                 Wei and Shouyi Yin",
  title =        "{PL-NPU}: an Energy-Efficient Edge-Device {DNN}
                 Training Processor With Posit-Based Logarithm-Domain
                 Computing",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "69",
  number =       "10",
  pages =        "4042--4055",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TCSI.2022.3184115",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}


bibtype: article
filename: fparith.bib
label: Waris:2022:AAR
author: Haroon Waris and Chenghua Wang and Chenyu Xu and Weiqiang Liu
title: AxRMs: Approximate Recursive Multipliers Using High-Performance Building Blocks
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 2
pages: 1229--1235
month: apr
monthnumber: 4
year: 2022
DOI: https://doi.org/10.1109/TETC.2021.3096515
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Haroon Waris and Chenghua Wang and Chenyu Xu and Weiqiang Liu
rawtitle: {AxRMs}: Approximate Recursive Multipliers Using High-Performance Building Blocks
entry:
@Article{Waris:2022:AAR,
  author =       "Haroon Waris and Chenghua Wang and Chenyu Xu and
                 Weiqiang Liu",
  title =        "{AxRMs}: Approximate Recursive Multipliers Using
                 High-Performance Building Blocks",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "2",
  pages =        "1229--1235",
  month =        apr # "\slash " # jun,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2021.3096515",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: article
filename: fparith.bib
label: Waris:2022:HPP
author: Haroon Waris and Chenghua Wang and Weiqiang Liu and Jie Han and Fabrizio Lombardi
title: Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 1
pages: 507--513
month: jan
monthnumber: 1
year: 2022
DOI: https://doi.org/10.1109/TETC.2020.3013977
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Haroon Waris and Chenghua Wang and Weiqiang Liu and Jie Han and Fabrizio Lombardi
rawtitle: Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers
entry:
@Article{Waris:2022:HPP,
  author =       "Haroon Waris and Chenghua Wang and Weiqiang Liu and
                 Jie Han and Fabrizio Lombardi",
  title =        "Hybrid Partial Product-Based High-Performance
                 Approximate Recursive Multipliers",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "1",
  pages =        "507--513",
  month =        jan # "\slash " # mar,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2020.3013977",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: article
filename: fparith.bib
label: Xie:2022:EHI
author: Jiafeng Xie and Pengzhou He and Xiaofang Wang and Jose L. Imana
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 10
number: 2
pages: 1222--1228
month: apr
monthnumber: 4
year: 2022
DOI: https://doi.org/10.1109/TETC.2021.3091982
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Jiafeng Xie and Pengzhou He and Xiaofang Wang and Jos{\'e} L. Ima{\~n}a
title:
Efficient Hardware Implementation of Finite Field Arithmetic $ A B + C A B + C $ for Binary Ring-LWE Based Post-Quantum Cryptography

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib

rawtitle:
Efficient Hardware Implementation of Finite Field Arithmetic {$ A B + C A B + C $} for Binary Ring-{LWE} Based Post-Quantum Cryptography

entry:
@Article{Xie:2022:EHI,
  author =       "Jiafeng Xie and Pengzhou He and Xiaofang Wang and
                 Jos{\'e} L. Ima{\~n}a",
  title =        "Efficient Hardware Implementation of Finite Field
                 Arithmetic {$ A B + C A B + C $} for Binary Ring-{LWE}
                 Based Post-Quantum Cryptography",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "2",
  pages =        "1222--1228",
  month =        apr # "\slash " # jun,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2021.3091982",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: You:2022:RVP
author: Chao-Xing You and Qi-Tong Wang and Han Zhong and Cheng Liu
editor: IEEE
booktitle: 2022 4th International Academic Exchange Conference on Science and Technology Innovation (IAECST)
title: RISC-V processor-based automatic access floating-point computing accelerated dataflow co-processor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 647--650
year: 2022
DOI: https://doi.org/10.1109/IAECST57965.2022.10061878
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Chao-Xing You and Qi-Tong Wang and Han Zhong and Cheng Liu
rawbooktitle: {2022 4th International Academic Exchange Conference on Science and Technology Innovation (IAECST)}
raweditor: {IEEE}
rawtitle:
{RISC-V} processor-based automatic access floating-point computing accelerated dataflow co-processor

entry:
@InProceedings{You:2022:RVP,
  author =       "Chao-Xing You and Qi-Tong Wang and Han Zhong and Cheng
                 Liu",
  editor =       "{IEEE}",
  booktitle =    "{2022 4th International Academic Exchange Conference
                 on Science and Technology Innovation (IAECST)}",
  title =        "{RISC-V} processor-based automatic access
                 floating-point computing accelerated dataflow
                 co-processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "647--650",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IAECST57965.2022.10061878",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Zacharelos:2022:ARM
title: Approximate Recursive Multipliers Using Low Power Building Blocks
crossref: IEEE:2022:ISC
pages: 67--67
year: 2022
DOI: https://doi.org/10.1109/ARITH54963.2022.00020
bibdate: Thu Sep 21 10:14:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:14:25 ???
keywords: ARITH 2022; ARITH-29
acknowledgement: ack-nhfb
rawtitle: Approximate Recursive Multipliers Using Low Power Building Blocks
author:
Efstratios Zacharelos and Italo Nunziata and Gerardo Saggese and Antonio G. M. Strollo and Ettore Napoli

rawauthor:
Efstratios Zacharelos and Italo Nunziata and Gerardo Saggese and Antonio G. M. Strollo and Ettore Napoli

entry:
@InProceedings{Zacharelos:2022:ARM,
  author =       "Efstratios Zacharelos and Italo Nunziata and Gerardo
                 Saggese and Antonio G. M. Strollo and Ettore Napoli",
  title =        "Approximate Recursive Multipliers Using Low Power
                 Building Blocks",
  crossref =     "IEEE:2022:ISC",
  pages =        "67--67",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00020",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2022; ARITH-29",
}


bibtype: article
filename: fparith.bib
label: Zhang:2022:HRD
author: Bo Zhang and Zeming Cheng and Massoud Pedram
title: High-Radix Design of a Scalable Montgomery Modular Multiplier With Low Latency
journal: j-IEEE-TRANS-COMPUT
volume: 71
number: 2
pages: 436--449
month: feb
monthnumber: 2
year: 2022
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2021.3052999
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jan 20 07:18:16 2022
bibtimestamp: 2022.01.20 07:18:16 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Bo Zhang and Zeming Cheng and Massoud Pedram
rawtitle: High-Radix Design of a Scalable {Montgomery} Modular Multiplier With Low Latency
entry:
@Article{Zhang:2022:HRD,
  author =       "Bo Zhang and Zeming Cheng and Massoud Pedram",
  title =        "High-Radix Design of a Scalable {Montgomery} Modular
                 Multiplier With Low Latency",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "2",
  pages =        "436--449",
  month =        feb,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2021.3052999",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jan 20 07:18:16 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Zhang:2022:SDF
author: Yi Zhang and Mengdi Sun and Xin Qi
title: Speedup of discrete Fourier transform by efficient modular arithmetic
journal: j-CCPE
volume: 34
number: 3
pages: e6564:1--e6564:??
day: 1
month: feb
monthnumber: 2
year: 2022
CODEN: CCPEBO
DOI: https://doi.org/10.1002/cpe.6564
ISSN: 1532-0626 (print), 1532-0634 (electronic) OR 15320626 (print), 15320634 (electronic)
ISSNL: 1532-0626 OR 15320626
bibdate: Tue Feb 22 09:50:06 MST 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/ccpe.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2022.02.22 09:50:06 MST
fjournal: Concurrency and Computation: Practice and Experience
acknowledgement: ack-nhfb
ajournal: Concurr. Comput.
journalURL: http://www.interscience.wiley.com/jpages/1532-0626
onlinedate: 15 September 2021
rawauthor: Yi Zhang and Mengdi Sun and Xin Qi
rawtitle: Speedup of discrete {Fourier} transform by efficient modular arithmetic
entry:
@Article{Zhang:2022:SDF,
  author =       "Yi Zhang and Mengdi Sun and Xin Qi",
  title =        "Speedup of discrete {Fourier} transform by efficient
                 modular arithmetic",
  journal =      j-CCPE,
  volume =       "34",
  number =       "3",
  pages =        "e6564:1--e6564:??",
  day =          "1",
  month =        feb,
  year =         "2022",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.6564",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Tue Feb 22 09:50:06 MST 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ccpe.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Concurr. Comput.",
  fjournal =     "Concurrency and Computation: Practice and Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
  onlinedate =   "15 September 2021",
}


bibtype: article
filename: fparith.bib
label: Zhao:2022:LML
title: LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
journal: j-IEEE-TRANS-COMPUT
volume: 71
number: 12
pages: 3179--3190
year: 2022
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3202747
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Oct 1 06:40:18 2025
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: {LNS-Madam}: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
author:
Jiawei Zhao and Steve Dai and Rangharajan Venkatesan and Brian Zimmer and Mustafa Ali and Ming-Yu Liu and Brucek Khailany and William J. Dally and Anima Anandkumar

keywords:
Arithmetic; Costs; Hardware; hardware acceleration; Machine learning; Neural networks; optimization; Quantization (signal); Table lookup; Training

rawauthor:
Jiawei Zhao and Steve Dai and Rangharajan Venkatesan and Brian Zimmer and Mustafa Ali and Ming-Yu Liu and Brucek Khailany and William J. Dally and Anima Anandkumar

entry:
@Article{Zhao:2022:LML,
  author =       "Jiawei Zhao and Steve Dai and Rangharajan Venkatesan
                 and Brian Zimmer and Mustafa Ali and Ming-Yu Liu and
                 Brucek Khailany and William J. Dally and Anima
                 Anandkumar",
  title =        "{LNS-Madam}: Low-Precision Training in Logarithmic
                 Number System Using Multiplicative Weight Update",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "12",
  pages =        "3179--3190",
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3202747",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Arithmetic; Costs; Hardware; hardware acceleration;
                 Machine learning; Neural networks; optimization;
                 Quantization (signal); Table lookup; Training",
}


bibtype: article
filename: fparith.bib
label: Zolfagharinejad:2022:PPE
author: Mohamadreza Zolfagharinejad and Mehdi Kamal and Ali Afzali-Khusha and Massoud Pedram
title: Posit Process Element for Using in Energy-Efficient DNN Accelerators
journal: j-IEEE-TRANS-VLSI-SYST
volume: 30
number: 6
pages: 844--848
year: 2022
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2022.3165510
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Mohamadreza Zolfagharinejad and Mehdi Kamal and Ali Afzali-Khusha and Massoud Pedram
rawtitle: Posit Process Element for Using in Energy-Efficient {DNN} Accelerators
entry:
@Article{Zolfagharinejad:2022:PPE,
  author =       "Mohamadreza Zolfagharinejad and Mehdi Kamal and Ali
                 Afzali-Khusha and Massoud Pedram",
  title =        "Posit Process Element for Using in Energy-Efficient
                 {DNN} Accelerators",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "30",
  number =       "6",
  pages =        "844--848",
  year =         "2022",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2022.3165510",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: article
filename: fparith.bib
label: Zou:2022:OFR
author: Daming Zou and Yuchen Gu and Yuanfeng Shi and MingZhe Wang and Yingfei Xiong and Zhendong Su
title: Oracle-free repair synthesis for floating-point programs
journal: j-PACMPL
volume: 6
number: OOPSLA2
pages: 159:1--159:??
month: oct
monthnumber: 10
year: 2022
DOI: https://doi.org/10.1145/3563322
ISSN: 2475-1421 (electronic) OR 24751421 (electronic)
ISSNL: 2475-1421 OR 24751421
bibdate: Sat Mar 11 09:08:36 MST 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2023.03.11 09:08:36 MST
URL: https://dl.acm.org/doi/10.1145/3563322
fjournal: Proceedings of the ACM on Programming Languages (PACMPL)
acknowledgement: ack-nhfb
articleno: 159
journalURL: https://dl.acm.org/loi/pacmpl
rawauthor: Daming Zou and Yuchen Gu and Yuanfeng Shi and MingZhe Wang and Yingfei Xiong and Zhendong Su
rawtitle: Oracle-free repair synthesis for floating-point programs
abstract:
The floating-point representation provides widely-used data types (such as ``float'' and ``double'') for modern numerical software. Numerical errors are inherent due to floating-point's approximate nature, and pose an important, well-known challenge. It is nontrivial to fix/repair numerical code to reduce numerical errors --- it requires either numerical expertise (for manual fixing) or high-precision oracles (for automatic repair); both are difficult requirements. To tackle this challenge, this paper introduces a principled dynamic approach that is fully automated and oracle-free for effectively repairing floating-point errors. The key of our approach is the novel notion of micro-structure that characterizes structural patterns of floating-point errors. We leverage micro-structures' statistical information on floating-point errors to effectively guide repair synthesis and validation. Compared with existing state-of-the-art repair approaches, our work is fully automatic and has the distinctive benefit of not relying on the difficult to obtain high-precision oracles. Evaluation results on 36 commonly-used numerical programs show that our approach is highly efficient and effective: (1) it is able to synthesize repairs instantaneously, and (2) versus the original programs, the repaired programs have orders of magnitude smaller floating-point errors, while having faster runtime performance

rawabstract:
The floating-point representation provides widely-used data types (such as ``float'' and ``double'') for modern numerical software. Numerical errors are inherent due to floating-point's approximate nature, and pose an important, well-known challenge. It is nontrivial to fix/repair numerical code to reduce numerical errors --- it requires either numerical expertise (for manual fixing) or high-precision oracles (for automatic repair); both are difficult requirements. To tackle this challenge, this paper introduces a principled dynamic approach that is fully automated and oracle-free for effectively repairing floating-point errors. The key of our approach is the novel notion of micro-structure that characterizes structural patterns of floating-point errors. We leverage micro-structures' statistical information on floating-point errors to effectively guide repair synthesis and validation. Compared with existing state-of-the-art repair approaches, our work is fully automatic and has the distinctive benefit of not relying on the difficult to obtain high-precision oracles. Evaluation results on 36 commonly-used numerical programs show that our approach is highly efficient and effective: (1) it is able to synthesize repairs instantaneously, and (2) versus the original programs, the repaired programs have orders of magnitude smaller floating-point errors, while having faster runtime performance

entry:
@Article{Zou:2022:OFR,
  author =       "Daming Zou and Yuchen Gu and Yuanfeng Shi and MingZhe
                 Wang and Yingfei Xiong and Zhendong Su",
  title =        "Oracle-free repair synthesis for floating-point
                 programs",
  journal =      j-PACMPL,
  volume =       "6",
  number =       "OOPSLA2",
  pages =        "159:1--159:??",
  month =        oct,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3563322",
  ISSN =         "2475-1421 (electronic)",
  ISSN-L =       "2475-1421",
  bibdate =      "Sat Mar 11 09:08:36 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3563322",
  abstract =     "The floating-point representation provides widely-used
                 data types (such as ``float'' and ``double'') for
                 modern numerical software. Numerical errors are
                 inherent due to floating-point's approximate nature,
                 and pose an important, well-known challenge. It is
                 nontrivial to fix/repair numerical code to reduce
                 numerical errors --- it requires either numerical
                 expertise (for manual fixing) or high-precision oracles
                 (for automatic repair); both are difficult
                 requirements. To tackle this challenge, this paper
                 introduces a principled dynamic approach that is fully
                 automated and oracle-free for effectively repairing
                 floating-point errors. The key of our approach is the
                 novel notion of micro-structure that characterizes
                 structural patterns of floating-point errors. We
                 leverage micro-structures' statistical information on
                 floating-point errors to effectively guide repair
                 synthesis and validation. Compared with existing
                 state-of-the-art repair approaches, our work is fully
                 automatic and has the distinctive benefit of not
                 relying on the difficult to obtain high-precision
                 oracles. Evaluation results on 36 commonly-used
                 numerical programs show that our approach is highly
                 efficient and effective: (1) it is able to synthesize
                 repairs instantaneously, and (2) versus the original
                 programs, the repaired programs have orders of
                 magnitude smaller floating-point errors, while having
                 faster runtime performance",
  acknowledgement = ack-nhfb,
  articleno =    "159",
  fjournal =     "Proceedings of the ACM on Programming Languages
                 (PACMPL)",
  journal-URL =  "https://dl.acm.org/loi/pacmpl",
}


bibtype: article
filename: fparith.bib
label: Abad:2023:HAT
author: Sudeh Shirkavand Saleh Abad and Mohammad Hossein Moaiyeri
journal: j-J-SUPERCOMPUTING
volume: 79
number: 3
pages: 3357--3372
month: feb
monthnumber: 2
year: 2023
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-022-04789-6
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Sat Feb 18 09:20:28 MST 2023
bibtimestamp: 2023.02.18 09:20:28 MST
URL: https://link.springer.com/article/10.1007/s11227-022-04789-6
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Sudeh Shirkavand Saleh Abad and Mohammad Hossein Moaiyeri
title:
Hardware-accuracy trade-offs for error-resilient applications using an ultra-efficient hybrid approximate multiplier

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib

rawtitle:
Hardware-accuracy trade-offs for error-resilient applications using an ultra-efficient hybrid approximate multiplier

entry:
@Article{Abad:2023:HAT,
  author =       "Sudeh Shirkavand Saleh Abad and Mohammad Hossein
                 Moaiyeri",
  title =        "Hardware-accuracy trade-offs for error-resilient
                 applications using an ultra-efficient hybrid
                 approximate multiplier",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "79",
  number =       "3",
  pages =        "3357--3372",
  month =        feb,
  year =         "2023",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-022-04789-6",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Sat Feb 18 09:20:28 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-022-04789-6",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Abdi:2023:FEF
author: Athena Abdi and Sina Shahoveisi
title: FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems
journal: j-J-SUPERCOMPUTING
volume: 79
number: 1
pages: 626--649
month: jan
monthnumber: 1
year: 2023
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-022-04698-8
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Sat Feb 18 09:20:27 MST 2023
bibtimestamp: 2023.02.18 09:20:27 MST
URL: https://link.springer.com/article/10.1007/s11227-022-04698-8
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Athena Abdi and Sina Shahoveisi
rawtitle: {FT-EALU}: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems
entry:
@Article{Abdi:2023:FEF,
  author =       "Athena Abdi and Sina Shahoveisi",
  title =        "{FT-EALU}: fault-tolerant arithmetic and logic unit
                 for critical embedded and real-time systems",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "79",
  number =       "1",
  pages =        "626--649",
  month =        jan,
  year =         "2023",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-022-04698-8",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Sat Feb 18 09:20:27 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-022-04698-8",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: inproceedings
filename: fparith.bib
label: Adela:2023:DIS
author: Noor Alhuda Saad Adela and Amani Najeeb Ben Yousuf and Mohamed Muftah Eljhani
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 130--134
month: may
monthnumber: 5
year: 2023
DOI: https://doi.org/10.1109/mi-sta57575.2023.10169623
bibdate: Thu Dec 7 11:55:39 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.07 11:55:39 ???
acknowledgement: ack-nhfb
rawauthor: Noor Alhuda Saad Adela and Amani Najeeb {Ben Yousuf} and Mohamed Muftah Eljhani
booktitle:
2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA)

title:
Design and Implementation of Single Precision Floating-point Arithmetic Logic Unit for RISC Processor on FPGA

rawbooktitle:
{2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA)}

rawtitle:
Design and Implementation of Single Precision Floating-point Arithmetic Logic Unit for {RISC} Processor on {FPGA}

entry:
@InProceedings{Adela:2023:DIS,
  author =       "Noor Alhuda Saad Adela and Amani Najeeb {Ben Yousuf}
                 and Mohamed Muftah Eljhani",
  booktitle =    "{2023 IEEE 3rd International Maghreb Meeting of the
                 Conference on Sciences and Techniques of Automatic
                 Control and Computer Engineering (MI-STA)}",
  title =        "Design and Implementation of Single Precision
                 Floating-point Arithmetic Logic Unit for {RISC}
                 Processor on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "130--134",
  month =        may,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/mi-sta57575.2023.10169623",
  bibdate =      "Thu Dec 7 11:55:39 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Alapati:2023:HIP
author: Madhu Sravya Alapati and Raghunandan Swain and Asisa Kumar Panigrahy
editor: IEEE
booktitle: 2023 7th International Conference on Trends in Electronics and Informatics (ICOEI)
title: Hardware Implementation of Posit Numeration System using FPGA for Signal Processing Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 278--282
year: 2023
DOI: https://doi.org/10.1109/ICOEI56765.2023.10125920
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Madhu Sravya Alapati and Raghunandan Swain and Asisa Kumar Panigrahy
rawbooktitle: {2023 7th International Conference on Trends in Electronics and Informatics (ICOEI)}
raweditor: {IEEE}
rawtitle: Hardware Implementation of Posit Numeration System using {FPGA} for Signal Processing Applications
entry:
@InProceedings{Alapati:2023:HIP,
  author =       "Madhu Sravya Alapati and Raghunandan Swain and Asisa
                 Kumar Panigrahy",
  editor =       "{IEEE}",
  booktitle =    "{2023 7th International Conference on Trends in
                 Electronics and Informatics (ICOEI)}",
  title =        "Hardware Implementation of Posit Numeration System
                 using {FPGA} for Signal Processing Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "278--282",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICOEI56765.2023.10125920",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Allred:2023:FNT
author: Taylor Allred and Xinyi Li and Ashton Wiersdorf and Ben Greenman and Ganesh Gopalakrishnan
booktitle: Julia Conference 2023
title: FlowFPX: Nimble Tools for Debugging Floating-Point Exceptions
pages: 8
year: 2023
bibdate: Mon Sep 11 06:29:11 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/julia.bib
bibtimestamp: 2023.09.11 06:29:11 ???
URL: https://live.juliacon.org/talk/A3LVDS
keywords: Julia programming language
acknowledgement: ack-nhfb
rawauthor: Taylor Allred and Xinyi Li and Ashton Wiersdorf and Ben Greenman and Ganesh Gopalakrishnan
rawbooktitle: Julia Conference 2023
rawtitle: {FlowFPX}: Nimble Tools for Debugging Floating-Point Exceptions
abstract:
Reliable numerical computations are central to scientific computing, but the floating-point arithmetic that enables large-scale models is error-prone. Numeric exceptions are a common occurrence and can propagate through code, leading to flawed results. This paper presents FlowFPX, a toolkit for systematically debugging floating-point exceptions by recording their flow, coalescing exception contexts, and fuzzing in select locations. These tools help scientists discover when exceptions happen and track down their origin, smoothing the way to a reliable codebase.

rawabstract:
Reliable numerical computations are central to scientific computing, but the floating-point arithmetic that enables large-scale models is error-prone. Numeric exceptions are a common occurrence and can propagate through code, leading to flawed results. This paper presents FlowFPX, a toolkit for systematically debugging floating-point exceptions by recording their flow, coalescing exception contexts, and fuzzing in select locations. These tools help scientists discover when exceptions happen and track down their origin, smoothing the way to a reliable codebase.

entry:
@InProceedings{Allred:2023:FNT,
  author =       "Taylor Allred and Xinyi Li and Ashton Wiersdorf and
                 Ben Greenman and Ganesh Gopalakrishnan",
  editor =       "????",
  booktitle =    "Julia Conference 2023",
  title =        "{FlowFPX}: Nimble Tools for Debugging Floating-Point
                 Exceptions",
  publisher =    "????",
  address =      "????",
  pages =        "8",
  year =         "2023",
  bibdate =      "Mon Sep 11 06:29:11 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/julia.bib",
  URL =          "https://live.juliacon.org/talk/A3LVDS",
  abstract =     "Reliable numerical computations are central to
                 scientific computing, but the floating-point arithmetic
                 that enables large-scale models is error-prone. Numeric
                 exceptions are a common occurrence and can propagate
                 through code, leading to flawed results. This paper
                 presents FlowFPX, a toolkit for systematically
                 debugging floating-point exceptions by recording their
                 flow, coalescing exception contexts, and fuzzing in
                 select locations. These tools help scientists discover
                 when exceptions happen and track down their origin,
                 smoothing the way to a reliable codebase.",
  acknowledgement = ack-nhfb,
  keywords =     "Julia programming language",
}


bibtype: article
filename: fparith.bib
label: Andrlon:2023:FNB
author: Mak Andrlon
title: Finding Normal Binary Floating-Point Factors Efficiently
journal: j-J-AUTOM-REASON
volume: 67
number: 1
pages: ??--??
month: mar
monthnumber: 3
year: 2023
CODEN: JAREEW
DOI: https://doi.org/10.1007/s10817-023-09659-1
ISSN: 0168-7433 (print), 1573-0670 (electronic) OR 01687433 (print), 15730670 (electronic)
ISSNL: 0168-7433 OR 01687433
bibdate: Mon Nov 27 10:20:09 MST 2023
bibtimestamp: 2023.11.27 10:20:09 MST
URL: https://link.springer.com/article/10.1007/s10817-023-09659-1
fjournal: Journal of Automated Reasoning
acknowledgement: ack-nhfb
ajournal: J. Autom. Reason.
articleno: 11
journalURL: http://link.springer.com/journal/10817
rawauthor: Mak Andrlon
rawtitle: Finding Normal Binary Floating-Point Factors Efficiently
entry:
@Article{Andrlon:2023:FNB,
  author =       "Mak Andrlon",
  title =        "Finding Normal Binary Floating-Point Factors
                 Efficiently",
  journal =      j-J-AUTOM-REASON,
  volume =       "67",
  number =       "1",
  pages =        "??--??",
  month =        mar,
  year =         "2023",
  CODEN =        "JAREEW",
  DOI =          "https://doi.org/10.1007/s10817-023-09659-1",
  ISSN =         "0168-7433 (print), 1573-0670 (electronic)",
  ISSN-L =       "0168-7433",
  bibdate =      "Mon Nov 27 10:20:09 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jautomreason.bib",
  URL =          "https://link.springer.com/article/10.1007/s10817-023-09659-1",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Autom. Reason.",
  articleno =    "11",
  fjournal =     "Journal of Automated Reasoning",
  journal-URL =  "http://link.springer.com/journal/10817",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2023:IWG
author: Anonymous
title: IEEE Working Group P3109 Interim Report on 8-bit Binary Floating-Point Formats
pages: 18
day: 18
month: sep
monthnumber: 9
year: 2023
bibdate: Thu Nov 30 05:10:41 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.30 05:10:41 ???
note: Version 0.5.1: 24 November 2023.
URL: https://github.com/P3109/Public/blob/main/Shared%20Reports/P3109%20WG%20Interim%20report.pdf
acknowledgement: ack-nhfb
howpublished: IEEE Web document.
rawauthor: Anonymous
rawnote: Version 0.5.1: 24 November 2023.
rawtitle: {IEEE Working Group P3109} Interim Report on 8-bit Binary Floating-Point Formats
remark:
The draft specifies encodings of unsigned zero, +/-Infinity, and quiet NaN, with precision 3, 4, and 5 bits (including the implicit not-stored leading bit), and subnormals.

entry:
@Misc{Anonymous:2023:IWG,
  author =       "Anonymous",
  title =        "{IEEE Working Group P3109} Interim Report on 8-bit
                 Binary Floating-Point Formats",
  howpublished = "IEEE Web document.",
  pages =        "18",
  day =          "18",
  month =        sep,
  year =         "2023",
  bibdate =      "Thu Nov 30 05:10:41 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Version 0.5.1: 24 November 2023.",
  URL =          "https://github.com/P3109/Public/blob/main/Shared%20Reports/P3109%20WG%20Interim%20report.pdf",
  acknowledgement = ack-nhfb,
  remark =       "The draft specifies encodings of unsigned zero,
                 +/-Infinity, and quiet NaN, with precision 3, 4, and 5
                 bits (including the implicit not-stored leading bit),
                 and subnormals.",
}


bibtype: techreport
filename: fparith.bib
label: Anonymous:2023:TDT
author: Anonymous
type: Report
institution: Tesla. Inc.
pages: 9
year: 2023
bibdate: Thu Nov 30 05:53:41 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.30 05:53:41 ???
URL: https://tesla-cdn.thron.com/static/MXMU3S_tesla-dojo-technology_1WDVZN.pdf
acknowledgement: ack-nhfb
rawauthor: Anonymous
title:
Tesla Dojo Technology: a guide to Tesla's configurable floating point formats and arithmetic: Tesla Configurable Float8 (CFloat8) & Float16 (CFloat16) Formats

abstract:
This standard specifies Tesla arithmetic formats and methods for the new 8-bit and 16-bit binary floating-point arithmetic in computer programming environments for deep learning neural network training. This standard also specifies exception conditions and the status flags thereof. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware

rawabstract:
This standard specifies Tesla arithmetic formats and methods for the new 8-bit and 16-bit binary floating-point arithmetic in computer programming environments for deep learning neural network training. This standard also specifies exception conditions and the status flags thereof. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware

rawtitle:
{Tesla Dojo Technology}: a guide to {Tesla}'s configurable floating point formats and arithmetic: {Tesla Configurable Float8 (CFloat8) \& Float16 (CFloat16)} Formats

entry:
@TechReport{Anonymous:2023:TDT,
  author =       "Anonymous",
  title =        "{Tesla Dojo Technology}: a guide to {Tesla}'s
                 configurable floating point formats and arithmetic:
                 {Tesla Configurable Float8 (CFloat8) \& Float16
                 (CFloat16)} Formats",
  type =         "Report",
  institution =  "Tesla. Inc.",
  pages =        "9",
  year =         "2023",
  bibdate =      "Thu Nov 30 05:53:41 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://tesla-cdn.thron.com/static/MXMU3S_tesla-dojo-technology_1WDVZN.pdf",
  abstract =     "This standard specifies Tesla arithmetic formats and
                 methods for the new 8-bit and 16-bit binary
                 floating-point arithmetic in computer programming
                 environments for deep learning neural network training.
                 This standard also specifies exception conditions and
                 the status flags thereof. An implementation of a
                 floating-point system conforming to this standard may
                 be realized entirely in software, entirely in hardware,
                 or in any combination of software and hardware",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: ARM:2023:ACA
author: ARM Corporation
title: ARM Compiler ARM C and C++ Libraries and Floating-Point Support User Guide Version 6.00
pages: 9
year: 2023
bibdate: Fri Dec 01 12:34:49 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.01 12:34:49 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: {ARM Corporation}
rawtitle: {ARM} Compiler {ARM C} and {C++} Libraries and Floating-Point Support User Guide Version 6.00
URL:
https://developer.arm.com/documentation/dui0808/a/floating-point-support/exception-types-recognized-by-the-arm-floating-point-environment

entry:
@Misc{ARM:2023:ACA,
  author =       "{ARM Corporation}",
  title =        "{ARM} Compiler {ARM C} and {C++} Libraries and
                 Floating-Point Support User Guide Version 6.00",
  howpublished = "Web site",
  year =         "2023",
  bibdate =      "Fri Dec 01 12:34:49 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://developer.arm.com/documentation/dui0808/a/floating-point-support/exception-types-recognized-by-the-arm-floating-point-environment",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Awais:2023:TOS
title: Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs
journal: j-TECS
volume: 22
number: 4
pages: 76:1--76:??
month: jul
monthnumber: 7
year: 2023
DOI: https://doi.org/10.1145/3564243
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Aug 10 07:21:24 MDT 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2023.08.10 07:21:24 MDT
URL: https://dl.acm.org/doi/10.1145/3564243
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
ajournal: ACM Trans. Embed. Comput. Syst.
articleno: 76
journalURL: https://dl.acm.org/loi/tecs
rawtitle: Toward Optimal Softcore Carry-aware Approximate Multipliers on {Xilinx} {FPGAs}
author:
Muhammad Awais and Ali Zahir and Syed Ayaz Ali Shah and Pedro Reviriego and Anees Ullah and Nasim Ullah and Adam Khan and Hazrat Ali

abstract:
Domain-specific accelerators for signal processing, image processing, and machine learning are increasingly being implemented on SRAM-based field-programmable gate arrays (FPGAs). Owing to the inherent error tolerance of such applications, approximate arithmetic operations, in particular, the design of approximate multipliers, have become an important research problem. Truncation of lower bits is a widely used approximation approach; however, analyzing and limiting the effects of carry-propagation due to this approximation has not been explored in detail yet. In this article, an optimized carry-aware approximate radix-4 Booth multiplier design is presented that leverages the built-in slice look-up tables (LUTs) and carry-chain resources in a novel configuration. The proposed multiplier simplifies the computation of the upper and lower bits and provides significant benefits in terms of FPGA resource usage (LUTs saving 38.5%--42.9%), Power Delay Product (PDP saving 49.4%--53%), performance metric (LUTs $ times $ critical path delay (CPD) $ times $ PDP saving 68.9%--73.1%) and errors (70% improvement in mean relative error distance) compared to the latest state-of-the-art designs. Therefore, the proposed designs are an attractive choice to implement multiplication on FPGA-based accelerators.

rawabstract:
Domain-specific accelerators for signal processing, image processing, and machine learning are increasingly being implemented on SRAM-based field-programmable gate arrays (FPGAs). Owing to the inherent error tolerance of such applications, approximate arithmetic operations, in particular, the design of approximate multipliers, have become an important research problem. Truncation of lower bits is a widely used approximation approach; however, analyzing and limiting the effects of carry-propagation due to this approximation has not been explored in detail yet. In this article, an optimized carry-aware approximate radix-4 Booth multiplier design is presented that leverages the built-in slice look-up tables (LUTs) and carry-chain resources in a novel configuration. The proposed multiplier simplifies the computation of the upper and lower bits and provides significant benefits in terms of FPGA resource usage (LUTs saving 38.5\%--42.9\%), Power Delay Product (PDP saving 49.4\%--53\%), performance metric (LUTs $ \times $ critical path delay (CPD) $ \times $ PDP saving 68.9\%--73.1\%) and errors (70\% improvement in mean relative error distance) compared to the latest state-of-the-art designs. Therefore, the proposed designs are an attractive choice to implement multiplication on FPGA-based accelerators.

rawauthor:
Muhammad Awais and Ali Zahir and Syed Ayaz Ali Shah and Pedro Reviriego and Anees Ullah and Nasim Ullah and Adam Khan and Hazrat Ali

entry:
@Article{Awais:2023:TOS,
  author =       "Muhammad Awais and Ali Zahir and Syed Ayaz Ali Shah
                 and Pedro Reviriego and Anees Ullah and Nasim Ullah and
                 Adam Khan and Hazrat Ali",
  title =        "Toward Optimal Softcore Carry-aware Approximate
                 Multipliers on {Xilinx} {FPGAs}",
  journal =      j-TECS,
  volume =       "22",
  number =       "4",
  pages =        "76:1--76:??",
  month =        jul,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3564243",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Aug 10 07:21:24 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3564243",
  abstract =     "Domain-specific accelerators for signal processing,
                 image processing, and machine learning are increasingly
                 being implemented on SRAM-based field-programmable gate
                 arrays (FPGAs). Owing to the inherent error tolerance
                 of such applications, approximate arithmetic
                 operations, in particular, the design of approximate
                 multipliers, have become an important research problem.
                 Truncation of lower bits is a widely used approximation
                 approach; however, analyzing and limiting the effects
                 of carry-propagation due to this approximation has not
                 been explored in detail yet. In this article, an
                 optimized carry-aware approximate radix-4 Booth
                 multiplier design is presented that leverages the
                 built-in slice look-up tables (LUTs) and carry-chain
                 resources in a novel configuration. The proposed
                 multiplier simplifies the computation of the upper and
                 lower bits and provides significant benefits in terms
                 of FPGA resource usage (LUTs saving 38.5\%--42.9\%),
                 Power Delay Product (PDP saving 49.4\%--53\%),
                 performance metric (LUTs $ \times $ critical path delay
                 (CPD) $ \times $ PDP saving 68.9\%--73.1\%) and errors
                 (70\% improvement in mean relative error distance)
                 compared to the latest state-of-the-art designs.
                 Therefore, the proposed designs are an attractive
                 choice to implement multiplication on FPGA-based
                 accelerators.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Embed. Comput. Syst.",
  articleno =    "76",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "https://dl.acm.org/loi/tecs",
}


bibtype: inproceedings
filename: fparith.bib
label: Badizadegan:2023:NRI
author: Nima Badizadegan
title: Newton--Raphson Integer Division for Area-Constrained Microcontrollers
crossref: IEEE:2023:PIS
pages: 9--15
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00024
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Nima Badizadegan
rawtitle: {Newton--Raphson} Integer Division for Area-Constrained Microcontrollers
keywords:
Approximation algorithms; Approximation methods; ARITH 2023; ARITH-30; Costs; Digital arithmetic; Division; Hardware; Integer Division; Iterative algorithms; Logic gates; Microarchitecture; Microcontrollers; Newton Raphson division; Newton Raphson method

entry:
@InProceedings{Badizadegan:2023:NRI,
  author =       "Nima Badizadegan",
  title =        "{Newton--Raphson} Integer Division for
                 Area-Constrained Microcontrollers",
  crossref =     "IEEE:2023:PIS",
  pages =        "9--15",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00024",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; Approximation methods; ARITH
                 2023; ARITH-30; Costs; Digital arithmetic; Division;
                 Hardware; Integer Division; Iterative algorithms; Logic
                 gates; Microarchitecture; Microcontrollers; Newton
                 Raphson division; Newton Raphson method",
}


bibtype: article
filename: fparith.bib
label: Bahoo:2023:EEG
author: Ali Akbar Bahoo and Omid Akbari and Muhammad Shafique
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 11
number: 4
pages: 851--867
month: oct
monthnumber: 10
year: 2023
DOI: https://doi.org/10.1109/TETC.2023.3279419
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Fri Apr 12 08:11:23 2024
bibtimestamp: 2024.04.12 08:11:23 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Ali Akbar Bahoo and Omid Akbari and Muhammad Shafique
title:
An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling

keywords:
Adders; Aging; Approximate computing; Complexity theory; Energy efficiency; energy efficiency; multiplier; Voltage; Voltage control; voltage overscaling

rawtitle:
An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling

entry:
@Article{Bahoo:2023:EEG,
  author =       "Ali Akbar Bahoo and Omid Akbari and Muhammad
                 Shafique",
  title =        "An Energy-Efficient Generic Accuracy Configurable
                 Multiplier Based on Block-Level Voltage Overscaling",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "11",
  number =       "4",
  pages =        "851--867",
  month =        oct # "\slash " # dec,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TETC.2023.3279419",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Fri Apr 12 08:11:23 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
  keywords =     "Adders; Aging; Approximate computing; Complexity
                 theory; Energy efficiency; energy efficiency;
                 multiplier; Voltage; Voltage control; voltage
                 overscaling",
}


bibtype: article
filename: fparith.bib
label: Bartels:2023:FFP
author: Tinko Bartels and Vissarion Fisikopoulos and Martin Weiser
title: Fast floating-point filters for robust predicates
journal: j-BIT-NUM-MATH
volume: 63
number: 2
pages: ??--??
month: jun
monthnumber: 6
year: 2023
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-023-00975-x
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Thu Aug 10 14:23:15 MDT 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.08.10 14:23:15 MDT
URL: https://link.springer.com/article/10.1007/s10543-023-00975-x
fjournal: BIT Numerical Mathematics
keywords: correct rounding; exact computation; floating-point arithmetic; rounding errors
acknowledgement: ack-nhfb
ajournal: Bit Num. Math.
articleno: 31
journalURL: http://link.springer.com/journal/10543
rawauthor: Tinko Bartels and Vissarion Fisikopoulos and Martin Weiser
rawtitle: Fast floating-point filters for robust predicates
abstract:
Geometric predicates are at the core of many algorithms, such as the construction of Delaunay triangulations, mesh processing and spatial relation tests. These algorithms have applications in scientific computing, geographic information systems and computer-aided design. With floating-point arithmetic, these geometric predicates can incur round-off errors that may lead to incorrect results and inconsistencies, causing computations to fail. This issue has been addressed using a combination of exact arithmetic for robustness and floating-point filters to mitigate the computational cost of exact computations. The implementation of exact computations and floating-point filters can be a difficult task, and code generation tools have been proposed to address this. We present a new C++ meta-programming framework for the generation of fast, robust predicates for arbitrary geometric predicates based on polynomial expressions. We combine and extend different approaches to filtering, branch reduction, and overflow avoidance that have previously been proposed. We show examples of how this approach produces correct results for data sets that could lead to incorrect predicate results with naive implementations. Our benchmark results demonstrate that our implementation surpasses state-of-the-art implementations.

rawabstract:
Geometric predicates are at the core of many algorithms, such as the construction of Delaunay triangulations, mesh processing and spatial relation tests. These algorithms have applications in scientific computing, geographic information systems and computer-aided design. With floating-point arithmetic, these geometric predicates can incur round-off errors that may lead to incorrect results and inconsistencies, causing computations to fail. This issue has been addressed using a combination of exact arithmetic for robustness and floating-point filters to mitigate the computational cost of exact computations. The implementation of exact computations and floating-point filters can be a difficult task, and code generation tools have been proposed to address this. We present a new C++ meta-programming framework for the generation of fast, robust predicates for arbitrary geometric predicates based on polynomial expressions. We combine and extend different approaches to filtering, branch reduction, and overflow avoidance that have previously been proposed. We show examples of how this approach produces correct results for data sets that could lead to incorrect predicate results with naive implementations. Our benchmark results demonstrate that our implementation surpasses state-of-the-art implementations.

entry:
@Article{Bartels:2023:FFP,
  author =       "Tinko Bartels and Vissarion Fisikopoulos and Martin
                 Weiser",
  title =        "Fast floating-point filters for robust predicates",
  journal =      j-BIT-NUM-MATH,
  volume =       "63",
  number =       "2",
  pages =        "??--??",
  month =        jun,
  year =         "2023",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-023-00975-x",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Thu Aug 10 14:23:15 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10543-023-00975-x",
  abstract =     "Geometric predicates are at the core of many
                 algorithms, such as the construction of Delaunay
                 triangulations, mesh processing and spatial relation
                 tests. These algorithms have applications in scientific
                 computing, geographic information systems and
                 computer-aided design. With floating-point arithmetic,
                 these geometric predicates can incur round-off errors
                 that may lead to incorrect results and inconsistencies,
                 causing computations to fail. This issue has been
                 addressed using a combination of exact arithmetic for
                 robustness and floating-point filters to mitigate the
                 computational cost of exact computations. The
                 implementation of exact computations and floating-point
                 filters can be a difficult task, and code generation
                 tools have been proposed to address this. We present a
                 new C++ meta-programming framework for the generation
                 of fast, robust predicates for arbitrary geometric
                 predicates based on polynomial expressions. We combine
                 and extend different approaches to filtering, branch
                 reduction, and overflow avoidance that have previously
                 been proposed. We show examples of how this approach
                 produces correct results for data sets that could lead
                 to incorrect predicate results with naive
                 implementations. Our benchmark results demonstrate that
                 our implementation surpasses state-of-the-art
                 implementations.",
  acknowledgement = ack-nhfb,
  ajournal =     "Bit Num. Math.",
  articleno =    "31",
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
  keywords =     "correct rounding; exact computation; floating-point
                 arithmetic; rounding errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Bavier:2023:VNF
author: Eric Bavier and Nicholas Knight and Hugues de Lassus Saint-Genies and Eric Love
title: Vectorized Nonlinear Functions with the RISC-V Vector Extension
crossref: IEEE:2023:PIS
pages: 127--130
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00032
bibdate: Wed May 8 09:17:31 2024
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Eric Bavier and Nicholas Knight and Hugues de Lassus Saint-Geni{\`e}s and Eric Love
rawtitle: Vectorized Nonlinear Functions with the {RISC-V} Vector Extension
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

keywords:
ARITH 2023; ARITH-30; floating point; Instruction sets; Libraries; Pipelines; RISC-V vectors; scalable vectors; Software; Software algorithms; vector mathematical functions; Vectors; Writing

entry:
@InProceedings{Bavier:2023:VNF,
  author =       "Eric Bavier and Nicholas Knight and Hugues de Lassus
                 Saint-Geni{\`e}s and Eric Love",
  title =        "Vectorized Nonlinear Functions with the {RISC-V}
                 Vector Extension",
  crossref =     "IEEE:2023:PIS",
  pages =        "127--130",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00032",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; floating point; Instruction
                 sets; Libraries; Pipelines; RISC-V vectors; scalable
                 vectors; Software; Software algorithms; vector
                 mathematical functions; Vectors; Writing",
}


bibtype: article
filename: fparith.bib
label: Belorgey:2023:MFE
journal: j-J-CRYPTOLOGY
volume: 36
number: 3
pages: ??--??
month: jul
monthnumber: 7
year: 2023
CODEN: JOCREQ
DOI: https://doi.org/10.1007/s00145-023-09464-4
ISSN: 0933-2790 (print), 1432-1378 (electronic) OR 09332790 (print), 14321378 (electronic)
ISSNL: 0933-2790 OR 09332790
bibdate: Tue Aug 1 08:28:21 MDT 2023
bibtimestamp: 2023.08.01 08:28:21 MDT
URL: https://link.springer.com/article/10.1007/s00145-023-09464-4
fjournal: Journal of Cryptology
acknowledgement: ack-nhfb
ajournal: J. Cryptology
articleno: 31
journalURL: http://link.springer.com/journal/145
author:
Mariya Georgieva Belorgey and Sergiu Carpov and Kevin Deforth and Dimitar Jetchev and Abson Sae-Tang and Marius Vuille and Nicolas Gama and Jon Katz and Iraklis Leontiadis and Mohsen Mohammadi

title:
Manticore: A Framework for Efficient Multiparty Computation Supporting Real Number and Boolean Arithmetic

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcryptology.bib

rawauthor:
Mariya Georgieva Belorgey and Sergiu Carpov and Kevin Deforth and Dimitar Jetchev and Abson Sae-Tang and Marius Vuille and Nicolas Gama and Jon Katz and Iraklis Leontiadis and Mohsen Mohammadi

rawtitle:
{Manticore}: A Framework for Efficient Multiparty Computation Supporting Real Number and {Boolean} Arithmetic

entry:
@Article{Belorgey:2023:MFE,
  author =       "Mariya Georgieva Belorgey and Sergiu Carpov and Kevin
                 Deforth and Dimitar Jetchev and Abson Sae-Tang and
                 Marius Vuille and Nicolas Gama and Jon Katz and Iraklis
                 Leontiadis and Mohsen Mohammadi",
  title =        "{Manticore}: A Framework for Efficient Multiparty
                 Computation Supporting Real Number and {Boolean}
                 Arithmetic",
  journal =      j-J-CRYPTOLOGY,
  volume =       "36",
  number =       "3",
  pages =        "??--??",
  month =        jul,
  year =         "2023",
  CODEN =        "JOCREQ",
  DOI =          "https://doi.org/10.1007/s00145-023-09464-4",
  ISSN =         "0933-2790 (print), 1432-1378 (electronic)",
  ISSN-L =       "0933-2790",
  bibdate =      "Tue Aug 1 08:28:21 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptology.bib",
  URL =          "https://link.springer.com/article/10.1007/s00145-023-09464-4",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Cryptology",
  articleno =    "31",
  fjournal =     "Journal of Cryptology",
  journal-URL =  "http://link.springer.com/journal/145",
}


bibtype: inproceedings
filename: fparith.bib
label: Beutel:2023:PFA
author: Moritz Beutel and Robert Strzodka
title: A Paradigm for Interval-Aware Programming
crossref: Gustafson:2023:NGA
pages: 38--60
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_3
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Moritz Beutel and Robert Strzodka
rawtitle: A Paradigm for Interval-Aware Programming
entry:
@InProceedings{Beutel:2023:PFA,
  author =       "Moritz Beutel and Robert Strzodka",
  title =        "A Paradigm for Interval-Aware Programming",
  crossref =     "Gustafson:2023:NGA",
  pages =        "38--60",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_3",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Blanchard:2023:NMD
author: Jeffrey D. Blanchard and Marc Chamberland
title: Newton's Method Without Division
journal: j-AMER-MATH-MONTHLY
volume: 130
number: 7
pages: 606--617
year: 2023
CODEN: AMMYAE
DOI: https://doi.org/10.1080/00029890.2022.2093573
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
bibdate: Fri Aug 25 08:24:37 MDT 2023
bibtimestamp: 2023.08.25 08:24:37 MDT
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: http://www.jstor.org/journals/00029890.html; https://www.tandfonline.com/loi/uamm20
onlinedate: 04 Aug 2023
rawauthor: Jeffrey D. Blanchard and Marc Chamberland
rawtitle: {Newton}'s Method Without Division
bibsource:
https://www.math.utah.edu/pub/tex/bib/amermathmonthly2020.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Blanchard:2023:NMD,
  author =       "Jeffrey D. Blanchard and Marc Chamberland",
  title =        "{Newton}'s Method Without Division",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "130",
  number =       "7",
  pages =        "606--617",
  year =         "2023",
  CODEN =        "AMMYAE",
  DOI =          "https://doi.org/10.1080/00029890.2022.2093573",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  bibdate =      "Fri Aug 25 08:24:37 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/amermathmonthly2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "http://www.jstor.org/journals/00029890.html;
                 https://www.tandfonline.com/loi/uamm20",
  onlinedate =   "04 Aug 2023",
}


bibtype: article
filename: fparith.bib
label: Boldo:2023:FPA
author: Sylvie Boldo and Claude-Pierre Jeannerod and Guillaume Melquiond and Jean-Michel Muller
title: Floating-point arithmetic
journal: j-ACTA-NUMERICA
volume: 32
pages: 203--290
month: may
monthnumber: 5
year: 2023
CODEN: ANUMFU
DOI: https://doi.org/10.1017/S0962492922000101
ISSN: 0962-4929 (print), 1474-0508 (electronic) OR 09624929 (print), 14740508 (electronic)
ISSNL: 0962-4929 OR 09624929
bibdate: Sat May 13 08:10:16 MDT 2023
bibtimestamp: 2023.05.13 08:10:16 MDT
fjournal: Acta Numerica
acknowledgement: ack-nhfb
ajournal: Acta Numer.
journalURL: http://journals.cambridge.org/action/displayJournal?jid=ANU
onlinedate: 11 May 2023
rawauthor: Sylvie Boldo and Claude-Pierre Jeannerod and Guillaume Melquiond and Jean-Michel Muller
rawtitle: Floating-point arithmetic
bibsource:
http://journals.cambridge.org/action/displayIssue?jid=ANU&volumeId=32&issueId=00; https://www.math.utah.edu/pub/tex/bib/actanumerica.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
https://www.cambridge.org/core/journals/acta-numerica/article/floatingpoint-arithmetic/287C4D5F6D4A43FBEEB1ABED2A405AAF

entry:
@Article{Boldo:2023:FPA,
  author =       "Sylvie Boldo and Claude-Pierre Jeannerod and Guillaume
                 Melquiond and Jean-Michel Muller",
  title =        "Floating-point arithmetic",
  journal =      j-ACTA-NUMERICA,
  volume =       "32",
  pages =        "203--290",
  month =        may,
  year =         "2023",
  CODEN =        "ANUMFU",
  DOI =          "https://doi.org/10.1017/S0962492922000101",
  ISSN =         "0962-4929 (print), 1474-0508 (electronic)",
  ISSN-L =       "0962-4929",
  bibdate =      "Sat May 13 08:10:16 MDT 2023",
  bibsource =    "http://journals.cambridge.org/action/displayIssue?jid=ANU&volumeId=32&issueId=00;
                 https://www.math.utah.edu/pub/tex/bib/actanumerica.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.cambridge.org/core/journals/acta-numerica/article/floatingpoint-arithmetic/287C4D5F6D4A43FBEEB1ABED2A405AAF",
  acknowledgement = ack-nhfb,
  ajournal =     "Acta Numer.",
  fjournal =     "Acta Numerica",
  journal-URL =  "http://journals.cambridge.org/action/displayJournal?jid=ANU",
  onlinedate =   "11 May 2023",
}


bibtype: article
filename: fparith.bib
label: Bommana:2023:DST
journal: j-TODAES
volume: 28
number: 3
pages: 32:1--32:??
month: may
monthnumber: 5
year: 2023
CODEN: ATASFO
DOI: https://doi.org/10.1145/3567423
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Wed May 17 08:06:20 MDT 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib
bibtimestamp: 2023.05.17 08:06:20 MDT
URL: https://dl.acm.org/doi/10.1145/3567423
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
articleno: 32
journalURL: https://dl.acm.org/loi/todaes
author:
Ashish Reddy Bommana and Susheel Ujwal Siddamshetty and Dhilleswararao Pudi and Arvind Thumatti K. R. and Srinivas Boppu and M. Sabarimalai Manikandan and Linga Reddy Cenkeramaddi

title:
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction

abstract:
Energy efficiency has become the new performance criterion in this era of pervasive embedded computing; thus, accelerator-rich multi-processor system-on-chips are commonly used in embedded computing hardware. Once computationally intensive machine learning applications gained much traction, they are now deployed in many application domains due to abundant and cheaply available computational capacity. In addition, there is a growing trend toward developing hardware accelerators for machine learning applications for embedded edge devices where performance and energy efficiency are critical. Although these hardware accelerators frequently use floating-point operations for accuracy, reduced-width floating-point formats are also used to reduce hardware complexity; thus, power consumption while maintaining accuracy. Vectorization concepts can also be used to improve performance, energy efficiency, and memory bandwidth. We propose the design of a vectorized floating-point adder/subtractor that supports arbitrary length floating-point formats with varying exponent and mantissa widths in this article. In comparison to existing designs in the literature, the proposed design is 2.57$ times $ area- and 1.56$ times $ power-efficient, and it supports true vectorization with no restrictions on exponent and mantissa widths.

rawabstract:
Energy efficiency has become the new performance criterion in this era of pervasive embedded computing; thus, accelerator-rich multi-processor system-on-chips are commonly used in embedded computing hardware. Once computationally intensive machine learning applications gained much traction, they are now deployed in many application domains due to abundant and cheaply available computational capacity. In addition, there is a growing trend toward developing hardware accelerators for machine learning applications for embedded edge devices where performance and energy efficiency are critical. Although these hardware accelerators frequently use floating-point operations for accuracy, reduced-width floating-point formats are also used to reduce hardware complexity; thus, power consumption while maintaining accuracy. Vectorization concepts can also be used to improve performance, energy efficiency, and memory bandwidth. We propose the design of a vectorized floating-point adder/subtractor that supports arbitrary length floating-point formats with varying exponent and mantissa widths in this article. In comparison to existing designs in the literature, the proposed design is 2.57$ \times $ area- and 1.56$ \times $ power-efficient, and it supports true vectorization with no restrictions on exponent and mantissa widths.

rawauthor:
Ashish Reddy Bommana and Susheel Ujwal Siddamshetty and Dhilleswararao Pudi and Arvind Thumatti K. R. and Srinivas Boppu and M. Sabarimalai Manikandan and Linga Reddy Cenkeramaddi

rawtitle:
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction

entry:
@Article{Bommana:2023:DST,
  author =       "Ashish Reddy Bommana and Susheel Ujwal Siddamshetty
                 and Dhilleswararao Pudi and Arvind Thumatti K. R. and
                 Srinivas Boppu and M. Sabarimalai Manikandan and Linga
                 Reddy Cenkeramaddi",
  title =        "Design of Synthesis-time Vectorized Arithmetic
                 Hardware for Tapered Floating-point Addition and
                 Subtraction",
  journal =      j-TODAES,
  volume =       "28",
  number =       "3",
  pages =        "32:1--32:??",
  month =        may,
  year =         "2023",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3567423",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Wed May 17 08:06:20 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3567423",
  abstract =     "Energy efficiency has become the new performance
                 criterion in this era of pervasive embedded computing;
                 thus, accelerator-rich multi-processor system-on-chips
                 are commonly used in embedded computing hardware. Once
                 computationally intensive machine learning applications
                 gained much traction, they are now deployed in many
                 application domains due to abundant and cheaply
                 available computational capacity. In addition, there is
                 a growing trend toward developing hardware accelerators
                 for machine learning applications for embedded edge
                 devices where performance and energy efficiency are
                 critical. Although these hardware accelerators
                 frequently use floating-point operations for accuracy,
                 reduced-width floating-point formats are also used to
                 reduce hardware complexity; thus, power consumption
                 while maintaining accuracy. Vectorization concepts can
                 also be used to improve performance, energy efficiency,
                 and memory bandwidth. We propose the design of a
                 vectorized floating-point adder/subtractor that
                 supports arbitrary length floating-point formats with
                 varying exponent and mantissa widths in this article.
                 In comparison to existing designs in the literature,
                 the proposed design is 2.57$ \times $ area- and 1.56$
                 \times $ power-efficient, and it supports true
                 vectorization with no restrictions on exponent and
                 mantissa widths.",
  acknowledgement = ack-nhfb,
  articleno =    "32",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}


bibtype: article
filename: fparith.bib
label: Bottcher:2023:TGO
author: Andreas Bottcher and Martin Kumm
title: Towards Globally Optimal Design of Multipliers for FPGAs
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 5
pages: 1261--1273
month: may
monthnumber: 5
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3238128
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Apr 28 11:15:52 2023
bibtimestamp: 2023.04.28 11:15:52 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Andreas B{\"o}ttcher and Martin Kumm
rawtitle: Towards Globally Optimal Design of Multipliers for {FPGAs}
entry:
@Article{Bottcher:2023:TGO,
  author =       "Andreas B{\"o}ttcher and Martin Kumm",
  title =        "Towards Globally Optimal Design of Multipliers for
                 {FPGAs}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "5",
  pages =        "1261--1273",
  month =        may,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3238128",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Apr 28 11:15:52 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2023:EUMb
author: Nicolas Brisebarre and Jean-Michel Muller and Joris Picot
crossref: IEEE:2023:PIS
pages: 88--88
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00036
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
keywords: ARITH 2023; ARITH-30; Digital arithmetic; Floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Jean-Michel Muller and Joris Picot
title:
Error in ulps of the multiplication or division by a correctly-rounded function or constant in binary floating-point arithmetic

note:
Published in ``IEEE Transactions on Emerging Topics in Computing, Volume: bf 11, Issue: 4, 01 October--December 2023'' and orally presented at ARITH 2023.

rawnote:
Published in ``IEEE Transactions on Emerging Topics in Computing, Volume: {\bf 11}, Issue: 4, 01 October--December 2023'' and orally presented at ARITH 2023.

rawtitle:
Error in ulps of the multiplication or division by a correctly-rounded function or constant in binary floating-point arithmetic

entry:
@InProceedings{Brisebarre:2023:EUMb,
  author =       "Nicolas Brisebarre and Jean-Michel Muller and Joris
                 Picot",
  title =        "Error in ulps of the multiplication or division by a
                 correctly-rounded function or constant in binary
                 floating-point arithmetic",
  crossref =     "IEEE:2023:PIS",
  pages =        "88--88",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00036",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in ``IEEE Transactions on Emerging Topics in
                 Computing, Volume: {\bf 11}, Issue: 4, 01
                 October--December 2023'' and orally presented at ARITH
                 2023.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Digital arithmetic;
                 Floating-point arithmetic",
}


bibtype: techreport
filename: fparith.bib
label: Brisebarre:2023:IPC
author: Nicolas Brisebarre and Guillaume Hanrot
title: Integer points close to a transcendental curve and correctly-rounded evaluation of a function
type: Preprint
institution: LIP --- Laboratoire de l'Informatique du Parallelisme
address: Lyon, France
pages: 66
year: 2023
bibdate: Fri Dec 08 10:07:21 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 10:07:21 ???
URL: https://hal.science/hal-03240179v4/file/tmd-hal-V4.pdf
keywords: correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Guillaume Hanrot
rawtitle: Integer points close to a transcendental curve and correctly-rounded evaluation of a function
abstract:
Despite several significant advances over the last 30 years, guaranteeing the correctly rounded evaluation of elementary functions, such as $ sqrt $, $ cos $, $ exp $, $ sqrt [3] $ for instance, is still a difficult issue. This can be formulated as a Diophantine approximation problem, called the Table Maker's Dilemma, which reduces to determining points with integer coordinates that are close to a curve. In this article, we propose two algorithmic approaches to tackle this problem, closely related to a celebrated work by Bombieri and Pila and to the so-called Coppersmith's method. We establish the underlying theoretical foundations, prove the algorithms, study their complexity and present practical experiments; we also compare our approach with previously existing ones. In particular, our results show that the development of a correctly rounded mathematical library for the binary128 format is now possible at a much smaller cost than with previously existing approaches

rawabstract:
Despite several significant advances over the last 30 years, guaranteeing the correctly rounded evaluation of elementary functions, such as $ \sqrt {} $, $ \cos $, $ \exp $, $ \sqrt [3]{} $ for instance, is still a difficult issue. This can be formulated as a Diophantine approximation problem, called the Table Maker's Dilemma, which reduces to determining points with integer coordinates that are close to a curve. In this article, we propose two algorithmic approaches to tackle this problem, closely related to a celebrated work by Bombieri and Pila and to the so-called Coppersmith's method. We establish the underlying theoretical foundations, prove the algorithms, study their complexity and present practical experiments; we also compare our approach with previously existing ones. In particular, our results show that the development of a correctly rounded mathematical library for the binary128 format is now possible at a much smaller cost than with previously existing approaches

entry:
@TechReport{Brisebarre:2023:IPC,
  author =       "Nicolas Brisebarre and Guillaume Hanrot",
  title =        "Integer points close to a transcendental curve and
                 correctly-rounded evaluation of a function",
  type =         "Preprint",
  institution =  "LIP --- Laboratoire de l'Informatique du
                 Parall{\'e}lisme",
  address =      "Lyon, France",
  pages =        "66",
  year =         "2023",
  bibdate =      "Fri Dec 08 10:07:21 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-03240179v4/file/tmd-hal-V4.pdf",
  abstract =     "Despite several significant advances over the last 30
                 years, guaranteeing the correctly rounded evaluation of
                 elementary functions, such as $ \sqrt {} $, $ \cos $, $
                 \exp $, $ \sqrt [3]{} $ for instance, is still a
                 difficult issue. This can be formulated as a
                 Diophantine approximation problem, called the Table
                 Maker's Dilemma, which reduces to determining points
                 with integer coordinates that are close to a curve. In
                 this article, we propose two algorithmic approaches to
                 tackle this problem, closely related to a celebrated
                 work by Bombieri and Pila and to the so-called
                 Coppersmith's method. We establish the underlying
                 theoretical foundations, prove the algorithms, study
                 their complexity and present practical experiments; we
                 also compare our approach with previously existing
                 ones. In particular, our results show that the
                 development of a correctly rounded mathematical library
                 for the binary128 format is now possible at a much
                 smaller cost than with previously existing approaches",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2023:TME
author: Nicolas Brisebarre and Silviu-Ioan Filip
title: Towards Machine-Efficient Rational $ L^infty $-Approximations of Mathematical Functions
crossref: IEEE:2023:PIS
pages: 119--126
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00029
bibdate: Wed May 8 09:17:31 2024
bibtimestamp: 2024.05.08 09:17:31 ???
keywords: Approximation algorithms; ARITH 2023; ARITH-30; Behavioral sciences; Digital arithmetic; Software
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Silviu-Ioan Filip
rawtitle: Towards Machine-Efficient Rational {$ L^\infty $}-Approximations of Mathematical Functions
entry:
@InProceedings{Brisebarre:2023:TME,
  author =       "Nicolas Brisebarre and Silviu-Ioan Filip",
  title =        "Towards Machine-Efficient Rational {$ L^\infty
                 $}-Approximations of Mathematical Functions",
  crossref =     "IEEE:2023:PIS",
  pages =        "119--126",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00029",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; ARITH 2023; ARITH-30;
                 Behavioral sciences; Digital arithmetic; Software",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2023:TSK
author: Nicolas Brisebarre and Jean-Michel Muller and Joris Picot
title: Testing the Sharpness of Known Error Bounds on the Fast Fourier Transform
crossref: IEEE:2023:PIS
pages: 89--92
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00027
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Jean-Michel Muller and Joris Picot
rawtitle: Testing the Sharpness of Known Error Bounds on the {Fast Fourier Transform}
keywords:
ARITH 2023; ARITH-30; Digital arithmetic; Error analysis; Fast Fourier Transform (FFT); Fast Fourier transforms; Floating-point arithmetic; Floating-Point arithmetic; Libraries; Testing

entry:
@InProceedings{Brisebarre:2023:TSK,
  author =       "Nicolas Brisebarre and Jean-Michel Muller and Joris
                 Picot",
  title =        "Testing the Sharpness of Known Error Bounds on the
                 {Fast Fourier Transform}",
  crossref =     "IEEE:2023:PIS",
  pages =        "89--92",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00027",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Digital arithmetic; Error
                 analysis; Fast Fourier Transform (FFT); Fast Fourier
                 transforms; Floating-point arithmetic; Floating-Point
                 arithmetic; Libraries; Testing",
}


bibtype: inproceedings
filename: fparith.bib
label: Brthel:2023:FTI
author: Moritz Barthel and Chen Yuxing and Nils Hulsmeier and Jochen Rust and Steffen Paul
title: Fused Three-Input SORN Arithmetic
crossref: Gustafson:2023:NGA
pages: 101--113
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_7
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Moritz B{\"a}rthel and Chen Yuxing and Nils H{\"u}lsmeier and Jochen Rust and Steffen Paul
rawtitle: Fused Three-Input {SORN} Arithmetic
entry:
@InProceedings{Brthel:2023:FTI,
  author =       "Moritz B{\"a}rthel and Chen Yuxing and Nils
                 H{\"u}lsmeier and Jochen Rust and Steffen Paul",
  title =        "Fused Three-Input {SORN} Arithmetic",
  crossref =     "Gustafson:2023:NGA",
  pages =        "101--113",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_7",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bruguera:2023:RFP
author: Javier D. Bruguera
title: Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 10
pages: 2990--3001
month: oct
monthnumber: 10
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3280136
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Sep 14 07:25:14 2023
bibtimestamp: 2023.09.14 07:25:14 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Javier D. Bruguera
rawtitle: Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units
abstract:
Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root. These iterative algorithms present a good trade-off in terms of performance, area and power. Traditionally, commercial processors have iterative division and square root units where the iteration logic is used over several cycles. The main drawbacks of these iterative units are long latency and low throughput due to the reuse of part of the logic over several cycles, and its hardware complexity with separated logic for division and square root. We present a radix-64 floating-point division and square root algorithm with a common iteration for division and square root and where, to have an affordable implementation, each radix-64 iteration is made of two simpler radix-8 iterations. The radix-64 algorithm allows to get low-latency operations, and the common division and square root radix-64 iteration results in some area reduction. The algorithm is mapped into two different microarchitectures: a low-latency and low area iterative unit, and a low-latency and high-throughput pipelined unit. In both units speculation between consecutive radix-8 iterations is used to reduce the timing.

rawabstract:
Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root. These iterative algorithms present a good trade-off in terms of performance, area and power. Traditionally, commercial processors have iterative division and square root units where the iteration logic is used over several cycles. The main drawbacks of these iterative units are long latency and low throughput due to the reuse of part of the logic over several cycles, and its hardware complexity with separated logic for division and square root. We present a radix-64 floating-point division and square root algorithm with a common iteration for division and square root and where, to have an affordable implementation, each radix-64 iteration is made of two simpler radix-8 iterations. The radix-64 algorithm allows to get low-latency operations, and the common division and square root radix-64 iteration results in some area reduction. The algorithm is mapped into two different microarchitectures: a low-latency and low area iterative unit, and a low-latency and high-throughput pipelined unit. In both units speculation between consecutive radix-8 iterations is used to reduce the timing.

entry:
@Article{Bruguera:2023:RFP,
  author =       "Javier D. Bruguera",
  title =        "Radix-64 Floating-Point Division and Square Root:
                 Iterative and Pipelined Units",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "10",
  pages =        "2990--3001",
  month =        oct,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3280136",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Sep 14 07:25:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Digit-recurrence algorithms are widely used in actual
                 microprocessors to compute floating-point division and
                 square root. These iterative algorithms present a good
                 trade-off in terms of performance, area and power.
                 Traditionally, commercial processors have iterative
                 division and square root units where the iteration
                 logic is used over several cycles. The main drawbacks
                 of these iterative units are long latency and low
                 throughput due to the reuse of part of the logic over
                 several cycles, and its hardware complexity with
                 separated logic for division and square root. We
                 present a radix-64 floating-point division and square
                 root algorithm with a common iteration for division and
                 square root and where, to have an affordable
                 implementation, each radix-64 iteration is made of two
                 simpler radix-8 iterations. The radix-64 algorithm
                 allows to get low-latency operations, and the common
                 division and square root radix-64 iteration results in
                 some area reduction. The algorithm is mapped into two
                 different microarchitectures: a low-latency and low
                 area iterative unit, and a low-latency and
                 high-throughput pipelined unit. In both units
                 speculation between consecutive radix-8 iterations is
                 used to reduce the timing.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Buckle:2023:HEY
author: David Buckle
title: How the estimate of $ sqrt 2 $ on YBC 7289 may have been calculated
journal: j-HIST-MATH
volume: 62
pages: 3--18
month: feb
monthnumber: 2
year: 2023
CODEN: HIMADS
DOI: https://doi.org/10.1016/j.hm.2022.08.002
ISSN: 0315-0860 (print), 1090-249X (electronic) OR 03150860 (print), 1090249X (electronic)
ISSNL: 0315-0860 OR 03150860
bibdate: Wed Mar 15 09:40:56 MDT 2023
bibtimestamp: 2023.03.15 09:40:56 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0315086022000477
fjournal: Historia Mathematica
keywords: Babylonian tablet YBC 7289
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03150860
rawauthor: David Buckle
rawtitle: How the estimate of $ \sqrt {2} $ on {YBC 7289} may have been calculated
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histmath.bib

abstract:
It remains unknown how the approximation of $ sqrt 2 $ scribed on Babylonian tablet YBC 7289 was calculated. In this article I show how it can be straightforwardly computed using a well-known regular number as the input for the Babylonian method of estimating square roots. My objective is to demonstrate that Babylonian mathematics was sufficiently evolved for the approximation to be easily derived and thus propose an approach that may have been used to calculate it.

rawabstract:
It remains unknown how the approximation of $ \sqrt {2} $ scribed on Babylonian tablet YBC 7289 was calculated. In this article I show how it can be straightforwardly computed using a well-known regular number as the input for the Babylonian method of estimating square roots. My objective is to demonstrate that Babylonian mathematics was sufficiently evolved for the approximation to be easily derived and thus propose an approach that may have been used to calculate it.

entry:
@Article{Buckle:2023:HEY,
  author =       "David Buckle",
  title =        "How the estimate of $ \sqrt {2} $ on {YBC 7289} may
                 have been calculated",
  journal =      j-HIST-MATH,
  volume =       "62",
  number =       "??",
  pages =        "3--18",
  month =        feb,
  year =         "2023",
  CODEN =        "HIMADS",
  DOI =          "https://doi.org/10.1016/j.hm.2022.08.002",
  ISSN =         "0315-0860 (print), 1090-249X (electronic)",
  ISSN-L =       "0315-0860",
  bibdate =      "Wed Mar 15 09:40:56 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histmath.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0315086022000477",
  abstract =     "It remains unknown how the approximation of $ \sqrt
                 {2} $ scribed on Babylonian tablet YBC 7289 was
                 calculated. In this article I show how it can be
                 straightforwardly computed using a well-known regular
                 number as the input for the Babylonian method of
                 estimating square roots. My objective is to demonstrate
                 that Babylonian mathematics was sufficiently evolved
                 for the approximation to be easily derived and thus
                 propose an approach that may have been used to
                 calculate it.",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Mathematica",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03150860",
  keywords =     "Babylonian tablet YBC 7289",
}


bibtype: article
filename: fparith.bib
label: Chen:2023:TLM
author: Benjamin Chen and Yu Li and Eugene Zima
title: On a Two-Layer Modular Arithmetic
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 57
number: 3
pages: 133--136
month: sep
monthnumber: 9
year: 2023
DOI: https://doi.org/10.1145/3637529.3637534
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Thu Dec 14 15:54:00 MST 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigsam.bib
bibtimestamp: 2023.12.14 15:54:00 MST
URL: https://dl.acm.org/doi/10.1145/3637529.3637534
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
ajournal: ACM Commun. Computer Algebr.
journalURL: https://dl.acm.org/loi/sigsam-cca
rawauthor: Benjamin Chen and Yu Li and Eugene Zima
rawtitle: On a Two-Layer Modular Arithmetic
abstract:
Two-layer organization of modular arithmetic is considered. Lower layer uses many moduli at hardware precision and simultaneous conversion to/from RNS as described in [2]. Upper layer uses specially selected large moduli allowing for fast reduction and / or reconstruction. Implementation of two different strategies for selecting moduli on the upper layer confirms practicality of proposed approach.

rawabstract:
Two-layer organization of modular arithmetic is considered. Lower layer uses many moduli at hardware precision and simultaneous conversion to/from RNS as described in [2]. Upper layer uses specially selected large moduli allowing for fast reduction and\slash or reconstruction. Implementation of two different strategies for selecting moduli on the upper layer confirms practicality of proposed approach.

entry:
@Article{Chen:2023:TLM,
  author =       "Benjamin Chen and Yu Li and Eugene Zima",
  title =        "On a Two-Layer Modular Arithmetic",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "57",
  number =       "3",
  pages =        "133--136",
  month =        sep,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3637529.3637534",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Thu Dec 14 15:54:00 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3637529.3637534",
  abstract =     "Two-layer organization of modular arithmetic is
                 considered. Lower layer uses many moduli at hardware
                 precision and simultaneous conversion to/from RNS as
                 described in [2]. Upper layer uses specially selected
                 large moduli allowing for fast reduction and\slash or
                 reconstruction. Implementation of two different
                 strategies for selecting moduli on the upper layer
                 confirms practicality of proposed approach.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Commun. Computer Algebr.",
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "https://dl.acm.org/loi/sigsam-cca",
}


bibtype: misc
filename: fparith.bib
label: Coonen:2023:IMP
author: Jerome Coonen and Rafi Nave
title: IEEE Milestone-Proposal: Intel 8087 Math Coprocessor
pages: 133--136
day: 21
month: sep
monthnumber: 9
year: 2023
bibdate: Sat Aug 23 07:49:24 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.08.23 07:49:24 ???
URL: https://ieeemilestones.ethw.org/Milestone-Proposal:Intel_8087_Math_Coprocessor
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Jerome Coonen and Rafi Nave
rawtitle: {IEEE} Milestone-Proposal: {Intel 8087} Math Coprocessor
entry:
@Misc{Coonen:2023:IMP,
  author =       "Jerome Coonen and Rafi Nave",
  title =        "{IEEE} Milestone-Proposal: {Intel 8087} Math
                 Coprocessor",
  howpublished = "Web site",
  day =          "21",
  month =        sep,
  year =         "2023",
  bibdate =      "Sat Aug 23 07:49:24 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeemilestones.ethw.org/Milestone-Proposal:Intel_8087_Math_Coprocessor",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Crespo:2023:TPP
author: Luis Crespo and Pedro Tomas and Nuno Roma and Nuno Neves
editor: IEEE
title: Trading Performance, Power, and Area on Low-Precision Posit MAC Units for CNN Training
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 46--56
year: 2023
DOI: https://doi.org/10.1109/SBAC-PAD59825.2023.00014
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Lu{\'\i}s Crespo and Pedro Tom{\'a}s and Nuno Roma and Nuno Neves
raweditor: {IEEE}
rawtitle: Trading Performance, Power, and Area on Low-Precision Posit {MAC} Units for {CNN} Training
booktitle:
2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

rawbooktitle:
{2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)}

entry:
@InProceedings{Crespo:2023:TPP,
  author =       "Lu{\'\i}s Crespo and Pedro Tom{\'a}s and Nuno Roma and
                 Nuno Neves",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 35th International Symposium on Computer
                 Architecture and High Performance Computing
                 (SBAC-PAD)}",
  title =        "Trading Performance, Power, and Area on Low-Precision
                 Posit {MAC} Units for {CNN} Training",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "46--56",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SBAC-PAD59825.2023.00014",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Defour:2023:CAN
author: David Defour and Franck Vedrine
title: Chromatic Analysis of Numerical Programs
crossref: IEEE:2023:PIS
pages: 97--100
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00012
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: David Defour and Franck Vedrine
rawtitle: Chromatic Analysis of Numerical Programs
keywords:
Additives; ARITH 2023; ARITH-30; Artificial neural networks; automatic differentiation; Digital arithmetic; Error analysis; IEEE-754; rounding error analysis; sensitivity analysis; Sensitivity analysis

entry:
@InProceedings{Defour:2023:CAN,
  author =       "David Defour and Franck Vedrine",
  title =        "Chromatic Analysis of Numerical Programs",
  crossref =     "IEEE:2023:PIS",
  pages =        "97--100",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00012",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Additives; ARITH 2023; ARITH-30; Artificial neural
                 networks; automatic differentiation; Digital
                 arithmetic; Error analysis; IEEE-754; rounding error
                 analysis; sensitivity analysis; Sensitivity analysis",
}


bibtype: inproceedings
filename: fparith.bib
label: deLamarliere:2023:SFP
author: Paul Geneau de Lamarliere and Guillaume Melquiond and Florian Faissole
title: Slimmer Formal Proofs for Mathematical Libraries
crossref: IEEE:2023:PIS
pages: 32--35
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00026
bibdate: Wed May 8 09:17:31 2024
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Paul Geneau de Lamarli{\`e}re and Guillaume Melquiond and Florian Faissole
rawtitle: Slimmer Formal Proofs for Mathematical Libraries
keywords:
ARITH 2023; ARITH-30; Behavioral sciences; Codes; Coq proof assistant; Costs; Digital arithmetic; Floating-point arithmetic; Formal methods; Libraries; Mathematical libraries; Writing

entry:
@InProceedings{deLamarliere:2023:SFP,
  author =       "Paul Geneau de Lamarli{\`e}re and Guillaume Melquiond
                 and Florian Faissole",
  title =        "Slimmer Formal Proofs for Mathematical Libraries",
  crossref =     "IEEE:2023:PIS",
  pages =        "32--35",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00026",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Behavioral sciences; Codes; Coq
                 proof assistant; Costs; Digital arithmetic;
                 Floating-point arithmetic; Formal methods; Libraries;
                 Mathematical libraries; Writing",
}


bibtype: inproceedings
filename: fparith.bib
label: Desrentes:2023:EDP
author: Oregane Desrentes and Benoit Dupont De Dinechin and Julien Le Maire
booktitle: 2023 26th Euromicro Conference on Digital System Design (DSD)
title: Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 642--649
year: 2023
DOI: https://doi.org/10.1109/DSD60849.2023.00093
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
keywords: Costs; Deep learning; Deep Learning; Digital systems; FP8; Posit8
acknowledgement: ack-nhfb
rawauthor: Or{\'e}gane Desrentes and Beno{\^\i}t Dupont {De Dinechin} and Julien {Le Maire}
rawbooktitle: {2023 26th Euromicro Conference on Digital System Design (DSD)}
rawtitle: Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning
entry:
@InProceedings{Desrentes:2023:EDP,
  author =       "Or{\'e}gane Desrentes and Beno{\^\i}t Dupont {De
                 Dinechin} and Julien {Le Maire}",
  booktitle =    "{2023 26th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Exact Dot Product Accumulate Operators for 8-bit
                 Floating-Point Deep Learning",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "642--649",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DSD60849.2023.00093",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Costs; Deep learning; Deep Learning; Digital systems;
                 FP8; Posit8",
}


bibtype: inproceedings
filename: fparith.bib
label: Desrentes:2023:EFD
author: Oregane Desrentes and Benoit Dupont de Dinechin and Florent de Dinechin
title: Exact Fused Dot Product Add Operators
crossref: IEEE:2023:PIS
pages: 151--158
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00016
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Or{\'e}gane Desrentes and Beno{\^\i}t Dupont de Dinechin and Florent de Dinechin
rawtitle: Exact Fused Dot Product Add Operators
keywords:
ARITH 2023; ARITH-30; BF16; Computer architecture; Digital arithmetic; dot product; FP32; FP64; Heuristic algorithms; High dynamic range; Low latency communication; three-term sum

entry:
@InProceedings{Desrentes:2023:EFD,
  author =       "Or{\'e}gane Desrentes and Beno{\^\i}t Dupont de
                 Dinechin and Florent de Dinechin",
  title =        "Exact Fused Dot Product Add Operators",
  crossref =     "IEEE:2023:PIS",
  pages =        "151--158",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00016",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; BF16; Computer architecture;
                 Digital arithmetic; dot product; FP32; FP64; Heuristic
                 algorithms; High dynamic range; Low latency
                 communication; three-term sum",
}


bibtype: article
filename: fparith.bib
label: Eckert:2023:EMM
title: Eidetic: an In-Memory Matrix Multiplication Accelerator for Neural Networks
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 6
pages: 1539--1553
month: jun
monthnumber: 6
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3214151
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed May 17 10:34:15 2023
bibtimestamp: 2023.05.17 10:34:15 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: {Eidetic}: an In-Memory Matrix Multiplication Accelerator for Neural Networks
author:
Charles Eckert and Arun Subramaniyan and Xiaowei Wang and Charles Augustine and Ravishankar Iyer and Reetuparna Das

abstract:
This paper presents the Eidetic architecture, which is an SRAM-based ASIC neural network accelerator that eliminates the need to continuously load weights from off-chip, while also minimizing the need to go off chip for intermediate results. Using in-situ arithmetic in the SRAM arrays, this architecture can supports a variety of precision types allowing for effective inference. We also present different data mapping policies for matrix-vector based networks (RNN and MLP) on the Eidetic architecture and describe the tradeoffs involved. With this architecture, multiple layers of a network can be concurrently mapped, storing both the layer weights and intermediate results on-chip, removing the energy and latency penalty of off-chip memory accesses. We evaluate Eidetic on Google's Neural Machine Translation System (GNMT) encoder and demonstrate a 17.20$ times $ increase in throughput and 7.77$ times $ reduction in average latency over a single TPUv2 chip.

rawabstract:
This paper presents the Eidetic architecture, which is an SRAM-based ASIC neural network accelerator that eliminates the need to continuously load weights from off-chip, while also minimizing the need to go off chip for intermediate results. Using in-situ arithmetic in the SRAM arrays, this architecture can supports a variety of precision types allowing for effective inference. We also present different data mapping policies for matrix-vector based networks (RNN and MLP) on the Eidetic architecture and describe the tradeoffs involved. With this architecture, multiple layers of a network can be concurrently mapped, storing both the layer weights and intermediate results on-chip, removing the energy and latency penalty of off-chip memory accesses. We evaluate Eidetic on Google's Neural Machine Translation System (GNMT) encoder and demonstrate a 17.20$ \times $ increase in throughput and 7.77$ \times $ reduction in average latency over a single TPUv2 chip.

rawauthor:
Charles Eckert and Arun Subramaniyan and Xiaowei Wang and Charles Augustine and Ravishankar Iyer and Reetuparna Das

entry:
@Article{Eckert:2023:EMM,
  author =       "Charles Eckert and Arun Subramaniyan and Xiaowei Wang
                 and Charles Augustine and Ravishankar Iyer and
                 Reetuparna Das",
  title =        "{Eidetic}: an In-Memory Matrix Multiplication
                 Accelerator for Neural Networks",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "6",
  pages =        "1539--1553",
  month =        jun,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3214151",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed May 17 10:34:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "This paper presents the Eidetic architecture, which is
                 an SRAM-based ASIC neural network accelerator that
                 eliminates the need to continuously load weights from
                 off-chip, while also minimizing the need to go off chip
                 for intermediate results. Using in-situ arithmetic in
                 the SRAM arrays, this architecture can supports a
                 variety of precision types allowing for effective
                 inference. We also present different data mapping
                 policies for matrix-vector based networks (RNN and MLP)
                 on the Eidetic architecture and describe the tradeoffs
                 involved. With this architecture, multiple layers of a
                 network can be concurrently mapped, storing both the
                 layer weights and intermediate results on-chip,
                 removing the energy and latency penalty of off-chip
                 memory accesses. We evaluate Eidetic on Google's Neural
                 Machine Translation System (GNMT) encoder and
                 demonstrate a 17.20$ \times $ increase in throughput
                 and 7.77$ \times $ reduction in average latency over a
                 single TPUv2 chip.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Edamatsu:2023:FMP
author: Takuya Edamatsu and Daisuke Takahashi
title: Fast Multiple-Precision Integer Division Using Intel AVX-512
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 11
number: 1
pages: 224--236
month: jan
monthnumber: 1
year: 2023
DOI: https://doi.org/10.1109/TETC.2022.3196147
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Takuya Edamatsu and Daisuke Takahashi
rawtitle: Fast Multiple-Precision Integer Division Using {Intel AVX-512}
abstract:
This paper reports on the implementation of a large integer division method that uses Intel Advanced Vector Extensions 512 (AVX-512), which is a 512-bit Single Instruction Multiple Data (SIMD) instruction set, and proposes a modification to a conventional division algorithm that makes it more SIMD instruction-friendly. More specifically, we use the Integer Fused Multiply-Add AVX-512 (AVX-512IFMA) subset, which is an instruction set that works well with large integer multiplication, to compute large integer divisions via a multiplication-based approach with a reciprocal. For the division process, we apply the most basic algorithm and divide-and-conquer methods and then use several techniques to compute efficiently with SIMD instructions in our implementation. We then combine these techniques and methods to implement our division function so that it can flexibly handle various sizes. To evaluate the performance of our proposed implementation, we executed our division program and the GNU Multiple Precision Arithmetic Library (GMP) on a Cannon Lake microarchitecture processor. A comparison of the execution times for our division program and GMP with various sizes showed that our method resulted in performance improvements of 25% to 35% on average, thus indicating that SIMD instructions are effective for fast arbitrary precision integer divisions.

rawabstract:
This paper reports on the implementation of a large integer division method that uses Intel Advanced Vector Extensions 512 (AVX-512), which is a 512-bit Single Instruction Multiple Data (SIMD) instruction set, and proposes a modification to a conventional division algorithm that makes it more SIMD instruction-friendly. More specifically, we use the Integer Fused Multiply-Add AVX-512 (AVX-512IFMA) subset, which is an instruction set that works well with large integer multiplication, to compute large integer divisions via a multiplication-based approach with a reciprocal. For the division process, we apply the most basic algorithm and divide-and-conquer methods and then use several techniques to compute efficiently with SIMD instructions in our implementation. We then combine these techniques and methods to implement our division function so that it can flexibly handle various sizes. To evaluate the performance of our proposed implementation, we executed our division program and the GNU Multiple Precision Arithmetic Library (GMP) on a Cannon Lake microarchitecture processor. A comparison of the execution times for our division program and GMP with various sizes showed that our method resulted in performance improvements of 25\% to 35\% on average, thus indicating that SIMD instructions are effective for fast arbitrary precision integer divisions.

entry:
@Article{Edamatsu:2023:FMP,
  author =       "Takuya Edamatsu and Daisuke Takahashi",
  title =        "Fast Multiple-Precision Integer Division Using {Intel
                 AVX-512}",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "11",
  number =       "1",
  pages =        "224--236",
  month =        jan # "\slash " # mar,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TETC.2022.3196147",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "This paper reports on the implementation of a large
                 integer division method that uses Intel Advanced Vector
                 Extensions 512 (AVX-512), which is a 512-bit Single
                 Instruction Multiple Data (SIMD) instruction set, and
                 proposes a modification to a conventional division
                 algorithm that makes it more SIMD instruction-friendly.
                 More specifically, we use the Integer Fused
                 Multiply-Add AVX-512 (AVX-512IFMA) subset, which is an
                 instruction set that works well with large integer
                 multiplication, to compute large integer divisions via
                 a multiplication-based approach with a reciprocal. For
                 the division process, we apply the most basic algorithm
                 and divide-and-conquer methods and then use several
                 techniques to compute efficiently with SIMD
                 instructions in our implementation. We then combine
                 these techniques and methods to implement our division
                 function so that it can flexibly handle various sizes.
                 To evaluate the performance of our proposed
                 implementation, we executed our division program and
                 the GNU Multiple Precision Arithmetic Library (GMP) on
                 a Cannon Lake microarchitecture processor. A comparison
                 of the execution times for our division program and GMP
                 with various sizes showed that our method resulted in
                 performance improvements of 25\% to 35\% on average,
                 thus indicating that SIMD instructions are effective
                 for fast arbitrary precision integer divisions.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Edavoor:2023:DAP
editor: IEEE
title: Design and Analysis of Posit Quire Processing Engine for Neural Network Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 252--257
year: 2023
DOI: https://doi.org/10.1109/VLSID57277.2023.00059
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
raweditor: {IEEE}
rawtitle: Design and Analysis of Posit Quire Processing Engine for Neural Network Applications
author:
Pranose J Edavoor and Aneesh Raveendran and David Selvakumar and Vivian Desalphine and Dharani Shankar G and Gopal Raut

booktitle:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)

rawauthor:
Pranose J Edavoor and Aneesh Raveendran and David Selvakumar and Vivian Desalphine and Dharani Shankar G and Gopal Raut

rawbooktitle:
{2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)}

entry:
@InProceedings{Edavoor:2023:DAP,
  author =       "Pranose J Edavoor and Aneesh Raveendran and David
                 Selvakumar and Vivian Desalphine and Dharani Shankar G
                 and Gopal Raut",
  editor =       "{IEEE}",
  booktitle =    "{2023 36th International Conference on VLSI Design and
                 2023 22nd International Conference on Embedded Systems
                 (VLSID)}",
  title =        "Design and Analysis of Posit Quire Processing Engine
                 for Neural Network Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "252--257",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSID57277.2023.00059",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: ElArar:2023:SRV
author: El-Mehdi El Arar and Devan Sohier and Pablo de Oliveira Castro and Eric Petit
title: Stochastic Rounding Variance and Probabilistic Bounds: a New Approach
journal: j-SIAM-J-SCI-COMP
volume: 45
number: 5
pages: C255--C275
month: oct
monthnumber: 10
year: 2023
CODEN: SJOCE3
DOI: https://doi.org/10.1137/22m1510819
ISSN: 1095-7197 OR 10957197
ISSNL: 1064-8275 OR 10648275
bibdate: Thu May 30 10:22:20 2024
bibtimestamp: 2024.05.30 10:22:20 ???
fjournal: SIAM Journal on Scientific Computing
keywords: error bounds; floating-point rounding; random rounding; stochastic rounding
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: El-Mehdi {El Arar} and Devan Sohier and Pablo de Oliveira Castro and Eric Petit
rawtitle: Stochastic Rounding Variance and Probabilistic Bounds: a New Approach
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{ElArar:2023:SRV,
  author =       "El-Mehdi {El Arar} and Devan Sohier and Pablo de
                 Oliveira Castro and Eric Petit",
  title =        "Stochastic Rounding Variance and Probabilistic Bounds:
                 a New Approach",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "45",
  number =       "5",
  pages =        "C255--C275",
  month =        oct,
  year =         "2023",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/22m1510819",
  ISSN =         "1095-7197",
  ISSN-L =       "1064-8275",
  bibdate =      "Thu May 30 10:22:20 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "error bounds; floating-point rounding; random
                 rounding; stochastic rounding",
}


bibtype: inproceedings
filename: fparith.bib
label: Fakhreddine:2023:ULT
author: Youssef Fakhreddine and Guillaume Revy
title: Using loop transformations for precision tuning in iterative programs
crossref: IEEE:2023:PIS
pages: 159--166
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00031
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Youssef Fakhreddine and Guillaume Revy
rawtitle: Using loop transformations for precision tuning in iterative programs
keywords:
ARITH 2023; ARITH-30; delta-debugging algorithm; Digital arithmetic; dynamic precision tuning tool; floating-point arithmetic; Instruction sets; Iterative methods; loop splitting and unrolling; mixed-precision; multiple-precision; Runtime; Tuning

entry:
@InProceedings{Fakhreddine:2023:ULT,
  author =       "Youssef Fakhreddine and Guillaume Revy",
  title =        "Using loop transformations for precision tuning in
                 iterative programs",
  crossref =     "IEEE:2023:PIS",
  pages =        "159--166",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00031",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; delta-debugging algorithm;
                 Digital arithmetic; dynamic precision tuning tool;
                 floating-point arithmetic; Instruction sets; Iterative
                 methods; loop splitting and unrolling; mixed-precision;
                 multiple-precision; Runtime; Tuning",
}


bibtype: inproceedings
filename: fparith.bib
label: Fan:2023:TFF
booktitle: 2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 798--808
year: 2023
DOI: https://doi.org/10.1109/IPDPS54959.2023.00085
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}
author:
Guang Fan and Fangyu Zheng and Lipeng Wan and Lili Gao and Yuan Zhao and Jiankuo Dong and Yixuan Song and Yuewu Wang and Jingqiang Lin

title:
Towards Faster Fully Homomorphic Encryption Implementation with Integer and Floating-point Computing Power of GPUs

keywords:
Arithmetic; Cryptography; Deep learning; Distributed processing; Floating point Computing Power; Fully Homomorphic Encryption; GPU; High Performance Implementation; Homomorphic encryption; Industries; Optimization

rawauthor:
Guang Fan and Fangyu Zheng and Lipeng Wan and Lili Gao and Yuan Zhao and Jiankuo Dong and Yixuan Song and Yuewu Wang and Jingqiang Lin

rawtitle:
Towards Faster Fully Homomorphic Encryption Implementation with Integer and Floating-point Computing Power of {GPUs}

entry:
@InProceedings{Fan:2023:TFF,
  author =       "Guang Fan and Fangyu Zheng and Lipeng Wan and Lili Gao
                 and Yuan Zhao and Jiankuo Dong and Yixuan Song and
                 Yuewu Wang and Jingqiang Lin",
  booktitle =    "{2023 IEEE International Parallel and Distributed
                 Processing Symposium (IPDPS)}",
  title =        "Towards Faster Fully Homomorphic Encryption
                 Implementation with Integer and Floating-point
                 Computing Power of {GPUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "798--808",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IPDPS54959.2023.00085",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Arithmetic; Cryptography; Deep learning; Distributed
                 processing; Floating point Computing Power; Fully
                 Homomorphic Encryption; GPU; High Performance
                 Implementation; Homomorphic encryption; Industries;
                 Optimization",
}


bibtype: article
filename: fparith.bib
label: Fasi:2023:CCL
author: Massimiliano Fasi and Mantas Mikaitis
title: CPFloat: a C Library for Simulating Low-precision Arithmetic
journal: j-TOMS
volume: 49
number: 2
pages: 18:1--18:??
month: jun
monthnumber: 6
year: 2023
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3585515
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Thu Jun 29 07:01:00 MDT 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2023.06.29 07:01:00 MDT
URL: https://dl.acm.org/doi/10.1145/3585515
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 18
journalURL: https://dl.acm.org/loi/toms
rawauthor: Massimiliano Fasi and Mantas Mikaitis
rawtitle: {CPFloat}: a {C} Library for Simulating Low-precision Arithmetic
abstract:
One can simulate low-precision floating-point arithmetic via software by executing each arithmetic operation in hardware and then rounding the result to the desired number of significant bits. For IEEE-compliant formats, rounding requires only standard mathematical library functions, but handling subnormals, underflow, and overflow demands special attention, and numerical errors can cause mathematically correct formulae to behave incorrectly in finite arithmetic. Moreover, the ensuing implementations are not necessarily efficient, as the library functions these techniques build upon are typically designed to handle a broad range of cases and may not be optimized for the specific needs of rounding algorithms. CPFloat is a C library for simulating low-precision arithmetics. It offers efficient routines for rounding, performing mathematical computations, and querying properties of the simulated low-precision format. The software exploits the bit-level floating-point representation of the format in which the numbers are stored and replaces costly library calls with low-level bit manipulations and integer arithmetic. In numerical experiments, the new techniques bring a considerable speedup (typically one order of magnitude or more) over existing alternatives in C, C++, and MATLAB. To our knowledge, CPFloat is currently the most efficient and complete library for experimenting with custom low-precision floating-point arithmetic.

rawabstract:
One can simulate low-precision floating-point arithmetic via software by executing each arithmetic operation in hardware and then rounding the result to the desired number of significant bits. For IEEE-compliant formats, rounding requires only standard mathematical library functions, but handling subnormals, underflow, and overflow demands special attention, and numerical errors can cause mathematically correct formulae to behave incorrectly in finite arithmetic. Moreover, the ensuing implementations are not necessarily efficient, as the library functions these techniques build upon are typically designed to handle a broad range of cases and may not be optimized for the specific needs of rounding algorithms. CPFloat is a C library for simulating low-precision arithmetics. It offers efficient routines for rounding, performing mathematical computations, and querying properties of the simulated low-precision format. The software exploits the bit-level floating-point representation of the format in which the numbers are stored and replaces costly library calls with low-level bit manipulations and integer arithmetic. In numerical experiments, the new techniques bring a considerable speedup (typically one order of magnitude or more) over existing alternatives in C, C++, and MATLAB. To our knowledge, CPFloat is currently the most efficient and complete library for experimenting with custom low-precision floating-point arithmetic.

entry:
@Article{Fasi:2023:CCL,
  author =       "Massimiliano Fasi and Mantas Mikaitis",
  title =        "{CPFloat}: a {C} Library for Simulating Low-precision
                 Arithmetic",
  journal =      j-TOMS,
  volume =       "49",
  number =       "2",
  pages =        "18:1--18:??",
  month =        jun,
  year =         "2023",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3585515",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Thu Jun 29 07:01:00 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3585515",
  abstract =     "One can simulate low-precision floating-point
                 arithmetic via software by executing each arithmetic
                 operation in hardware and then rounding the result to
                 the desired number of significant bits. For
                 IEEE-compliant formats, rounding requires only standard
                 mathematical library functions, but handling
                 subnormals, underflow, and overflow demands special
                 attention, and numerical errors can cause
                 mathematically correct formulae to behave incorrectly
                 in finite arithmetic. Moreover, the ensuing
                 implementations are not necessarily efficient, as the
                 library functions these techniques build upon are
                 typically designed to handle a broad range of cases and
                 may not be optimized for the specific needs of rounding
                 algorithms. CPFloat is a C library for simulating
                 low-precision arithmetics. It offers efficient routines
                 for rounding, performing mathematical computations, and
                 querying properties of the simulated low-precision
                 format. The software exploits the bit-level
                 floating-point representation of the format in which
                 the numbers are stored and replaces costly library
                 calls with low-level bit manipulations and integer
                 arithmetic. In numerical experiments, the new
                 techniques bring a considerable speedup (typically one
                 order of magnitude or more) over existing alternatives
                 in C, C++, and MATLAB. To our knowledge, CPFloat is
                 currently the most efficient and complete library for
                 experimenting with custom low-precision floating-point
                 arithmetic.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Filippas:2023:RPF
booktitle: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
title: Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 18:1--18:??
month: jun
monthnumber: 6
year: 2023
DOI: https://doi.org/10.1109/aicas57966.2023.10168556
bibdate: Thu Dec 7 11:54:15 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.07 11:54:15 ???
acknowledgement: ack-nhfb
rawbooktitle: 2023 {IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)}
rawtitle: Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines
author:
Dionysios Filippas and Christodoulos Peltekis and Giorgos Dimitrakopoulos and Chrysostomos Nicopoulos

rawauthor:
Dionysios Filippas and Christodoulos Peltekis and Giorgos Dimitrakopoulos and Chrysostomos Nicopoulos

entry:
@InProceedings{Filippas:2023:RPF,
  author =       "Dionysios Filippas and Christodoulos Peltekis and
                 Giorgos Dimitrakopoulos and Chrysostomos Nicopoulos",
  booktitle =    "2023 {IEEE 5th International Conference on Artificial
                 Intelligence Circuits and Systems (AICAS)}",
  title =        "Reduced-Precision Floating-Point Arithmetic in
                 Systolic Arrays with Skewed Pipelines",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  month =        jun,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/aicas57966.2023.10168556",
  bibdate =      "Thu Dec 7 11:54:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  pagecount =    "5",
}


bibtype: inproceedings
filename: fparith.bib
label: Flatt:2023:MIA
author: Oliver Flatt and Pavel Panchekha
title: Making Interval Arithmetic Robust to Overflow
crossref: IEEE:2023:PIS
pages: 44--47
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00022
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Oliver Flatt and Pavel Panchekha
rawtitle: Making Interval Arithmetic Robust to Overflow
keywords:
ARITH 2023; ARITH-30; computable reals; Digital arithmetic; Interval arithmetic; Libraries; Mathematics computing; multiple precision arithmetic; overflow

entry:
@InProceedings{Flatt:2023:MIA,
  author =       "Oliver Flatt and Pavel Panchekha",
  title =        "Making Interval Arithmetic Robust to Overflow",
  crossref =     "IEEE:2023:PIS",
  pages =        "44--47",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00022",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; computable reals; Digital
                 arithmetic; Interval arithmetic; Libraries; Mathematics
                 computing; multiple precision arithmetic; overflow",
}


bibtype: techreport
filename: fparith.bib
label: Fog:2023:FPE
author: Agner Fog
title: Floating point exception tracking and NAN propagation
type: Report
institution: Technical University of Denmark
address: Lyngby, Denmark
pages: 10
day: 27
month: apr
monthnumber: 4
year: 2023
bibdate: Tue May 09 08:55:38 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.05.09 08:55:38 ???
URL: https://www.agner.org/optimize/nan_propagation.pdf
remark: See also earlier cite Fog:2020:FPE and later revisions cite Fog:2024:FPE.
acknowledgement: ack-nhfb
rawauthor: Agner Fog
rawtitle: Floating point exception tracking and {NAN} propagation
abstract:
The most common methods for detecting floating point errors are based on exception trapping or a global status register. These methods are inefficient in modern systems that use out-of-order parallelism and single-instruction-multiple-data (SIMD) parallelism for improving performance. It is argued that a method based on NAN propagation is more efficient and deterministic. Problems with NAN propagation in current systems are discussed. Examples of implementation in the C++ vector class library and in an experimental instruction set named ForwardCom are presented. The IEEE-754 standard for floating point arithmetic may need adjustment to accommodate the needs of modern forms of parallelism.

entry:
@TechReport{Fog:2023:FPE,
  author =       "Agner Fog",
  title =        "Floating point exception tracking and {NAN}
                 propagation",
  type =         "Report",
  institution =  "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "10",
  day =          "27",
  month =        apr,
  year =         "2023",
  bibdate =      "Tue May 09 08:55:38 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/nan_propagation.pdf",
  abstract =     "The most common methods for detecting floating point
                 errors are based on exception trapping or a global
                 status register. These methods are inefficient in
                 modern systems that use out-of-order parallelism and
                 single-instruction-multiple-data (SIMD) parallelism for
                 improving performance. It is argued that a method based
                 on NAN propagation is more efficient and deterministic.
                 Problems with NAN propagation in current systems are
                 discussed. Examples of implementation in the C++ vector
                 class library and in an experimental instruction set
                 named ForwardCom are presented. The IEEE-754 standard
                 for floating point arithmetic may need adjustment to
                 accommodate the needs of modern forms of parallelism.",
  acknowledgement = ack-nhfb,
  remark =       "See also earlier \cite{Fog:2020:FPE} and later
                 revisions \cite{Fog:2024:FPE}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Gavarini:2023:RRN
author: G. Gavarini and A. Ruospo and E. Sanchez
title: On the resilience of representative and novel data formats in CNNs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/DFT59622.2023.10313551
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: G. Gavarini and A. Ruospo and E. Sanchez
rawtitle: On the resilience of representative and novel data formats in {CNNs}
booktitle:
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

keywords:
Convolutional neural networks; Deep Neural Network; Fault Injection; FP32; INT8; Measurement; Memory management; Posit; POSIT16; POSIT32; Power demand; Reliability; Task analysis; Training; Very large scale integration

rawbooktitle:
{2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}

entry:
@InProceedings{Gavarini:2023:RRN,
  author =       "G. Gavarini and A. Ruospo and E. Sanchez",
  booktitle =    "{2023 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "On the resilience of representative and novel data
                 formats in {CNNs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DFT59622.2023.10313551",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Convolutional neural networks; Deep Neural Network;
                 Fault Injection; FP32; INT8; Measurement; Memory
                 management; Posit; POSIT16; POSIT32; Power demand;
                 Reliability; Task analysis; Training; Very large scale
                 integration",
}


bibtype: inproceedings
filename: fparith.bib
label: Glint:2023:HSC
editor: IEEE
booktitle: 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)
title: Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 469--474
year: 2023
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)}
raweditor: {IEEE}
rawtitle: Hardware-Software Codesign of {DNN} Accelerators using Approximate Posit Multipliers
author:
Tom Glint and Kailash Prasad and Jinay Dagli and Krishil Gandhi and Aryan Gupta and Vrajesh Patel and Neel Shah and Joycee Mekie

rawauthor:
Tom Glint and Kailash Prasad and Jinay Dagli and Krishil Gandhi and Aryan Gupta and Vrajesh Patel and Neel Shah and Joycee Mekie

entry:
@InProceedings{Glint:2023:HSC,
  author =       "Tom Glint and Kailash Prasad and Jinay Dagli and
                 Krishil Gandhi and Aryan Gupta and Vrajesh Patel and
                 Neel Shah and Joycee Mekie",
  editor =       "{IEEE}",
  booktitle =    "{2023 28th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "Hardware-Software Codesign of {DNN} Accelerators using
                 Approximate Posit Multipliers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "469--474",
  year =         "2023",
  DOI =          "",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Gorodecky:2023:SAC
author: Danila Gorodecky and Leonel Sousa
title: Scalable architecture of constant division on FPGA
crossref: IEEE:2023:PIS
pages: 16--23
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00025
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Danila Gorodecky and Leonel Sousa
rawtitle: Scalable architecture of constant division on {FPGA}
keywords:
ARITH 2023; ARITH-30; Boolean functions; Computer architecture; Costs; Delays; Digital arithmetic; Field programmable gate arrays; Hardware

entry:
@InProceedings{Gorodecky:2023:SAC,
  author =       "Danila Gorodecky and Leonel Sousa",
  title =        "Scalable architecture of constant division on {FPGA}",
  crossref =     "IEEE:2023:PIS",
  pages =        "16--23",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00025",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Boolean functions; Computer
                 architecture; Costs; Delays; Digital arithmetic; Field
                 programmable gate arrays; Hardware",
}


bibtype: inproceedings
filename: fparith.bib
label: Graillat:2023:PCH
author: Stef Graillat and Youness Ibrahimy and Clothilde Jeangoudoux and Christoph Lauter
title: A parallel compensated Horner scheme for SIMD architecture
crossref: IEEE:2023:PIS
pages: 131--138
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00010
bibdate: Wed May 8 09:17:31 2024
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Youness Ibrahimy and Clothilde Jeangoudoux and Christoph Lauter
rawtitle: A parallel compensated {Horner} scheme for {SIMD} architecture
keywords:
ARITH 2023; ARITH-30; AVX; compensated algorithms; Computer architecture; Computers; Costs; Digital arithmetic; error-free transformations; Horner scheme; Limiting; parallel algorithms; polynomial evaluation; Registers; rounding errors; Scalability; SIMD

entry:
@InProceedings{Graillat:2023:PCH,
  author =       "Stef Graillat and Youness Ibrahimy and Clothilde
                 Jeangoudoux and Christoph Lauter",
  title =        "A parallel compensated {Horner} scheme for {SIMD}
                 architecture",
  crossref =     "IEEE:2023:PIS",
  pages =        "131--138",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00010",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; AVX; compensated algorithms;
                 Computer architecture; Computers; Costs; Digital
                 arithmetic; error-free transformations; Horner scheme;
                 Limiting; parallel algorithms; polynomial evaluation;
                 Registers; rounding errors; Scalability; SIMD",
}


bibtype: inproceedings
filename: fparith.bib
label: Grale:2023:IMM
author: Trenton J. Grale and Earl E. Swartzlander
title: Improved Montgomery Multiplication
crossref: IEEE:2023:PIS
pages: 60--67
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00019
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Trenton J. Grale and Earl E. Swartzlander
rawtitle: Improved {Montgomery} Multiplication
keywords:
ARITH 2023; ARITH-30; Computational modeling; Computer architecture; Costs; digit multiplication; Digital arithmetic; Hardware; modular arithmetic; modular multiplication; Parallel processing; Rescheduled Montgomery Multiplier; Serial Montgomery Model; Taxonomy

entry:
@InProceedings{Grale:2023:IMM,
  author =       "Trenton J. Grale and Earl E. Swartzlander",
  title =        "Improved {Montgomery} Multiplication",
  crossref =     "IEEE:2023:PIS",
  pages =        "60--67",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00019",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Computational modeling; Computer
                 architecture; Costs; digit multiplication; Digital
                 arithmetic; Hardware; modular arithmetic; modular
                 multiplication; Parallel processing; Rescheduled
                 Montgomery Multiplier; Serial Montgomery Model;
                 Taxonomy",
}


bibtype: inproceedings
filename: fparith.bib
label: Gunaratne:2023:EUL
author: Thushara Kanchana Gunaratne
crossref: Gustafson:2023:NGA
pages: 155--170
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_10
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Thushara Kanchana Gunaratne
title:
Evaluation of the Use of Low Precision Floating-Point Arithmetic for Applications in Radio Astronomy

rawtitle:
Evaluation of the Use of Low Precision Floating-Point Arithmetic for Applications in Radio Astronomy

entry:
@InProceedings{Gunaratne:2023:EUL,
  author =       "Thushara Kanchana Gunaratne",
  title =        "Evaluation of the Use of Low Precision Floating-Point
                 Arithmetic for Applications in Radio Astronomy",
  crossref =     "Gustafson:2023:NGA",
  pages =        "155--170",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_10",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Gustafson:2023:DFT
author: John L. Gustafson and Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
title: Decoding-Free Two-Input Arithmetic for Low-Precision Real Numbers
crossref: Gustafson:2023:NGA
pages: 61--76
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_4
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: John L. Gustafson and Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawtitle: Decoding-Free Two-Input Arithmetic for Low-Precision Real Numbers
entry:
@InProceedings{Gustafson:2023:DFT,
  author =       "John L. Gustafson and Marco Cococcioni and Federico
                 Rossi and Emanuele Ruffaldi and Sergio Saponara",
  title =        "Decoding-Free Two-Input Arithmetic for Low-Precision
                 Real Numbers",
  crossref =     "Gustafson:2023:NGA",
  pages =        "61--76",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_4",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Hallman:2023:PAD
author: Eric Hallman and Ilse C. F. Ipsen
title: Precision-aware deterministic and probabilistic error bounds for floating point summation
journal: j-NUM-MATH
volume: 155
number: 1--2
pages: 83--119
month: oct
monthnumber: 10
year: 2023
CODEN: NUMMA7
DOI: https://doi.org/10.1007/s00211-023-01370-y
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
bibdate: Thu Sep 28 06:27:49 MDT 2023
bibtimestamp: 2023.09.28 06:27:49 MDT
URL: https://link.springer.com/article/10.1007/s00211-023-01370-y
fjournal: Numerische Mathematik
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
ajournal: Num. Math.
journalURL: http://link.springer.com/journal/211
rawauthor: Eric Hallman and Ilse C. F. Ipsen
rawtitle: Precision-aware deterministic and probabilistic error bounds for floating point summation
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/i/ipsen-ilse-c-f.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/nummath2020.bib

entry:
@Article{Hallman:2023:PAD,
  author =       "Eric Hallman and Ilse C. F. Ipsen",
  title =        "Precision-aware deterministic and probabilistic error
                 bounds for floating point summation",
  journal =      j-NUM-MATH,
  volume =       "155",
  number =       "1--2",
  pages =        "83--119",
  month =        oct,
  year =         "2023",
  CODEN =        "NUMMA7",
  DOI =          "https://doi.org/10.1007/s00211-023-01370-y",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  bibdate =      "Thu Sep 28 06:27:49 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/i/ipsen-ilse-c-f.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/nummath2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s00211-023-01370-y",
  acknowledgement = ack-nhfb,
  ajournal =     "Num. Math.",
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
  keywords =     "accurate floating-point summation",
}


bibtype: misc
filename: fparith.bib
label: Harris:2023:UMR
author: David Harris
title: Unified minimally redundant radix 4 DivSqrt selection intervals and constants
pages: 83--119
year: 2023
bibdate: Thu Dec 28 10:11:34 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.28 10:11:34 ???
URL: https://bit.ly/3fLR81z
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: David Harris
rawtitle: Unified minimally redundant radix 4 {DivSqrt} selection intervals and constants
remark:
URL leads to undated Google Docs spreadsheet with interleaved commentary. Cited in cite Harris:2024:UDS.

entry:
@Misc{Harris:2023:UMR,
  author =       "David Harris",
  title =        "Unified minimally redundant radix 4 {DivSqrt}
                 selection intervals and constants",
  howpublished = "Web document",
  year =         "2023",
  bibdate =      "Thu Dec 28 10:11:34 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://bit.ly/3fLR81z",
  acknowledgement = ack-nhfb,
  remark =       "URL leads to undated Google Docs spreadsheet with
                 interleaved commentary. Cited in
                 \cite{Harris:2024:UDS}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Ho:2023:BBE
author: Nhut-Minh Ho and Duy-Thanh Nguyen and John L. Gustafson and Weng-Fai Wong
title: Bedot: Bit Efficient Dot Product for Deep Generative Models
crossref: Gustafson:2023:NGA
pages: 19--37
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_2
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Nhut-Minh Ho and Duy-Thanh Nguyen and John L. Gustafson and Weng-Fai Wong
rawtitle: {Bedot}: Bit Efficient Dot Product for Deep Generative Models
entry:
@InProceedings{Ho:2023:BBE,
  author =       "Nhut-Minh Ho and Duy-Thanh Nguyen and John L.
                 Gustafson and Weng-Fai Wong",
  title =        "{Bedot}: Bit Efficient Dot Product for Deep Generative
                 Models",
  crossref =     "Gustafson:2023:NGA",
  pages =        "19--37",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_2",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hoffmann:2023:ASE
author: Alexandre Hoffmann and Yves Durand and Jerome Fereyre
title: Accelerating spectral elements method with extended precision: a case study
journal: International Journal of Applied Physics and Mathematics
volume: 14
number: 2
pages: 45--58
year: 2023
CODEN: IJAPJ3
DOI: https://doi.org/10.17706/ijapm
ISSN: 2010-362X OR 2010362X
ISSNL: 2010-362X OR 2010362X
bibdate: Wed Jun 12 16:34:44 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.12 16:34:44 ???
remark: In Proc. 12th Int. Conf. Pure Appl. Math. (ICPAM).
acknowledgement: ack-nhfb
ajournal: Int. J. Appl. Phys. Math.
rawauthor: Alexandre Hoffmann and Yves Durand and J{\'e}r{\^o}me Fereyre
rawtitle: Accelerating spectral elements method with extended precision: a case study
entry:
@Article{Hoffmann:2023:ASE,
  author =       "Alexandre Hoffmann and Yves Durand and J{\'e}r{\^o}me
                 Fereyre",
  title =        "Accelerating spectral elements method with extended
                 precision: a case study",
  journal =      "International Journal of Applied Physics and
                 Mathematics",
  volume =       "14",
  number =       "2",
  pages =        "45--58",
  year =         "2023",
  CODEN =        "IJAPJ3",
  DOI =          "https://doi.org/10.17706/ijapm",
  ISSN =         "2010-362X",
  ISSN-L =       "2010-362X",
  bibdate =      "Wed Jun 12 16:34:44 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Int. J. Appl. Phys. Math.",
  remark =       "In Proc. 12th Int. Conf. Pure Appl. Math. (ICPAM).",
}


bibtype: inproceedings
filename: fparith.bib
label: Hong:2023:LCH
author: Wanyuan Hong and Hui Chen and Lianghua Quan and Yuxiang Fu and Li Li
booktitle: 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ISCAS46773.2023.10181944
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Wanyuan Hong and Hui Chen and Lianghua Quan and Yuxiang Fu and Li Li
rawbooktitle: {2023 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation
keywords:
CMOS technology; Computer architecture; CORDIC; Digital signal processing; floating-point; Frequency synthesizers; high precision; low cost; Navigation; Nth root; Power demand; Simulation; SRT

entry:
@InProceedings{Hong:2023:LCH,
  author =       "Wanyuan Hong and Hui Chen and Lianghua Quan and
                 Yuxiang Fu and Li Li",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Low-Cost High-Precision Architecture for Arbitrary
                 Floating-Point Nth Root Computation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181944",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "CMOS technology; Computer architecture; CORDIC;
                 Digital signal processing; floating-point; Frequency
                 synthesizers; high precision; low cost; Navigation; Nth
                 root; Power demand; Simulation; SRT",
}


bibtype: article
filename: fparith.bib
label: Hu:2023:TWF
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 70
number: 11
pages: 4216--4220
year: 2023
DOI: https://doi.org/10.1109/TCSII.2023.3283418
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
author:
Xianwu Hu and Yu Wang and Zizhao Ma and Gan Wen and Zeming Wang and Zhichao Lu and Yunlong Liu and Yanlei Li and Xingdong Liang and Xiaoyang Zeng and Yufeng Xie

title:
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication

keywords:
Arrays; Common Information Model (computing); Compute in memory; Energy efficiency; floating-point; fully parallel input; Low latency communication; MAC; Memory management; Microprocessors; triangle weights arrangement; Voltage

rawauthor:
Xianwu Hu and Yu Wang and Zizhao Ma and Gan Wen and Zeming Wang and Zhichao Lu and Yunlong Liu and Yanlei Li and Xingdong Liang and Xiaoyang Zeng and Yufeng Xie

rawtitle:
An 8.8 {TFLOPS/W} Floating-Point {RRAM}-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication

entry:
@Article{Hu:2023:TWF,
  author =       "Xianwu Hu and Yu Wang and Zizhao Ma and Gan Wen and
                 Zeming Wang and Zhichao Lu and Yunlong Liu and Yanlei
                 Li and Xingdong Liang and Xiaoyang Zeng and Yufeng
                 Xie",
  title =        "An 8.8 {TFLOPS/W} Floating-Point {RRAM}-Based
                 Compute-in-Memory Macro Using Low Latency
                 Triangle-Style Mantissa Multiplication",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "11",
  pages =        "4216--4220",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3283418",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "Arrays; Common Information Model (computing); Compute
                 in memory; Energy efficiency; floating-point; fully
                 parallel input; Low latency communication; MAC; Memory
                 management; Microprocessors; triangle weights
                 arrangement; Voltage",
}


bibtype: techreport
filename: fparith.bib
label: Hubrecht:2023:TCRa
author: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
title: Towards a correctly-rounded and fast power function in binary64 arithmetic
type: Report
institution: DI-ENS --- Departement d'informatique --- ENS Paris
address: Paris, France
pages: 4216--4220
day: 12
month: jul
monthnumber: 7
year: 2023
bibdate: Mon May 13 12:00:21 2024
bibtimestamp: 2024.05.13 12:00:21 ???
URL: https://inria.hal.science/hal-04159652v1/
remark: This is a longer version of cite Hubrecht:2023:TCRb with proofs.
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
rawtitle: Towards a correctly-rounded and fast power function in binary64 arithmetic
abstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed in an extended version of this paper, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

rawabstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed in an extended version of this paper, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

entry:
@TechReport{Hubrecht:2023:TCRa,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and Paul
                 Zimmermann",
  title =        "Towards a correctly-rounded and fast power function in
                 binary64 arithmetic",
  type =         "Report",
  institution =  "DI-ENS --- D{\'e}partement d'informatique --- ENS
                 Paris",
  address =      "Paris, France",
  day =          "12",
  month =        jul,
  year =         "2023",
  bibdate =      "Mon May 13 12:00:21 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04159652v1/",
  abstract =     "We design algorithms for the correct rounding of the
                 power function $ x^y $ in the binary64 IEEE 754 format,
                 for all rounding modes, modulo the knowledge of
                 hardest-to-round cases. Our implementation of these
                 algorithms largely outperforms previous
                 correctly-rounded implementations and is not far from
                 the efficiency of current mathematical libraries, which
                 are not correctly-rounded. Still, we expect our
                 algorithms can be further improved for speed. The
                 proofs of correctness are fully detailed in an extended
                 version of this paper, with the goal to enable a formal
                 proof of these algorithms. We hope this work will
                 motivate the next IEEE 754 revision committee to
                 require correct rounding for mathematical functions.",
  acknowledgement = ack-nhfb,
  remark =       "This is a longer version of \cite{Hubrecht:2023:TCRb}
                 with proofs.",
}


bibtype: inproceedings
filename: fparith.bib
label: Hubrecht:2023:TCRb
author: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
title: Towards a correctly-rounded and fast power function in binary64 arithmetic
crossref: IEEE:2023:PIS
pages: 111--118
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00028
bibdate: Fri Dec 08 15:03:08 2023
bibtimestamp: 2023.12.08 15:03:08 ???
remark: See also longer versions cite Hubrecht:2023:TCRa,Hubrecht:2024:TCR.
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann
rawtitle: Towards a correctly-rounded and fast power function in binary64 arithmetic
URL:
https://arith2023.arithsymposium.org/slides/S6_PaulZimmermannS6P1.pdf; https://inria.hal.science/hal-04159652v1/file/pow.pdf; https://inria.hal.science/hal-04326201

abstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

keywords:
ARITH 2023; ARITH-30; binary64 format; correct rounding; Digital arithmetic; double precision; efficiency; Error analysis; IEEE 754; Libraries; power function; Prediction algorithms; Software; Software algorithms; Switches

rawabstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed, with the goal to enable a formal proof of these algorithms. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

entry:
@InProceedings{Hubrecht:2023:TCRb,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and Paul
                 Zimmermann",
  title =        "Towards a correctly-rounded and fast power function in
                 binary64 arithmetic",
  crossref =     "IEEE:2023:PIS",
  pages =        "111--118",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00028",
  bibdate =      "Fri Dec 08 15:03:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arith2023.arithsymposium.org/slides/S6_PaulZimmermannS6P1.pdf;
                 https://inria.hal.science/hal-04159652v1/file/pow.pdf;
                 https://inria.hal.science/hal-04326201",
  abstract =     "We design algorithms for the correct rounding of the
                 power function $ x^y $ in the binary64 IEEE 754 format,
                 for all rounding modes, modulo the knowledge of
                 hardest-to-round cases. Our implementation of these
                 algorithms largely outperforms previous
                 correctly-rounded implementations and is not far from
                 the efficiency of current mathematical libraries, which
                 are not correctly-rounded. Still, we expect our
                 algorithms can be further improved for speed. The
                 proofs of correctness are fully detailed, with the goal
                 to enable a formal proof of these algorithms. We hope
                 this work will motivate the next IEEE 754 revision
                 committee to require correct rounding for mathematical
                 functions.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; binary64 format; correct
                 rounding; Digital arithmetic; double precision;
                 efficiency; Error analysis; IEEE 754; Libraries; power
                 function; Prediction algorithms; Software; Software
                 algorithms; Switches",
  remark =       "See also longer versions
                 \cite{Hubrecht:2023:TCRa,Hubrecht:2024:TCR}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Hulsmeier:2023:HSH
author: Nils Hulsmeier and Moritz Barthel and Jochen Rust and Steffen Paul
title: Hybrid SORN Hardware Accelerator for Support Vector Machines
crossref: Gustafson:2023:NGA
pages: 77--87
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_5
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Nils H{\"u}lsmeier and Moritz B{\"a}rthel and Jochen Rust and Steffen Paul
rawtitle: Hybrid {SORN} Hardware Accelerator for Support Vector Machines
entry:
@InProceedings{Hulsmeier:2023:HSH,
  author =       "Nils H{\"u}lsmeier and Moritz B{\"a}rthel and Jochen
                 Rust and Steffen Paul",
  title =        "Hybrid {SORN} Hardware Accelerator for Support Vector
                 Machines",
  crossref =     "Gustafson:2023:NGA",
  pages =        "77--87",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_5",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: IEEE:2023:MIS
author: IEEE
title: Milestones: IEEE Standard 754 for Binary Floating-Point Arithmetic, 1985. (J. Coonen, proposer)
pages: 77--87
day: 3
month: may
monthnumber: 5
year: 2023
DOI: https://ethw.org/Milestones:IEEE_Standard_754_for_Binary_Floating-Point_Arithmetic,_1985
bibdate: Wed Aug 07 15:36:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 15:36:31 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: {IEEE}
rawtitle: Milestones: {IEEE Standard 754 for Binary Floating-Point Arithmetic, 1985. (J. Coonen, proposer)}
entry:
@Misc{IEEE:2023:MIS,
  author =       "{IEEE}",
  title =        "Milestones: {IEEE Standard 754 for Binary
                 Floating-Point Arithmetic, 1985. (J. Coonen,
                 proposer)}",
  howpublished = "Web site",
  day =          "3",
  month =        may,
  year =         "2023",
  DOI =          "https://ethw.org/Milestones:IEEE_Standard_754_for_Binary_Floating-Point_Arithmetic,_1985",
  bibdate =      "Wed Aug 07 15:36:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: IEEE:2023:UWG
author: IEEE
title: IEEE Working Group P3109 Interim Report on 8-bit Binary Floating-point Formats
pages: 18
day: 24
month: nov
monthnumber: 11
year: 2023
bibdate: Sat Dec 16 10:36:07 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 10:36:07 ???
URL: https://github.com/P3109/Public/blob/main/Shared%20Reports/P3109%20WG%20Interim%20report.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: {IEEE}
rawtitle: {IEEE Working Group P3109} Interim Report on 8-bit Binary Floating-point Formats
remark:
Table 2 on page 4 contains a compact summary of binary8pp, binary8p5, binary8p4, binary8p3, binary16, binary32, and binary64 data layouts.

entry:
@Misc{IEEE:2023:UWG,
  author =       "{IEEE}",
  title =        "{IEEE Working Group P3109} Interim Report on 8-bit
                 Binary Floating-point Formats",
  howpublished = "Web document",
  pages =        "18",
  day =          "24",
  month =        nov,
  year =         "2023",
  bibdate =      "Sat Dec 16 10:36:07 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/P3109/Public/blob/main/Shared%20Reports/P3109%20WG%20Interim%20report.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Table 2 on page 4 contains a compact summary of
                 binary8p\{p\}, binary8p5, binary8p4, binary8p3,
                 binary16, binary32, and binary64 data layouts.",
}


bibtype: techreport
filename: fparith.bib
label: Innocente:2023:AMF
author: Vincenzo Innocente and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 21
day: 14
month: feb
monthnumber: 2
year: 2023
bibdate: Fri Dec 08 08:28:52 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 08:28:52 ???
acknowledgement: ack-nhfb
rawauthor: Vincenzo Innocente and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
URL:
https://inria.hal.science/hal-03141101; https://members.loria.fr/PZimmermann/papers/glibc237-20230214.pdf

remark:
Tabular comparison of AMD, Apple, CUDA, GNU, Intel, Musl, Newlib, OpenLibm, and RadeonOpenCompute (ROCm) lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Innocente:2023:AMF,
  author =       "Vincenzo Innocente and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "21",
  day =          "14",
  month =        feb,
  year =         "2023",
  bibdate =      "Fri Dec 08 08:28:52 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-03141101;
                 https://members.loria.fr/PZimmermann/papers/glibc237-20230214.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, CUDA, GNU, Intel,
                 Musl, Newlib, OpenLibm, and RadeonOpenCompute (ROCm) lm
                 libraries for correct rounding, versus results from
                 MPFR.",
}


bibtype: inproceedings
filename: fparith.bib
label: Jaberipur:2023:MMF
author: Ghassem Jaberipur and Saeid Gorgin and Navid Ahamadian and Jeong-A Lee
title: Modulo-($ 2^q - 3$) Multiplication with Fully Modular Partial Product Generation and Reduction
crossref: IEEE:2023:PIS
pages: 68--75
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00023
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Ghassem Jaberipur and Saeid Gorgin and Navid Ahamadian and Jeong-A Lee
rawtitle: Modulo-($ 2^q - 3$) Multiplication with Fully Modular Partial Product Generation and Reduction
keywords:
ARITH 2023; ARITH-30; Costs; Delays; Digital arithmetic; Energy measurement; Fully modular multiplication; Market research; Partial product reduction; Residue number system; Software; Software algorithms

entry:
@InProceedings{Jaberipur:2023:MMF,
  author =       "Ghassem Jaberipur and Saeid Gorgin and Navid Ahamadian
                 and Jeong-A Lee",
  title =        "Modulo-($ 2^q - 3$) Multiplication with Fully Modular
                 Partial Product Generation and Reduction",
  crossref =     "IEEE:2023:PIS",
  pages =        "68--75",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00023",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Costs; Delays; Digital
                 arithmetic; Energy measurement; Fully modular
                 multiplication; Market research; Partial product
                 reduction; Residue number system; Software; Software
                 algorithms",
}


bibtype: inproceedings
filename: fparith.bib
label: Joshi:2023:AEV
author: Rajeev Joshi and Lakshmi Kavya Kalyanam and Srinivas Katkoori
booktitle: 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
title: Area Efficient VLSI ASIC Implementation of Multilayer Perceptrons
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2023
DOI: https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10133986
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Rajeev Joshi and Lakshmi Kavya Kalyanam and Srinivas Katkoori
rawbooktitle: {2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)}
rawtitle: Area Efficient {VLSI ASIC} Implementation of Multilayer Perceptrons
keywords:
Annealing; Artificial neural networks; ASICs; Edge-AI; FP32; IEEE 754; IoT; Metaheuristic optimization; Metaheuristics; Neural Networks; Neurons; Perturbation methods; Simulated annealing; Very large scale integration; VLSI

entry:
@InProceedings{Joshi:2023:AEV,
  author =       "Rajeev Joshi and Lakshmi Kavya Kalyanam and Srinivas
                 Katkoori",
  booktitle =    "{2023 International VLSI Symposium on Technology,
                 Systems and Applications (VLSI-TSA/VLSI-DAT)}",
  title =        "Area Efficient {VLSI ASIC} Implementation of
                 Multilayer Perceptrons",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10133986",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Annealing; Artificial neural networks; ASICs; Edge-AI;
                 FP32; IEEE 754; IoT; Metaheuristic optimization;
                 Metaheuristics; Neural Networks; Neurons; Perturbation
                 methods; Simulated annealing; Very large scale
                 integration; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: K:2023:DEE
editor: IEEE
title: Design of Energy Efficient and Low Delay Posit Multiplier
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/VLSID57277.2023.00042
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
raweditor: {IEEE}
rawtitle: Design of Energy Efficient and Low Delay Posit Multiplier
author:
Lakshmi Bhanuprakash Reddy K and Haripriya R S and Keerthija Puli and Subba Ramkumar Reddy Annapalli and Vikramkumar Pudi

booktitle:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)

rawauthor:
Lakshmi Bhanuprakash Reddy K and Haripriya R S and Keerthija Puli and Subba Ramkumar Reddy Annapalli and Vikramkumar Pudi

rawbooktitle:
{2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)}

entry:
@InProceedings{K:2023:DEE,
  author =       "Lakshmi Bhanuprakash Reddy K and Haripriya R S and
                 Keerthija Puli and Subba Ramkumar Reddy Annapalli and
                 Vikramkumar Pudi",
  editor =       "{IEEE}",
  booktitle =    "{2023 36th International Conference on VLSI Design and
                 2023 22nd International Conference on Embedded Systems
                 (VLSID)}",
  title =        "Design of Energy Efficient and Low Delay Posit
                 Multiplier",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSID57277.2023.00042",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kapoor:2023:FVF
author: Ashish Kapoor and Warren Ferguson and Himanshu Jain and Sudipta Kundu
title: Formal Verification of Floating-Point Division
crossref: IEEE:2023:PIS
pages: 93--96
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00018
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Ashish Kapoor and Warren Ferguson and Himanshu Jain and Sudipta Kundu
rawtitle: Formal Verification of Floating-Point Division
keywords:
ARITH 2023; ARITH-30; datapath verification; Digital arithmetic; equivalence checking; floating-point division; Formal verification; formal verification; Software

entry:
@InProceedings{Kapoor:2023:FVF,
  author =       "Ashish Kapoor and Warren Ferguson and Himanshu Jain
                 and Sudipta Kundu",
  title =        "Formal Verification of Floating-Point Division",
  crossref =     "IEEE:2023:PIS",
  pages =        "93--96",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00018",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; datapath verification; Digital
                 arithmetic; equivalence checking; floating-point
                 division; Formal verification; formal verification;
                 Software",
}


bibtype: inproceedings
filename: fparith.bib
label: Kavvousanos:2023:IRL
author: E. Kavvousanos and V. Sakellariou and I. Kouretas and V. Paliouras and T. Stouraitis
crossref: IEEE:2023:PIS
pages: 102--109
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00020
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: E. Kavvousanos and V. Sakellariou and I. Kouretas and V. Paliouras and T. Stouraitis
title:
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization

keywords:
ARITH 2023; ARITH-30; Artificial neural networks; Computer architecture; Degradation; Digital arithmetic; hardware acceleration; Machine learning; Neural network hardware; neural networks; residue number system; sparsity; Training

rawtitle:
Improving Residue-Level Sparsity in {RNS-based} Neural Network Hardware Accelerators via Regularization

entry:
@InProceedings{Kavvousanos:2023:IRL,
  author =       "E. Kavvousanos and V. Sakellariou and I. Kouretas and
                 V. Paliouras and T. Stouraitis",
  title =        "Improving Residue-Level Sparsity in {RNS-based} Neural
                 Network Hardware Accelerators via Regularization",
  crossref =     "IEEE:2023:PIS",
  pages =        "102--109",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00020",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Artificial neural networks;
                 Computer architecture; Degradation; Digital arithmetic;
                 hardware acceleration; Machine learning; Neural network
                 hardware; neural networks; residue number system;
                 sparsity; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Kellison:2023:LLF
author: Ariel E. Kellison and Andrew W. Appel and Mohit Tekriwal and David Bindel
title: LAProof: a Library of Formal Proofs of Accuracy and Correctness for Linear Algebra Programs
crossref: IEEE:2023:PIS
pages: 36--43
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00021
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Ariel E. Kellison and Andrew W. Appel and Mohit Tekriwal and David Bindel
rawtitle: {LAProof}: a Library of Formal Proofs of Accuracy and Correctness for Linear Algebra Programs
keywords:
ARITH 2023; ARITH-30; Error analysis; floating-point arithmetic; formal verification; Libraries; Mathematical models; program verification; rounding error analysis; Roundoff errors; Sparse matrices; Stability analysis; Vectors

entry:
@InProceedings{Kellison:2023:LLF,
  author =       "Ariel E. Kellison and Andrew W. Appel and Mohit
                 Tekriwal and David Bindel",
  title =        "{LAProof}: a Library of Formal Proofs of Accuracy and
                 Correctness for Linear Algebra Programs",
  crossref =     "IEEE:2023:PIS",
  pages =        "36--43",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00021",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Error analysis; floating-point
                 arithmetic; formal verification; Libraries;
                 Mathematical models; program verification; rounding
                 error analysis; Roundoff errors; Sparse matrices;
                 Stability analysis; Vectors",
}


bibtype: article
filename: fparith.bib
label: Kim:2023:BNL
author: Jongho Kim and Young H. Oh and Hyeonsik Kim and Jae W. Lee and Jintae Kim
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 70
number: 9
pages: 3228--3232
year: 2023
DOI: https://doi.org/10.1109/TCSII.2023.3273290
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Jongho Kim and Young H. Oh and Hyeonsik Kim and Jae W. Lee and Jintae Kim
title:
A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch

keywords:
Capacitors; charge injection SAR (ci-SAR); Circuit stability; Clamps; Computing-in-memory (CIM); Delays; digital-to-time converter (DTC); Microprocessors; multiply-and-accumulate (MAC); Throughput; Voltage

rawtitle:
A 4-bit 4.5-ns-Latency {Pseudo-ReRAM} Computing-In-Memory Macro With Self Error-Correcting {DTC}-Based {WL} Drivers and 6-bit {CDAC}-Less Column {ADCs} Having Ultra-Narrow Pitch

entry:
@Article{Kim:2023:BNL,
  author =       "Jongho Kim and Young H. Oh and Hyeonsik Kim and Jae W.
                 Lee and Jintae Kim",
  title =        "A 4-bit 4.5-ns-Latency {Pseudo-ReRAM}
                 Computing-In-Memory Macro With Self Error-Correcting
                 {DTC}-Based {WL} Drivers and 6-bit {CDAC}-Less Column
                 {ADCs} Having Ultra-Narrow Pitch",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "9",
  pages =        "3228--3232",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3273290",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "Capacitors; charge injection SAR (ci-SAR); Circuit
                 stability; Clamps; Computing-in-memory (CIM); Delays;
                 digital-to-time converter (DTC); Microprocessors;
                 multiply-and-accumulate (MAC); Throughput; Voltage",
}


bibtype: article
filename: fparith.bib
label: Kim:2023:MMS
author: Whijin Kim and Hana Kim and Jihye Lee and Hyunji Kim and Ji-Hoon Kim
title: Multi-Mode SpMV Accelerator for Transprecision PageRank With Real-World Graphs
journal: j-IEEE-ACCESS
volume: 11
pages: 6261--6272
year: 2023
DOI: https://doi.org/10.1109/ACCESS.2023.3237079
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:40:18 2025
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Whijin Kim and Hana Kim and Jihye Lee and Hyunji Kim and Ji-Hoon Kim
rawtitle: Multi-Mode {SpMV} Accelerator for Transprecision {PageRank} With Real-World Graphs
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pagerank.bib

keywords:
floating-point multiplier; graph processing; half-precision (FP16); Hardware; Hypertext systems; Internet; Magnetic flux; PageRank (PR); single-precision (FP32); Social networking (online); Sparse matrices; sparse matrix vector multiplication (SpMV); Transprecision; Web search

entry:
@Article{Kim:2023:MMS,
  author =       "Whijin Kim and Hana Kim and Jihye Lee and Hyunji Kim
                 and Ji-Hoon Kim",
  title =        "Multi-Mode {SpMV} Accelerator for Transprecision
                 {PageRank} With Real-World Graphs",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  pages =        "6261--6272",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3237079",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pagerank.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "floating-point multiplier; graph processing;
                 half-precision (FP16); Hardware; Hypertext systems;
                 Internet; Magnetic flux; PageRank (PR);
                 single-precision (FP32); Social networking (online);
                 Sparse matrices; sparse matrix vector multiplication
                 (SpMV); Transprecision; Web search",
}


bibtype: article
filename: fparith.bib
label: Klower:2023:POC
author: Milan Klower and Peter V. Coveney and E. Adam Paxton and Tim N. Palmer
title: Periodic orbits in chaotic systems simulated at low precision
journal: j-SCI-REP
volume: 13
number: 1
pages: 6261--6272
month: jul
monthnumber: 7
year: 2023
CODEN: SRCEC3
DOI: https://doi.org/10.1038/s41598-023-37004-4
ISSN: 2045-2322 OR 20452322
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
fjournal: Scientific Reports
keywords: posit arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.nature.com/srep/
rawauthor: Milan Kl{\"o}wer and Peter V. Coveney and E. Adam Paxton and Tim N. Palmer
rawtitle: Periodic orbits in chaotic systems simulated at low precision
entry:
@Article{Klower:2023:POC,
  author =       "Milan Kl{\"o}wer and Peter V. Coveney and E. Adam
                 Paxton and Tim N. Palmer",
  title =        "Periodic orbits in chaotic systems simulated at low
                 precision",
  journal =      j-SCI-REP,
  volume =       "13",
  number =       "1",
  month =        jul,
  year =         "2023",
  CODEN =        "SRCEC3",
  DOI =          "https://doi.org/10.1038/s41598-023-37004-4",
  ISSN =         "2045-2322",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Scientific Reports",
  journal-URL =  "http://www.nature.com/srep/",
  keywords =     "posit arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Krishna:2023:RNF
author: Bharath Krishna
title: Rounding Numbers in the Financial Domain!
pages: 6261--6272
day: 1
month: jan
monthnumber: 1
year: 2023
bibdate: Tue Feb 27 14:40:22 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.27 14:40:22 ???
URL: https://www.foundingminds.com/rounding-numbers-in-the-financial-domain/
keywords: decimal floating-point arithmetic; rounding errors
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Bharath Krishna
rawtitle: Rounding Numbers in the Financial Domain!
note:
Includes important mention of financial regulatory sites, with this text taken verbatim from the article, because such information may be hard to find elsewhere: * International Financial Reporting Standards (IFRS): IFRS is a set of accounting standards developed by the International Accounting Standards Board (IASB). It includes guidelines on rounding financial numbers in financial statements, such as the requirement to round amounts to the nearest whole number or the nearest multiple of 10; * Generally Accepted Accounting Principles (GAAP): GAAP is a set of accounting standards used in the United States. It includes similar guidelines on rounding financial numbers as IFRS and requires that any rounding errors should be immaterial and insignificant. * International Organization for Standardization (ISO): ISO has a standard for Rounding off numerical values, which is ISO 80000-1:2009. It provides guidelines on rounding numerical values in general and not specific to the finance domain, but it's widely used in financial systems. * The Federal Reserve Board (FRB): The FRB, the central banking system of the United States, has guidelines on rounding financial numbers for bank reporting and financial statement preparation. * The European Central Bank (ECB): The ECB, the central banking system of the European Union, has similar guidelines on rounding financial numbers as the FRB.

rawnote:
Includes important mention of financial regulatory sites, with this text taken verbatim from the article, because such information may be hard to find elsewhere: * International Financial Reporting Standards (IFRS): IFRS is a set of accounting standards developed by the International Accounting Standards Board (IASB). It includes guidelines on rounding financial numbers in financial statements, such as the requirement to round amounts to the nearest whole number or the nearest multiple of 10; * Generally Accepted Accounting Principles (GAAP): GAAP is a set of accounting standards used in the United States. It includes similar guidelines on rounding financial numbers as IFRS and requires that any rounding errors should be immaterial and insignificant. * International Organization for Standardization (ISO): ISO has a standard for Rounding off numerical values, which is ISO 80000-1:2009. It provides guidelines on rounding numerical values in general and not specific to the finance domain, but it's widely used in financial systems. * The Federal Reserve Board (FRB): The FRB, the central banking system of the United States, has guidelines on rounding financial numbers for bank reporting and financial statement preparation. * The European Central Bank (ECB): The ECB, the central banking system of the European Union, has similar guidelines on rounding financial numbers as the FRB.

entry:
@Misc{Krishna:2023:RNF,
  author =       "Bharath Krishna",
  title =        "Rounding Numbers in the Financial Domain!",
  howpublished = "Web site",
  day =          "1",
  month =        jan,
  year =         "2023",
  bibdate =      "Tue Feb 27 14:40:22 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Includes important mention of financial regulatory
                 sites, with this text taken verbatim from the article,
                 because such information may be hard to find
                 elsewhere:

                 * International Financial Reporting Standards (IFRS):
                 IFRS is a set of accounting standards developed by the
                 International Accounting Standards Board (IASB). It
                 includes guidelines on rounding financial numbers in
                 financial statements, such as the requirement to round
                 amounts to the nearest whole number or the nearest
                 multiple of 10;

                 * Generally Accepted Accounting Principles (GAAP): GAAP
                 is a set of accounting standards used in the United
                 States. It includes similar guidelines on rounding
                 financial numbers as IFRS and requires that any
                 rounding errors should be immaterial and
                 insignificant.

                 * International Organization for Standardization (ISO):
                 ISO has a standard for Rounding off numerical values,
                 which is ISO 80000-1:2009. It provides guidelines on
                 rounding numerical values in general and not specific
                 to the finance domain, but it's widely used in
                 financial systems.

                 * The Federal Reserve Board (FRB): The FRB, the central
                 banking system of the United States, has guidelines on
                 rounding financial numbers for bank reporting and
                 financial statement preparation.

                 * The European Central Bank (ECB): The ECB, the central
                 banking system of the European Union, has similar
                 guidelines on rounding financial numbers as the FRB.",
  URL =          "https://www.foundingminds.com/rounding-numbers-in-the-financial-domain/",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic; rounding errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Kuo:2023:CMP
author: Pei-Hsuan Kuo and Yu-Hsiang Huang and Juinn-Dar Huang
booktitle: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/AICAS57966.2023.10168572
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Pei-Hsuan Kuo and Yu-Hsiang Huang and Juinn-Dar Huang
rawbooktitle: {2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)}
title:
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning

keywords:
Computer architecture; configurable; Deep learning; deep learning; floating-point multiplier design; Hardware; Learning (artificial intelligence); Logic gates; multi-precision computation; Pipelines; Throughput

rawtitle:
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning

entry:
@InProceedings{Kuo:2023:CMP,
  author =       "Pei-Hsuan Kuo and Yu-Hsiang Huang and Juinn-Dar
                 Huang",
  booktitle =    "{2023 IEEE 5th International Conference on Artificial
                 Intelligence Circuits and Systems (AICAS)}",
  title =        "Configurable Multi-Precision Floating-Point Multiplier
                 Architecture Design for Computation in Deep Learning",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/AICAS57966.2023.10168572",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture; configurable; Deep learning;
                 deep learning; floating-point multiplier design;
                 Hardware; Learning (artificial intelligence); Logic
                 gates; multi-precision computation; Pipelines;
                 Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Kurian:2023:PER
author: Ashley Kurian and M. Ramesh Kini
booktitle: Lecture Notes in Networks and Systems
title: Posit Extended RISC-V Processor and Its Enhancement Using Data Type Casting
publisher: Springer Nature
address: Singapore
pages: 571--586
year: 2023
DOI: https://doi.org/10.1007/978-981-19-6634-7_40
ISBN: 981-19663-4-6 OR 9811966346
ISBN13: 978-981-19663-4-7 OR 9789811966347
ISSN: 2367-3389 OR 23673389
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Ashley Kurian and M. Ramesh Kini
rawbooktitle: Lecture Notes in Networks and Systems
rawtitle: Posit Extended {RISC-V} Processor and Its Enhancement Using Data Type Casting
entry:
@InProceedings{Kurian:2023:PER,
  author =       "Ashley Kurian and M. Ramesh Kini",
  booktitle =    "Lecture Notes in Networks and Systems",
  title =        "Posit Extended {RISC-V} Processor and Its Enhancement
                 Using Data Type Casting",
  publisher =    "Springer Nature",
  address =      "Singapore",
  pages =        "571--586",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-981-19-6634-7_40",
  ISBN =         "981-19663-4-6",
  ISBN-13 =      "978-981-19663-4-7",
  ISSN =         "2367-3389",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Laguna:2023:FIT
author: Ignacio Laguna and Anh Tran and Ganesh Gopalakrishnan
journal: j-PARALLEL-COMPUTING
volume: 117
pages: 103042:1--103042:13
month: sep
monthnumber: 9
year: 2023
CODEN: PACOEJ
DOI: https://doi.org/10.1016/j.parco.2023.103042
ISSN: 0167-8191 (print), 1872-7336 (electronic) OR 01678191 (print), 18727336 (electronic)
ISSNL: 0167-8191 OR 01678191
bibdate: Thu Sep 7 08:37:05 MDT 2023
bibtimestamp: 2023.09.07 08:37:05 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0167819123000480
fjournal: Parallel Computing
acknowledgement: ack-nhfb
articleno: 103042
journalURL: http://www.sciencedirect.com/science/journal/01678191
rawauthor: Ignacio Laguna and Anh Tran and Ganesh Gopalakrishnan
title:
Finding inputs that trigger floating-point exceptions in heterogeneous computing via Bayesian optimization

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/parallelcomputing.bib

rawtitle:
Finding inputs that trigger floating-point exceptions in heterogeneous computing via {Bayesian} optimization

entry:
@Article{Laguna:2023:FIT,
  author =       "Ignacio Laguna and Anh Tran and Ganesh
                 Gopalakrishnan",
  title =        "Finding inputs that trigger floating-point exceptions
                 in heterogeneous computing via {Bayesian}
                 optimization",
  journal =      j-PARALLEL-COMPUTING,
  volume =       "117",
  number =       "??",
  pages =        "103042:1--103042:13",
  month =        sep,
  year =         "2023",
  CODEN =        "PACOEJ",
  DOI =          "https://doi.org/10.1016/j.parco.2023.103042",
  ISSN =         "0167-8191 (print), 1872-7336 (electronic)",
  ISSN-L =       "0167-8191",
  bibdate =      "Thu Sep 7 08:37:05 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/parallelcomputing.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167819123000480",
  acknowledgement = ack-nhfb,
  articleno =    "103042",
  fjournal =     "Parallel Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01678191",
}


bibtype: inproceedings
filename: fparith.bib
label: Lee:2023:WFF
author: Sunwoo Lee and Jeongwoo Park and Dongsuk Jeon
booktitle: ESSCIRC 2023 --- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 221--224
year: 2023
DOI: https://doi.org/10.1109/ESSCIRC59616.2023.10268686
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Sunwoo Lee and Jeongwoo Park and Dongsuk Jeon
rawbooktitle: {ESSCIRC 2023 --- IEEE 49th European Solid State Circuits Conference (ESSCIRC)}
title:
A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array

keywords:
Convolution; Deep Learning; Logarithmic Weight; Low-precision Training; Memory management; Parallel processing; Power demand; Reconfigurable PE Array; Routing; System-on-chip; Training

rawtitle:
A {4.27TFLOPS/W} {FP4/FP8} Hybrid-Precision Neural Network Training Processor Using Shift-Add {MAC} and Reconfigurable {PE} Array

entry:
@InProceedings{Lee:2023:WFF,
  author =       "Sunwoo Lee and Jeongwoo Park and Dongsuk Jeon",
  booktitle =    "{ESSCIRC 2023 --- IEEE 49th European Solid State
                 Circuits Conference (ESSCIRC)}",
  title =        "A {4.27TFLOPS/W} {FP4/FP8} Hybrid-Precision Neural
                 Network Training Processor Using Shift-Add {MAC} and
                 Reconfigurable {PE} Array",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "221--224",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ESSCIRC59616.2023.10268686",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Convolution; Deep Learning; Logarithmic Weight;
                 Low-precision Training; Memory management; Parallel
                 processing; Power demand; Reconfigurable PE Array;
                 Routing; System-on-chip; Training",
}


bibtype: article
filename: fparith.bib
label: Leitersdorf:2023:AHT
title: AritPIM: High-Throughput In-Memory Arithmetic
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 11
number: 3
pages: 720--735
month: jul
monthnumber: 7
year: 2023
DOI: https://doi.org/10.1109/TETC.2023.3268137
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawtitle: {AritPIM}: High-Throughput In-Memory Arithmetic
author:
Orian Leitersdorf and Dean Leitersdorf and Jonathan Gal and Mor Dahan and Ronny Ronen and Shahar Kvatinsky

abstract:
Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the form of parallel bitwise logic operations. We develop novel algorithmic techniques for PIM that, combined with new perspectives on computer arithmetic, extend this bitwise parallelism to the four fundamental arithmetic operations (addition, subtraction, multiplication, and division), for both fixed-point and floating-point numbers, and using both bit-serial and bit-parallel approaches. We propose a state-of-the-art suite of arithmetic algorithms, demonstrating the first algorithm in the literature of digital PIM for a majority of cases --- including cases previously considered impossible for digital PIM, such as floating-point addition. Through a case study on memristive PIM, we compare the proposed algorithms to an NVIDIA RTX 3070 GPU and demonstrate significant throughput and energy improvements.

rawabstract:
Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the form of parallel bitwise logic operations. We develop novel algorithmic techniques for PIM that, combined with new perspectives on computer arithmetic, extend this bitwise parallelism to the four fundamental arithmetic operations (addition, subtraction, multiplication, and division), for both fixed-point and floating-point numbers, and using both bit-serial and bit-parallel approaches. We propose a state-of-the-art suite of arithmetic algorithms, demonstrating the first algorithm in the literature of digital PIM for a majority of cases --- including cases previously considered impossible for digital PIM, such as floating-point addition. Through a case study on memristive PIM, we compare the proposed algorithms to an NVIDIA RTX 3070 GPU and demonstrate significant throughput and energy improvements.

rawauthor:
Orian Leitersdorf and Dean Leitersdorf and Jonathan Gal and Mor Dahan and Ronny Ronen and Shahar Kvatinsky

entry:
@Article{Leitersdorf:2023:AHT,
  author =       "Orian Leitersdorf and Dean Leitersdorf and Jonathan
                 Gal and Mor Dahan and Ronny Ronen and Shahar
                 Kvatinsky",
  title =        "{AritPIM}: High-Throughput In-Memory Arithmetic",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "11",
  number =       "3",
  pages =        "720--735",
  month =        jul # "\slash " # sep,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TETC.2023.3268137",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "Digital processing-in-memory (PIM) architectures are
                 rapidly emerging to overcome the memory-wall bottleneck
                 by integrating logic within memory elements. Such
                 architectures provide vast computational power within
                 the memory itself in the form of parallel bitwise logic
                 operations. We develop novel algorithmic techniques for
                 PIM that, combined with new perspectives on computer
                 arithmetic, extend this bitwise parallelism to the four
                 fundamental arithmetic operations (addition,
                 subtraction, multiplication, and division), for both
                 fixed-point and floating-point numbers, and using both
                 bit-serial and bit-parallel approaches. We propose a
                 state-of-the-art suite of arithmetic algorithms,
                 demonstrating the first algorithm in the literature of
                 digital PIM for a majority of cases --- including cases
                 previously considered impossible for digital PIM, such
                 as floating-point addition. Through a case study on
                 memristive PIM, we compare the proposed algorithms to
                 an NVIDIA RTX 3070 GPU and demonstrate significant
                 throughput and energy improvements.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Leong:2023:LFU
author: Siew Hoon Leong and John L. Gustafson
title: Lossless FFTs Using Posit Arithmetic
crossref: Gustafson:2023:NGA
pages: 1--18
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_1
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Siew Hoon Leong and John L. Gustafson
rawtitle: Lossless {FFTs} Using Posit Arithmetic
entry:
@InProceedings{Leong:2023:LFU,
  author =       "Siew Hoon Leong and John L. Gustafson",
  title =        "Lossless {FFTs} Using Posit Arithmetic",
  crossref =     "Gustafson:2023:NGA",
  pages =        "1--18",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_1",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2023:DEG
publisher: pub-ACM
address: pub-ACM:adr
pages: 59--71
month: aug
monthnumber: 8
year: 2023
DOI: https://doi.org/10.1145/3588195.3592991
bibdate: Thu Sep 7 09:13:15 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.07 09:13:15 ???
URL: https://dl.acm.org/doi/10.1145/3588195.3592991; https://github.com/LLNL/GPU-FPX
acknowledgement: ack-nhfb
author:
Xinyi Li and Ignacio Laguna and Bo Fang and Katarzyna Swirydowicz and Ang Li and Ganesh Gopalakrishnan

booktitle:
Proceedings of the 32nd International Symposium on High-Performance Parallel and Distributed Computing

title:
Design and Evaluation of GPU-FPX: a Low-Overhead tool for Floating-Point Exception Detection in NVIDIA GPUs

abstract:
Floating-point exceptions occurring during numerical computations can be a serious threat to the validity of the computed results if they are not caught and diagnosed Unfortunately, on NVIDIA GPUs --- today's most widely used types and which do not have hardware exception traps --- this task must be carried out in software. Given the prevalence of closed-source kernels, efficient binary-level exception tracking is essential. It is also important to know how exceptions flow through the code, whether they alter the code behavior and additionally whether these exceptions can be detected at the program outputs or are killed inside program flow-paths. In this paper, we introduce GPU-FPX, a tool that has low overhead, allows for deep understanding of the origin and flow of exceptions, and also how exceptions are modified by code optimizations. We measure GPU-FPX's performance over 151 widely used GPU programs coming from HPC and ML, detecting 26 serious exceptions that were previously not reported. Our results show that GPU-FPX is $ 16 times $ faster with respect to the geometric-mean runtime in relation to the only comparable prior tool, while also helping debug a larger class of codes more effectively.

rawabstract:
Floating-point exceptions occurring during numerical computations can be a serious threat to the validity of the computed results if they are not caught and diagnosed Unfortunately, on NVIDIA GPUs --- today's most widely used types and which do not have hardware exception traps --- this task must be carried out in software. Given the prevalence of closed-source kernels, efficient binary-level exception tracking is essential. It is also important to know how exceptions flow through the code, whether they alter the code behavior and additionally whether these exceptions can be detected at the program outputs or are killed inside program flow-paths. In this paper, we introduce GPU-FPX, a tool that has low overhead, allows for deep understanding of the origin and flow of exceptions, and also how exceptions are modified by code optimizations. We measure GPU-FPX's performance over 151 widely used GPU programs coming from HPC and ML, detecting 26 serious exceptions that were previously not reported. Our results show that GPU-FPX is $ 16 \times $ faster with respect to the geometric-mean runtime in relation to the only comparable prior tool, while also helping debug a larger class of codes more effectively.

rawauthor:
Xinyi Li and Ignacio Laguna and Bo Fang and Katarzyna Swirydowicz and Ang Li and Ganesh Gopalakrishnan

rawbooktitle:
Proceedings of the {32nd International Symposium on High-Performance Parallel and Distributed Computing}

rawtitle:
Design and Evaluation of {GPU-FPX}: a Low-Overhead tool for Floating-Point Exception Detection in {NVIDIA GPUs}

entry:
@InProceedings{Li:2023:DEG,
  author =       "Xinyi Li and Ignacio Laguna and Bo Fang and Katarzyna
                 Swirydowicz and Ang Li and Ganesh Gopalakrishnan",
  booktitle =    "Proceedings of the {32nd International Symposium on
                 High-Performance Parallel and Distributed Computing}",
  title =        "Design and Evaluation of {GPU-FPX}: a Low-Overhead
                 tool for Floating-Point Exception Detection in {NVIDIA
                 GPUs}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "59--71",
  month =        aug,
  year =         "2023",
  DOI =          "https://doi.org/10.1145/3588195.3592991",
  bibdate =      "Thu Sep 7 09:13:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3588195.3592991;
                 https://github.com/LLNL/GPU-FPX",
  abstract =     "Floating-point exceptions occurring during numerical
                 computations can be a serious threat to the validity of
                 the computed results if they are not caught and
                 diagnosed Unfortunately, on NVIDIA GPUs --- today's
                 most widely used types and which do not have hardware
                 exception traps --- this task must be carried out in
                 software. Given the prevalence of closed-source
                 kernels, efficient binary-level exception tracking is
                 essential. It is also important to know how exceptions
                 flow through the code, whether they alter the code
                 behavior and additionally whether these exceptions can
                 be detected at the program outputs or are killed inside
                 program flow-paths. In this paper, we introduce
                 GPU-FPX, a tool that has low overhead, allows for deep
                 understanding of the origin and flow of exceptions, and
                 also how exceptions are modified by code optimizations.
                 We measure GPU-FPX's performance over 151 widely used
                 GPU programs coming from HPC and ML, detecting 26
                 serious exceptions that were previously not reported.
                 Our results show that GPU-FPX is $ 16 \times $ faster
                 with respect to the geometric-mean runtime in relation
                 to the only comparable prior tool, while also helping
                 debug a larger class of codes more effectively.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Li:2023:DSE
author: He Li and Jiawei Liang and Hongxiang Fan and Yongming Tang
title: Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 6
pages: 1822--1829
month: jun
monthnumber: 6
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3215891
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed May 17 10:34:15 2023
bibtimestamp: 2023.05.17 10:34:15 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: He Li and Jiawei Liang and Hongxiang Fan and Yongming Tang
rawtitle: Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic
abstract:
Quantum computing has been considered as an emerging approach in addressing problems which are not easily solvable using classical computers. In parallel to the physical implementation of quantum processors, quantum algorithms have been actively developed for real-life applications to show quantum advantages, many of which benefit from quantum arithmetic algorithms and their efficient implementations. As one of the most important operations, quantum addition has been adopted in Shor's algorithm and quantum linear algebra algorithms. Although various least-significant digit-first quantum adders have been introduced in previous work, interest in investigating the efficient implementation of most-significant digit-first addition is growing. In this work, we propose a novel design method for most-significant digit-first addition with several quantum circuit optimisations to reduce the number of quantum bits (i.e. qubits), quantum gates, and circuit depth. An open-source library of different arithmetic operators based on our proposed method is presented, where all circuits are implemented on IBM Qiskit SDK. Extensive experiments demonstrate that our proposed design, together with the optimisation techniques, reduces T-depth by up-to 4.0$ times $, T-count by 3.5$ times $, and qubit consumption by 1.2$ times $.

rawabstract:
Quantum computing has been considered as an emerging approach in addressing problems which are not easily solvable using classical computers. In parallel to the physical implementation of quantum processors, quantum algorithms have been actively developed for real-life applications to show quantum advantages, many of which benefit from quantum arithmetic algorithms and their efficient implementations. As one of the most important operations, quantum addition has been adopted in Shor's algorithm and quantum linear algebra algorithms. Although various least-significant digit-first quantum adders have been introduced in previous work, interest in investigating the efficient implementation of most-significant digit-first addition is growing. In this work, we propose a novel design method for most-significant digit-first addition with several quantum circuit optimisations to reduce the number of quantum bits (i.e. qubits), quantum gates, and circuit depth. An open-source library of different arithmetic operators based on our proposed method is presented, where all circuits are implemented on IBM Qiskit SDK. Extensive experiments demonstrate that our proposed design, together with the optimisation techniques, reduces T-depth by up-to 4.0$ \times $, T-count by 3.5$ \times $, and qubit consumption by 1.2$ \times $.

entry:
@Article{Li:2023:DSE,
  author =       "He Li and Jiawei Liang and Hongxiang Fan and Yongming
                 Tang",
  title =        "Design Space Exploration for Efficient Quantum
                 Most-Significant Digit-First Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "6",
  pages =        "1822--1829",
  month =        jun,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3215891",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed May 17 10:34:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Quantum computing has been considered as an emerging
                 approach in addressing problems which are not easily
                 solvable using classical computers. In parallel to the
                 physical implementation of quantum processors, quantum
                 algorithms have been actively developed for real-life
                 applications to show quantum advantages, many of which
                 benefit from quantum arithmetic algorithms and their
                 efficient implementations. As one of the most important
                 operations, quantum addition has been adopted in Shor's
                 algorithm and quantum linear algebra algorithms.
                 Although various least-significant digit-first quantum
                 adders have been introduced in previous work, interest
                 in investigating the efficient implementation of
                 most-significant digit-first addition is growing. In
                 this work, we propose a novel design method for
                 most-significant digit-first addition with several
                 quantum circuit optimisations to reduce the number of
                 quantum bits (i.e. qubits), quantum gates, and circuit
                 depth. An open-source library of different arithmetic
                 operators based on our proposed method is presented,
                 where all circuits are implemented on IBM Qiskit SDK.
                 Extensive experiments demonstrate that our proposed
                 design, together with the optimisation techniques,
                 reduces T-depth by up-to 4.0$ \times $, T-count by 3.5$
                 \times $, and qubit consumption by 1.2$ \times $.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Li:2023:EEB
author: Ruiyuan Li and Zheng Li and Yi Wu and Chao Chen and Yu Zheng
title: Elf: Erasing-Based Lossless Floating-Point Compression
journal: j-PROC-VLDB-ENDOWMENT
volume: 16
number: 7
pages: 1763--1776
month: mar
monthnumber: 3
year: 2023
DOI: https://doi.org/10.14778/3587136.3587149
ISSN: 2150-8097 OR 21508097
bibdate: Tue May 9 09:08:30 MDT 2023
bibtimestamp: 2023.05.09 09:08:30 MDT
URL: https://dl.acm.org/doi/10.14778/3587136.3587149
fjournal: Proceedings of the VLDB Endowment
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/pvldb
rawauthor: Ruiyuan Li and Zheng Li and Yi Wu and Chao Chen and Yu Zheng
rawtitle: {Elf}: Erasing-Based Lossless Floating-Point Compression
bibsource:
https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/vldbe.bib

abstract:
There are a prohibitively large number of floating-point time series data generated at an unprecedentedly high rate. An efficient, compact and lossless compression for time series data is of great importance for a wide range of scenarios. Most existing lossless floating-point compression methods are based on the XOR operation, but they do not fully exploit the trailing zeros, which usually results in an unsatisfactory compression ratio. This paper proposes an Erasing-based Lossless Floating-point compression algorithm, i.e., pkg Elf. The main idea of pkg Elf is to erase the last few bits (i.e., set them to zero) of floating-point values, so the XORed values are supposed to contain many trailing zeros. The challenges of the erasing-based method are three-fold. First, how to quickly determine the erased bits? Second, how to losslessly recover the original data from the erased ones? Third, how to compactly encode the erased data? Through rigorous mathematical analysis, pkg Elf can directly determine the erased bits and restore the original values without losing any precision. To further improve the compression ratio, we propose a novel encoding strategy for the XORed values with many trailing zeros. pkg Elf works in a streaming fashion. It takes only $ O(N) $ (where $N$ is the length of a time series) in time and $ O(1)$ in space, and achieves a notable compression ratio with a theoretical guarantee. Extensive experiments using 22 datasets show the powerful performance of pkg Elf compared with 9 advanced competitors.

rawabstract:
There are a prohibitively large number of floating-point time series data generated at an unprecedentedly high rate. An efficient, compact and lossless compression for time series data is of great importance for a wide range of scenarios. Most existing lossless floating-point compression methods are based on the XOR operation, but they do not fully exploit the trailing zeros, which usually results in an unsatisfactory compression ratio. This paper proposes an Erasing-based Lossless Floating-point compression algorithm, i.e., \pkg{Elf}. The main idea of \pkg{Elf} is to erase the last few bits (i.e., set them to zero) of floating-point values, so the XORed values are supposed to contain many trailing zeros. The challenges of the erasing-based method are three-fold. First, how to quickly determine the erased bits? Second, how to losslessly recover the original data from the erased ones? Third, how to compactly encode the erased data? Through rigorous mathematical analysis, \pkg{Elf} can directly determine the erased bits and restore the original values without losing any precision. To further improve the compression ratio, we propose a novel encoding strategy for the XORed values with many trailing zeros. \pkg{Elf} works in a streaming fashion. It takes only $ O(N) $ (where $N$ is the length of a time series) in time and $ O(1)$ in space, and achieves a notable compression ratio with a theoretical guarantee. Extensive experiments using 22 datasets show the powerful performance of \pkg{Elf} compared with 9 advanced competitors.

entry:
@Article{Li:2023:EEB,
  author =       "Ruiyuan Li and Zheng Li and Yi Wu and Chao Chen and Yu
                 Zheng",
  title =        "{Elf}: Erasing-Based Lossless Floating-Point
                 Compression",
  journal =      j-PROC-VLDB-ENDOWMENT,
  volume =       "16",
  number =       "7",
  pages =        "1763--1776",
  month =        mar,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.14778/3587136.3587149",
  ISSN =         "2150-8097",
  bibdate =      "Tue May 9 09:08:30 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/vldbe.bib",
  URL =          "https://dl.acm.org/doi/10.14778/3587136.3587149",
  abstract =     "There are a prohibitively large number of
                 floating-point time series data generated at an
                 unprecedentedly high rate. An efficient, compact and
                 lossless compression for time series data is of great
                 importance for a wide range of scenarios. Most existing
                 lossless floating-point compression methods are based
                 on the XOR operation, but they do not fully exploit the
                 trailing zeros, which usually results in an
                 unsatisfactory compression ratio. This paper proposes
                 an Erasing-based Lossless Floating-point compression
                 algorithm, i.e., \pkg{Elf}. The main idea of \pkg{Elf}
                 is to erase the last few bits (i.e., set them to zero)
                 of floating-point values, so the XORed values are
                 supposed to contain many trailing zeros. The challenges
                 of the erasing-based method are three-fold. First, how
                 to quickly determine the erased bits? Second, how to
                 losslessly recover the original data from the erased
                 ones? Third, how to compactly encode the erased data?
                 Through rigorous mathematical analysis, \pkg{Elf} can
                 directly determine the erased bits and restore the
                 original values without losing any precision. To
                 further improve the compression ratio, we propose a
                 novel encoding strategy for the XORed values with many
                 trailing zeros. \pkg{Elf} works in a streaming fashion.
                 It takes only $ O(N) $ (where $N$ is the length of a
                 time series) in time and $ O(1)$ in space, and achieves
                 a notable compression ratio with a theoretical
                 guarantee. Extensive experiments using 22 datasets show
                 the powerful performance of \pkg{Elf} compared with 9
                 advanced competitors.",
  acknowledgement = ack-nhfb,
  fjournal =     "Proceedings of the VLDB Endowment",
  journal-URL =  "https://dl.acm.org/loi/pvldb",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2023:POS
author: Qiong Li and Chao Fang and Zhongfeng Wang
editor: IEEE
booktitle: 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
title: PDPU: an Open-Source Posit Dot-Product Unit for Deep Learning Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ISCAS46773.2023.10182007
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Qiong Li and Chao Fang and Zhongfeng Wang
rawbooktitle: {2023 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: {IEEE}
rawtitle: {PDPU}: an Open-Source Posit Dot-Product Unit for Deep Learning Applications
entry:
@InProceedings{Li:2023:POS,
  author =       "Qiong Li and Chao Fang and Zhongfeng Wang",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{PDPU}: an Open-Source Posit Dot-Product Unit for Deep
                 Learning Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10182007",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Liu:2023:CHR
author: Zixuan Liu and Xiaoyu Song and Zhuowei Wang and Yan Wang and Jian-Tao Zhou
title: Constructing High Radix Quotient Digit Selection Tables for SRT Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 7
pages: 2111--2119
month: jul
monthnumber: 7
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3235978
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 1 10:59:22 2023
bibtimestamp: 2023.07.01 10:59:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Zixuan Liu and Xiaoyu Song and Zhuowei Wang and Yan Wang and Jian-Tao Zhou
rawtitle: Constructing High Radix Quotient Digit Selection Tables for {SRT} Division and Square Root
entry:
@Article{Liu:2023:CHR,
  author =       "Zixuan Liu and Xiaoyu Song and Zhuowei Wang and Yan
                 Wang and Jian-Tao Zhou",
  title =        "Constructing High Radix Quotient Digit Selection
                 Tables for {SRT} Division and Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "7",
  pages =        "2111--2119",
  month =        jul,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3235978",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 1 10:59:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Livesay:2023:AFF
title: Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs
journal: j-IEEE-MICRO
volume: 43
number: 5
pages: 55--63
month: sep
monthnumber: 9
year: 2023
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2023.3253052
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Thu Sep 14 06:42:28 2023
bibtimestamp: 2023.09.14 06:42:28 ???
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40
rawtitle: Accelerating Finite Field Arithmetic for Homomorphic Encryption on {GPUs}
author:
Neal Livesay and Gilbert Jonatan and Evelio Mora and Kaustubh Shivdikar and Rashmi Agrawal and Ajay Joshi and Jose L. Abellan and John Kim and David Kaeli

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib

rawauthor:
Neal Livesay and Gilbert Jonatan and Evelio Mora and Kaustubh Shivdikar and Rashmi Agrawal and Ajay Joshi and Jos{\'e} L. Abell{\'a}n and John Kim and David Kaeli

entry:
@Article{Livesay:2023:AFF,
  author =       "Neal Livesay and Gilbert Jonatan and Evelio Mora and
                 Kaustubh Shivdikar and Rashmi Agrawal and Ajay Joshi
                 and Jos{\'e} L. Abell{\'a}n and John Kim and David
                 Kaeli",
  title =        "Accelerating Finite Field Arithmetic for Homomorphic
                 Encryption on {GPUs}",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "5",
  pages =        "55--63",
  month =        sep # "\slash " # oct,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3253052",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Sep 14 06:42:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}


bibtype: inproceedings
filename: fparith.bib
label: Lo:2023:BGB
author: Yun-Chen Lo and Ren-Shuo Liu
booktitle: 2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO)
title: Bucket Getter: a Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1002--1015
year: 2023
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Yun-Chen Lo and Ren-Shuo Liu
rawbooktitle: {2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO)}
rawtitle: {Bucket Getter}: a Bucket-based Processing Engine for Low-bit Block Floating Point {(BFP) DNNs}
keywords:
Artificial neural networks; Bucket-based accumulation; Computer architecture; Deep learning; Engines; Floating-point architecture; Gettering; Hardware; Microarchitecture; Organizations

entry:
@InProceedings{Lo:2023:BGB,
  author =       "Yun-Chen Lo and Ren-Shuo Liu",
  booktitle =    "{2023 56th IEEE/ACM International Symposium on
                 Microarchitecture (MICRO)}",
  title =        "{Bucket Getter}: a Bucket-based Processing Engine for
                 Low-bit Block Floating Point {(BFP) DNNs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1002--1015",
  year =         "2023",
  DOI =          "",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Artificial neural networks; Bucket-based accumulation;
                 Computer architecture; Deep learning; Engines;
                 Floating-point architecture; Gettering; Hardware;
                 Microarchitecture; Organizations",
}


bibtype: inproceedings
filename: fparith.bib
label: Mai:2023:TWC
author: Yangzhan Mai and Mingyu Wang and Chuanghao Zhang and Baiqing Zhong and Zhiyi Yu
booktitle: 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ISCAS46773.2023.10182197
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Yangzhan Mai and Mingyu Wang and Chuanghao Zhang and Baiqing Zhong and Zhiyi Yu
rawbooktitle: {2023 IEEE International Symposium on Circuits and Systems (ISCAS)}
title:
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips

keywords:
AI accelerators; Computation-in-memory (CIM); Energy efficiency; Floating-point; Neural networks; Parallel Alignment; Simulation; SRAM; Throughput; Training; Voltage measurement

rawtitle:
A 1.97 {TFLOPS/W} Configurable {SRAM}-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient {AI} Chips

entry:
@InProceedings{Mai:2023:TWC,
  author =       "Yangzhan Mai and Mingyu Wang and Chuanghao Zhang and
                 Baiqing Zhong and Zhiyi Yu",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "A 1.97 {TFLOPS/W} Configurable {SRAM}-Based
                 Floating-Point Computation-in-Memory Macro for
                 Energy-Efficient {AI} Chips",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10182197",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AI accelerators; Computation-in-memory (CIM); Energy
                 efficiency; Floating-point; Neural networks; Parallel
                 Alignment; Simulation; SRAM; Throughput; Training;
                 Voltage measurement",
}


bibtype: inproceedings
filename: fparith.bib
label: Malathi:2023:DRV
author: D Malathi and R Sneha and M Shanmugapriya and S Sethurajan
editor: IEEE
booktitle: 2023 4th International Conference on Signal Processing and Communication (ICSPC)
title: Design of RISC-V Processing Unit Using Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 427--431
year: 2023
DOI: https://doi.org/10.1109/ICSPC57692.2023.10125646
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: D Malathi and R Sneha and M Shanmugapriya and S Sethurajan
rawbooktitle: {2023 4th International Conference on Signal Processing and Communication (ICSPC)}
raweditor: {IEEE}
rawtitle: Design of {RISC-V} Processing Unit Using Posit Number System
entry:
@InProceedings{Malathi:2023:DRV,
  author =       "D Malathi and R Sneha and M Shanmugapriya and S
                 Sethurajan",
  editor =       "{IEEE}",
  booktitle =    "{2023 4th International Conference on Signal
                 Processing and Communication (ICSPC)}",
  title =        "Design of {RISC-V} Processing Unit Using Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "427--431",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICSPC57692.2023.10125646",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Mansfield:2023:MSR
author: Daniel F. Mansfield
title: Mesopotamian square root approximation by a sequence of rectangles
journal: j-BRITISH-J-HIST-MATH
volume: 38
number: 3
pages: 175--188
year: 2023
DOI: https://doi.org/10.1080/26375451.2023.2215652
ISSN: 1749-8430 (print), 1749-8341 (electronic) OR 17498430 (print), 17498341 (electronic)
ISSNL: 1749-8341 OR 17498341
bibdate: Thu Apr 25 11:06:30 MDT 2024
bibtimestamp: 2024.04.25 11:06:30 MDT
URL: http://www.tandfonline.com/doi/full/10.1080/26375451.2023.2215652
fjournal: BSHM Bulletin: Journal of the British Society for the History of Mathematics
acknowledgement: ack-nhfb
ajournal: BSHM Bull.
journalURL: http://www.tandfonline.com/loi/tbsh20
onlinedate: 09 Jun 2023
rawauthor: Daniel F. Mansfield
rawtitle: {Mesopotamian} square root approximation by a sequence of rectangles
bibsource:
https://www.math.utah.edu/pub/tex/bib/bshm.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Mansfield:2023:MSR,
  author =       "Daniel F. Mansfield",
  title =        "{Mesopotamian} square root approximation by a sequence
                 of rectangles",
  journal =      j-BRITISH-J-HIST-MATH,
  volume =       "38",
  number =       "3",
  pages =        "175--188",
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1080/26375451.2023.2215652",
  ISSN =         "1749-8430 (print), 1749-8341 (electronic)",
  ISSN-L =       "1749-8341",
  bibdate =      "Thu Apr 25 11:06:30 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bshm.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.tandfonline.com/doi/full/10.1080/26375451.2023.2215652",
  acknowledgement = ack-nhfb,
  ajournal =     "BSHM Bull.",
  fjournal =     "BSHM Bulletin: Journal of the British Society for the
                 History of Mathematics",
  journal-URL =  "http://www.tandfonline.com/loi/tbsh20",
  onlinedate =   "09 Jun 2023",
}


bibtype: article
filename: fparith.bib
label: Martin-Dorel:2023:EFP
author: Erik Martin-Dorel and Guillaume Melquiond and Pierre Roux
title: Enabling Floating-Point Arithmetic in the Coq Proof Assistant
journal: j-J-AUTOM-REASON
volume: 67
number: 4
pages: ??--??
month: dec
monthnumber: 12
year: 2023
CODEN: JAREEW
DOI: https://doi.org/10.1007/s10817-023-09679-x
ISSN: 0168-7433 (print), 1573-0670 (electronic) OR 01687433 (print), 15730670 (electronic)
ISSNL: 0168-7433 OR 01687433
bibdate: Mon Nov 27 10:14:54 MST 2023
bibtimestamp: 2023.11.27 10:14:54 MST
URL: https://link.springer.com/article/10.1007/s10817-023-09679-x
fjournal: Journal of Automated Reasoning
acknowledgement: ack-nhfb
ajournal: J. Autom. Reason.
articleno: 33
journalURL: http://link.springer.com/journal/10817
rawauthor: {\'E}rik Martin-Dorel and Guillaume Melquiond and Pierre Roux
rawtitle: Enabling Floating-Point Arithmetic in the {Coq} Proof Assistant
entry:
@Article{Martin-Dorel:2023:EFP,
  author =       "{\'E}rik Martin-Dorel and Guillaume Melquiond and
                 Pierre Roux",
  title =        "Enabling Floating-Point Arithmetic in the {Coq} Proof
                 Assistant",
  journal =      j-J-AUTOM-REASON,
  volume =       "67",
  number =       "4",
  pages =        "??--??",
  month =        dec,
  year =         "2023",
  CODEN =        "JAREEW",
  DOI =          "https://doi.org/10.1007/s10817-023-09679-x",
  ISSN =         "0168-7433 (print), 1573-0670 (electronic)",
  ISSN-L =       "0168-7433",
  bibdate =      "Mon Nov 27 10:14:54 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jautomreason.bib",
  URL =          "https://link.springer.com/article/10.1007/s10817-023-09679-x",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Autom. Reason.",
  articleno =    "33",
  fjournal =     "Journal of Automated Reasoning",
  journal-URL =  "http://link.springer.com/journal/10817",
}


bibtype: article
filename: fparith.bib
label: Melquiond:2023:WFV
author: Guillaume Melquiond and Raphael Rieu-Helft
title: WhyMP, a formally verified arbitrary-precision integer library
journal: j-J-SYMBOLIC-COMP
volume: 115
pages: 74--95
month: mar
monthnumber: 3
year: 2023
CODEN: JSYCEH
DOI: https://doi.org/10.1016/j.jsc.2022.07.007
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Sat Sep 17 06:23:51 MDT 2022
bibtimestamp: 2022.09.17 06:23:51 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0747717122000657
fjournal: Journal of Symbolic Computation
keywords: Deductive program verification; Integer arithmetic; Mathematical library
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07477171
rawauthor: Guillaume Melquiond and Rapha{\"e}l Rieu-Helft
rawtitle: {WhyMP}, a formally verified arbitrary-precision integer library
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/gnu.bib; https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib

abstract:
Arbitrary-precision integer libraries such as GMP are a critical building block of computer algebra systems. GMP provides state-of-the-art algorithms that are intricate enough to justify formal verification. In this paper, we present a C library that has been formally verified using the Why3 verification platform in about four person-years. This verification deals not only with safety, but with full functional correctness. It has been performed using a mixture of mechanically checked handwritten proofs and automated theorem proving. We have implemented and verified a nontrivial subset of GMP's algorithms, including their optimizations and intricacies. Our library provides the same interface as GMP and is almost as efficient for smaller inputs. We detail our verification methodology and the algorithms we have implemented, and include some benchmarks to compare our library with GMP.

rawabstract:
Arbitrary-precision integer libraries such as GMP are a critical building block of computer algebra systems. GMP provides state-of-the-art algorithms that are intricate enough to justify formal verification. In this paper, we present a C library that has been formally verified using the Why3 verification platform in about four person-years. This verification deals not only with safety, but with full functional correctness. It has been performed using a mixture of mechanically checked handwritten proofs and automated theorem proving. We have implemented and verified a nontrivial subset of GMP's algorithms, including their optimizations and intricacies. Our library provides the same interface as GMP and is almost as efficient for smaller inputs. We detail our verification methodology and the algorithms we have implemented, and include some benchmarks to compare our library with GMP.

entry:
@Article{Melquiond:2023:WFV,
  author =       "Guillaume Melquiond and Rapha{\"e}l Rieu-Helft",
  title =        "{WhyMP}, a formally verified arbitrary-precision
                 integer library",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "115",
  number =       "??",
  pages =        "74--95",
  month =        mar # "\slash " # apr,
  year =         "2023",
  CODEN =        "JSYCEH",
  DOI =          "https://doi.org/10.1016/j.jsc.2022.07.007",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Sat Sep 17 06:23:51 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0747717122000657",
  abstract =     "Arbitrary-precision integer libraries such as GMP are
                 a critical building block of computer algebra systems.
                 GMP provides state-of-the-art algorithms that are
                 intricate enough to justify formal verification. In
                 this paper, we present a C library that has been
                 formally verified using the Why3 verification platform
                 in about four person-years. This verification deals not
                 only with safety, but with full functional correctness.
                 It has been performed using a mixture of mechanically
                 checked handwritten proofs and automated theorem
                 proving. We have implemented and verified a nontrivial
                 subset of GMP's algorithms, including their
                 optimizations and intricacies. Our library provides the
                 same interface as GMP and is almost as efficient for
                 smaller inputs. We detail our verification methodology
                 and the algorithms we have implemented, and include
                 some benchmarks to compare our library with GMP.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
  keywords =     "Deductive program verification; Integer arithmetic;
                 Mathematical library",
}


bibtype: article
filename: fparith.bib
label: Mezzarobba:2023:REA
author: Marc Mezzarobba
title: Rounding error analysis of linear recurrences using generating series
journal: j-ELECTRON-TRANS-NUMER-ANAL
volume: 58
pages: 196--227
year: 2023
ISSN: 1068-9613 (print), 1097-4067 (electronic) OR 10689613 (print), 10974067 (electronic)
ISSNL: 1068-9613 OR 10689613
bibdate: Mon Jun 3 08:23:58 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/etna.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.03 08:23:58 MDT
fjournal: Electronic Transactions on Numerical Analysis
acknowledgement: ack-nhfb
ajournal: Electron. Trans. Numer. Anal.
journalURL: http://etna.mcs.kent.edu/
rawauthor: Marc Mezzarobba
rawtitle: Rounding error analysis of linear recurrences using generating series
URL:
https://etna.math.kent.edu/vol.58.2023/pp196-227.dir/pp196-227.pdf; https://etna.math.kent.edu/volumes/2021-2030/vol58/abstract.php?vol=58&pages=196-227

abstract:
We develop a toolbox for the error analysis of linear recurrences with constant or polynomial coefficients, based on generating series, Cauchy's method of majorants, and simple results from analytic combinatorics. We illustrate the power of the approach by several nontrivial application examples. Among these examples are a new worst-case analysis of an algorithm for computing the Bernoulli numbers and a new algorithm for evaluating differentially finite functions in interval arithmetic while avoiding interval blow-up

rawabstract:
We develop a toolbox for the error analysis of linear recurrences with constant or polynomial coefficients, based on generating series, Cauchy's method of majorants, and simple results from analytic combinatorics. We illustrate the power of the approach by several nontrivial application examples. Among these examples are a new worst-case analysis of an algorithm for computing the Bernoulli numbers and a new algorithm for evaluating differentially finite functions in interval arithmetic while avoiding interval blow-up

entry:
@Article{Mezzarobba:2023:REA,
  author =       "Marc Mezzarobba",
  title =        "Rounding error analysis of linear recurrences using
                 generating series",
  journal =      j-ELECTRON-TRANS-NUMER-ANAL,
  volume =       "58",
  pages =        "196--227",
  year =         "2023",
  CODEN =        "????",
  ISSN =         "1068-9613 (print), 1097-4067 (electronic)",
  ISSN-L =       "1068-9613",
  bibdate =      "Mon Jun 3 08:23:58 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/etna.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://etna.math.kent.edu/vol.58.2023/pp196-227.dir/pp196-227.pdf;
                 https://etna.math.kent.edu/volumes/2021-2030/vol58/abstract.php?vol=58&pages=196-227",
  abstract =     "We develop a toolbox for the error analysis of linear
                 recurrences with constant or polynomial coefficients,
                 based on generating series, Cauchy's method of
                 majorants, and simple results from analytic
                 combinatorics. We illustrate the power of the approach
                 by several nontrivial application examples. Among these
                 examples are a new worst-case analysis of an algorithm
                 for computing the Bernoulli numbers and a new algorithm
                 for evaluating differentially finite functions in
                 interval arithmetic while avoiding interval blow-up",
  acknowledgement = ack-nhfb,
  ajournal =     "Electron. Trans. Numer. Anal.",
  fjournal =     "Electronic Transactions on Numerical Analysis",
  journal-URL =  "http://etna.mcs.kent.edu/",
}


bibtype: techreport
filename: fparith.bib
label: Micikevicius:2023:OBF
title: OCP 8-bit floating point specification (OFP8): Revision 1.0.
type: Technical report
institution: Open Compute Project
pages: 16
day: 20
month: jun
monthnumber: 6
year: 2023
bibdate: Thu Nov 30 05:39:50 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.30 05:39:50 ???
acknowledgement: ack-nhfb
rawtitle: {OCP} 8-bit floating point specification ({OFP8}): Revision 1.0.
author:
Paulius Micikevicius and Stuart Oberman and Marius Cornea Pradeep Dubey and Andres Rodriguez and Ian Bratt and Richard Grisenthwaite and Chiachen Chou Norm Jouppi and Amber Huffman and Michael Schulte and Ralph Wittig and Dharmesh Jani and Summer Deng

URL:
https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-06-20-pdf

rawauthor:
Paulius Micikevicius and Stuart Oberman and Marius Cornea Pradeep Dubey and Andres Rodriguez and Ian Bratt and Richard Grisenthwaite and Chiachen Chou Norm Jouppi and Amber Huffman and Michael Schulte and Ralph Wittig and Dharmesh Jani and Summer Deng

entry:
@TechReport{Micikevicius:2023:OBF,
  author =       "Paulius Micikevicius and Stuart Oberman and Marius
                 Cornea Pradeep Dubey and Andres Rodriguez and Ian Bratt
                 and Richard Grisenthwaite and Chiachen Chou Norm Jouppi
                 and Amber Huffman and Michael Schulte and Ralph Wittig
                 and Dharmesh Jani and Summer Deng",
  title =        "{OCP} 8-bit floating point specification ({OFP8}):
                 Revision 1.0.",
  type =         "Technical report",
  institution =  "Open Compute Project",
  address =      "????",
  pages =        "16",
  day =          "20",
  month =        jun,
  year =         "2023",
  bibdate =      "Thu Nov 30 05:39:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-06-20-pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Mikaitis:2023:MMT
author: Mantas Mikaitis
title: Monotonicity of Multi-Term Floating-Point Adders
journal: arxiv.org
pages: 1--13
day: 3
month: apr
monthnumber: 4
year: 2023
bibdate: Thu Apr 06 15:33:19 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2023.04.06 15:33:19 ???
URL: https://arxiv.org/pdf/2304.01407.pdf
keywords: dot product; floating-point arithmetic; matrix multiply; monotonicity; multi-term addition
remark: arXiv:2304.01407v1
acknowledgement: ack-nhfb
rawauthor: Mantas Mikaitis
rawtitle: Monotonicity of Multi-Term Floating-Point Adders
abstract:
In the literature on algorithms for performing the multi-term addition $ s_n = sum _i = 1^n x_i $ using floating-point arithmetic it is often shown that a hardware unit that has single normalization and rounding improves precision, area, latency, and power consumption, compared with the use of standard add or fused multiply--add units. However, non-monotonicity can appear when computing sums with a subclass of multi-term addition units, which currently is not explored in the literature. We demonstrate that common techniques for performing multi-term addition with $ n geq 4 $, without normalization of intermediate quantities, can result in non-monotonicity-increasing one of the addends $ x_i $ decreases the sum sn. Summation is required in dot product and matrix multiplication operations, operations that have increasingly started appearing in the hardware of supercomputers, thus knowing where monotonicity is preserved can be of interest to the users of these machines. Our results suggest that non-monotonicity of summation, in some of the commercial hardware devices that implement a specific class of multi-term adders, is a feature that may have appeared unintentionally as a consequence of design choices that reduce circuit area and other metrics. To demonstrate our findings, we use formal proofs as well as a numerical simulation of non-monotonic multi-term adders in MATLAB

rawabstract:
In the literature on algorithms for performing the multi-term addition $ s_n = \sum_{i = 1}^n x_i $ using floating-point arithmetic it is often shown that a hardware unit that has single normalization and rounding improves precision, area, latency, and power consumption, compared with the use of standard add or fused multiply--add units. However, non-monotonicity can appear when computing sums with a subclass of multi-term addition units, which currently is not explored in the literature. We demonstrate that common techniques for performing multi-term addition with $ n \geq 4 $, without normalization of intermediate quantities, can result in non-monotonicity-increasing one of the addends $ x_i $ decreases the sum sn. Summation is required in dot product and matrix multiplication operations, operations that have increasingly started appearing in the hardware of supercomputers, thus knowing where monotonicity is preserved can be of interest to the users of these machines. Our results suggest that non-monotonicity of summation, in some of the commercial hardware devices that implement a specific class of multi-term adders, is a feature that may have appeared unintentionally as a consequence of design choices that reduce circuit area and other metrics. To demonstrate our findings, we use formal proofs as well as a numerical simulation of non-monotonic multi-term adders in MATLAB

entry:
@Article{Mikaitis:2023:MMT,
  author =       "Mantas Mikaitis",
  title =        "Monotonicity of Multi-Term Floating-Point Adders",
  journal =      "arxiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--13",
  day =          "3",
  month =        apr,
  year =         "2023",
  bibdate =      "Thu Apr 06 15:33:19 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://arxiv.org/pdf/2304.01407.pdf",
  abstract =     "In the literature on algorithms for performing the
                 multi-term addition $ s_n = \sum_{i = 1}^n x_i $ using
                 floating-point arithmetic it is often shown that a
                 hardware unit that has single normalization and
                 rounding improves precision, area, latency, and power
                 consumption, compared with the use of standard add or
                 fused multiply--add units. However, non-monotonicity
                 can appear when computing sums with a subclass of
                 multi-term addition units, which currently is not
                 explored in the literature. We demonstrate that common
                 techniques for performing multi-term addition with $ n
                 \geq 4 $, without normalization of intermediate
                 quantities, can result in non-monotonicity-increasing
                 one of the addends $ x_i $ decreases the sum sn.
                 Summation is required in dot product and matrix
                 multiplication operations, operations that have
                 increasingly started appearing in the hardware of
                 supercomputers, thus knowing where monotonicity is
                 preserved can be of interest to the users of these
                 machines. Our results suggest that non-monotonicity of
                 summation, in some of the commercial hardware devices
                 that implement a specific class of multi-term adders,
                 is a feature that may have appeared unintentionally as
                 a consequence of design choices that reduce circuit
                 area and other metrics. To demonstrate our findings, we
                 use formal proofs as well as a numerical simulation of
                 non-monotonic multi-term adders in MATLAB",
  acknowledgement = ack-nhfb,
  keywords =     "dot product; floating-point arithmetic; matrix
                 multiply; monotonicity; multi-term addition",
  remark =       "arXiv:2304.01407v1",
}


bibtype: inproceedings
filename: fparith.bib
label: Mirsalari:2023:OSO
booktitle: 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--8
year: 2023
DOI: https://doi.org/10.1109/ICECS58634.2023.10382758
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}
author:
Seyed Ahmad Mirsalari and Saba Yousefzadeh and Giuseppe Tagliavini and Dimitrios Stathis and Ahmed Hemani

title:
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms

keywords:
approximate computing; genome identification; Genomics; Instruction sets; Microorganisms; parallel ultra-low-power platform; Pathogens; RISC-V; Self-organizing feature maps; Self-organizing maps; smallFloat data types; Software algorithms; Throughput

rawauthor:
Seyed Ahmad Mirsalari and Saba Yousefzadeh and Giuseppe Tagliavini and Dimitrios Stathis and Ahmed Hemani

rawtitle:
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms

entry:
@InProceedings{Mirsalari:2023:OSO,
  author =       "Seyed Ahmad Mirsalari and Saba Yousefzadeh and
                 Giuseppe Tagliavini and Dimitrios Stathis and Ahmed
                 Hemani",
  booktitle =    "{2023 30th IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "Optimizing Self-Organizing Maps for Bacterial Genome
                 Identification on Parallel Ultra-Low-Power Platforms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICECS58634.2023.10382758",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "approximate computing; genome identification;
                 Genomics; Instruction sets; Microorganisms; parallel
                 ultra-low-power platform; Pathogens; RISC-V;
                 Self-organizing feature maps; Self-organizing maps;
                 smallFloat data types; Software algorithms;
                 Throughput",
}


