# bibtab

bibtype: article
filename: fparith.bib
label: Mudawar:2023:EVI
author: Muhamed F. Mudawar
title: Exact Versus Inexact Decimal Floating-Point Numbers and Arithmetic
journal: j-IEEE-ACCESS
volume: 11
pages: 17891--17905
year: 2023
DOI: https://doi.org/10.1109/ACCESS.2023.3244891
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Muhamed F. Mudawar
rawtitle: Exact Versus Inexact Decimal Floating-Point Numbers and Arithmetic
keywords:
Adders; Arithmetic; Encoding; exact versus inexact decimal arithmetic; exact versus inexact decimal numbers; exact versus inexact zeros; Floating-point arithmetic; Hardware; IEEE 754 standard; Program processors; Software engineering

entry:
@Article{Mudawar:2023:EVI,
  author =       "Muhamed F. Mudawar",
  title =        "Exact Versus Inexact Decimal Floating-Point Numbers
                 and Arithmetic",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  pages =        "17891--17905",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3244891",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Adders; Arithmetic; Encoding; exact versus inexact
                 decimal arithmetic; exact versus inexact decimal
                 numbers; exact versus inexact zeros; Floating-point
                 arithmetic; Hardware; IEEE 754 standard; Program
                 processors; Software engineering",
}


bibtype: article
filename: fparith.bib
label: Murillo:2023:GPB
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella and Christian Pilato
title: Generating Posit-Based Accelerators With High-Level Synthesis
journal: j-IEEE-TRANS-CIRCUITS-SYST-1
volume: 70
number: 10
pages: 4040--4052
year: 2023
DOI: https://doi.org/10.1109/TCSI.2023.3299009
ISSN: 1549-8328 (print), 1558-0806 (electronic) OR 15498328 (print), 15580806 (electronic)
ISSNL: 1549-8328 OR 15498328
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Circuits and Systems I: Regular Papers
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella and Christian Pilato
rawtitle: Generating Posit-Based Accelerators With High-Level Synthesis
entry:
@Article{Murillo:2023:GPB,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella and Christian Pilato",
  title =        "Generating Posit-Based Accelerators With High-Level
                 Synthesis",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "70",
  number =       "10",
  pages =        "4040--4052",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSI.2023.3299009",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}


bibtype: article
filename: fparith.bib
label: Murillo:2023:HMP
author: Raul Murillo and Javier Hormigo and Alberto A. Del Barrio and Guillermo Botella
title: HUB Meets Posit: Arithmetic Units Implementation
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
pages: 1--1
year: 2023
DOI: https://doi.org/10.1109/TCSII.2023.3307488
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Raul Murillo and Javier Hormigo and Alberto A. {Del Barrio} and Guillermo Botella
rawtitle: {HUB} Meets Posit: Arithmetic Units Implementation
entry:
@Article{Murillo:2023:HMP,
  author =       "Raul Murillo and Javier Hormigo and Alberto A. {Del
                 Barrio} and Guillermo Botella",
  title =        "{HUB} Meets Posit: Arithmetic Units Implementation",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  pages =        "1--1",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3307488",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2023:PPL
author: Raul Murillo and David Mallasen and Alberto A. Del Barrio and Guillermo Botella
title: PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers
crossref: Gustafson:2023:NGA
pages: 171--188
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_11
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Raul Murillo and David Mallas{\'e}n and Alberto A. Del Barrio and Guillermo Botella
rawtitle: {PLAUs}: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers
entry:
@InProceedings{Murillo:2023:PPL,
  author =       "Raul Murillo and David Mallas{\'e}n and Alberto A. Del
                 Barrio and Guillermo Botella",
  title =        "{PLAUs}: Posit Logarithmic Approximate Units to
                 Implement Low-Cost Operations with Real Numbers",
  crossref =     "Gustafson:2023:NGA",
  pages =        "171--188",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_11",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2023:SDA
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella
editor: IEEE
title: A Suite of Division Algorithms for Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 41--44
year: 2023
DOI: https://doi.org/10.1109/ASAP57973.2023.00020
bibdate: Thu Nov 16 15:55:09 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.16 15:55:09 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella
raweditor: {IEEE}
rawtitle: A Suite of Division Algorithms for Posit Arithmetic
booktitle:
2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto, Portugal

ISBN13:
979-83-503-4686-2 (print), 979-83-503-4685-5 (e-book) OR 9798350346862 (print), 9798350346855 (ebook)

rawbooktitle:
2023 {IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto, Portugal}

entry:
@InProceedings{Murillo:2023:SDA,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella",
  editor =       "{IEEE}",
  booktitle =    "2023 {IEEE 34th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto,
                 Portugal}",
  title =        "A Suite of Division Algorithms for Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "41--44",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ASAP57973.2023.00020",
  ISBN-13 =      "979-83-503-4686-2 (print), 979-83-503-4685-5
                 (e-book)",
  bibdate =      "Thu Nov 16 15:55:09 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Mushtak:2023:FNP
author: Noble Mushtak and Daniel Lemire
title: Fast number parsing without fallback
journal: j-SPE
volume: 53
number: 7
pages: 1467--1471
month: jul
monthnumber: 7
year: 2023
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.3198
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Thu Jun 29 14:46:14 MDT 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib
bibtimestamp: 2023.06.29 14:46:14 MDT
note: See original work cite Lemire:2021:NPG.
fjournal: Software --- Practice and Experience
acknowledgement: ack-nhfb
ajournal: Softw. Pract. Exp.
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 04 March 2023
rawauthor: Noble Mushtak and Daniel Lemire
rawnote: See original work \cite{Lemire:2021:NPG}.
rawtitle: Fast number parsing without fallback
abstract:
In recent work, Lemire (2021) presented a fast algorithm to convert number strings into binary floating-point numbers. The algorithm has been adopted by several important systems: for example, it is part of the runtime libraries of GCC 12, Rust 1.55, and Go 1.16. The algorithm parses any number string with a significand containing no more than 19 digits into an IEEE floating-point number. However, there is a check leading to a fallback function to ensure correctness. This fallback function is never called in practice. We prove that the fallback is unnecessary. Thus we can slightly simplify the algorithm and its implementation.

rawabstract:
In recent work, Lemire (2021) presented a fast algorithm to convert number strings into binary floating-point numbers. The algorithm has been adopted by several important systems: for example, it is part of the runtime libraries of GCC 12, Rust 1.55, and Go 1.16. The algorithm parses any number string with a significand containing no more than 19 digits into an IEEE floating-point number. However, there is a check leading to a fallback function to ensure correctness. This fallback function is never called in practice. We prove that the fallback is unnecessary. Thus we can slightly simplify the algorithm and its implementation.

entry:
@Article{Mushtak:2023:FNP,
  author =       "Noble Mushtak and Daniel Lemire",
  title =        "Fast number parsing without fallback",
  journal =      j-SPE,
  volume =       "53",
  number =       "7",
  pages =        "1467--1471",
  month =        jul,
  year =         "2023",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.3198",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Thu Jun 29 14:46:14 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib",
  note =         "See original work \cite{Lemire:2021:NPG}.",
  abstract =     "In recent work, Lemire (2021) presented a fast
                 algorithm to convert number strings into binary
                 floating-point numbers. The algorithm has been adopted
                 by several important systems: for example, it is part
                 of the runtime libraries of GCC 12, Rust 1.55, and Go
                 1.16. The algorithm parses any number string with a
                 significand containing no more than 19 digits into an
                 IEEE floating-point number. However, there is a check
                 leading to a fallback function to ensure correctness.
                 This fallback function is never called in practice. We
                 prove that the fallback is unnecessary. Thus we can
                 slightly simplify the algorithm and its
                 implementation.",
  acknowledgement = ack-nhfb,
  ajournal =     "Softw. Pract. Exp.",
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  onlinedate =   "04 March 2023",
}


bibtype: article
filename: fparith.bib
label: Nadalini:2023:RPF
author: Davide Nadalini and Manuele Rusci and Luca Benini and Francesco Conti
journal: j-FUT-GEN-COMP-SYS
volume: 149
pages: 212--226
month: dec
monthnumber: 12
year: 2023
CODEN: FGSEVI
DOI: https://doi.org/10.1016/j.future.2023.07.020
ISSN: 0167-739X (print), 1872-7115 (electronic) OR 0167739X (print), 18727115 (electronic)
ISSNL: 0167-739X OR 0167739X
bibdate: Thu Sep 21 08:18:51 MDT 2023
bibtimestamp: 2023.09.21 08:18:51 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0167739X23002728
fjournal: Future Generation Computer Systems
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/0167739X
rawauthor: Davide Nadalini and Manuele Rusci and Luca Benini and Francesco Conti
title:
Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib

rawtitle:
Reduced precision floating-point optimization for {Deep Neural Network On-Device Learning} on microcontrollers

entry:
@Article{Nadalini:2023:RPF,
  author =       "Davide Nadalini and Manuele Rusci and Luca Benini and
                 Francesco Conti",
  title =        "Reduced precision floating-point optimization for
                 {Deep Neural Network On-Device Learning} on
                 microcontrollers",
  journal =      j-FUT-GEN-COMP-SYS,
  volume =       "149",
  number =       "??",
  pages =        "212--226",
  month =        dec,
  year =         "2023",
  CODEN =        "FGSEVI",
  DOI =          "https://doi.org/10.1016/j.future.2023.07.020",
  ISSN =         "0167-739X (print), 1872-7115 (electronic)",
  ISSN-L =       "0167-739X",
  bibdate =      "Thu Sep 21 08:18:51 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167739X23002728",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Generation Computer Systems",
  journal-URL =  "http://www.sciencedirect.com/science/journal/0167739X",
}


bibtype: inproceedings
filename: fparith.bib
label: Nadalini:2023:TWR
editor: IEEE
booktitle: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/ISVLSI59464.2023.10238679
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}
raweditor: {IEEE}
author:
Alessandro Nadalini and Georg Rutishauser and Alessio Burrello and Nazareno Bruschi and Angelo Garofalo and Luca Benini and Francesco Conti and Davide Rossi

title:
A 3 TOPS / W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

rawauthor:
Alessandro Nadalini and Georg Rutishauser and Alessio Burrello and Nazareno Bruschi and Angelo Garofalo and Luca Benini and Francesco Conti and Davide Rossi

rawtitle:
A 3 {TOPS\slash W RISC-V} Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

entry:
@InProceedings{Nadalini:2023:TWR,
  author =       "Alessandro Nadalini and Georg Rutishauser and Alessio
                 Burrello and Nazareno Bruschi and Angelo Garofalo and
                 Luca Benini and Francesco Conti and Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Computer Society Annual Symposium on VLSI
                 (ISVLSI)}",
  title =        "A 3 {TOPS\slash W RISC-V} Parallel Cluster for
                 Inference of Fine-Grain Mixed-Precision Quantized
                 Neural Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISVLSI59464.2023.10238679",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Nazareth:2023:CGN
author: John Lawrence Nazareth
title: Concise Guide to Numerical Algorithmics: The Foundations and Spirit of Scientific Computing
publisher: pub-SV
address: pub-SV:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1007/978-3-031-21762-3
ISBN: 3-031-21762-4 OR 3031217624
ISBN13: 978-3-031-21762-3 OR 9783031217623
ISSN: 2191-5776 OR 21915776
ISSNL: 2191-5768 OR 21915768
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
series: SpringerBriefs in Computer Science
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: John Lawrence Nazareth
rawtitle: Concise Guide to Numerical Algorithmics: The Foundations and Spirit of Scientific Computing
entry:
@Book{Nazareth:2023:CGN,
  author =       "John Lawrence Nazareth",
  title =        "Concise Guide to Numerical Algorithmics: The
                 Foundations and Spirit of Scientific Computing",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-21762-3",
  ISBN =         "3-031-21762-4",
  ISBN-13 =      "978-3-031-21762-3",
  ISSN =         "2191-5776",
  ISSN-L =       "2191-5768",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "SpringerBriefs in Computer Science",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Noh:2023:FFD
author: Seock-Hwan Noh and Jahyun Koo and Seunghyun Lee and Jongse Park and Jaeha Kung
title: FlexBlock: a Flexible DNN Training Accelerator With Multi-Mode Block Floating Point Support
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 9
pages: 2522--2535
month: sep
monthnumber: 9
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3253050
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Aug 10 06:30:56 2023
bibtimestamp: 2023.08.10 06:30:56 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Seock-Hwan Noh and Jahyun Koo and Seunghyun Lee and Jongse Park and Jaeha Kung
rawtitle: {FlexBlock}: a Flexible {DNN} Training Accelerator With Multi-Mode Block Floating Point Support
entry:
@Article{Noh:2023:FFD,
  author =       "Seock-Hwan Noh and Jahyun Koo and Seunghyun Lee and
                 Jongse Park and Jaeha Kung",
  title =        "{FlexBlock}: a Flexible {DNN} Training Accelerator
                 With Multi-Mode Block Floating Point Support",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "9",
  pages =        "2522--2535",
  month =        sep,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3253050",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Aug 10 06:30:56 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: NVIDIA:2023:FPI
author: NVIDIA Corporation
title: Floating Point and IEEE 754 Compliance for NVIDIA GPUs
pages: 2522--2535
month: oct
monthnumber: 10
year: 2023
bibdate: Fri Dec 01 12:26:53 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.01 12:26:53 ???
URL: https://docs.nvidia.com/cuda/floating-point/
acknowledgement: ack-nhfb
howpublished: NVIDIA Web site.
rawauthor: {NVIDIA Corporation}
rawtitle: Floating Point and {IEEE 754} Compliance for {NVIDIA GPUs}
remark:
The document discusses IEEE 754 conformance, CUDA, fused multiply-add, dot products, and GPU issues. It also says: ``NVIDIA GPUs differ from the x86 architecture in that rounding modes are encoded within each floating point instruction instead of dynamically using a floating point control word. Trap handlers for floating point exceptions are not supported. On the GPU there is no status flag to indicate when calculations have overflowed, underflowed, or have involved inexact arithmetic.''

entry:
@Misc{NVIDIA:2023:FPI,
  author =       "{NVIDIA Corporation}",
  title =        "Floating Point and {IEEE 754} Compliance for {NVIDIA
                 GPUs}",
  howpublished = "NVIDIA Web site.",
  month =        oct,
  year =         "2023",
  bibdate =      "Fri Dec 01 12:26:53 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://docs.nvidia.com/cuda/floating-point/",
  acknowledgement = ack-nhfb,
  remark =       "The document discusses IEEE 754 conformance, CUDA,
                 fused multiply-add, dot products, and GPU issues. It
                 also says: ``NVIDIA GPUs differ from the x86
                 architecture in that rounding modes are encoded within
                 each floating point instruction instead of dynamically
                 using a floating point control word. Trap handlers for
                 floating point exceptions are not supported. On the GPU
                 there is no status flag to indicate when calculations
                 have overflowed, underflowed, or have involved inexact
                 arithmetic.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:2023:RLR
author: Hyun Woo Oh and Seongmo An and Won Sik Jeong and Seung Eun Lee
editor: IEEE
booktitle: 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
title: RF2P: a Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/ISLPED58423.2023.10244582
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Hyun Woo Oh and Seongmo An and Won Sik Jeong and Seung Eun Lee
rawbooktitle: {2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)}
raweditor: {IEEE}
rawtitle: {RF2P}: a Lightweight {RISC} Processor Optimized for Rapid Migration from {IEEE-754} to Posit
entry:
@InProceedings{Oh:2023:RLR,
  author =       "Hyun Woo Oh and Seongmo An and Won Sik Jeong and Seung
                 Eun Lee",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE/ACM International Symposium on Low Power
                 Electronics and Design (ISLPED)}",
  title =        "{RF2P}: a Lightweight {RISC} Processor Optimized for
                 Rapid Migration from {IEEE-754} to Posit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISLPED58423.2023.10244582",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Oliver:2023:ASF
booktitle: 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
title: Accelerating SpMV on FPGAs Through Block-Row Compress: a Task-Based Approach
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 151--158
year: 2023
DOI: https://doi.org/10.1109/FPL60245.2023.00029
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)}
rawtitle: Accelerating {SpMV} on {FPGAs} Through Block-Row Compress: a Task-Based Approach
author:
Jose Oliver and Carlos Alvarez and Teresa Cervero and Xavier Martorell and John D. Davis and Eduard Ayguade

keywords:
double-precision; Encoding; FP64; FPGA; HBM; High-performance computing; HLS; Memory management; Proposals; Scalability; Sparse matrices; Sparse matrix representation; SpMV; System-on-chip; Task analysis

rawauthor:
Jos{\'e} Oliver and Carlos {\'A}lvarez and Teresa Cervero and Xavier Martorell and John D. Davis and Eduard Ayguad{\'e}

entry:
@InProceedings{Oliver:2023:ASF,
  author =       "Jos{\'e} Oliver and Carlos {\'A}lvarez and Teresa
                 Cervero and Xavier Martorell and John D. Davis and
                 Eduard Ayguad{\'e}",
  booktitle =    "{2023 33rd International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "Accelerating {SpMV} on {FPGAs} Through Block-Row
                 Compress: a Task-Based Approach",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "151--158",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/FPL60245.2023.00029",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "double-precision; Encoding; FP64; FPGA; HBM;
                 High-performance computing; HLS; Memory management;
                 Proposals; Scalability; Sparse matrices; Sparse matrix
                 representation; SpMV; System-on-chip; Task analysis",
}


bibtype: inproceedings
filename: fparith.bib
label: P:2023:AOF
author: Gayathri G P and Jaya S and Krishnakumar Rao S
editor: IEEE
booktitle: 2023 International Conference on Control, Communication and Computing (ICCC)
title: An Area Optimized Floating-Point Coprocessor for RISC-V Processor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ICCC57789.2023.10165397
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Gayathri G P and Jaya S and Krishnakumar Rao S
rawbooktitle: {2023 International Conference on Control, Communication and Computing (ICCC)}
raweditor: {IEEE}
rawtitle: An Area Optimized Floating-Point Coprocessor for {RISC-V} Processor
entry:
@InProceedings{P:2023:AOF,
  author =       "Gayathri G P and Jaya S and Krishnakumar Rao S",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on Control,
                 Communication and Computing (ICCC)}",
  title =        "An Area Optimized Floating-Point Coprocessor for
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCC57789.2023.10165397",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: P:2023:ITO
author: Ponsuganth Ilangovan P. and Rohan Rayan and Vinay Shankar Saxena
title: Improving the Stability of Kalman Filters with Posit Arithmetic
crossref: Gustafson:2023:NGA
pages: 134--154
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_9
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Ponsuganth Ilangovan P. and Rohan Rayan and Vinay Shankar Saxena
rawtitle: Improving the Stability of {Kalman} Filters with Posit Arithmetic
entry:
@InProceedings{P:2023:ITO,
  author =       "Ponsuganth Ilangovan P. and Rohan Rayan and Vinay
                 Shankar Saxena",
  title =        "Improving the Stability of {Kalman} Filters with Posit
                 Arithmetic",
  crossref =     "Gustafson:2023:NGA",
  pages =        "134--154",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_9",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Park:2023:FDL
editor: IEEE
booktitle: 2023 IEEE / ACM International Symposium on Low Power Electronics and Design (ISLPED)
title: Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/ISLPED58423.2023.10244431
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 {IEEE\slash ACM} International Symposium on Low Power Electronics and Design (ISLPED)}
raweditor: {IEEE}
rawtitle: {Florian}: Developing a Low-Power {RISC-V} Multicore Processor with a Shared Lightweight {FPU}
author:
Jina Park and Kyuseung Han and Eunjin Choi and Sukho Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram

rawauthor:
Jina Park and Kyuseung Han and Eunjin Choi and Sukho Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram

entry:
@InProceedings{Park:2023:FDL,
  author =       "Jina Park and Kyuseung Han and Eunjin Choi and Sukho
                 Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram",
  editor =       "{IEEE}",
  booktitle =    "{2023 {IEEE\slash ACM} International Symposium on Low
                 Power Electronics and Design (ISLPED)}",
  title =        "{Florian}: Developing a Low-Power {RISC-V} Multicore
                 Processor with a Shared Lightweight {FPU}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISLPED58423.2023.10244431",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Pasca:2023:ELP
author: Bogdan Pasca and Martin Langhammer
title: Extracting low-precision floating-point adders from embedded hard FP DSP Blocks on FPGAs
crossref: IEEE:2023:PIS
pages: 139--142
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00017
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Bogdan Pasca and Martin Langhammer
rawtitle: Extracting low-precision floating-point adders from embedded hard {FP DSP} Blocks on {FPGAs}
keywords:
adder; Adders; ARITH 2023; ARITH-30; bfloat16; Computer architecture; Costs; Digital arithmetic; DSP; extraction; Field programmable gate arrays; floating-point; FP-DSP; FPGA; half-precision; mapping

entry:
@InProceedings{Pasca:2023:ELP,
  author =       "Bogdan Pasca and Martin Langhammer",
  title =        "Extracting low-precision floating-point adders from
                 embedded hard {FP DSP} Blocks on {FPGAs}",
  crossref =     "IEEE:2023:PIS",
  pages =        "139--142",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00017",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "adder; Adders; ARITH 2023; ARITH-30; bfloat16;
                 Computer architecture; Costs; Digital arithmetic; DSP;
                 extraction; Field programmable gate arrays;
                 floating-point; FP-DSP; FPGA; half-precision; mapping",
}


bibtype: article
filename: fparith.bib
label: Perez:2023:TIL
title: Training and inference of large language models using 8-bit floating point
journal: arXiv.org
pages: 1--22
day: 29
month: sep
monthnumber: 9
year: 2023
DOI: https://doi.org/10.48550/arXiv.2309.17224
bibdate: Wed Aug 07 16:34:17 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 16:34:17 ???
URL: https://arxiv.org/abs/2309.17224
acknowledgement: ack-nhfb
rawtitle: Training and inference of large language models using 8-bit floating point
author:
Sergio P. Perez and Yan Zhang and James Briggs and Charlie Blake and Josh Levy-Kramer and Paul Balanca and Carlo Luschi and Stephen Barlow and Andrew William Fitzgibbon

abstract:
FP8 formats are gaining popularity to boost the computational efficiency for training and inference of large deep learning models. Their main challenge is that a careful choice of scaling is needed to prevent degradation due to the reduced dynamic range compared to higher-precision formats. Although there exists ample literature about selecting such scalings for INT formats, this critical aspect has yet to be addressed for FP8. This paper presents a methodology to select the scalings for FP8 linear layers, based on dynamically updating per-tensor scales for the weights, gradients and activations. We apply this methodology to train and validate large language models of the type of GPT and Llama 2 using FP8, for model sizes ranging from 111M to 70B. To facilitate the understanding of the FP8 dynamics, our results are accompanied by plots of the per-tensor scale distribution for weights, activations and gradients during both training and inference.

rawabstract:
FP8 formats are gaining popularity to boost the computational efficiency for training and inference of large deep learning models. Their main challenge is that a careful choice of scaling is needed to prevent degradation due to the reduced dynamic range compared to higher-precision formats. Although there exists ample literature about selecting such scalings for INT formats, this critical aspect has yet to be addressed for FP8. This paper presents a methodology to select the scalings for FP8 linear layers, based on dynamically updating per-tensor scales for the weights, gradients and activations. We apply this methodology to train and validate large language models of the type of GPT and Llama 2 using FP8, for model sizes ranging from 111M to 70B. To facilitate the understanding of the FP8 dynamics, our results are accompanied by plots of the per-tensor scale distribution for weights, activations and gradients during both training and inference.

rawauthor:
Sergio P. Perez and Yan Zhang and James Briggs and Charlie Blake and Josh Levy-Kramer and Paul Balanca and Carlo Luschi and Stephen Barlow and Andrew William Fitzgibbon

entry:
@Article{Perez:2023:TIL,
  author =       "Sergio P. Perez and Yan Zhang and James Briggs and
                 Charlie Blake and Josh Levy-Kramer and Paul Balanca and
                 Carlo Luschi and Stephen Barlow and Andrew William
                 Fitzgibbon",
  title =        "Training and inference of large language models using
                 8-bit floating point",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--22",
  day =          "29",
  month =        sep,
  year =         "2023",
  DOI =          "https://doi.org/10.48550/arXiv.2309.17224",
  bibdate =      "Wed Aug 07 16:34:17 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/2309.17224",
  abstract =     "FP8 formats are gaining popularity to boost the
                 computational efficiency for training and inference of
                 large deep learning models. Their main challenge is
                 that a careful choice of scaling is needed to prevent
                 degradation due to the reduced dynamic range compared
                 to higher-precision formats. Although there exists
                 ample literature about selecting such scalings for INT
                 formats, this critical aspect has yet to be addressed
                 for FP8. This paper presents a methodology to select
                 the scalings for FP8 linear layers, based on
                 dynamically updating per-tensor scales for the weights,
                 gradients and activations. We apply this methodology to
                 train and validate large language models of the type of
                 GPT and Llama 2 using FP8, for model sizes ranging from
                 111M to 70B. To facilitate the understanding of the FP8
                 dynamics, our results are accompanied by plots of the
                 per-tensor scale distribution for weights, activations
                 and gradients during both training and inference.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Perotti:2023:YOS
author: Matteo Perotti and Matheus Cavalcante and Alessandro Ottaviano and Jiantao Liu and Luca Benini
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 70
number: 10
pages: 3732--3736
year: 2023
DOI: https://doi.org/10.1109/TCSII.2023.3292579
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Matteo Perotti and Matheus Cavalcante and Alessandro Ottaviano and Jiantao Liu and Luca Benini
title:
Yun: an Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS

rawtitle:
{Yun}: an Open-Source, 64-Bit {RISC-V}-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm {CMOS}

entry:
@Article{Perotti:2023:YOS,
  author =       "Matteo Perotti and Matheus Cavalcante and Alessandro
                 Ottaviano and Jiantao Liu and Luca Benini",
  title =        "{Yun}: an Open-Source, 64-Bit {RISC-V}-Based Vector
                 Processor With Multi-Precision Integer and
                 Floating-Point Support in 65-nm {CMOS}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "10",
  pages =        "3732--3736",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3292579",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}


bibtype: misc
filename: fparith.bib
label: Pilipovic:2023:EEN
author: Ratko Pilipovic and Patricio Bulic and Uros Lotric
title: Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier
pages: 3732--3736
day: 19
month: feb
monthnumber: 2
year: 2023
DOI: https://doi.org/10.36227/techrxiv.22123127.v1
bibdate: Fri Sep 29 14:34:35 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 14:34:35 ???
acknowledgement: ack-nhfb
howpublished: TechRxiv preprint.
rawauthor: Ratko Pilipovi{\'c} and Patricio Buli{\'c} and Uro{\v{s}} Lotri{\v{c}}
rawtitle: Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier
URL:
https://www.techrxiv.org/articles/preprint/Energy-efficient_neural_network_learning_with_accuracy-adjustable_floating-point_multiplier/22123127

abstract:
This paper proposes a novel approximate bfloat16 multiplier with on-the-fly adjustable accuracy for energy-efficient learning in deep neural networks. The size of the proposed multiplier is only 62% of the size of the exact bfloat16 multiplier. Furthermore, its energy footprint is up to five times smaller than the footprint of the exact bfloat multiplier. We demonstrate the advantages of the proposed multiplier in deep neural network learning, where we successfully train the ResNet-20 network on the CIFAR-10 dataset from scratch.

rawabstract:
This paper proposes a novel approximate bfloat16 multiplier with on-the-fly adjustable accuracy for energy-efficient learning in deep neural networks. The size of the proposed multiplier is only 62\% of the size of the exact bfloat16 multiplier. Furthermore, its energy footprint is up to five times smaller than the footprint of the exact bfloat multiplier. We demonstrate the advantages of the proposed multiplier in deep neural network learning, where we successfully train the ResNet-20 network on the CIFAR-10 dataset from scratch.

entry:
@Misc{Pilipovic:2023:EEN,
  author =       "Ratko Pilipovi{\'c} and Patricio Buli{\'c} and
                 Uro{\v{s}} Lotri{\v{c}}",
  title =        "Energy-efficient neural network learning with
                 accuracy-adjustable floating-point multiplier",
  howpublished = "TechRxiv preprint.",
  day =          "19",
  month =        feb,
  year =         "2023",
  DOI =          "https://doi.org/10.36227/techrxiv.22123127.v1",
  bibdate =      "Fri Sep 29 14:34:35 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.techrxiv.org/articles/preprint/Energy-efficient_neural_network_learning_with_accuracy-adjustable_floating-point_multiplier/22123127",
  abstract =     "This paper proposes a novel approximate bfloat16
                 multiplier with on-the-fly adjustable accuracy for
                 energy-efficient learning in deep neural networks. The
                 size of the proposed multiplier is only 62\% of the
                 size of the exact bfloat16 multiplier. Furthermore, its
                 energy footprint is up to five times smaller than the
                 footprint of the exact bfloat multiplier. We
                 demonstrate the advantages of the proposed multiplier
                 in deep neural network learning, where we successfully
                 train the ResNet-20 network on the CIFAR-10 dataset
                 from scratch.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Postpischil:2023:WDI
author: Eric Postpischil
pages: 3732--3736
year: 2023
bibdate: Wed Dec 20 06:59:51 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 06:59:51 ???
remark: Discusses Jim Blinn's approximate logarithm for the IEEE 32-bit binary format cite Blinn:1997:JBC.
acknowledgement: ack-nhfb
howpublished: Stack Overflow Web site.
rawauthor: Eric Postpischil
title:
Why does the integer representation of a floating point number offer a piecewise linear approximation to the logarithm?

URL:
https://stackoverflow.com/questions/75772363/why-does-the-integer-representation-of-a-floating-point-number-offer-a-piecewise

rawtitle:
Why does the integer representation of a floating point number offer a piecewise linear approximation to the logarithm?

entry:
@Misc{Postpischil:2023:WDI,
  author =       "Eric Postpischil",
  title =        "Why does the integer representation of a floating
                 point number offer a piecewise linear approximation to
                 the logarithm?",
  howpublished = "Stack Overflow Web site.",
  year =         "2023",
  bibdate =      "Wed Dec 20 06:59:51 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://stackoverflow.com/questions/75772363/why-does-the-integer-representation-of-a-floating-point-number-offer-a-piecewise",
  acknowledgement = ack-nhfb,
  remark =       "Discusses Jim Blinn's approximate logarithm for the
                 IEEE 32-bit binary format \cite{Blinn:1997:JBC}.",
}


bibtype: article
filename: fparith.bib
label: Reinsch:2023:SVD
author: Christian Reinsch and Mathias Richter
title: Singular value decomposition in extended double precision arithmetic
journal: j-NUMER-ALGORITHMS
volume: 93
number: 3
pages: 1137--1155
year: 2023
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-022-01459-9
ISSN: 1017-1398,1572-9265 OR 10171398,15729265
ISSNL: 1017-1398 OR 10171398
MRclass: 65F55 (65F25 65G50)
MRnumber: 4598587
bibdate: Sat Aug 2 16:11:52 2025
bibtimestamp: 2025.08.02 16:11:52 ???
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
authordates: Christian H. Reinsch (?? ?? 1934--8 October 2022)
journalURL: http://link.springer.com/journal/11075
rawauthor: Christian Reinsch and Mathias Richter
rawtitle: Singular value decomposition in extended double precision arithmetic
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/r/reinsch-christian-h.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Reinsch:2023:SVD,
  author =       "Christian Reinsch and Mathias Richter",
  title =        "Singular value decomposition in extended double
                 precision arithmetic",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "93",
  number =       "3",
  pages =        "1137--1155",
  year =         "2023",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-022-01459-9",
  ISSN =         "1017-1398,1572-9265",
  ISSN-L =       "1017-1398",
  MRclass =      "65F55 (65F25 65G50)",
  MRnumber =     "4598587",
  bibdate =      "Sat Aug 2 16:11:52 2025",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/r/reinsch-christian-h.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  author-dates = "Christian H. Reinsch (?? ?? 1934--8 October 2022)",
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
}


bibtype: inproceedings
filename: fparith.bib
label: Ren:2023:EAM
author: Pengchang Ren and Reiji Suda and Vorapong Suppakitpaisarn
title: Efficient Additions and Montgomery Reductions of Large Integers for SIMD
crossref: IEEE:2023:PIS
pages: 48--59
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00034
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Pengchang Ren and Reiji Suda and Vorapong Suppakitpaisarn
rawtitle: Efficient Additions and {Montgomery} Reductions of Large Integers for {SIMD}
keywords:
additions; ARITH 2023; ARITH-30; arithmetic for cryptography; AVX-512; Cryptography; Digital arithmetic; Montgomery reduction; Pipelines; Program processors; SIMD; Standards; SVE

entry:
@InProceedings{Ren:2023:EAM,
  author =       "Pengchang Ren and Reiji Suda and Vorapong
                 Suppakitpaisarn",
  title =        "Efficient Additions and {Montgomery} Reductions of
                 Large Integers for {SIMD}",
  crossref =     "IEEE:2023:PIS",
  pages =        "48--59",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00034",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "additions; ARITH 2023; ARITH-30; arithmetic for
                 cryptography; AVX-512; Cryptography; Digital
                 arithmetic; Montgomery reduction; Pipelines; Program
                 processors; SIMD; Standards; SVE",
}


bibtype: article
filename: fparith.bib
label: Robert:2023:FMM
author: Jean-Marc Robert and Pascal Veron
journal: j-J-CRYPTO-ENG
volume: 13
number: 1
pages: 37--55
month: apr
monthnumber: 4
year: 2023
DOI: https://doi.org/10.1007/s13389-021-00278-3
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Fri Jun 2 12:32:10 MDT 2023
bibtimestamp: 2023.06.02 12:32:10 MDT
URL: https://link.springer.com/article/10.1007/s13389-021-00278-3
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
ajournal: J. Crypto. Eng.
journalURL: http://link.springer.com/journal/13389
rawauthor: Jean-Marc Robert and Pascal V{\'e}ron
title:
Faster multiplication over $ mathbb F_2 [X] $ using AVX512 instruction set and VPCLMULQDQ instruction

rawtitle:
Faster multiplication over {$ \mathbb {F}_2 [X] $} using {AVX512} instruction set and {VPCLMULQDQ} instruction

entry:
@Article{Robert:2023:FMM,
  author =       "Jean-Marc Robert and Pascal V{\'e}ron",
  title =        "Faster multiplication over {$ \mathbb {F}_2 [X] $}
                 using {AVX512} instruction set and {VPCLMULQDQ}
                 instruction",
  journal =      j-J-CRYPTO-ENG,
  volume =       "13",
  number =       "1",
  pages =        "37--55",
  month =        apr,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-021-00278-3",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Fri Jun 2 12:32:10 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "https://link.springer.com/article/10.1007/s13389-021-00278-3",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Crypto. Eng.",
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Rump:2023:IPP
author: Siegfried M. Rump
title: IEEE-754 Precision-$p$ base-$ beta $ Arithmetic Implemented in Binary
journal: j-TOMS
volume: 49
number: 4
pages: 32:1--32:??
month: dec
monthnumber: 12
year: 2023
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3596218
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Dec 23 05:40:24 MST 2023
bibtimestamp: 2023.12.23 05:40:24 MST
URL: https://dl.acm.org/doi/10.1145/3596218; https://www.tuhh.de/ti3/paper/rump/Ru23b.pdf
fjournal: ACM Transactions on Mathematical Software (TOMS)
remark: Received 6 December 2021; revised 10 October 2022; accepted 30 March 2023.
acknowledgement: ack-nhfb
ajournal: ACM Trans. Math. Softw.
articleno: 32
journalURL: https://dl.acm.org/loi/toms
rawauthor: Siegfried M. Rump
rawtitle: {IEEE-754} Precision-$p$ base-$ \beta $ Arithmetic Implemented in Binary
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We show how an IEEE-754 conformant precision-$p$ base-$ beta $ arithmetic can be implemented based on some binary floating-point and/or integer arithmetic. This includes the four basic operations and square root subject to the five IEEE-754 rounding modes, namely he nearest roundings with roundTiesToEven and roundTiesToAway, the directed roundings downwards and upwards, as well as rounding towards zero. Exceptional values like $ infty $ or NaN are covered according to the IEEE-754 arithmetic standard. The results of the precision-$p$ base-$ beta $ operations are computed using some underlying precision-$q$ binary arithmetic. We distinguish two cases. When using a precision-$q$ binary integer arithmetic, the base-$ beta $ precision $p$ is limited for all operations by $ beta ^2 p leq 2^q$, whereas using a precision-$q$ binary floating-point arithmetic imposes stronger limits on the base-$ beta $ precision, namely $ beta ^2p leq 2^q$ for addition and multiplication, $ beta ^2p leq 2^q - 1$ for division and $ beta ^2p leq 2^q - 3$ for the square root. Those limitations cannot be improved. The algorithms are implemented in a Matlab/Octave flbeta-toolbox with the choice of using uint64 or binary64 as underlying arithmetic. The former allows larger precisions, the latter is advantageous for the square root, whereas computing times are similar. The flbeta-toolbox offers precision-$p$ base-$ beta $ scalar, vector and matrix operations including sparse matrices as well as corresponding interval operations. The base $ beta $ can be chosen in the range $ beta $ [2,64]. The flbeta-toolbox will be part of Version 13 of INTLAB [18], the Matlab/Octave toolbox for reliable computing.

rawabstract:
We show how an IEEE-754 conformant precision-$p$ base-$ \beta $ arithmetic can be implemented based on some binary floating-point and/or integer arithmetic. This includes the four basic operations and square root subject to the five IEEE-754 rounding modes, namely he nearest roundings with roundTiesToEven and roundTiesToAway, the directed roundings downwards and upwards, as well as rounding towards zero. Exceptional values like $ \infty $ or NaN are covered according to the IEEE-754 arithmetic standard. The results of the precision-$p$ base-$ \beta $ operations are computed using some underlying precision-$q$ binary arithmetic. We distinguish two cases. When using a precision-$q$ binary integer arithmetic, the base-$ \beta $ precision $p$ is limited for all operations by $ \beta^{2 p} \leq 2^q$, whereas using a precision-$q$ binary floating-point arithmetic imposes stronger limits on the base-$ \beta $ precision, namely $ \beta^{2p} \leq 2^q$ for addition and multiplication, $ \beta^{2p} \leq 2^{q - 1}$ for division and $ \beta^{2p} \leq 2^{q - 3}$ for the square root. Those limitations cannot be improved. The algorithms are implemented in a Matlab/Octave flbeta-toolbox with the choice of using uint64 or binary64 as underlying arithmetic. The former allows larger precisions, the latter is advantageous for the square root, whereas computing times are similar. The flbeta-toolbox offers precision-$p$ base-$ \beta $ scalar, vector and matrix operations including sparse matrices as well as corresponding interval operations. The base $ \beta $ can be chosen in the range $ \beta $ [2,64]. The flbeta-toolbox will be part of Version 13 of INTLAB [18], the Matlab/Octave toolbox for reliable computing.

entry:
@Article{Rump:2023:IPP,
  author =       "Siegfried M. Rump",
  title =        "{IEEE-754} Precision-$p$ base-$ \beta $ Arithmetic
                 Implemented in Binary",
  journal =      j-TOMS,
  volume =       "49",
  number =       "4",
  pages =        "32:1--32:??",
  month =        dec,
  year =         "2023",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3596218",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Dec 23 05:40:24 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3596218;
                 https://www.tuhh.de/ti3/paper/rump/Ru23b.pdf",
  abstract =     "We show how an IEEE-754 conformant precision-$p$
                 base-$ \beta $ arithmetic can be implemented based on
                 some binary floating-point and/or integer arithmetic.
                 This includes the four basic operations and square root
                 subject to the five IEEE-754 rounding modes, namely he
                 nearest roundings with roundTiesToEven and
                 roundTiesToAway, the directed roundings downwards and
                 upwards, as well as rounding towards zero. Exceptional
                 values like $ \infty $ or NaN are covered according to
                 the IEEE-754 arithmetic standard.

                 The results of the precision-$p$ base-$ \beta $
                 operations are computed using some underlying
                 precision-$q$ binary arithmetic. We distinguish two
                 cases. When using a precision-$q$ binary integer
                 arithmetic, the base-$ \beta $ precision $p$ is limited
                 for all operations by $ \beta^{2 p} \leq 2^q$, whereas
                 using a precision-$q$ binary floating-point arithmetic
                 imposes stronger limits on the base-$ \beta $
                 precision, namely $ \beta^{2p} \leq 2^q$ for addition
                 and multiplication, $ \beta^{2p} \leq 2^{q - 1}$ for
                 division and $ \beta^{2p} \leq 2^{q - 3}$ for the
                 square root. Those limitations cannot be improved.

                 The algorithms are implemented in a Matlab/Octave
                 flbeta-toolbox with the choice of using uint64 or
                 binary64 as underlying arithmetic. The former allows
                 larger precisions, the latter is advantageous for the
                 square root, whereas computing times are similar. The
                 flbeta-toolbox offers precision-$p$ base-$ \beta $
                 scalar, vector and matrix operations including sparse
                 matrices as well as corresponding interval operations.
                 The base $ \beta $ can be chosen in the range $ \beta $
                 [2,64]. The flbeta-toolbox will be part of Version 13
                 of INTLAB [18], the Matlab/Octave toolbox for reliable
                 computing.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Math. Softw.",
  articleno =    "32",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  remark =       "Received 6 December 2021; revised 10 October 2022;
                 accepted 30 March 2023.",
}


bibtype: inproceedings
filename: fparith.bib
label: Rydahl:2023:PPA
author: Anton Rydahl and Joseph Huber and Ethan Luis Mcdonough and Johannes Doerfert
title: Precision and Performance Analysis of C Standard Math Library Functions on GPUs
publisher: pub-ACM
address: pub-ACM:adr
pages: 32:1--32:??
month: nov
monthnumber: 11
year: 2023
DOI: https://doi.org/10.1145/3624062.3624166
bibdate: Fri Dec 8 12:56:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 12:56:08 ???
acknowledgement: ack-nhfb
rawauthor: Anton Rydahl and Joseph Huber and Ethan Luis Mcdonough and Johannes Doerfert
rawtitle: Precision and Performance Analysis of {C} Standard Math Library Functions on {GPUs}
booktitle:
Proceedings of the SC 23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

abstract:
With the advent of GPU computing, executing large program sections on accelerators has become increasingly important. Efforts are being made to support the C standard library, LIBC, on GPUs via LLVM machinery. Therefore, the C standard math library, LIBM, must be supported on GPUs. So far, LLVM frontends, such as Clang, have relied on GPU vendor implementations of LIBM functionality wrapped into (mostly) LIBM-compatible forwarding functions.par We propose a novel LIBM for GPUs reusing a collection of LLVM target-agnostic implementations and built-ins alongside vendor implementations of most single and double-precision floating point math functions. Our approach allows selecting between individual implementations based on the GPU target as opposed to the current approach, which serves only the single third-party library implementation. Our extensive numerical analysis highlights the various implementations differences in performance and precision. Our solution allows users to choose the implementation that maximizes speed while meeting their specific precision requirements.

rawabstract:
With the advent of GPU computing, executing large program sections on accelerators has become increasingly important. Efforts are being made to support the C standard library, LIBC, on GPUs via LLVM machinery. Therefore, the C standard math library, LIBM, must be supported on GPUs. So far, LLVM frontends, such as Clang, have relied on GPU vendor implementations of LIBM functionality wrapped into (mostly) LIBM-compatible forwarding functions.\par We propose a novel LIBM for GPUs reusing a collection of LLVM target-agnostic implementations and built-ins alongside vendor implementations of most single and double-precision floating point math functions. Our approach allows selecting between individual implementations based on the GPU target as opposed to the current approach, which serves only the single third-party library implementation. Our extensive numerical analysis highlights the various implementations differences in performance and precision. Our solution allows users to choose the implementation that maximizes speed while meeting their specific precision requirements.

rawbooktitle:
Proceedings of the {SC 23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}

entry:
@InProceedings{Rydahl:2023:PPA,
  author =       "Anton Rydahl and Joseph Huber and Ethan Luis Mcdonough
                 and Johannes Doerfert",
  booktitle =    "Proceedings of the {SC 23 Workshops of The
                 International Conference on High Performance Computing,
                 Network, Storage, and Analysis}",
  title =        "Precision and Performance Analysis of {C} Standard
                 Math Library Functions on {GPUs}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  month =        nov,
  year =         "2023",
  DOI =          "https://doi.org/10.1145/3624062.3624166",
  bibdate =      "Fri Dec 8 12:56:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "With the advent of GPU computing, executing large
                 program sections on accelerators has become
                 increasingly important. Efforts are being made to
                 support the C standard library, LIBC, on GPUs via LLVM
                 machinery. Therefore, the C standard math library,
                 LIBM, must be supported on GPUs. So far, LLVM
                 frontends, such as Clang, have relied on GPU vendor
                 implementations of LIBM functionality wrapped into
                 (mostly) LIBM-compatible forwarding functions.\par

                 We propose a novel LIBM for GPUs reusing a collection
                 of LLVM target-agnostic implementations and built-ins
                 alongside vendor implementations of most single and
                 double-precision floating point math functions. Our
                 approach allows selecting between individual
                 implementations based on the GPU target as opposed to
                 the current approach, which serves only the single
                 third-party library implementation. Our extensive
                 numerical analysis highlights the various
                 implementations differences in performance and
                 precision. Our solution allows users to choose the
                 implementation that maximizes speed while meeting their
                 specific precision requirements.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Safieh:2023:EBR
author: Malek Safieh and Andreas Furch and Fabrizio De Santis
title: An Efficient Barrett Reduction Algorithm for Gaussian Integer Moduli
crossref: IEEE:2023:PIS
pages: 76--83
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00011
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Malek Safieh and Andreas Furch and Fabrizio {De Santis}
rawtitle: An Efficient {Barrett} Reduction Algorithm for {Gaussian} Integer Moduli
keywords:
ARITH 2023; ARITH-30; Barrett Reduction; Computational complexity; Computational efficiency; Costs; Digital arithmetic; Gaussian Integers; Modular Arithmetic; Modulo Reduction

entry:
@InProceedings{Safieh:2023:EBR,
  author =       "Malek Safieh and Andreas Furch and Fabrizio {De
                 Santis}",
  title =        "An Efficient {Barrett} Reduction Algorithm for
                 {Gaussian} Integer Moduli",
  crossref =     "IEEE:2023:PIS",
  pages =        "76--83",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00011",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Barrett Reduction; Computational
                 complexity; Computational efficiency; Costs; Digital
                 arithmetic; Gaussian Integers; Modular Arithmetic;
                 Modulo Reduction",
}


bibtype: inproceedings
filename: fparith.bib
label: Saikia:2023:FIA
booktitle: ESSCIRC 2023 --- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
title: FP-IMC: a 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 405--408
year: 2023
DOI: https://doi.org/10.1109/ESSCIRC59616.2023.10268770
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {ESSCIRC 2023 --- IEEE 49th European Solid State Circuits Conference (ESSCIRC)}
rawtitle: {FP-IMC}: a 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro
author:
Jyotishman Saikia and Amitesh Sridharan and Injune Yeo and Shreyas Venkataramanaiah and Deliang Fan and Jae-Sun Seo

keywords:
Artificial neural networks; Computational modeling; Computer architecture; Digital in-memory computing; Europe; floating-point acceleration; In-memory computing; Throughput; Training

rawauthor:
Jyotishman Saikia and Amitesh Sridharan and Injune Yeo and Shreyas Venkataramanaiah and Deliang Fan and Jae-Sun Seo

entry:
@InProceedings{Saikia:2023:FIA,
  author =       "Jyotishman Saikia and Amitesh Sridharan and Injune Yeo
                 and Shreyas Venkataramanaiah and Deliang Fan and
                 Jae-Sun Seo",
  booktitle =    "{ESSCIRC 2023 --- IEEE 49th European Solid State
                 Circuits Conference (ESSCIRC)}",
  title =        "{FP-IMC}: a 28nm All-Digital Configurable
                 Floating-Point In-Memory Computing Macro",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "405--408",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ESSCIRC59616.2023.10268770",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Artificial neural networks; Computational modeling;
                 Computer architecture; Digital in-memory computing;
                 Europe; floating-point acceleration; In-memory
                 computing; Throughput; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Sajid:2023:ODN
author: Shoaib Sajid and Sereiwatha Ros and Hyung-Won Kim
booktitle: 2023 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)
title: Optimizing Deep Neural Network with Brain Floating Half-Precision Format
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/ICCE-Asia59966.2023.10326380
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Shoaib Sajid and Sereiwatha Ros and Hyung-Won Kim
rawbooktitle: {2023 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)}
rawtitle: Optimizing Deep Neural Network with Brain Floating Half-Precision Format
keywords:
Accuracy; Artificial neural networks; BFLOAT16; Brain modeling; Computational modeling; Convergence; Costs; Deep Learning; Energy consumption; Half-Precision Format; Memory Efficiency; Memory management; Training

entry:
@InProceedings{Sajid:2023:ODN,
  author =       "Shoaib Sajid and Sereiwatha Ros and Hyung-Won Kim",
  booktitle =    "{2023 IEEE International Conference on Consumer
                 Electronics-Asia (ICCE-Asia)}",
  title =        "Optimizing Deep Neural Network with Brain Floating
                 Half-Precision Format",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCE-Asia59966.2023.10326380",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Artificial neural networks; BFLOAT16; Brain
                 modeling; Computational modeling; Convergence; Costs;
                 Deep Learning; Energy consumption; Half-Precision
                 Format; Memory Efficiency; Memory management;
                 Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Sakellariou:2023:MFR
title: A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity
crossref: IEEE:2023:PIS
pages: 101--101
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00037
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawtitle: A multiplier-Free {RNS}-Based {CNN} accelerator exploiting bit-Level sparsity
author:
Vasilis Sakellariou and Vassilis Paliouras and Ioannis Kouretas and Hani Saleh and Thanos Stouraitis

keywords:
Analytical models; ARITH 2023; ARITH-30; Benchmark testing; Digital arithmetic; Encoding; Energy efficiency; Throughput; Vectors

rawauthor:
Vasilis Sakellariou and Vassilis Paliouras and Ioannis Kouretas and Hani Saleh and Thanos Stouraitis

entry:
@InProceedings{Sakellariou:2023:MFR,
  author =       "Vasilis Sakellariou and Vassilis Paliouras and Ioannis
                 Kouretas and Hani Saleh and Thanos Stouraitis",
  title =        "A multiplier-Free {RNS}-Based {CNN} accelerator
                 exploiting bit-Level sparsity",
  crossref =     "IEEE:2023:PIS",
  pages =        "101--101",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00037",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Analytical models; ARITH 2023; ARITH-30; Benchmark
                 testing; Digital arithmetic; Encoding; Energy
                 efficiency; Throughput; Vectors",
}


bibtype: article
filename: fparith.bib
label: Schilling:2023:BSR
author: Jonathan Schilling and Jakob Svensson and Udo Hofel and Joachim Geiger and Henning Thomsen
title: Biot--Savart routines with minimal floating point error
journal: j-COMP-PHYS-COMM
volume: 287
pages: Article 108692
month: jun
monthnumber: 6
year: 2023
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2023.108692
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Fri Mar 17 07:49:53 MDT 2023
bibtimestamp: 2023.03.17 07:49:53 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0010465523000371
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Jonathan Schilling and Jakob Svensson and Udo H{\"o}fel and Joachim Geiger and Henning Thomsen
rawtitle: {Biot--Savart} routines with minimal floating point error
bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Schilling:2023:BSR,
  author =       "Jonathan Schilling and Jakob Svensson and Udo
                 H{\"o}fel and Joachim Geiger and Henning Thomsen",
  title =        "{Biot--Savart} routines with minimal floating point
                 error",
  journal =      j-COMP-PHYS-COMM,
  volume =       "287",
  number =       "??",
  pages =        "Article 108692",
  month =        jun,
  year =         "2023",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2023.108692",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Fri Mar 17 07:49:53 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465523000371",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: inproceedings
filename: fparith.bib
label: Seo:2023:DPHa
author: Jihee Seo and Dae Hyun Kim
title: Dual-Purpose Hardware Algorithms and Architectures. Part 1: Floating-Point Division
crossref: IEEE:2023:PIS
pages: 24--31
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00013
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Jihee Seo and Dae Hyun Kim
rawtitle: Dual-Purpose Hardware Algorithms and Architectures. {Part 1}: Floating-Point Division
keywords:
ARITH 2023; ARITH-30; Computer architecture; Costs; Digital arithmetic; Divider; Energy consumption; Floating-Point Arithmetic; Hardware; Online Division; Simulation; Throughput

entry:
@InProceedings{Seo:2023:DPHa,
  author =       "Jihee Seo and Dae Hyun Kim",
  title =        "Dual-Purpose Hardware Algorithms and Architectures.
                 {Part 1}: Floating-Point Division",
  crossref =     "IEEE:2023:PIS",
  pages =        "24--31",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00013",
  bibdate =      "Wed May 8 09:17:31 2024",
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  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Computer architecture; Costs;
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                 Simulation; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Seo:2023:DPHb
author: Jihee Seo and Dae Hyun Kim
title: Dual-Purpose Hardware Algorithms and Architectures. Part 2: Integer Division
crossref: IEEE:2023:PIS
pages: 1--8
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00014
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Jihee Seo and Dae Hyun Kim
rawtitle: Dual-Purpose Hardware Algorithms and Architectures. {Part 2}: Integer Division
keywords:
ARITH 2023; ARITH-30; Computer architecture; Costs; Digital arithmetic; Divider; Energy consumption; Hardware; Integer Arithmetic; Online Division; Simulation

entry:
@InProceedings{Seo:2023:DPHb,
  author =       "Jihee Seo and Dae Hyun Kim",
  title =        "Dual-Purpose Hardware Algorithms and Architectures.
                 {Part 2}: Integer Division",
  crossref =     "IEEE:2023:PIS",
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00014",
  bibdate =      "Wed May 8 09:17:31 2024",
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  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Computer architecture; Costs;
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                 Simulation",
}


bibtype: inproceedings
filename: fparith.bib
label: Shah:2023:DPU
author: Nimish Shah and Wannes Meert and Marian Verhelst
booktitle: Efficient Execution of Irregular Dataflow Graphs
publisher: pub-SV
address: pub-SV:adr
pages: 69--88
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7_4
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
rawbooktitle: Efficient Execution of Irregular Dataflow Graphs
title:
DAG Processing Unit Version 1 (DPU): Efficient Execution of Irregular Workloads on a Multicore Processor

rawtitle:
{DAG} Processing Unit Version 1 ({DPU}): Efficient Execution of Irregular Workloads on a Multicore Processor

entry:
@InProceedings{Shah:2023:DPU,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  booktitle =    "Efficient Execution of Irregular Dataflow Graphs",
  title =        "{DAG} Processing Unit Version 1 ({DPU}): Efficient
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  publisher =    pub-SV,
  address =      pub-SV:adr,
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  DOI =          "https://doi.org/10.1007/978-3-031-33136-7_4",
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  acknowledgement = ack-nhfb,
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bibtype: book
filename: fparith.bib
label: Shah:2023:EEI
author: Nimish Shah and Wannes Meert and Marian Verhelst
publisher: pub-SV
address: pub-SV:adr
pages: 69--88
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
title:
Efficient Execution of Irregular Dataflow Graphs: Hardware / Software Co-optimization for Probabilistic AI and Sparse Linear Algebra

rawtitle:
Efficient Execution of Irregular Dataflow Graphs: Hardware\slash Software Co-optimization for Probabilistic {AI} and Sparse Linear Algebra

entry:
@Book{Shah:2023:EEI,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  title =        "Efficient Execution of Irregular Dataflow Graphs:
                 Hardware\slash Software Co-optimization for
                 Probabilistic {AI} and Sparse Linear Algebra",
  publisher =    pub-SV,
  address =      pub-SV:adr,
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  DOI =          "https://doi.org/10.1007/978-3-031-33136-7",
  ISBN =         "3-031-33136-2",
  ISBN-13 =      "978-3-031-33136-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Shah:2023:IWR
author: Nimish Shah and Wannes Meert and Marian Verhelst
booktitle: Efficient Execution of Irregular Dataflow Graphs
title: Irregular Workloads at Risk of Losing the Hardware Lottery
publisher: pub-SV
address: pub-SV:adr
pages: 1--21
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7_1
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
rawbooktitle: Efficient Execution of Irregular Dataflow Graphs
rawtitle: Irregular Workloads at Risk of Losing the Hardware Lottery
entry:
@InProceedings{Shah:2023:IWR,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  booktitle =    "Efficient Execution of Irregular Dataflow Graphs",
  title =        "Irregular Workloads at Risk of Losing the Hardware
                 Lottery",
  publisher =    pub-SV,
  address =      pub-SV:adr,
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  DOI =          "https://doi.org/10.1007/978-3-031-33136-7_1",
  ISBN =         "3-031-33136-2",
  ISBN-13 =      "978-3-031-33136-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
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bibtype: inproceedings
filename: fparith.bib
label: Shah:2023:SDR
author: Nimish Shah and Wannes Meert and Marian Verhelst
booktitle: Efficient Execution of Irregular Dataflow Graphs
publisher: pub-SV
address: pub-SV:adr
pages: 23--41
year: 2023
DOI: https://doi.org/10.1007/978-3-031-33136-7_2
ISBN: 3-031-33136-2 OR 3031331362
ISBN13: 978-3-031-33136-7 OR 9783031331367
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Nimish Shah and Wannes Meert and Marian Verhelst
rawbooktitle: Efficient Execution of Irregular Dataflow Graphs
title:
Suitable Data Representation: A Study of Fixed-Point, Floating-Point, and PositTM Formats for Probabilistic AI

rawtitle:
Suitable Data Representation: A Study of Fixed-Point, Floating-Point, and {PositTM} Formats for Probabilistic {AI}

entry:
@InProceedings{Shah:2023:SDR,
  author =       "Nimish Shah and Wannes Meert and Marian Verhelst",
  booktitle =    "Efficient Execution of Irregular Dataflow Graphs",
  title =        "Suitable Data Representation: A Study of Fixed-Point,
                 Floating-Point, and {PositTM} Formats for Probabilistic
                 {AI}",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "23--41",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-33136-7_2",
  ISBN =         "3-031-33136-2",
  ISBN-13 =      "978-3-031-33136-7",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Shahbazi:2023:OHI
author: Karim Shahbazi and Seok-Bum Ko
title: An Optimized Hardware Implementation of Modular Multiplication of Binary Ring LWE
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 11
number: 3
pages: 817--821
month: jul
monthnumber: 7
year: 2023
DOI: https://doi.org/10.1109/TETC.2023.3280470
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Karim Shahbazi and Seok-Bum Ko
rawtitle: An Optimized Hardware Implementation of Modular Multiplication of Binary Ring {LWE}
entry:
@Article{Shahbazi:2023:OHI,
  author =       "Karim Shahbazi and Seok-Bum Ko",
  title =        "An Optimized Hardware Implementation of Modular
                 Multiplication of Binary Ring {LWE}",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "11",
  number =       "3",
  pages =        "817--821",
  month =        jul # "\slash " # sep,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TETC.2023.3280470",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: article
filename: fparith.bib
label: Sharma:2023:CQE
title: CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism
journal: j-J-SYST-ARCH
volume: 135
pages: 102801
year: 2023
CODEN: JSARFB
DOI: https://doi.org/10.1016/j.sysarc.2022.102801
ISSN: 1383-7621 (print), 1873-6165 (electronic) OR 13837621 (print), 18736165 (electronic)
ISSNL: 1383-7621 OR 13837621
bibdate: Wed May 22 14:56:32 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2024.05.22 14:56:32 ???
URL: https://www.sciencedirect.com/science/article/pii/S1383762122002867
fjournal: Journal of Systems Architecture
keywords: Posit-arithmetic, RISC-V, Open-source hardware, Custom-instructions
acknowledgement: ack-nhfb
ajournal: J. Syst. Arch.
journalURL: https://www.sciencedirect.com/journal/journal-of-systems-architecture
rawtitle: {CLARINET}: A quire-enabled {RISC-V}-based framework for posit arithmetic empiricism
author:
Niraj N. Sharma and Riya Jain and Mohana Madhumita Pokkuluri and Sachin B. Patkar and Rainer Leupers and Rishiyur S. Nikhil and Farhad Merchant

rawauthor:
Niraj N. Sharma and Riya Jain and Mohana Madhumita Pokkuluri and Sachin B. Patkar and Rainer Leupers and Rishiyur S. Nikhil and Farhad Merchant

entry:
@Article{Sharma:2023:CQE,
  author =       "Niraj N. Sharma and Riya Jain and Mohana Madhumita
                 Pokkuluri and Sachin B. Patkar and Rainer Leupers and
                 Rishiyur S. Nikhil and Farhad Merchant",
  title =        "{CLARINET}: A quire-enabled {RISC-V}-based framework
                 for posit arithmetic empiricism",
  journal =      j-J-SYST-ARCH,
  volume =       "135",
  pages =        "102801",
  year =         "2023",
  CODEN =        "JSARFB",
  DOI =          "https://doi.org/10.1016/j.sysarc.2022.102801",
  ISSN =         "1383-7621 (print), 1873-6165 (electronic)",
  ISSN-L =       "1383-7621",
  bibdate =      "Wed May 22 14:56:32 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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  URL =          "https://www.sciencedirect.com/science/article/pii/S1383762122002867",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Syst. Arch.",
  fjournal =     "Journal of Systems Architecture",
  journal-URL =  "https://www.sciencedirect.com/journal/journal-of-systems-architecture",
  keywords =     "Posit-arithmetic, RISC-V, Open-source hardware,
                 Custom-instructions",
}


bibtype: inproceedings
filename: fparith.bib
label: Shekhawat:2023:PPH
author: Diksha Shekhawat and Jugal Gandhi and M. Santosh and Jai Gopal Pandey
title: PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
crossref: Gustafson:2023:NGA
pages: 88--100
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_6
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Diksha Shekhawat and Jugal Gandhi and M. Santosh and Jai Gopal Pandey
rawtitle: {PHAc}: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
entry:
@InProceedings{Shekhawat:2023:PPH,
  author =       "Diksha Shekhawat and Jugal Gandhi and M. Santosh and
                 Jai Gopal Pandey",
  title =        "{PHAc}: Posit Hardware Accelerator for Efficient
                 Arithmetic Logic Operations",
  crossref =     "Gustafson:2023:NGA",
  pages =        "88--100",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_6",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Shen:2023:CCA
author: Shiyu Shen and Hao Yang and Yu Liu and Zhe Liu and Yunlei Zhao
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 7
pages: 1999--2010
month: jul
monthnumber: 7
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3227874
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 1 10:59:22 2023
bibtimestamp: 2023.07.01 10:59:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
rawauthor: Shiyu Shen and Hao Yang and Yu Liu and Zhe Liu and Yunlei Zhao
title:
CARM: CUDA-Accelerated RNS Multiplication in Word-Wise Homomorphic Encryption Schemes for Internet of Things

journalURL:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12

rawtitle:
{CARM}: {CUDA-Accelerated RNS Multiplication} in Word-Wise Homomorphic Encryption Schemes for {Internet of Things}

entry:
@Article{Shen:2023:CCA,
  author =       "Shiyu Shen and Hao Yang and Yu Liu and Zhe Liu and
                 Yunlei Zhao",
  title =        "{CARM}: {CUDA-Accelerated RNS Multiplication} in
                 Word-Wise Homomorphic Encryption Schemes for {Internet
                 of Things}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "7",
  pages =        "1999--2010",
  month =        jul,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3227874",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 1 10:59:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
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bibtype: inproceedings
filename: fparith.bib
label: Silva:2023:TAB
author: Himeshi De Silva and Hongshi Tan and Nhut-Minh Ho and John L. Gustafson and Weng-Fai Wong
title: Towards a Better 16-Bit Number Representation for Training Neural Networks
crossref: Gustafson:2023:NGA
pages: 114--133
year: 2023
DOI: https://doi.org/10.1007/978-3-031-32180-1_8
bibdate: Sat Dec 16 08:52:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 08:52:12 ???
acknowledgement: ack-nhfb
rawauthor: Himeshi De Silva and Hongshi Tan and Nhut-Minh Ho and John L. Gustafson and Weng-Fai Wong
rawtitle: Towards a Better 16-Bit Number Representation for Training Neural Networks
entry:
@InProceedings{Silva:2023:TAB,
  author =       "Himeshi De Silva and Hongshi Tan and Nhut-Minh Ho and
                 John L. Gustafson and Weng-Fai Wong",
  title =        "Towards a Better 16-Bit Number Representation for
                 Training Neural Networks",
  crossref =     "Gustafson:2023:NGA",
  pages =        "114--133",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-32180-1_8",
  bibdate =      "Sat Dec 16 08:52:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Sohn:2023:EFP
author: Jongwook Sohn and David K. Dean and Eric Quintana and Wing Shek Wong
title: Enhanced Floating-Point Multiply-Add with Full Denormal Support
crossref: IEEE:2023:PIS
pages: 143--150
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00015
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Jongwook Sohn and David K. Dean and Eric Quintana and Wing Shek Wong
rawtitle: Enhanced Floating-Point Multiply-Add with Full Denormal Support
keywords:
ARITH 2023; ARITH-30; Delays; Digital arithmetic; Encoding; floating-point arithmetic; floating-point denormal numbers; Floating-point multiply-add; high-speed computer arithmetic; Logic arrays; Next generation networking; Optimization

entry:
@InProceedings{Sohn:2023:EFP,
  author =       "Jongwook Sohn and David K. Dean and Eric Quintana and
                 Wing Shek Wong",
  title =        "Enhanced Floating-Point Multiply-Add with Full
                 Denormal Support",
  crossref =     "IEEE:2023:PIS",
  pages =        "143--150",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00015",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Delays; Digital arithmetic;
                 Encoding; floating-point arithmetic; floating-point
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                 high-speed computer arithmetic; Logic arrays; Next
                 generation networking; Optimization",
}


bibtype: misc
filename: fparith.bib
label: Sukop:2023:HDB
author: Juraj Sukop and Niels Moller
title: On HGCD-D bounds
type: Report
pages: 143--150
day: 7
month: feb
monthnumber: 2
year: 2023
bibdate: Thu Feb 09 11:15:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.02.09 11:15:45 ???
URL: https://hal.science/hal-03976898
acknowledgement: ack-nhfb
rawauthor: Juraj Sukop and Niels M{\"o}ller
rawtitle: On {HGCD-D} bounds
abstract:
An improved bound for one of the founding relations of HGCD-D algorithm is presented. This allows to put a lower limit on the iteration count of the first sdiv loop, to impose a particular structure on the accumulated quotients and to bound the size of the largest matrix element. The matrix product M.M' is proved to have its upper and lower size bound differ by at most two bits

rawabstract:
An improved bound for one of the founding relations of HGCD-D algorithm is presented. This allows to put a lower limit on the iteration count of the first sdiv loop, to impose a particular structure on the accumulated quotients and to bound the size of the largest matrix element. The matrix product M.M' is proved to have its upper and lower size bound differ by at most two bits

entry:
@Misc{Sukop:2023:HDB,
  author =       "Juraj Sukop and Niels M{\"o}ller",
  title =        "On {HGCD-D} bounds",
  type =         "Report",
  day =          "7",
  month =        feb,
  year =         "2023",
  bibdate =      "Thu Feb 09 11:15:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-03976898",
  abstract =     "An improved bound for one of the founding relations of
                 HGCD-D algorithm is presented. This allows to put a
                 lower limit on the iteration count of the first sdiv
                 loop, to impose a particular structure on the
                 accumulated quotients and to bound the size of the
                 largest matrix element. The matrix product M.M' is
                 proved to have its upper and lower size bound differ by
                 at most two bits",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Taka:2023:MME
author: Endri Taka and Aman Arora and Kai-Chiang Wu and Diana Marculescu
booktitle: 2023 International Conference on Field Programmable Technology (ICFPT)
title: MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 96--105
year: 2023
DOI: https://doi.org/10.1109/ICFPT59805.2023.00016
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Endri Taka and Aman Arora and Kai-Chiang Wu and Diana Marculescu
rawbooktitle: {2023 International Conference on Field Programmable Technology (ICFPT)}
rawtitle: {MaxEVA}: Maximizing the Efficiency of Matrix Multiplication on {Versal AI Engine}
keywords:
AI Engine; Artificial intelligence; Deep Learning; Energy efficiency; Engines; FPGA; Hardware Acceleration; Matrix Multiplication; Performance evaluation; Program processors; System-on-Chip; Technological innovation; Throughput; Versal

entry:
@InProceedings{Taka:2023:MME,
  author =       "Endri Taka and Aman Arora and Kai-Chiang Wu and Diana
                 Marculescu",
  booktitle =    "{2023 International Conference on Field Programmable
                 Technology (ICFPT)}",
  title =        "{MaxEVA}: Maximizing the Efficiency of Matrix
                 Multiplication on {Versal AI Engine}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "96--105",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICFPT59805.2023.00016",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AI Engine; Artificial intelligence; Deep Learning;
                 Energy efficiency; Engines; FPGA; Hardware
                 Acceleration; Matrix Multiplication; Performance
                 evaluation; Program processors; System-on-Chip;
                 Technological innovation; Throughput; Versal",
}


bibtype: article
filename: fparith.bib
label: Talpes:2023:MDT
title: The Microarchitecture of DOJO, Tesla's Exa-Scale Computer
journal: j-IEEE-MICRO
volume: 43
number: 3
pages: 31--39
month: may
monthnumber: 5
year: 2023
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2023.3258906
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Thu May 18 07:38:12 2023
bibtimestamp: 2023.05.18 07:38:12 ???
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40
rawtitle: The Microarchitecture of {DOJO}, {Tesla}'s Exa-Scale Computer
author:
Emil Talpes and Debjit Das Sarma and Doug Williams and Sahil Arora and Thomas Kunjan and Benjamin Floering and Ankit Jalote and Christopher Hsiong and Chandrasekhar Poorna and Vaidehi Samant and John Sicilia and Anantha Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer and Ben Herzberg and Bill McGee and Ganesh Venkataramanan and Pete Banon

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/hot-chips.bib; https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

remark:
DOJO is based on RISC-V64 with instruction set extensions. Its arithmetic supports 8-, 16-, 32-, and 64-bit integers, and IEEE 754 FP32 (1/8/23), plus FP16 (1/5/10), BFP16 (1/8/7), CFP8 (1/4/3), CFP8 (1/5/2), and CFP16 (1/5/10) floating-point formats. The latter is unusual having an external register that records the exponent bias (0, 31, or 63), so that it supports three different ranges of numbers. There is no support for FP64 or longer formats. There is support for stochastic rounding.

rawauthor:
Emil Talpes and Debjit Das Sarma and Doug Williams and Sahil Arora and Thomas Kunjan and Benjamin Floering and Ankit Jalote and Christopher Hsiong and Chandrasekhar Poorna and Vaidehi Samant and John Sicilia and Anantha Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer and Ben Herzberg and Bill McGee and Ganesh Venkataramanan and Pete Banon

entry:
@Article{Talpes:2023:MDT,
  author =       "Emil Talpes and Debjit Das Sarma and Doug Williams and
                 Sahil Arora and Thomas Kunjan and Benjamin Floering and
                 Ankit Jalote and Christopher Hsiong and Chandrasekhar
                 Poorna and Vaidehi Samant and John Sicilia and Anantha
                 Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer
                 and Ben Herzberg and Bill McGee and Ganesh
                 Venkataramanan and Pete Banon",
  title =        "The Microarchitecture of {DOJO}, {Tesla}'s Exa-Scale
                 Computer",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "3",
  pages =        "31--39",
  month =        may # "\slash " # jun,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3258906",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu May 18 07:38:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
  remark =       "DOJO is based on RISC-V64 with instruction set
                 extensions. Its arithmetic supports 8-, 16-, 32-, and
                 64-bit integers, and IEEE 754 FP32 (1/8/23), plus FP16
                 (1/5/10), BFP16 (1/8/7), CFP8 (1/4/3), CFP8 (1/5/2),
                 and CFP16 (1/5/10) floating-point formats. The latter
                 is unusual having an external register that records the
                 exponent bias (0, 31, or 63), so that it supports three
                 different ranges of numbers. There is no support for
                 FP64 or longer formats. There is support for stochastic
                 rounding.",
}


bibtype: inproceedings
filename: fparith.bib
label: Tompazi:2023:ABT
author: Styliani Tompazi and Georgios Karakonstantis
title: AI-based Timing Error Modelling: a Case Study on a Pipelined Floating-point Core
crossref: IEEE:2023:PIS
pages: 110--110
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00035
bibdate: Wed May 8 09:17:31 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Styliani Tompazi and Georgios Karakonstantis
rawtitle: {AI}-based Timing Error Modelling: a Case Study on a Pipelined Floating-point Core
keywords:
ARITH 2023; ARITH-30; Computational modeling; Digital arithmetic; Machine learning; Nanoscale devices; Timing; Training

entry:
@InProceedings{Tompazi:2023:ABT,
  author =       "Styliani Tompazi and Georgios Karakonstantis",
  title =        "{AI}-based Timing Error Modelling: a Case Study on a
                 Pipelined Floating-point Core",
  crossref =     "IEEE:2023:PIS",
  pages =        "110--110",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00035",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; Computational modeling; Digital
                 arithmetic; Machine learning; Nanoscale devices;
                 Timing; Training",
}


bibtype: article
filename: fparith.bib
label: Towhidy:2023:DIA
author: Ahmad Towhidy and Reza Omidi and Karim Mohammadi
title: On the Design of Iterative Approximate Floating-Point Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 6
pages: 1623--1635
month: jun
monthnumber: 6
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2022.3216465
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed May 17 10:34:15 2023
bibtimestamp: 2023.05.17 10:34:15 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ahmad Towhidy and Reza Omidi and Karim Mohammadi
rawtitle: On the Design of Iterative Approximate Floating-Point Multipliers
abstract:
Approximate multipliers provide power and area-saving for error-resilient applications. In this paper, we first propose two approximate floating-point multipliers based on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point iterative pseudo-Booth (IPB). The accuracy of proposed multipliers can be tuned by three parameters: iteration, encoder's radix (R), and word length after truncation (W). Next, we developed the conventional iterative multipliers with a simplified steering circuit for their correction part to eliminate the power consumption of multipliers. The proposed iterative multipliers are compared with conventional iterative integer multipliers implemented by a simplified steering circuit for the floating-point area. The results reveal that the proposed PB-R4-W4 and IPB-R16-W19, compared to the exact floating-point multiplier, provide up to 98.9% and 67.5% reductions in power consumption, respectively, in TSMC 180nm CMOS technology. Also, their MRED values are, respectively, 2.9% and ($ 7.4 times 10 -4$)%. Finally, we evaluated the functionality of the proposed multipliers for real-life applications, including a hyper-plane classifier and two image processing applications of smoothing and sharpening.

rawabstract:
Approximate multipliers provide power and area-saving for error-resilient applications. In this paper, we first propose two approximate floating-point multipliers based on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point iterative pseudo-Booth (IPB). The accuracy of proposed multipliers can be tuned by three parameters: iteration, encoder's radix (R), and word length after truncation (W). Next, we developed the conventional iterative multipliers with a simplified steering circuit for their correction part to eliminate the power consumption of multipliers. The proposed iterative multipliers are compared with conventional iterative integer multipliers implemented by a simplified steering circuit for the floating-point area. The results reveal that the proposed PB-R4-W4 and IPB-R16-W19, compared to the exact floating-point multiplier, provide up to 98.9\% and 67.5\% reductions in power consumption, respectively, in TSMC 180nm CMOS technology. Also, their MRED values are, respectively, 2.9\% and ($ 7.4 \times 10 {-4}$)\%. Finally, we evaluated the functionality of the proposed multipliers for real-life applications, including a hyper-plane classifier and two image processing applications of smoothing and sharpening.

entry:
@Article{Towhidy:2023:DIA,
  author =       "Ahmad Towhidy and Reza Omidi and Karim Mohammadi",
  title =        "On the Design of Iterative Approximate Floating-Point
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "6",
  pages =        "1623--1635",
  month =        jun,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3216465",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed May 17 10:34:15 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Approximate multipliers provide power and area-saving
                 for error-resilient applications. In this paper, we
                 first propose two approximate floating-point
                 multipliers based on two-dimensional pseudo-Booth
                 encoding: floating-point pseudo-Booth (PB), and
                 floating-point iterative pseudo-Booth (IPB). The
                 accuracy of proposed multipliers can be tuned by three
                 parameters: iteration, encoder's radix (R), and word
                 length after truncation (W). Next, we developed the
                 conventional iterative multipliers with a simplified
                 steering circuit for their correction part to eliminate
                 the power consumption of multipliers. The proposed
                 iterative multipliers are compared with conventional
                 iterative integer multipliers implemented by a
                 simplified steering circuit for the floating-point
                 area. The results reveal that the proposed PB-R4-W4 and
                 IPB-R16-W19, compared to the exact floating-point
                 multiplier, provide up to 98.9\% and 67.5\% reductions
                 in power consumption, respectively, in TSMC 180nm CMOS
                 technology. Also, their MRED values are, respectively,
                 2.9\% and ($ 7.4 \times 10 {-4}$)\%. Finally, we
                 evaluated the functionality of the proposed multipliers
                 for real-life applications, including a hyper-plane
                 classifier and two image processing applications of
                 smoothing and sharpening.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Tu:2023:TGW
booktitle: 2023 IEEE International Solid-State Circuits Conference (ISSCC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 254--256
year: 2023
DOI: https://doi.org/10.1109/ISSCC42615.2023.10067285
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2023 IEEE International Solid-State Circuits Conference (ISSCC)}
author:
Fengbin Tu and Yiqi Wang and Zihan Wu and Weiwei Wu and Leibo Liu and Yang Hu and Shaojun Wei and Shouyi Yin

title:
16.4 TensorCIM: a 28nm 3.7nJ / Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration

keywords:
Algebra; Bandwidth; Computational modeling; Computer architecture; Deep learning; Program processors; Tensors

rawauthor:
Fengbin Tu and Yiqi Wang and Zihan Wu and Weiwei Wu and Leibo Liu and Yang Hu and Shaojun Wei and Shouyi Yin

rawtitle:
16.4 {TensorCIM}: a {28nm 3.7nJ}\slash Gather and {8.3TFLOPS/W} {FP32} Digital-{CIM} Tensor Processor for {MCM-CIM}-Based Beyond-{NN} Acceleration

entry:
@InProceedings{Tu:2023:TGW,
  author =       "Fengbin Tu and Yiqi Wang and Zihan Wu and Weiwei Wu
                 and Leibo Liu and Yang Hu and Shaojun Wei and Shouyi
                 Yin",
  booktitle =    "{2023 IEEE International Solid-State Circuits
                 Conference (ISSCC)}",
  title =        "16.4 {TensorCIM}: a {28nm 3.7nJ}\slash Gather and
                 {8.3TFLOPS/W} {FP32} Digital-{CIM} Tensor Processor for
                 {MCM-CIM}-Based Beyond-{NN} Acceleration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "254--256",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISSCC42615.2023.10067285",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algebra; Bandwidth; Computational modeling; Computer
                 architecture; Deep learning; Program processors;
                 Tensors",
}


bibtype: inproceedings
filename: fparith.bib
label: Ullah:2023:DRE
author: Salim Ullah and Siva Satyendra Sahoo and Akash Kumar
booktitle: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing
publisher: pub-SV
address: pub-SV:adr
pages: 89--119
month: oct
monthnumber: 10
year: 2023
DOI: https://doi.org/10.1007/978-3-031-19568-6_4
ISBN: 3-031-19568-X OR 303119568X
ISBN13: 978-3-031-19568-6 OR 9783031195686
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Salim Ullah and Siva Satyendra Sahoo and Akash Kumar
rawbooktitle: Embedded Machine Learning for Cyber-Physical, {IoT}, and Edge Computing
title:
Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations

rawtitle:
Designing Resource-Efficient Hardware Arithmetic for {FPGA}-Based Accelerators Leveraging Approximations and Mixed Quantizations

entry:
@InProceedings{Ullah:2023:DRE,
  author =       "Salim Ullah and Siva Satyendra Sahoo and Akash Kumar",
  booktitle =    "Embedded Machine Learning for Cyber-Physical, {IoT},
                 and Edge Computing",
  title =        "Designing Resource-Efficient Hardware Arithmetic for
                 {FPGA}-Based Accelerators Leveraging Approximations and
                 Mixed Quantizations",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "89--119",
  month =        oct,
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-3-031-19568-6_4",
  ISBN =         "3-031-19568-X",
  ISBN-13 =      "978-3-031-19568-6",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: V:2023:IFP
author: Velmurugan V M and Ayub Khan A and Bharanidharan S
booktitle: 2023 International Conference on Next Generation Electronics (NEleX)
title: Implementation of Floating Point CORDIC Algorithm Using 45 nm Technology For COS SINE Generation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2023
DOI: https://doi.org/10.1109/NEleX59773.2023.10420961
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Velmurugan V M and Ayub Khan A and Bharanidharan S
rawbooktitle: {2023 International Conference on Next Generation Electronics (NEleX)}
keywords:
Arithmetic; Arrays; atan; Codes; Coordinate Rotation Digital Computer; Field Programmable Gate Arrays; FPUs; Graphic Data System; Hardware design languages; Logic gates; Next generation networking; Standards

rawtitle:
Implementation of Floating Point {CORDIC} Algorithm Using 45 nm Technology For {COS} {SINE} Generation

entry:
@InProceedings{V:2023:IFP,
  author =       "Velmurugan V M and Ayub Khan A and Bharanidharan S",
  booktitle =    "{2023 International Conference on Next Generation
                 Electronics (NEleX)}",
  title =        "Implementation of Floating Point {CORDIC} Algorithm
                 Using 45 nm Technology For {COS} {SINE} Generation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/NEleX59773.2023.10420961",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Arithmetic; Arrays; atan; Codes; Coordinate Rotation
                 Digital Computer; Field Programmable Gate Arrays; FPUs;
                 Graphic Data System; Hardware design languages; Logic
                 gates; Next generation networking; Standards",
}


bibtype: article
filename: fparith.bib
label: Valuev:2023:DFA
author: Georgii Valuev and Maria Valueva and Mikhail Babenko and Andrei Tchernykh
journal: j-IEEE-ACCESS
volume: 11
pages: 26807--26819
year: 2023
DOI: https://doi.org/10.1109/ACCESS.2023.3258689
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:08:36 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:08:36 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Georgii Valuev and Maria Valueva and Mikhail Babenko and Andrei Tchernykh
title:
Digital Filter Architecture Based on Modified Winograd Method F(2$ times $ 2, 5$ times $ 5) and Residue Number System

keywords:
Computer architecture; digital filter; digital signal processing; field-programmable gate array; Filtering; Filtering algorithms; Finite impulse response filters; Hardware; IIR filters; Performance evaluation; Residue number system; Winograd method

rawtitle:
Digital Filter Architecture Based on Modified {Winograd} Method F(2$ \times $ 2, 5$ \times $ 5) and Residue Number System

entry:
@Article{Valuev:2023:DFA,
  author =       "Georgii Valuev and Maria Valueva and Mikhail Babenko
                 and Andrei Tchernykh",
  title =        "Digital Filter Architecture Based on Modified
                 {Winograd} Method F(2$ \times $ 2, 5$ \times $ 5) and
                 Residue Number System",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  pages =        "26807--26819",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3258689",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:08:36 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Computer architecture; digital filter; digital signal
                 processing; field-programmable gate array; Filtering;
                 Filtering algorithms; Finite impulse response filters;
                 Hardware; IIR filters; Performance evaluation; Residue
                 number system; Winograd method",
}


bibtype: article
filename: fparith.bib
label: Venkataramanaiah:2023:NBF
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 58
number: 7
pages: 1885--1897
year: 2023
CODEN: IJSCBC
DOI: https://doi.org/10.1109/JSSC.2023.3269148
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
author:
Shreyas Kolala Venkataramanaiah and Jian Meng and Han-Sok Suh and Injune Yeo and Jyotishman Saikia and Sai Kiran Cherupally and Yichi Zhang and Zhiru Zhang and Jae-Sun Seo

title:
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity

keywords:
Activation sparsity; CNNs; Convolution; convolutional neural network (CNN) training processor; Convolutional neural networks; Energy efficiency; energy-efficient accelerator; Hardware; Memory management; Random access memory; Training; weight sparsity (WS)

rawauthor:
Shreyas Kolala Venkataramanaiah and Jian Meng and Han-Sok Suh and Injune Yeo and Jyotishman Saikia and Sai Kiran Cherupally and Yichi Zhang and Zhiru Zhang and Jae-Sun Seo

rawtitle:
A 28-nm 8-bit Floating-Point {Tensor Core}-Based Programmable {CNN} Training Processor With Dynamic Structured Sparsity

entry:
@Article{Venkataramanaiah:2023:NBF,
  author =       "Shreyas Kolala Venkataramanaiah and Jian Meng and
                 Han-Sok Suh and Injune Yeo and Jyotishman Saikia and
                 Sai Kiran Cherupally and Yichi Zhang and Zhiru Zhang
                 and Jae-Sun Seo",
  title =        "A 28-nm 8-bit Floating-Point {Tensor Core}-Based
                 Programmable {CNN} Training Processor With Dynamic
                 Structured Sparsity",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "58",
  number =       "7",
  pages =        "1885--1897",
  year =         "2023",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2023.3269148",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "Activation sparsity; CNNs; Convolution; convolutional
                 neural network (CNN) training processor; Convolutional
                 neural networks; Energy efficiency; energy-efficient
                 accelerator; Hardware; Memory management; Random access
                 memory; Training; weight sparsity (WS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Vollmer:2023:UHA
author: Morgane Vollmer and Karim Bigou and Arnaud Tisserand
title: Using Hierarchical Approach to Speed-up RNS Base Extensions in Homomorphic Encryption Context
crossref: IEEE:2023:PIS
pages: 84--87
year: 2023
DOI: https://doi.org/10.1109/ARITH58626.2023.00030
bibdate: Wed May 8 09:17:31 2024
bibtimestamp: 2024.05.08 09:17:31 ???
acknowledgement: ack-nhfb
rawauthor: Morgane Vollmer and Karim Bigou and Arnaud Tisserand
rawtitle: Using Hierarchical Approach to Speed-up {RNS} Base Extensions in Homomorphic Encryption Context
keywords:
ARITH 2023; ARITH-30; base extension; Costs; Digital arithmetic; homomorphic encryption; Homomorphic encryption; Multicore processing; Parallel processing; residue number system; Software; Software algorithms

entry:
@InProceedings{Vollmer:2023:UHA,
  author =       "Morgane Vollmer and Karim Bigou and Arnaud Tisserand",
  title =        "Using Hierarchical Approach to Speed-up {RNS} Base
                 Extensions in Homomorphic Encryption Context",
  crossref =     "IEEE:2023:PIS",
  pages =        "84--87",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ARITH58626.2023.00030",
  bibdate =      "Wed May 8 09:17:31 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2023; ARITH-30; base extension; Costs; Digital
                 arithmetic; homomorphic encryption; Homomorphic
                 encryption; Multicore processing; Parallel processing;
                 residue number system; Software; Software algorithms",
}


bibtype: article
filename: fparith.bib
label: Weihong:2023:SDM
author: Bi Weihong and Jin Yun and Li Jiaxin and Sun Lingling and Fu Guangwei and Jin Wa
title: In-Situ Detection Method of Jellyfish Based on Improved Faster R-CNN and FP16
journal: j-IEEE-ACCESS
volume: 11
pages: 81803--81814
year: 2023
DOI: https://doi.org/10.1109/ACCESS.2023.3300655
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Bi Weihong and Jin Yun and Li Jiaxin and Sun Lingling and Fu Guangwei and Jin Wa
rawtitle: In-Situ Detection Method of Jellyfish Based on Improved Faster {R-CNN} and {FP16}
keywords:
Aquaculture; Convolutional neural networks; Faster R-CNN; Feature extraction; FP16; in-situ detection; jellyfish; Jellyfish; Monitoring; Residual neural networks; Resnet50; Sea measurements; Sea surface; Software; Toxicology; Training

entry:
@Article{Weihong:2023:SDM,
  author =       "Bi Weihong and Jin Yun and Li Jiaxin and Sun Lingling
                 and Fu Guangwei and Jin Wa",
  title =        "In-Situ Detection Method of Jellyfish Based on
                 Improved Faster {R-CNN} and {FP16}",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  pages =        "81803--81814",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3300655",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Aquaculture; Convolutional neural networks; Faster
                 R-CNN; Feature extraction; FP16; in-situ detection;
                 jellyfish; Jellyfish; Monitoring; Residual neural
                 networks; Resnet50; Sea measurements; Sea surface;
                 Software; Toxicology; Training",
}


bibtype: manual
filename: fparith.bib
label: Whitehead:2023:FPI
author: Nathan Whitehead and Alex Fit-florea
title: Floating Point and IEEE 754 Compliance for NVIDIA GPUs
organization: NVIDIA
pages: 28
day: 24
month: aug
monthnumber: 8
year: 2023
bibdate: Mon Sep 11 07:26:37 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:26:37 ???
acknowledgement: ack-nhfb
rawauthor: Nathan Whitehead and Alex Fit-florea
rawtitle: Floating Point and {IEEE 754} Compliance for {NVIDIA GPUs}
URL:
https://docs.nvidia.com/cuda/floating-point/; https://docs.nvidia.com/cuda/pdf/Floating_Point_on_NVIDIA_GPU.pdf

abstract:
A number of issues related to floating point accuracy and compliance are a frequent source of confusion on both CPUs and GPUs. The purpose of this white paper is to discuss the most common issues related to NVIDIA GPUs and to supplement the documentation in the CUDA C++ Programming Guide

TOC:
1 Floating Point / 3 1.1 Formats / 3 1.2 Operations and Accuracy / 4 1.3 The Fused Multiply-Add (FMA) / 5 2 Dot Product: An Accuracy Example / 7 2.1 Example Algorithms / 7 2.2 Comparison / 8 3 CUDA and Floating Point / 9 3.1 Compute Capability 2.0 and Above / 9 3.2 Rounding Modes / 9 3.3 Controlling Fused Multiply-add / 10 3.4 Compiler Flags / 11 3.5 Differences from x86 / 11 4 Considerations for a Heterogeneous World / 13 4.1 Mathematical Function Accuracy / 13 4.2 x87 and SSE / 14 4.3 Core Counts / 14 4.4 Verifying GPU Results / 14 5 Concrete Recommendations / 17 6 Acknowledgements / 19 7 References / 21 8 Notices / 23 8.1 Notice / 23 8.2 OpenCL / 24 8.3 Trademarks / 24

rawabstract:
A number of issues related to floating point accuracy and compliance are a frequent source of confusion on both CPUs and GPUs. The purpose of this white paper is to discuss the most common issues related to NVIDIA GPUs and to supplement the documentation in the CUDA C++ Programming Guide

rawTOC:
1 Floating Point / 3 \\ 1.1 Formats / 3 \\ 1.2 Operations and Accuracy / 4 \\ 1.3 The Fused Multiply-Add (FMA) / 5 \\ 2 Dot Product: An Accuracy Example / 7 \\ 2.1 Example Algorithms / 7 \\ 2.2 Comparison / 8 \\ 3 CUDA and Floating Point / 9 \\ 3.1 Compute Capability 2.0 and Above / 9 \\ 3.2 Rounding Modes / 9 \\ 3.3 Controlling Fused Multiply-add / 10 \\ 3.4 Compiler Flags / 11 \\ 3.5 Differences from x86 / 11 \\ 4 Considerations for a Heterogeneous World / 13 \\ 4.1 Mathematical Function Accuracy / 13 \\ 4.2 x87 and SSE / 14 \\ 4.3 Core Counts / 14 \\ 4.4 Verifying GPU Results / 14 \\ 5 Concrete Recommendations / 17 \\ 6 Acknowledgements / 19 \\ 7 References / 21 \\ 8 Notices / 23 \\ 8.1 Notice / 23 \\ 8.2 OpenCL / 24 \\ 8.3 Trademarks / 24

entry:
@Manual{Whitehead:2023:FPI,
  author =       "Nathan Whitehead and Alex Fit-florea",
  title =        "Floating Point and {IEEE 754} Compliance for {NVIDIA
                 GPUs}",
  organization = "NVIDIA",
  address =      "????",
  pages =        "28",
  day =          "24",
  month =        aug,
  year =         "2023",
  bibdate =      "Mon Sep 11 07:26:37 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://docs.nvidia.com/cuda/floating-point/;
                 https://docs.nvidia.com/cuda/pdf/Floating_Point_on_NVIDIA_GPU.pdf",
  abstract =     "A number of issues related to floating point accuracy
                 and compliance are a frequent source of confusion on
                 both CPUs and GPUs. The purpose of this white paper is
                 to discuss the most common issues related to NVIDIA
                 GPUs and to supplement the documentation in the CUDA
                 C++ Programming Guide",
  acknowledgement = ack-nhfb,
  tableofcontents = "1 Floating Point / 3 \\
                 1.1 Formats / 3 \\
                 1.2 Operations and Accuracy / 4 \\
                 1.3 The Fused Multiply-Add (FMA) / 5 \\
                 2 Dot Product: An Accuracy Example / 7 \\
                 2.1 Example Algorithms / 7 \\
                 2.2 Comparison / 8 \\
                 3 CUDA and Floating Point / 9 \\
                 3.1 Compute Capability 2.0 and Above / 9 \\
                 3.2 Rounding Modes / 9 \\
                 3.3 Controlling Fused Multiply-add / 10 \\
                 3.4 Compiler Flags / 11 \\
                 3.5 Differences from x86 / 11 \\
                 4 Considerations for a Heterogeneous World / 13 \\
                 4.1 Mathematical Function Accuracy / 13 \\
                 4.2 x87 and SSE / 14 \\
                 4.3 Core Counts / 14 \\
                 4.4 Verifying GPU Results / 14 \\
                 5 Concrete Recommendations / 17 \\
                 6 Acknowledgements / 19 \\
                 7 References / 21 \\
                 8 Notices / 23 \\
                 8.1 Notice / 23 \\
                 8.2 OpenCL / 24 \\
                 8.3 Trademarks / 24",
}


bibtype: book
filename: fparith.bib
label: Wilkinson:2023:REA
author: J. H. (James Hardy) Wilkinson
title: Rounding Errors in Algebraic Processes
volume: 89
publisher: pub-SIAM
address: pub-SIAM:adr
pages: xiii + 161
year: 2023
ISBN: 1-61197-751-7 OR 1611977517
ISBN13: 978-1-61197-751-6 OR 9781611977516
LCCN: QA275 .W64 2023
bibdate: Wed Aug 7 17:00:33 MDT 2024
bibtimestamp: 2024.08.07 17:00:33 MDT
note: New foreword by N. J. Higham.
series: Classics in applied mathematics
subject: Roundoff errors; Erreurs d'arrondi; Roundoff errors
TOC: The fundamental arithmetic operations Computations involving polynomials Matrix computations
acknowledgement: ack-nhfb
authordates: James H. Wilkinson (27 September 1919--5 October 1986)
rawauthor: J. H. (James Hardy) Wilkinson
rawnote: New foreword by N. J. Higham.
rawtitle: Rounding Errors in Algebraic Processes
rawTOC: The fundamental arithmetic operations \\ Computations involving polynomials \\ Matrix computations
bibsource:
fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/bibnet/authors/w/wilkinson-james-hardy.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
booktitle Rounding Errors in Algebraic Processes was the first book to give systematic analyses of the effects of rounding errors on a variety of key computations involving polynomials and matrices. A detailed analysis is given of the rounding errors made in the elementary arithmetic operations and inner products, for both floating-point arithmetic and fixed-point arithmetic. The results are then applied in the error analyses of a variety of computations involving polynomials as well as the solution of linear systems, matrix inversion, and eigenvalue computations. The conditioning of these problems is investigated. The aim was to provide a unified method of treatment, and emphasis is placed on the underlying concepts.

remark:
``ldots a republication originally published by Her Majesty's Stationery Office under British Crown copyright in 1963''-- title page verso.

rawabstract:
\booktitle{Rounding Errors in Algebraic Processes} was the first book to give systematic analyses of the effects of rounding errors on a variety of key computations involving polynomials and matrices. A detailed analysis is given of the rounding errors made in the elementary arithmetic operations and inner products, for both floating-point arithmetic and fixed-point arithmetic. The results are then applied in the error analyses of a variety of computations involving polynomials as well as the solution of linear systems, matrix inversion, and eigenvalue computations. The conditioning of these problems is investigated. The aim was to provide a unified method of treatment, and emphasis is placed on the underlying concepts.

entry:
@Book{Wilkinson:2023:REA,
  author =       "J. H. (James Hardy) Wilkinson",
  title =        "Rounding Errors in Algebraic Processes",
  volume =       "89",
  publisher =    pub-SIAM,
  address =      pub-SIAM:adr,
  pages =        "xiii + 161",
  year =         "2023",
  ISBN =         "1-61197-751-7",
  ISBN-13 =      "978-1-61197-751-6",
  LCCN =         "QA275 .W64 2023",
  bibdate =      "Wed Aug 7 17:00:33 MDT 2024",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/w/wilkinson-james-hardy.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "New foreword by N. J. Higham.",
  series =       "Classics in applied mathematics",
  abstract =     "\booktitle{Rounding Errors in Algebraic Processes} was
                 the first book to give systematic analyses of the
                 effects of rounding errors on a variety of key
                 computations involving polynomials and matrices. A
                 detailed analysis is given of the rounding errors made
                 in the elementary arithmetic operations and inner
                 products, for both floating-point arithmetic and
                 fixed-point arithmetic. The results are then applied in
                 the error analyses of a variety of computations
                 involving polynomials as well as the solution of linear
                 systems, matrix inversion, and eigenvalue computations.
                 The conditioning of these problems is investigated. The
                 aim was to provide a unified method of treatment, and
                 emphasis is placed on the underlying concepts.",
  acknowledgement = ack-nhfb,
  author-dates = "James H. Wilkinson (27 September 1919--5 October
                 1986)",
  remark =       "``\ldots{}a republication originally published by Her
                 Majesty's Stationery Office under British Crown
                 copyright in 1963''-- title page verso.",
  subject =      "Roundoff errors; Erreurs d'arrondi; Roundoff errors",
  tableofcontents = "The fundamental arithmetic operations \\
                 Computations involving polynomials \\
                 Matrix computations",
}


bibtype: article
filename: fparith.bib
label: Wong:2023:KNS
journal: j-IEEE-TRANS-COMPUT
volume: 72
number: 7
pages: 1830--1842
month: jul
monthnumber: 7
year: 2023
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3238129
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 1 10:59:22 2023
bibtimestamp: 2023.07.01 10:59:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
author:
Zheng-Yan Wong and Denis C.-K. Wong and Wai-Kong Lee and Kai-Ming Mok and Wun-She Yap and Ayesha Khalid

title:
KaratSaber: New Speed Records for Saber Polynomial Multiplication Using Efficient Karatsuba FPGA Architecture

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

rawauthor:
Zheng-Yan Wong and Denis C.-K. Wong and Wai-Kong Lee and Kai-Ming Mok and Wun-She Yap and Ayesha Khalid

rawtitle:
{KaratSaber}: New Speed Records for {Saber} Polynomial Multiplication Using Efficient {Karatsuba} {FPGA} Architecture

entry:
@Article{Wong:2023:KNS,
  author =       "Zheng-Yan Wong and Denis C.-K. Wong and Wai-Kong Lee
                 and Kai-Ming Mok and Wun-She Yap and Ayesha Khalid",
  title =        "{KaratSaber}: New Speed Records for {Saber} Polynomial
                 Multiplication Using Efficient {Karatsuba} {FPGA}
                 Architecture",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "7",
  pages =        "1830--1842",
  month =        jul,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3238129",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 1 10:59:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Yang:2023:ATF
author: Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and Yuan-Ming Chang and Jenq-Kuen Lee
title: Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension
journal: j-TODAES
volume: 28
number: 3
pages: 33:1--33:??
month: may
monthnumber: 5
year: 2023
CODEN: ATASFO
DOI: https://doi.org/10.1145/3569939
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Wed May 17 08:06:20 MDT 2023
bibtimestamp: 2023.05.17 08:06:20 MDT
URL: https://dl.acm.org/doi/10.1145/3569939
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
articleno: 33
journalURL: https://dl.acm.org/loi/todaes
rawauthor: Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and Yuan-Ming Chang and Jenq-Kuen Lee
rawtitle: Auto-tuning Fixed-point Precision with {TVM} on {RISC-V} Packed {SIMD} Extension
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib

abstract:
Today, as deep learning (DL) is applied more often in daily life, dedicated processors such as CPUs and GPUs have become very important for accelerating model executions. With the growth of technology, people are becoming accustomed to using edge devices, such as mobile phones, smart watches, and VR devices in their daily lives. A variety of technologies using DL are gradually being applied to these edge devices. However, there is a large number of computations in DL. It faces a challenging problem how to provide solutions in the edge devices. In this article, the proposed method enables a flow with the RISC-V Packed extension (P extension) in TVM. TVM, an open deep learning compiler for neural network models, is growing as a key infrastructure for DL computing. RISC-V is an open instruction set architecture (ISA) with customized and flexible features. The Packed-SIMD extension is a RISC-V extension that enables subword single-instruction multiple-data (SIMD) computations in RISC-V architectures to support fallback engines in AI computing. In the proposed flow, a fixed-point type that is supported by an integer of 16-bit type and saturation instructions is added to replace the original 32-bit float type. In addition, an auto-tuning method is proposed to use a uniform selector mechanism (USM) to find the binary point position for fixed-point type use. The tensorization feature of TVM can be used to optimize specific hardware such as subword SIMD instructions with RISC-V P extension. With our experiment on the Spike simulator, the proposed method with the USM can improve performance by approximately 2.54 to 6.15$ times $ in terms of instruction counts with little accuracy loss.

rawabstract:
Today, as deep learning (DL) is applied more often in daily life, dedicated processors such as CPUs and GPUs have become very important for accelerating model executions. With the growth of technology, people are becoming accustomed to using edge devices, such as mobile phones, smart watches, and VR devices in their daily lives. A variety of technologies using DL are gradually being applied to these edge devices. However, there is a large number of computations in DL. It faces a challenging problem how to provide solutions in the edge devices. In this article, the proposed method enables a flow with the RISC-V Packed extension (P extension) in TVM. TVM, an open deep learning compiler for neural network models, is growing as a key infrastructure for DL computing. RISC-V is an open instruction set architecture (ISA) with customized and flexible features. The Packed-SIMD extension is a RISC-V extension that enables subword single-instruction multiple-data (SIMD) computations in RISC-V architectures to support fallback engines in AI computing. In the proposed flow, a fixed-point type that is supported by an integer of 16-bit type and saturation instructions is added to replace the original 32-bit float type. In addition, an auto-tuning method is proposed to use a uniform selector mechanism (USM) to find the binary point position for fixed-point type use. The tensorization feature of TVM can be used to optimize specific hardware such as subword SIMD instructions with RISC-V P extension. With our experiment on the Spike simulator, the proposed method with the USM can improve performance by approximately 2.54 to 6.15$ \times $ in terms of instruction counts with little accuracy loss.

entry:
@Article{Yang:2023:ATF,
  author =       "Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and
                 Yuan-Ming Chang and Jenq-Kuen Lee",
  title =        "Auto-tuning Fixed-point Precision with {TVM} on
                 {RISC-V} Packed {SIMD} Extension",
  journal =      j-TODAES,
  volume =       "28",
  number =       "3",
  pages =        "33:1--33:??",
  month =        may,
  year =         "2023",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3569939",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Wed May 17 08:06:20 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3569939",
  abstract =     "Today, as deep learning (DL) is applied more often in
                 daily life, dedicated processors such as CPUs and GPUs
                 have become very important for accelerating model
                 executions. With the growth of technology, people are
                 becoming accustomed to using edge devices, such as
                 mobile phones, smart watches, and VR devices in their
                 daily lives. A variety of technologies using DL are
                 gradually being applied to these edge devices. However,
                 there is a large number of computations in DL. It faces
                 a challenging problem how to provide solutions in the
                 edge devices. In this article, the proposed method
                 enables a flow with the RISC-V Packed extension (P
                 extension) in TVM. TVM, an open deep learning compiler
                 for neural network models, is growing as a key
                 infrastructure for DL computing. RISC-V is an open
                 instruction set architecture (ISA) with customized and
                 flexible features. The Packed-SIMD extension is a
                 RISC-V extension that enables subword
                 single-instruction multiple-data (SIMD) computations in
                 RISC-V architectures to support fallback engines in AI
                 computing. In the proposed flow, a fixed-point type
                 that is supported by an integer of 16-bit type and
                 saturation instructions is added to replace the
                 original 32-bit float type. In addition, an auto-tuning
                 method is proposed to use a uniform selector mechanism
                 (USM) to find the binary point position for fixed-point
                 type use. The tensorization feature of TVM can be used
                 to optimize specific hardware such as subword SIMD
                 instructions with RISC-V P extension. With our
                 experiment on the Spike simulator, the proposed method
                 with the USM can improve performance by approximately
                 2.54 to 6.15$ \times $ in terms of instruction counts
                 with little accuracy loss.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}


bibtype: article
filename: fparith.bib
label: Zhang:2023:EAP
author: Hao Zhang and Seok-Bum Ko
title: Efficient Approximate Posit Multipliers for Deep Learning Computation
journal: j-IEEE-J-EMERG-SEL-TOP-CIRCUITS-SYST
volume: 13
number: 1
pages: 201--211
year: 2023
DOI: https://doi.org/10.1109/JETCAS.2022.3231642
ISSN: 2156-3357 (print), 2156-3365 (electronic) OR 21563357 (print), 21563365 (electronic)
ISSNL: 2156-3357 OR 21563357
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5503868
rawauthor: Hao Zhang and Seok-Bum Ko
rawtitle: Efficient Approximate Posit Multipliers for Deep Learning Computation
entry:
@Article{Zhang:2023:EAP,
  author =       "Hao Zhang and Seok-Bum Ko",
  title =        "Efficient Approximate Posit Multipliers for Deep
                 Learning Computation",
  journal =      j-IEEE-J-EMERG-SEL-TOP-CIRCUITS-SYST,
  volume =       "13",
  number =       "1",
  pages =        "201--211",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/JETCAS.2022.3231642",
  ISSN =         "2156-3357 (print), 2156-3365 (electronic)",
  ISSN-L =       "2156-3357",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal on Emerging and Selected Topics in
                 Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5503868",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhuang:2023:HPL
author: Jinming Zhuang and Zhuoping Yang and Peipei Zhou
booktitle: 2023 60th ACM/IEEE Design Automation Conference (DAC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2023
DOI: https://doi.org/10.1109/DAC56929.2023.10247981
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Jinming Zhuang and Zhuoping Yang and Peipei Zhou
rawbooktitle: {2023 60th ACM/IEEE Design Automation Conference (DAC)}
title:
High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives

keywords:
Complexity theory; Computational modeling; Computer architecture; Design automation; Design methodology; Energy efficiency; heterogeneous system-on-chip; matrix multiply; support for multiple data types; Throughput; Versal ACAP

rawtitle:
High Performance, Low Power Matrix Multiply Design on {ACAP}: from Architecture, Design Challenges and {DSE} Perspectives

entry:
@InProceedings{Zhuang:2023:HPL,
  author =       "Jinming Zhuang and Zhuoping Yang and Peipei Zhou",
  booktitle =    "{2023 60th ACM/IEEE Design Automation Conference
                 (DAC)}",
  title =        "High Performance, Low Power Matrix Multiply Design on
                 {ACAP}: from Architecture, Design Challenges and {DSE}
                 Perspectives",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DAC56929.2023.10247981",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Complexity theory; Computational modeling; Computer
                 architecture; Design automation; Design methodology;
                 Energy efficiency; heterogeneous system-on-chip; matrix
                 multiply; support for multiple data types; Throughput;
                 Versal ACAP",
}


bibtype: article
filename: fparith.bib
label: Zlatopolski:2023:PAV
author: Dmitry Zlatopolski
title: ``Perfect Arithmetic'' by Vaclav Josef Pelikan
journal: j-HIST-MATH
volume: 62
pages: 40--50
month: feb
monthnumber: 2
year: 2023
CODEN: HIMADS
DOI: https://doi.org/10.1016/j.hm.2022.09.002
ISSN: 0315-0860 (print), 1090-249X (electronic) OR 03150860 (print), 1090249X (electronic)
ISSNL: 0315-0860 OR 03150860
bibdate: Wed Mar 15 09:40:56 MDT 2023
bibtimestamp: 2023.03.15 09:40:56 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0315086022000659
fjournal: Historia Mathematica
keywords: base conversion; binary arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03150860
rawauthor: Dmitry Zlatopolski
rawtitle: {``Perfect Arithmetic'' by Vaclav Josef Pelikan}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histmath.bib

abstract:
The present article describes for the first time the book of Vaclav Josef Pelikan titled booktitle Arithmeticus Perfectus Qui tria numerare nescit. Seu Arithmetica dualis, In qua Numerando non proceditur, nisi ad duo, & tamen omnes quaestiones Arithmeticae negotio facili enodari possunt, published in Prague in 1712. The book is written in Latin on 86 pages and consists of a dedication, a message to the reader and four chapters. Operations in the binary system, including the extraction of square and cube roots, methods of converting numbers from the decimal system to the binary system and vice versa, etc., are given. In general, we may say that the book by Vaclav Josef Pelikan is the first fully fledged and methodologically sound textbook of arithmetic using the binary number system as well as containing original methods of solution.

rawabstract:
The present article describes for the first time the book of Vaclav Josef Pelikan titled \booktitle{Arithmeticus Perfectus Qui tria numerare nescit. Seu Arithmetica dualis, In qua Numerando non proceditur, nisi ad duo, \& tamen omnes quaestiones Arithmeticae negotio facili enodari possunt}, published in Prague in 1712. The book is written in Latin on 86 pages and consists of a dedication, a message to the reader and four chapters. Operations in the binary system, including the extraction of square and cube roots, methods of converting numbers from the decimal system to the binary system and vice versa, etc., are given. In general, we may say that the book by Vaclav Josef Pelikan is the first fully fledged and methodologically sound textbook of arithmetic using the binary number system as well as containing original methods of solution.

entry:
@Article{Zlatopolski:2023:PAV,
  author =       "Dmitry Zlatopolski",
  title =        "{``Perfect Arithmetic'' by Vaclav Josef Pelikan}",
  journal =      j-HIST-MATH,
  volume =       "62",
  number =       "??",
  pages =        "40--50",
  month =        feb,
  year =         "2023",
  CODEN =        "HIMADS",
  DOI =          "https://doi.org/10.1016/j.hm.2022.09.002",
  ISSN =         "0315-0860 (print), 1090-249X (electronic)",
  ISSN-L =       "0315-0860",
  bibdate =      "Wed Mar 15 09:40:56 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histmath.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0315086022000659",
  abstract =     "The present article describes for the first time the
                 book of Vaclav Josef Pelikan titled
                 \booktitle{Arithmeticus Perfectus Qui tria numerare
                 nescit. Seu Arithmetica dualis, In qua Numerando non
                 proceditur, nisi ad duo, \& tamen omnes quaestiones
                 Arithmeticae negotio facili enodari possunt}, published
                 in Prague in 1712. The book is written in Latin on 86
                 pages and consists of a dedication, a message to the
                 reader and four chapters. Operations in the binary
                 system, including the extraction of square and cube
                 roots, methods of converting numbers from the decimal
                 system to the binary system and vice versa, etc., are
                 given. In general, we may say that the book by Vaclav
                 Josef Pelikan is the first fully fledged and
                 methodologically sound textbook of arithmetic using the
                 binary number system as well as containing original
                 methods of solution.",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Mathematica",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03150860",
  keywords =     "base conversion; binary arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Aggarwal:2024:SBP
booktitle: 2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
title: Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 297--303
year: 2024
DOI: https://doi.org/10.1109/FPL64840.2024.00048
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 34th International Conference on Field-Programmable Logic and Applications (FPL)}
rawtitle: Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on {FPGAs}
author:
Shivam Aggarwal and Hans Jakob Damsgaard and Alessandro Pappalardo and Giuseppe Franco and Thomas B. Preuss er and Michaela Blott and Tulika Mitra

keywords:
Accuracy; Costs; Data models; Field programmable gate arrays; minifloats; multiply-accumulate; Neural networks; Numerical models; quantization; Quantization (signal); Resource management; Training; Transformers

rawauthor:
Shivam Aggarwal and Hans Jakob Damsgaard and Alessandro Pappalardo and Giuseppe Franco and Thomas B. Preu{\ss}er and Michaela Blott and Tulika Mitra

entry:
@InProceedings{Aggarwal:2024:SBP,
  author =       "Shivam Aggarwal and Hans Jakob Damsgaard and
                 Alessandro Pappalardo and Giuseppe Franco and Thomas B.
                 Preu{\ss}er and Michaela Blott and Tulika Mitra",
  booktitle =    "{2024 34th International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "Shedding the Bits: Pushing the Boundaries of
                 Quantization with Minifloats on {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "297--303",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/FPL64840.2024.00048",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Costs; Data models; Field programmable gate
                 arrays; minifloats; multiply-accumulate; Neural
                 networks; Numerical models; quantization; Quantization
                 (signal); Resource management; Training; Transformers",
}


bibtype: inproceedings
filename: fparith.bib
label: Ahmadpour:2024:MMM
author: Zabihollah Ahmadpour and Ghassem Jaberipur and Jeong-A Lee
title: Montgomery Modular Multiplication via Single-Base Residue Number Systems
crossref: IEEE:2024:PIS
pages: 17--23
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00013
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Zabihollah Ahmadpour and Ghassem Jaberipur and Jeong-A Lee
rawtitle: {Montgomery} Modular Multiplication via Single-Base Residue Number Systems
entry:
@InProceedings{Ahmadpour:2024:MMM,
  author =       "Zabihollah Ahmadpour and Ghassem Jaberipur and Jeong-A
                 Lee",
  title =        "{Montgomery} Modular Multiplication via Single-Base
                 Residue Number Systems",
  crossref =     "IEEE:2024:PIS",
  pages =        "17--23",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00013",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: book
filename: fparith.bib
label: Alsuhli:2024:NSD
title: Number Systems for Deep Neural Network Architectures
publisher: pub-SV
address: pub-SV:adr
pages: 17--23
year: 2024
DOI: https://doi.org/10.1007/978-3-031-38133-1
ISBN: 3-031-38133-5 OR 3031381335
ISBN13: 978-3-031-38133-1 OR 9783031381331
ISSN: 2690-0327 OR 26900327
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
series: Synthesis Lectures on Engineering, Science, and Technology
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawtitle: Number Systems for Deep Neural Network Architectures
author:
Ghada Alsuhli and Vasilis Sakellariou and Hani Saleh and Mahmoud Al-Qutayri and Baker Mohammad and Thanos Stouraitis

rawauthor:
Ghada Alsuhli and Vasilis Sakellariou and Hani Saleh and Mahmoud Al-Qutayri and Baker Mohammad and Thanos Stouraitis

entry:
@Book{Alsuhli:2024:NSD,
  author =       "Ghada Alsuhli and Vasilis Sakellariou and Hani Saleh
                 and Mahmoud Al-Qutayri and Baker Mohammad and Thanos
                 Stouraitis",
  title =        "Number Systems for Deep Neural Network Architectures",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  year =         "2024",
  DOI =          "https://doi.org/10.1007/978-3-031-38133-1",
  ISBN =         "3-031-38133-5",
  ISBN-13 =      "978-3-031-38133-1",
  ISSN =         "2690-0327",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Synthesis Lectures on Engineering, Science, and
                 Technology",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Angioli:2024:DIE
title: Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 7
pages: 1767--1779
month: jul
monthnumber: 7
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2024.3386060
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jun 12 15:57:24 2024
bibtimestamp: 2024.06.12 15:57:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
author:
Marco Angioli and Marcello Barbirotta and Abdallah Cheikh and Antonio Mastrandrea and Francesco Menichelli and Saeid Jamili and Mauro Olivieri

keywords:
Benchmark testing; Clocks; computer arithmetic; Field programmable gate arrays; Frequency conversion; Hardware; high-speed arithmetic; integer division; low-power design; real-time and embedded systems; Registers; Signal processing algorithms; Variable-latency divider

rawauthor:
Marco Angioli and Marcello Barbirotta and Abdallah Cheikh and Antonio Mastrandrea and Francesco Menichelli and Saeid Jamili and Mauro Olivieri

entry:
@Article{Angioli:2024:DIE,
  author =       "Marco Angioli and Marcello Barbirotta and Abdallah
                 Cheikh and Antonio Mastrandrea and Francesco Menichelli
                 and Saeid Jamili and Mauro Olivieri",
  title =        "Design, Implementation and Evaluation of a New
                 Variable Latency Integer Division Scheme",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "7",
  pages =        "1767--1779",
  month =        jul,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2024.3386060",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jun 12 15:57:24 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Benchmark testing; Clocks; computer arithmetic; Field
                 programmable gate arrays; Frequency conversion;
                 Hardware; high-speed arithmetic; integer division;
                 low-power design; real-time and embedded systems;
                 Registers; Signal processing algorithms;
                 Variable-latency divider",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:CP
author: Anonymous
title: [Copyright page]
crossref: IEEE:2024:PIS
pages: 4--4
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00003
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {[Copyright} page]
entry:
@InProceedings{Anonymous:2024:CP,
  author =       "Anonymous",
  title =        "{[Copyright} page]",
  crossref =     "IEEE:2024:PIS",
  pages =        "4--4",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00003",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:OCA
author: Anonymous
title: Organizing Committee: ARITH 2024
crossref: IEEE:2024:PIS
pages: 10--10
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00006
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Organizing Committee: ARITH 2024}
entry:
@InProceedings{Anonymous:2024:OCA,
  author =       "Anonymous",
  title =        "{Organizing Committee: ARITH 2024}",
  crossref =     "IEEE:2024:PIS",
  pages =        "10--10",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00006",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:PCA
author: Anonymous
title: Program Committee: ARITH 2024
crossref: IEEE:2024:PIS
pages: 11--11
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00007
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Program Committee: ARITH 2024}
entry:
@InProceedings{Anonymous:2024:PCA,
  author =       "Anonymous",
  title =        "{Program Committee: ARITH 2024}",
  crossref =     "IEEE:2024:PIS",
  pages =        "11--11",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00007",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:RLA
author: Anonymous
title: Reviewers List: ARITH 2024
crossref: IEEE:2024:PIS
pages: 14--15
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00009
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Reviewers List: ARITH 2024}
entry:
@InProceedings{Anonymous:2024:RLA,
  author =       "Anonymous",
  title =        "{Reviewers List: ARITH 2024}",
  crossref =     "IEEE:2024:PIS",
  pages =        "14--15",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00009",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:SA
author: Anonymous
title: Sponsors: ARITH 2024
crossref: IEEE:2024:PIS
pages: 16--17
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00010
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Sponsors: ARITH 2024}
entry:
@InProceedings{Anonymous:2024:SA,
  author =       "Anonymous",
  title =        "{Sponsors: ARITH 2024}",
  crossref =     "IEEE:2024:PIS",
  pages =        "16--17",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00010",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:SCA
author: Anonymous
title: Steering Committee: ARITH 2024
crossref: IEEE:2024:PIS
pages: 12--13
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00008
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {Steering Committee: ARITH 2024}
entry:
@InProceedings{Anonymous:2024:SCA,
  author =       "Anonymous",
  title =        "{Steering Committee: ARITH 2024}",
  crossref =     "IEEE:2024:PIS",
  pages =        "12--13",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00008",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:TPa
author: Anonymous
title: [Title page 1]
crossref: IEEE:2024:PIS
pages: 1--1
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00001
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {[Title} page 1]
entry:
@InProceedings{Anonymous:2024:TPa,
  author =       "Anonymous",
  title =        "{[Title} page 1]",
  crossref =     "IEEE:2024:PIS",
  pages =        "1--1",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00001",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2024:TPb
author: Anonymous
title: [Title page 2]
crossref: IEEE:2024:PIS
pages: 3--3
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00002
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: {[Title} page 2]
entry:
@InProceedings{Anonymous:2024:TPb,
  author =       "Anonymous",
  title =        "{[Title} page 2]",
  crossref =     "IEEE:2024:PIS",
  pages =        "3--3",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00002",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: article
filename: fparith.bib
label: Aonishi:2024:HVF
title: Highly Versatile FPGA-Implemented Cyber Coherent Ising Machine
journal: j-IEEE-ACCESS
volume: 12
pages: 175843--175865
year: 2024
DOI: https://doi.org/10.1109/ACCESS.2024.3504008
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawtitle: Highly Versatile {FPGA}-Implemented {Cyber Coherent Ising Machine}
author:
Toru Aonishi and Tatsuya Nagasawa and Toshiyuki Koizumi and Mastiyage Don Sudeera Hasaranga Gunathilaka and Kazushi Mimura and Masato Okada and Satoshi Kako and Yoshihisa Yamamoto

keywords:
Bifurcation; Coherent Ising machine; combinatorial optimization; compressed sensing; Computational modeling; Computer architecture; Couplings; Field programmable gate arrays; FPGA; Integrated circuit modeling; Jacobian matrices; Mathematical models; Multiaccess communication; Optimization; versatile architecture

rawauthor:
Toru Aonishi and Tatsuya Nagasawa and Toshiyuki Koizumi and Mastiyage Don Sudeera Hasaranga Gunathilaka and Kazushi Mimura and Masato Okada and Satoshi Kako and Yoshihisa Yamamoto

entry:
@Article{Aonishi:2024:HVF,
  author =       "Toru Aonishi and Tatsuya Nagasawa and Toshiyuki
                 Koizumi and Mastiyage Don Sudeera Hasaranga Gunathilaka
                 and Kazushi Mimura and Masato Okada and Satoshi Kako
                 and Yoshihisa Yamamoto",
  title =        "Highly Versatile {FPGA}-Implemented {Cyber Coherent
                 Ising Machine}",
  journal =      j-IEEE-ACCESS,
  volume =       "12",
  pages =        "175843--175865",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ACCESS.2024.3504008",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Bifurcation; Coherent Ising machine; combinatorial
                 optimization; compressed sensing; Computational
                 modeling; Computer architecture; Couplings; Field
                 programmable gate arrays; FPGA; Integrated circuit
                 modeling; Jacobian matrices; Mathematical models;
                 Multiaccess communication; Optimization; versatile
                 architecture",
}


bibtype: inproceedings
filename: fparith.bib
label: Arzelier:2024:REA
author: Denis Arzelier and Florent Brehard and Mioara Joldes and Marc Mezzarobba
title: Rounding Error Analysis of an Orbital Collision Probability Evaluation Algorithm
crossref: IEEE:2024:PIS
pages: 96--103
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00025
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Denis Arzelier and Florent Br{\'e}hard and Mioara Joldes and Marc Mezzarobba
rawtitle: Rounding Error Analysis of an Orbital Collision Probability Evaluation Algorithm
entry:
@InProceedings{Arzelier:2024:REA,
  author =       "Denis Arzelier and Florent Br{\'e}hard and Mioara
                 Joldes and Marc Mezzarobba",
  title =        "Rounding Error Analysis of an Orbital Collision
                 Probability Evaluation Algorithm",
  crossref =     "IEEE:2024:PIS",
  pages =        "96--103",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00025",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: article
filename: fparith.bib
label: Bandil:2024:HIU
author: Lalit Bandil and Bal Chand Nagar
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 12
pages: 2734--2746
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2024.3457731
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Nov 20 07:36:48 2024
bibtimestamp: 2024.11.20 07:36:48 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Lalit Bandil and Bal Chand Nagar
title:
Hardware Implementation of Unsigned Approximate Hybrid Square Rooters for Error-Resilient Applications

keywords:
Accuracy; accuracy metrics; Approximate computing; Arithmetic; Computers; Hardware; hardware implementation; image processing; Image restoration; low power; Measurement; Multiplexing; square rooter

rawtitle:
Hardware Implementation of Unsigned Approximate Hybrid Square Rooters for Error-Resilient Applications

entry:
@Article{Bandil:2024:HIU,
  author =       "Lalit Bandil and Bal Chand Nagar",
  title =        "Hardware Implementation of Unsigned Approximate Hybrid
                 Square Rooters for Error-Resilient Applications",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "12",
  pages =        "2734--2746",
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2024.3457731",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Nov 20 07:36:48 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Accuracy; accuracy metrics; Approximate computing;
                 Arithmetic; Computers; Hardware; hardware
                 implementation; image processing; Image restoration;
                 low power; Measurement; Multiplexing; square rooter",
}


bibtype: inproceedings
filename: fparith.bib
label: Basavaraju:2024:EHA
author: Mahati Basavaraju and Vinay Rayapati and Madhav Rao
booktitle: 2024 25th International Symposium on Quality Electronic Design (ISQED)
title: Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--8
year: 2024
DOI: https://doi.org/10.1109/ISQED60706.2024.10528686
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Mahati Basavaraju and Vinay Rayapati and Madhav Rao
rawbooktitle: {2024 25th International Symposium on Quality Electronic Design (ISQED)}
rawtitle: Exploring Hardware Activation Function Design: {CORDIC} Architecture in Diverse Floating Formats
keywords:
Activation Function; Artificial neural networks; BFloat; Computer architecture; CORDIC; Costs; Data Representation; Floating Point; Focusing; Hardware; Libraries; Measurement; Neural networks; POSIT; Sigmoid; Softmax; Tanh; TensorFloat

entry:
@InProceedings{Basavaraju:2024:EHA,
  author =       "Mahati Basavaraju and Vinay Rayapati and Madhav Rao",
  booktitle =    "{2024 25th International Symposium on Quality
                 Electronic Design (ISQED)}",
  title =        "Exploring Hardware Activation Function Design:
                 {CORDIC} Architecture in Diverse Floating Formats",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ISQED60706.2024.10528686",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Activation Function; Artificial neural networks;
                 BFloat; Computer architecture; CORDIC; Costs; Data
                 Representation; Floating Point; Focusing; Hardware;
                 Libraries; Measurement; Neural networks; POSIT;
                 Sigmoid; Softmax; Tanh; TensorFloat",
}


bibtype: inproceedings
filename: fparith.bib
label: BenAli:2024:SRE
author: Sami Ben Ali and Silviu-Ioan Filip and Olivier Sentieys
booktitle: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
title: A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2024
DOI: https://doi.org/10.23919/DATE58400.2024.10546735
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Sami {Ben Ali} and Silviu-Ioan Filip and Olivier Sentieys
rawbooktitle: {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
rawtitle: A Stochastic Rounding-Enabled Low-Precision Floating-Point {MAC} for {DNN} Training
keywords:
Artificial neural networks; Computational modeling; DNN; Hardware; low-precision MAC unit; Measurement; Stochastic processes; stochastic rounding; Systolic arrays; Training

entry:
@InProceedings{BenAli:2024:SRE,
  author =       "Sami {Ben Ali} and Silviu-Ioan Filip and Olivier
                 Sentieys",
  booktitle =    "{2024 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "A Stochastic Rounding-Enabled Low-Precision
                 Floating-Point {MAC} for {DNN} Training",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2024",
  DOI =          "https://doi.org/10.23919/DATE58400.2024.10546735",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Artificial neural networks; Computational modeling;
                 DNN; Hardware; low-precision MAC unit; Measurement;
                 Stochastic processes; stochastic rounding; Systolic
                 arrays; Training",
}


bibtype: article
filename: fparith.bib
label: Benmaghnia:2024:CGN
author: Hanane Benmaghnia and Matthieu Martel and Yassamine Seladji
title: Code Generation for Neural Networks Based on Fixed-point Arithmetic
journal: j-TECS
volume: 23
number: 5
pages: 68:1--68:??
month: sep
monthnumber: 9
year: 2024
DOI: https://doi.org/10.1145/3563945
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Wed Sep 25 11:16:16 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2024.09.25 11:16:16 MDT
URL: https://dl.acm.org/doi/10.1145/3563945
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
ajournal: ACM Trans. Embed. Comput. Syst.
articleno: 68
journalURL: https://dl.acm.org/loi/tecs
rawauthor: Hanane Benmaghnia and Matthieu Martel and Yassamine Seladji
rawtitle: Code Generation for Neural Networks Based on Fixed-point Arithmetic
abstract:
Over the past few years, neural networks have started penetrating safety critical systems to make decisions as, for example, in robots, rockets, and autonomous driving cars. Neural networks based on floating-point arithmetic are very time and memory consuming, which are not compatible with embedded systems known to have limited resources. They are also very sensitive to the precision in which they have been trained, so changing this precision generally degrades the quality of their answers. To deal with that, we introduce a new technique to generate a fixed-point code for a trained neural network. This technique is based on fixed-point arithmetic with mixed-precision. This arithmetic is based on integer operations only, which are compatible with small memory devices. The obtained neural network has the same behavior as the initial one (based on the floating-point arithmetic) up to an error threshold defined by the user. The experimental results show the efficiency of our tool SyFix in terms of memory saved and the accuracy of the computations.

rawabstract:
Over the past few years, neural networks have started penetrating safety critical systems to make decisions as, for example, in robots, rockets, and autonomous driving cars. Neural networks based on floating-point arithmetic are very time and memory consuming, which are not compatible with embedded systems known to have limited resources. They are also very sensitive to the precision in which they have been trained, so changing this precision generally degrades the quality of their answers. To deal with that, we introduce a new technique to generate a fixed-point code for a trained neural network. This technique is based on fixed-point arithmetic with mixed-precision. This arithmetic is based on integer operations only, which are compatible with small memory devices. The obtained neural network has the same behavior as the initial one (based on the floating-point arithmetic) up to an error threshold defined by the user. The experimental results show the efficiency of our tool SyFix in terms of memory saved and the accuracy of the computations.

entry:
@Article{Benmaghnia:2024:CGN,
  author =       "Hanane Benmaghnia and Matthieu Martel and Yassamine
                 Seladji",
  title =        "Code Generation for Neural Networks Based on
                 Fixed-point Arithmetic",
  journal =      j-TECS,
  volume =       "23",
  number =       "5",
  pages =        "68:1--68:??",
  month =        sep,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3563945",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Wed Sep 25 11:16:16 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3563945",
  abstract =     "Over the past few years, neural networks have started
                 penetrating safety critical systems to make decisions
                 as, for example, in robots, rockets, and autonomous
                 driving cars. Neural networks based on floating-point
                 arithmetic are very time and memory consuming, which
                 are not compatible with embedded systems known to have
                 limited resources. They are also very sensitive to the
                 precision in which they have been trained, so changing
                 this precision generally degrades the quality of their
                 answers. To deal with that, we introduce a new
                 technique to generate a fixed-point code for a trained
                 neural network. This technique is based on fixed-point
                 arithmetic with mixed-precision. This arithmetic is
                 based on integer operations only, which are compatible
                 with small memory devices. The obtained neural network
                 has the same behavior as the initial one (based on the
                 floating-point arithmetic) up to an error threshold
                 defined by the user. The experimental results show the
                 efficiency of our tool SyFix in terms of memory saved
                 and the accuracy of the computations.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Embed. Comput. Syst.",
  articleno =    "68",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "https://dl.acm.org/loi/tecs",
}


bibtype: inproceedings
filename: fparith.bib
label: Bertaccini:2024:ERV
author: Luca Bertaccini and Siyuan Shen and Torsten Hoefler and Luca Benini
booktitle: 2024 IEEE 42nd International Conference on Computer Design (ICCD)
title: Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 268--275
year: 2024
DOI: https://doi.org/10.1109/ICCD63220.2024.00048
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Luca Bertaccini and Siyuan Shen and Torsten Hoefler and Luca Benini
rawbooktitle: {2024 IEEE 42nd International Conference on Computer Design (ICCD)}
rawtitle: Extending {RISC-V} for Efficient Overflow Recovery in Mixed-Precision Computations
keywords:
Artificial neural networks; Computer architecture; Dynamic range; Energy storage; floating-point; Hardware; Heuristic algorithms; Inference algorithms; Instruction sets; isa extension; Machine learning; mixed-precision computing; overflow recovery; risc-v; Training

entry:
@InProceedings{Bertaccini:2024:ERV,
  author =       "Luca Bertaccini and Siyuan Shen and Torsten Hoefler
                 and Luca Benini",
  booktitle =    "{2024 IEEE 42nd International Conference on Computer
                 Design (ICCD)}",
  title =        "Extending {RISC-V} for Efficient Overflow Recovery in
                 Mixed-Precision Computations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "268--275",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ICCD63220.2024.00048",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Artificial neural networks; Computer architecture;
                 Dynamic range; Energy storage; floating-point;
                 Hardware; Heuristic algorithms; Inference algorithms;
                 Instruction sets; isa extension; Machine learning;
                 mixed-precision computing; overflow recovery; risc-v;
                 Training",
}


bibtype: article
filename: fparith.bib
label: Bertaccini:2024:MRV
title: MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 12
number: 4
pages: 1040--1055
year: 2024
DOI: https://doi.org/10.1109/TETC.2024.3365354
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Tue Sep 9 13:42:38 2025
bibtimestamp: 2025.09.09 13:42:38 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawtitle: {MiniFloats} on {RISC-V} Cores: {ISA} Extensions With Mixed-Precision Short Dot Products
author:
Luca Bertaccini and Gianna Paulin and Matheus Cavalcante and Tim Fischer and Stefan Mach and Luca Benini

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

keywords:
Artificial neural networks; Computational modeling; Computer architecture; Dynamic range; floating-point architectures; Hardware; ISA extension; NN training; RISC-V; Stochastic processes; Training; Transprecision computing; widening dot product

rawauthor:
Luca Bertaccini and Gianna Paulin and Matheus Cavalcante and Tim Fischer and Stefan Mach and Luca Benini

entry:
@Article{Bertaccini:2024:MRV,
  author =       "Luca Bertaccini and Gianna Paulin and Matheus
                 Cavalcante and Tim Fischer and Stefan Mach and Luca
                 Benini",
  title =        "{MiniFloats} on {RISC-V} Cores: {ISA} Extensions With
                 Mixed-Precision Short Dot Products",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "12",
  number =       "4",
  pages =        "1040--1055",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/TETC.2024.3365354",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Tue Sep 9 13:42:38 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
  keywords =     "Artificial neural networks; Computational modeling;
                 Computer architecture; Dynamic range; floating-point
                 architectures; Hardware; ISA extension; NN training;
                 RISC-V; Stochastic processes; Training; Transprecision
                 computing; widening dot product",
}


bibtype: inproceedings
filename: fparith.bib
label: Bottcher:2024:SLB
author: Andreas Bottcher and Martin Kumm
title: Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
crossref: IEEE:2024:PIS
pages: 124--131
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00029
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Andreas B{\"o}ttcher and Martin Kumm
rawtitle: Small Logic-based Multipliers with Incomplete Sub-Multipliers for {FPGAs}
entry:
@InProceedings{Bottcher:2024:SLB,
  author =       "Andreas B{\"o}ttcher and Martin Kumm",
  title =        "Small Logic-based Multipliers with Incomplete
                 Sub-Multipliers for {FPGAs}",
  crossref =     "IEEE:2024:PIS",
  pages =        "124--131",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00029",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: techreport
filename: fparith.bib
label: Brisebarre:2024:CRE
author: Nicolas Brisebarre and Guillaume Hanrot and Jean-Michel Muller and Paul Zimmermann
title: Correctly-rounded evaluation of a function: why, how, and at what cost?
type: Report
number: hal-04474530
institution: CNRS --- Centre National de la Recherche Scientifique and others
address: Paris, France
pages: 29
day: 23
month: feb
monthnumber: 2
year: 2024
bibdate: Fri Feb 23 16:11:08 2024
bibtimestamp: 2024.02.23 16:11:08 ???
URL: https://hal.science/hal-04474530
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Guillaume Hanrot and Jean-Michel Muller and Paul Zimmermann
rawtitle: Correctly-rounded evaluation of a function: why, how, and at what cost?
abstract:
The goal of this paper is to convince the reader that a future standard for floating-point arithmetic should require the availability of a correctly-rounded version of a well-chosen core set of elementary functions. We discuss the interest and feasibility of this requirement. We also give answers to common objections we have received over the last 10 years.

keywords:
algorithmic number theory; approximation theory; Computer arithmetic; elementary functions; floating-point arithmetic; lattice basis reduction; LLL algorithm; standardization

rawabstract:
The goal of this paper is to convince the reader that a future standard for floating-point arithmetic should require the availability of a correctly-rounded version of a well-chosen core set of elementary functions. We discuss the interest and feasibility of this requirement. We also give answers to common objections we have received over the last 10 years.

entry:
@TechReport{Brisebarre:2024:CRE,
  author =       "Nicolas Brisebarre and Guillaume Hanrot and
                 Jean-Michel Muller and Paul Zimmermann",
  title =        "Correctly-rounded evaluation of a function: why, how,
                 and at what cost?",
  type =         "Report",
  number =       "hal-04474530",
  institution =  "CNRS --- Centre National de la Recherche Scientifique
                 and others",
  address =      "Paris, France",
  pages =        "29",
  day =          "23",
  month =        feb,
  year =         "2024",
  bibdate =      "Fri Feb 23 16:11:08 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-04474530",
  abstract =     "The goal of this paper is to convince the reader that
                 a future standard for floating-point arithmetic should
                 require the availability of a correctly-rounded version
                 of a well-chosen core set of elementary functions. We
                 discuss the interest and feasibility of this
                 requirement. We also give answers to common objections
                 we have received over the last 10 years.",
  acknowledgement = ack-nhfb,
  keywords =     "algorithmic number theory; approximation theory;
                 Computer arithmetic; elementary functions;
                 floating-point arithmetic; lattice basis reduction; LLL
                 algorithm; standardization",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2024:EUM
author: Nicolas Brisebarre and Jean-Michel Muller and Joris Picot
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 12
number: 2
pages: 656--666
year: 2024
DOI: https://doi.org/10.1109/TETC.2023.3294986
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Fri Sep 29 10:36:37 2023
bibtimestamp: 2023.09.29 10:36:37 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Nicolas Brisebarre and Jean-Michel Muller and Joris Picot
title:
Error in Ulps of the Multiplication or Division by a Correctly-Rounded Function or Constant in Binary Floating-Point Arithmetic

abstract:
Assume we use a binary floating-point arithmetic and that RN is the round-to-nearest function. Also assume that c is a constant or a real function of one or more variables, and that we have at our disposal a correctly rounded implementation of c, say c' = RN(c). For evaluating xc(resp.x / corc / x), the natural way is to replace it by RN(x.c') (resp.RN(x / c') or RN(c' / x)), that is, to call function c' and to perform a floating-point multiplication or division. This can be generalized to the approximation of n / d by RN(n' / d') and the approximation of n d by RN(n'.d'), where n' = RN(n) and d' = RN(d), and n and d are functions for which we have at our disposal a correctly rounded implementation. We discuss tight error bounds in ulps of such approximations. From our results, one immediately obtains tight error bounds for calculations such as x * pi, ln(2) / x, x / (y + z), (x + y) * z, x / sqrt(y), sqrt(x) / y, (x + y)(z + t), (x + y) / (z + t), (x + y) / (zt), etc. in floating-point arithmetic.

keywords:
Arithmetic; Blogs; correct rounding; Floating-point arithmetic; Libraries; Lips; Measurement uncertainty; multiplication by a constant; numerical error; Standards; Toy manufacturing industry; ulp

rawabstract:
Assume we use a binary floating-point arithmetic and that RN is the round-to-nearest function. Also assume that c is a constant or a real function of one or more variables, and that we have at our disposal a correctly rounded implementation of c, say c' = RN(c). For evaluating xc(resp.x / corc / x), the natural way is to replace it by RN(x.c') (resp.RN(x / c') or RN(c' / x)), that is, to call function c' and to perform a floating-point multiplication or division. This can be generalized to the approximation of n / d by RN(n' / d') and the approximation of n d by RN(n'.d'), where n' = RN(n) and d' = RN(d), and n and d are functions for which we have at our disposal a correctly rounded implementation. We discuss tight error bounds in ulps of such approximations. From our results, one immediately obtains tight error bounds for calculations such as x * pi, ln(2) / x, x / (y + z), (x + y) * z, x / sqrt(y), sqrt(x) / y, (x + y)(z + t), (x + y) / (z + t), (x + y) / (zt), etc. in floating-point arithmetic.

rawtitle:
Error in Ulps of the Multiplication or Division by a Correctly-Rounded Function or Constant in Binary Floating-Point Arithmetic

entry:
@Article{Brisebarre:2024:EUM,
  author =       "Nicolas Brisebarre and Jean-Michel Muller and Joris
                 Picot",
  title =        "Error in Ulps of the Multiplication or Division by a
                 Correctly-Rounded Function or Constant in Binary
                 Floating-Point Arithmetic",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "12",
  number =       "2",
  pages =        "656--666",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/TETC.2023.3294986",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Fri Sep 29 10:36:37 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "Assume we use a binary floating-point arithmetic and
                 that RN is the round-to-nearest function. Also assume
                 that c is a constant or a real function of one or more
                 variables, and that we have at our disposal a correctly
                 rounded implementation of c, say c' = RN(c). For
                 evaluating xc(resp.x / corc / x), the natural way is to
                 replace it by RN(x.c') (resp.RN(x / c') or RN(c' / x)),
                 that is, to call function c' and to perform a
                 floating-point multiplication or division. This can be
                 generalized to the approximation of n / d by RN(n' /
                 d') and the approximation of n d by RN(n'.d'), where n'
                 = RN(n) and d' = RN(d), and n and d are functions for
                 which we have at our disposal a correctly rounded
                 implementation. We discuss tight error bounds in ulps
                 of such approximations. From our results, one
                 immediately obtains tight error bounds for calculations
                 such as x * pi, ln(2) / x, x / (y + z), (x + y) * z, x
                 / sqrt(y), sqrt(x) / y, (x + y)(z + t), (x + y) / (z +
                 t), (x + y) / (zt), etc. in floating-point
                 arithmetic.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
  keywords =     "Arithmetic; Blogs; correct rounding; Floating-point
                 arithmetic; Libraries; Lips; Measurement uncertainty;
                 multiplication by a constant; numerical error;
                 Standards; Toy manufacturing industry; ulp",
}


bibtype: article
filename: fparith.bib
label: Brogi:2024:FPP
author: F. Brogi and S. Bna and G. Boga and G. Amati and T. Esposti Ongaro and M. Cerminara
title: On floating point precision in computational fluid dynamics using OpenFOAM
journal: j-FUT-GEN-COMP-SYS
volume: 152
pages: 1--16
month: mar
monthnumber: 3
year: 2024
CODEN: FGSEVI
DOI: https://doi.org/10.1016/j.future.2023.10.006
ISSN: 0167-739X (print), 1872-7115 (electronic) OR 0167739X (print), 18727115 (electronic)
ISSNL: 0167-739X OR 0167739X
bibdate: Sat Dec 16 07:26:57 MST 2023
bibtimestamp: 2023.12.16 07:26:57 MST
URL: http://www.sciencedirect.com/science/article/pii/S0167739X23003813
fjournal: Future Generation Computer Systems
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/0167739X
rawauthor: F. Brogi and S. Bn{\`a} and G. Boga and G. Amati and T. Esposti Ongaro and M. Cerminara
rawtitle: On floating point precision in computational fluid dynamics using {OpenFOAM}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib

entry:
@Article{Brogi:2024:FPP,
  author =       "F. Brogi and S. Bn{\`a} and G. Boga and G. Amati and
                 T. Esposti Ongaro and M. Cerminara",
  title =        "On floating point precision in computational fluid
                 dynamics using {OpenFOAM}",
  journal =      j-FUT-GEN-COMP-SYS,
  volume =       "152",
  number =       "??",
  pages =        "1--16",
  month =        mar,
  year =         "2024",
  CODEN =        "FGSEVI",
  DOI =          "https://doi.org/10.1016/j.future.2023.10.006",
  ISSN =         "0167-739X (print), 1872-7115 (electronic)",
  ISSN-L =       "0167-739X",
  bibdate =      "Sat Dec 16 07:26:57 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167739X23003813",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Generation Computer Systems",
  journal-URL =  "http://www.sciencedirect.com/science/journal/0167739X",
}


bibtype: article
filename: fparith.bib
label: Cai:2024:TEV
author: Luwei Cai and Fu Song and Taolue Chen
title: Towards Efficient Verification of Constant-Time Cryptographic Implementations
journal: Proceedings of the ACM on Software Engineering
volume: 1
number: FSE
pages: 1019--1042
month: jul
monthnumber: 7
year: 2024
DOI: https://doi.org/10.1145/3643772
ISSN: 2994-970X OR 2994970X
bibdate: Tue Aug 27 07:37:07 2024
bibtimestamp: 2024.08.27 07:37:07 ???
acknowledgement: ack-nhfb
rawauthor: Luwei Cai and Fu Song and Taolue Chen
rawtitle: Towards Efficient Verification of Constant-Time Cryptographic Implementations
abstract:
Timing side-channel attacks exploit secret-dependent execution time to fully or partially recover secrets of cryptographic implementations, posing a severe threat to software security. Constant-time programming discipline is an effective software-based countermeasure against timing side-channel attacks, but developing constant-time implementations turns out to be challenging and error-prone. Current verification approaches/tools suffer from scalability and precision issues when applied to production software in practice. In this paper, we put forward practical verification approaches based on a novel synergy of taint analysis and safety verification of self-composed programs. Specifically, we first use an IFDS-based lightweight taint analysis to prove that a large number of potential (timing) side-channel sources do not actually leak secrets. We then resort to a precise taint analysis and a safety verification approach to determine whether the remaining potential side-channel sources can actually leak secrets. These include novel constructions of taint-directed semi-cross-product of the original program and its Boolean abstraction, and a taint-directed self-composition of the program. Our approach is implemented as a cross-platform and fully automated tool CT-Prover. The experiments confirm its efficiency and effectiveness in verifying real-world benchmarks from modern cryptographic and SSL/TLS libraries. In particular, CT-Prover identify new, confirmed vulnerabilities of open-source SSL libraries (e.g., Mbed SSL, BearSSL) and significantly outperforms the state-of-the-art tool

keywords:
constant-time cryptographic implementation; Formal security models; Formal software verification; formal verification; Logic and verification; Program analysis; Security and privacy; Software and its engineering; taint analysis; Theory of computation; Timing side-channel

rawabstract:
Timing side-channel attacks exploit secret-dependent execution time to fully or partially recover secrets of cryptographic implementations, posing a severe threat to software security. Constant-time programming discipline is an effective software-based countermeasure against timing side-channel attacks, but developing constant-time implementations turns out to be challenging and error-prone. Current verification approaches/tools suffer from scalability and precision issues when applied to production software in practice. In this paper, we put forward practical verification approaches based on a novel synergy of taint analysis and safety verification of self-composed programs. Specifically, we first use an IFDS-based lightweight taint analysis to prove that a large number of potential (timing) side-channel sources do not actually leak secrets. We then resort to a precise taint analysis and a safety verification approach to determine whether the remaining potential side-channel sources can actually leak secrets. These include novel constructions of taint-directed semi-cross-product of the original program and its Boolean abstraction, and a taint-directed self-composition of the program. Our approach is implemented as a cross-platform and fully automated tool CT-Prover. The experiments confirm its efficiency and effectiveness in verifying real-world benchmarks from modern cryptographic and SSL/TLS libraries. In particular, CT-Prover identify new, confirmed vulnerabilities of open-source SSL libraries (e.g., Mbed SSL, BearSSL) and significantly outperforms the state-of-the-art tool

entry:
@Article{Cai:2024:TEV,
  author =       "Luwei Cai and Fu Song and Taolue Chen",
  title =        "Towards Efficient Verification of Constant-Time
                 Cryptographic Implementations",
  journal =      "Proceedings of the ACM on Software Engineering",
  volume =       "1",
  number =       "FSE",
  pages =        "1019--1042",
  month =        jul,
  year =         "2024",
  DOI =          "https://doi.org/10.1145/3643772",
  ISSN =         "2994-970X",
  bibdate =      "Tue Aug 27 07:37:07 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Timing side-channel attacks exploit secret-dependent
                 execution time to fully or partially recover secrets of
                 cryptographic implementations, posing a severe threat
                 to software security. Constant-time programming
                 discipline is an effective software-based
                 countermeasure against timing side-channel attacks, but
                 developing constant-time implementations turns out to
                 be challenging and error-prone. Current verification
                 approaches/tools suffer from scalability and precision
                 issues when applied to production software in practice.
                 In this paper, we put forward practical verification
                 approaches based on a novel synergy of taint analysis
                 and safety verification of self-composed programs.
                 Specifically, we first use an IFDS-based lightweight
                 taint analysis to prove that a large number of
                 potential (timing) side-channel sources do not actually
                 leak secrets. We then resort to a precise taint
                 analysis and a safety verification approach to
                 determine whether the remaining potential side-channel
                 sources can actually leak secrets. These include novel
                 constructions of taint-directed semi-cross-product of
                 the original program and its Boolean abstraction, and a
                 taint-directed self-composition of the program. Our
                 approach is implemented as a cross-platform and fully
                 automated tool CT-Prover. The experiments confirm its
                 efficiency and effectiveness in verifying real-world
                 benchmarks from modern cryptographic and SSL/TLS
                 libraries. In particular, CT-Prover identify new,
                 confirmed vulnerabilities of open-source SSL libraries
                 (e.g., Mbed SSL, BearSSL) and significantly outperforms
                 the state-of-the-art tool",
  acknowledgement = ack-nhfb,
  keywords =     "constant-time cryptographic implementation; Formal
                 security models; Formal software verification; formal
                 verification; Logic and verification; Program analysis;
                 Security and privacy; Software and its engineering;
                 taint analysis; Theory of computation; Timing
                 side-channel",
}


bibtype: article
filename: fparith.bib
label: Cameron:2024:AHM
author: Thomas R. Cameron and Stef Graillat
title: Accurate Horner methods in real and complex floating-point arithmetic
journal: j-BIT-NUM-MATH
volume: 64
number: 2
pages: ??--??
month: jun
monthnumber: 6
year: 2024
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-024-01017-w
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Tue May 28 15:02:24 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.28 15:02:24 MDT
URL: https://link.springer.com/article/10.1007/s10543-024-01017-w
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
ajournal: Bit Num. Math.
articleno: 17
journalURL: http://link.springer.com/journal/10543
rawauthor: Thomas R. Cameron and Stef Graillat
rawtitle: Accurate {Horner} methods in real and complex floating-point arithmetic
entry:
@Article{Cameron:2024:AHM,
  author =       "Thomas R. Cameron and Stef Graillat",
  title =        "Accurate {Horner} methods in real and complex
                 floating-point arithmetic",
  journal =      j-BIT-NUM-MATH,
  volume =       "64",
  number =       "2",
  pages =        "??--??",
  month =        jun,
  year =         "2024",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-024-01017-w",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Tue May 28 15:02:24 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10543-024-01017-w",
  acknowledgement = ack-nhfb,
  ajournal =     "Bit Num. Math.",
  articleno =    "17",
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: article
filename: fparith.bib
label: Campos:2024:FGC
author: Nelson Campos and Eran Edirisinghe and Slava Chesnokov and Daniel Larkin
title: Fast Generation of Custom Floating-Point Spatial Filters on FPGAs
journal: j-IEEE-ACCESS
volume: 12
pages: 167059--167071
year: 2024
DOI: https://doi.org/10.1109/ACCESS.2024.3486066
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Nelson Campos and Eran Edirisinghe and Slava Chesnokov and Daniel Larkin
rawtitle: Fast Generation of Custom Floating-Point Spatial Filters on {FPGAs}
keywords:
Convolution; Domain specific languages; Domain-specific language; embedded video processing; Fast Fourier transforms; Field programmable gate arrays; floating-point arithmetic; FPGA; Hardware; Kernel; Mathematical models; real-time; Real-time systems; Spatial filters; Streaming media

entry:
@Article{Campos:2024:FGC,
  author =       "Nelson Campos and Eran Edirisinghe and Slava Chesnokov
                 and Daniel Larkin",
  title =        "Fast Generation of Custom Floating-Point Spatial
                 Filters on {FPGAs}",
  journal =      j-IEEE-ACCESS,
  volume =       "12",
  pages =        "167059--167071",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ACCESS.2024.3486066",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Convolution; Domain specific languages;
                 Domain-specific language; embedded video processing;
                 Fast Fourier transforms; Field programmable gate
                 arrays; floating-point arithmetic; FPGA; Hardware;
                 Kernel; Mathematical models; real-time; Real-time
                 systems; Spatial filters; Streaming media",
}


bibtype: techreport
filename: fparith.bib
label: Caprioli:2024:ACM
author: Paul Caprioli and Vincenzo Innocente and Paul Zimmermann
title: Accuracy of Complex Mathematical Operations and Functions in Single and Double Precision
type: Report
number: hal-04714173
institution: High Performance Kernels LLC
pages: 8
day: 30
month: sep
monthnumber: 9
year: 2024
bibdate: Mon Sep 30 06:08:35 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.09.30 06:08:35 ???
URL: https://inria.hal.science/hal-04714173v1
acknowledgement: ack-nhfb
rawauthor: Paul Caprioli and Vincenzo Innocente and Paul Zimmermann
rawtitle: Accuracy of Complex Mathematical Operations and Functions in Single and Double Precision
entry:
@TechReport{Caprioli:2024:ACM,
  author =       "Paul Caprioli and Vincenzo Innocente and Paul
                 Zimmermann",
  title =        "Accuracy of Complex Mathematical Operations and
                 Functions in Single and Double Precision",
  type =         "Report",
  number =       "hal-04714173",
  institution =  "High Performance Kernels LLC",
  address =      "????",
  pages =        "8",
  day =          "30",
  month =        sep,
  year =         "2024",
  bibdate =      "Mon Sep 30 06:08:35 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04714173v1",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2024:HCH
author: Hui Chen and Lianghua Quan and Weiqiang Liu
title: HGH-CORDIC: a High-Radix Generalized Hyperbolic COordinate Rotation Digital Computer
crossref: IEEE:2024:PIS
pages: 88--95
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00024
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
acknowledgement: ack-nhfb
rawauthor: Hui Chen and Lianghua Quan and Weiqiang Liu
rawtitle: {HGH-CORDIC}: a {High-Radix Generalized Hyperbolic COordinate Rotation Digital Computer}
keywords:
Accuracy; ARITH 2024; ARITH-31; Convergence; Digital arithmetic; Digital computers; exponential; generalized; Hardware; hardware implementation; High-radix; hyperbolic CORDIC; logarithmic; Software

entry:
@InProceedings{Chen:2024:HCH,
  author =       "Hui Chen and Lianghua Quan and Weiqiang Liu",
  title =        "{HGH-CORDIC}: a {High-Radix Generalized Hyperbolic
                 COordinate Rotation Digital Computer}",
  crossref =     "IEEE:2024:PIS",
  pages =        "88--95",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00024",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; ARITH 2024; ARITH-31; Convergence; Digital
                 arithmetic; Digital computers; exponential;
                 generalized; Hardware; hardware implementation;
                 High-radix; hyperbolic CORDIC; logarithmic; Software",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2024:MPF
booktitle: 2024 4th International Conference on Electronic Information Engineering and Computer (EIECT)
title: A Multiple Precision Floating-Point Arithmetic Unit Based on the RISC-V Instruction Set
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 573--578
year: 2024
DOI: https://doi.org/10.1109/EIECT64462.2024.10867213
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 4th International Conference on Electronic Information Engineering and Computer (EIECT)}
rawtitle: A Multiple Precision Floating-Point Arithmetic Unit Based on the {RISC-V} Instruction Set
author:
Jianxin Chen and Hong Hao and Shuai Wang and Lele Li and Xinxin Zhao and Fan Yu and Jing Wang and Guilong Xu and Zongqi Sun and Kai Jiang

keywords:
Accuracy; Faces; Floating-point arithmetic; Floating-Point Unit (FPU); FPGA; GPGPU; Image processing; Instruction sets; Machine learning; Multi-Precision Formats; RISC-V; SIMD Operations; Single instruction multiple data; Vectors

rawauthor:
Jianxin Chen and Hong Hao and Shuai Wang and Lele Li and Xinxin Zhao and Fan Yu and Jing Wang and Guilong Xu and Zongqi Sun and Kai Jiang

entry:
@InProceedings{Chen:2024:MPF,
  author =       "Jianxin Chen and Hong Hao and Shuai Wang and Lele Li
                 and Xinxin Zhao and Fan Yu and Jing Wang and Guilong Xu
                 and Zongqi Sun and Kai Jiang",
  booktitle =    "{2024 4th International Conference on Electronic
                 Information Engineering and Computer (EIECT)}",
  title =        "A Multiple Precision Floating-Point Arithmetic Unit
                 Based on the {RISC-V} Instruction Set",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "573--578",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/EIECT64462.2024.10867213",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Faces; Floating-point arithmetic;
                 Floating-Point Unit (FPU); FPGA; GPGPU; Image
                 processing; Instruction sets; Machine learning;
                 Multi-Precision Formats; RISC-V; SIMD Operations;
                 Single instruction multiple data; Vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Chu:2024:NNR
author: Yu-Da Chu and Pei-Hsuan Kuo and Lyu-Ming Ho and Juinn-Dar Huang
booktitle: 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 437--441
year: 2024
DOI: https://doi.org/10.1109/AICAS59952.2024.10595902
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Yu-Da Chu and Pei-Hsuan Kuo and Lyu-Ming Ho and Juinn-Dar Huang
rawbooktitle: {2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)}
title:
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems

keywords:
Accuracy; Circuits and systems; Costs; Deep learning; number representation; quantization; Quantization (signal); recommendation system; Runtime; Training

rawtitle:
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems

entry:
@InProceedings{Chu:2024:NNR,
  author =       "Yu-Da Chu and Pei-Hsuan Kuo and Lyu-Ming Ho and
                 Juinn-Dar Huang",
  booktitle =    "{2024 IEEE 6th International Conference on AI Circuits
                 and Systems (AICAS)}",
  title =        "A Novel Number Representation and Its Hardware Support
                 for Accurate Low-Bit Quantization on Large Recommender
                 Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "437--441",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/AICAS59952.2024.10595902",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Circuits and systems; Costs; Deep learning;
                 number representation; quantization; Quantization
                 (signal); recommendation system; Runtime; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Coward:2024:CPA
author: Samuel Coward and Theo Drane and Emiliano Morini and George A. Constantinides
title: Combining Power and Arithmetic Optimization via Datapath Rewriting
crossref: IEEE:2024:PIS
pages: 24--31
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00014
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Samuel Coward and Theo Drane and Emiliano Morini and George A. Constantinides
rawtitle: Combining Power and Arithmetic Optimization via Datapath Rewriting
entry:
@InProceedings{Coward:2024:CPA,
  author =       "Samuel Coward and Theo Drane and Emiliano Morini and
                 George A. Constantinides",
  title =        "Combining Power and Arithmetic Optimization via
                 Datapath Rewriting",
  crossref =     "IEEE:2024:PIS",
  pages =        "24--31",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00014",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Cui:2024:TEC
author: Ziying Cui and Ke Chen and Bi Wu and Chenggang Yan and Yu Gong and Weiqiang Liu
title: A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration
crossref: IEEE:2024:PIS
pages: 116--123
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00028
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Ziying Cui and Ke Chen and Bi Wu and Chenggang Yan and Yu Gong and Weiqiang Liu
rawtitle: A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration
entry:
@InProceedings{Cui:2024:TEC,
  author =       "Ziying Cui and Ke Chen and Bi Wu and Chenggang Yan and
                 Yu Gong and Weiqiang Liu",
  title =        "A Time Efficient Comprehensive Model of Approximate
                 Multipliers for Design Space Exploration",
  crossref =     "IEEE:2024:PIS",
  pages =        "116--123",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00028",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: book
filename: fparith.bib
label: deDinechin:2024:ASA
author: Florent de Dinechin and Martin Kumm
publisher: pub-SV-CHAM
address: pub-SV-CHAM:adr
pages: xxiii + 804
year: 2024
DOI: https://doi.org/10.1007/978-3-031-42808-1
LCCN: QA76.9.C62 D56 2024
bibdate: Fri Dec 8 13:09:29 MST 2023
bibtimestamp: 2023.12.08 13:09:29 MST
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Martin Kumm
title:
Application-specific Arithmetic: Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era

ISBN:
3-031-42807-2, 3-031-42808-0 (e-book), 3-031-42809-9, 3-031-42810-2 OR 3031428072, 3031428080 (ebook), 3031428099, 3031428102

ISBN13:
978-3-031-42807-4, 978-3-031-42808-1 (e-book), 978-3-031-42809-8, 978-3-031-42810-4 OR 9783031428074, 9783031428081 (ebook), 9783031428098, 9783031428104

bibsource:
fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://perso.citi-lab.fr/fdedinec/ASA-book/errata.pdf; https://link.springer.com/book/10.1007/978-3-031-42808-1

abstract:
Written by two experts of the domain, this book presents the most recent advances in computer arithmetic hardware, with a focus on application-specific arithmetic beyond the classic operators and the standard precisions. It targets silicon designers who have to do better with less in the post-Moore era, and FPGA developers who want to exploit the full possibilities of reconfigurable computing platforms. Presents a unique focus on application-specific computer arithmetic; Helps developers gain a deep understanding of the arithmetic in their projects, and tailor it to their application; Illustrates concepts and architectures by actual implementations, using the FloPoCo open-source hardware generator.

TOC:
1: Introduction 2: Number Formats 3: Computing Just Right: Accuracy Specification and Error Analysis 4: Field Programmable Gate Arrays Part 1 Revisiting Classic Arithmetic 5: Fixed-Point Addition 6: Fixed-Point Comparison 7: Sums of Weighted Bits 8: Fixed-Point Multiplication 9: Fixed-Point Division 10: Shifters and Leading Bit Counters 11: Basic Floating-Point Operators Part 2 Operator Specialization 12: Multiplication by Constants 13: Division by Constants 14: Fixed-Point Squares, Cubes, and Other Integer Powers 15: Specialization and Fusion of Floating-Point Operators Part 3 Generic Methods for Fixed-Point Function Approximation 16: Generalities on Fixed-Point Function Approximation 17: Function Evaluation Using Tables and Additions 18: Polynomial-Based Architectures for Function Evaluation 19: Digit Recurrence for Algebraic Functions Part 4 Example Composite Operators 20: Fixed-Point Sine and Cosine 21: Floating-Point Accumulation and Sum-of-Products 22: Floating-Point Exponential Part 5 Application Domains 23: Arithmetic in The Design of Linear Time-Invariant Filters 24: Arithmetic for Deep Learning Part 6 Appendix 25: Appendix A: Custom Arithmetic Datapath Design with FloPoCo 26: Appendix B: Optimization Using Integer Linear Programming

rawabstract:
Written by two experts of the domain, this book presents the most recent advances in computer arithmetic hardware, with a focus on application-specific arithmetic beyond the classic operators and the standard precisions. It targets silicon designers who have to do better with less in the post-Moore era, and FPGA developers who want to exploit the full possibilities of reconfigurable computing platforms. Presents a unique focus on application-specific computer arithmetic; Helps developers gain a deep understanding of the arithmetic in their projects, and tailor it to their application; Illustrates concepts and architectures by actual implementations, using the FloPoCo open-source hardware generator.

rawtitle:
Application-specific Arithmetic: Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era

rawTOC:
1: Introduction \\ 2: Number Formats \\ 3: Computing Just Right: Accuracy Specification and Error Analysis \\ 4: Field Programmable Gate Arrays \\ \\ Part 1 Revisiting Classic Arithmetic \\ 5: Fixed-Point Addition \\ 6: Fixed-Point Comparison \\ 7: Sums of Weighted Bits \\ 8: Fixed-Point Multiplication \\ 9: Fixed-Point Division \\ 10: Shifters and Leading Bit Counters \\ 11: Basic Floating-Point Operators \\ \\ Part 2 Operator Specialization \\ 12: Multiplication by Constants \\ 13: Division by Constants \\ 14: Fixed-Point Squares, Cubes, and Other Integer Powers \\ 15: Specialization and Fusion of Floating-Point Operators \\ \\ Part 3 Generic Methods for Fixed-Point Function Approximation \\ 16: Generalities on Fixed-Point Function Approximation \\ 17: Function Evaluation Using Tables and Additions \\ 18: Polynomial-Based Architectures for Function Evaluation \\ 19: Digit Recurrence for Algebraic Functions \\ \\ Part 4 Example Composite Operators \\ 20: Fixed-Point Sine and Cosine \\ 21: Floating-Point Accumulation and Sum-of-Products \\ 22: Floating-Point Exponential \\ \\ Part 5 Application Domains \\ 23: Arithmetic in The Design of Linear Time-Invariant Filters \\ 24: Arithmetic for Deep Learning \\ \\ Part 6 Appendix \\ 25: Appendix A: Custom Arithmetic Datapath Design with FloPoCo \\ 26: Appendix B: Optimization Using Integer Linear Programming

entry:
@Book{deDinechin:2024:ASA,
  author =       "Florent de Dinechin and Martin Kumm",
  title =        "Application-specific Arithmetic: Computing Just Right
                 for the Reconfigurable Computer and the Dark Silicon
                 Era",
  publisher =    pub-SV-CHAM,
  address =      pub-SV-CHAM:adr,
  pages =        "xxiii + 804",
  year =         "2024",
  DOI =          "https://doi.org/10.1007/978-3-031-42808-1",
  ISBN =         "3-031-42807-2, 3-031-42808-0 (e-book), 3-031-42809-9,
                 3-031-42810-2",
  ISBN-13 =      "978-3-031-42807-4, 978-3-031-42808-1 (e-book),
                 978-3-031-42809-8, 978-3-031-42810-4",
  LCCN =         "QA76.9.C62 D56 2024",
  bibdate =      "Fri Dec 8 13:09:29 MST 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://perso.citi-lab.fr/fdedinec/ASA-book/errata.pdf;
                 https://link.springer.com/book/10.1007/978-3-031-42808-1",
  abstract =     "Written by two experts of the domain, this book
                 presents the most recent advances in computer
                 arithmetic hardware, with a focus on
                 application-specific arithmetic beyond the classic
                 operators and the standard precisions. It targets
                 silicon designers who have to do better with less in
                 the post-Moore era, and FPGA developers who want to
                 exploit the full possibilities of reconfigurable
                 computing platforms. Presents a unique focus on
                 application-specific computer arithmetic; Helps
                 developers gain a deep understanding of the arithmetic
                 in their projects, and tailor it to their application;
                 Illustrates concepts and architectures by actual
                 implementations, using the FloPoCo open-source hardware
                 generator.",
  acknowledgement = ack-nhfb,
  tableofcontents = "1: Introduction \\
                 2: Number Formats \\
                 3: Computing Just Right: Accuracy Specification and
                 Error Analysis \\
                 4: Field Programmable Gate Arrays \\
                 \\
                 Part 1 Revisiting Classic Arithmetic \\
                 5: Fixed-Point Addition \\
                 6: Fixed-Point Comparison \\
                 7: Sums of Weighted Bits \\
                 8: Fixed-Point Multiplication \\
                 9: Fixed-Point Division \\
                 10: Shifters and Leading Bit Counters \\
                 11: Basic Floating-Point Operators \\
                 \\
                 Part 2 Operator Specialization \\
                 12: Multiplication by Constants \\
                 13: Division by Constants \\
                 14: Fixed-Point Squares, Cubes, and Other Integer
                 Powers \\
                 15: Specialization and Fusion of Floating-Point
                 Operators \\
                 \\
                 Part 3 Generic Methods for Fixed-Point Function
                 Approximation \\
                 16: Generalities on Fixed-Point Function Approximation
                 \\
                 17: Function Evaluation Using Tables and Additions \\
                 18: Polynomial-Based Architectures for Function
                 Evaluation \\
                 19: Digit Recurrence for Algebraic Functions \\
                 \\
                 Part 4 Example Composite Operators \\
                 20: Fixed-Point Sine and Cosine \\
                 21: Floating-Point Accumulation and Sum-of-Products \\
                 22: Floating-Point Exponential \\
                 \\
                 Part 5 Application Domains \\
                 23: Arithmetic in The Design of Linear Time-Invariant
                 Filters \\
                 24: Arithmetic for Deep Learning \\
                 \\
                 Part 6 Appendix \\
                 25: Appendix A: Custom Arithmetic Datapath Design with
                 FloPoCo \\
                 26: Appendix B: Optimization Using Integer Linear
                 Programming",
}


bibtype: misc
filename: fparith.bib
label: Demmel:2024:EDS
author: Jim Demmel
title: Exploring the Design Space of Exception Handling
pages: 42
day: 22
month: aug
monthnumber: 8
year: 2024
bibdate: Tue Aug 27 08:09:27 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.27 08:09:27 ???
URL: ExceptionHandling_22Aug2024.pdf
acknowledgement: ack-nhfb
howpublished: Posting to STDS-754 mailing list.
rawauthor: Jim Demmel
rawtitle: Exploring the Design Space of Exception Handling
note:
Lecture slides on progress in research on floating-point exception handling, notably in LAPACK and the BLAS (Basic Linear Algebra Subroutines).

rawnote:
Lecture slides on progress in research on floating-point exception handling, notably in LAPACK and the BLAS (Basic Linear Algebra Subroutines).

entry:
@Misc{Demmel:2024:EDS,
  author =       "Jim Demmel",
  title =        "Exploring the Design Space of Exception Handling",
  howpublished = "Posting to STDS-754 mailing list.",
  pages =        "42",
  day =          "22",
  month =        aug,
  year =         "2024",
  bibdate =      "Tue Aug 27 08:09:27 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Lecture slides on progress in research on
                 floating-point exception handling, notably in LAPACK
                 and the BLAS (Basic Linear Algebra Subroutines).",
  URL =          "ExceptionHandling_22Aug2024.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Deng:2024:FPE
author: Bobin Deng and Bhargava Nadendla and Kun Suo and Yixin Xie and Dan Chia-Tien Lo
title: Fixed-point Encoding and Architecture Exploration for Residue Number Systems
journal: j-TACO
volume: 21
number: 3
pages: 53:1--53:??
month: sep
monthnumber: 9
year: 2024
DOI: https://doi.org/10.1145/3664923
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Sat Sep 21 06:05:41 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib
bibtimestamp: 2024.09.21 06:05:41 MDT
URL: https://dl.acm.org/doi/10.1145/3664923
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Archit. Code Optim.
articleno: 53
journalURL: https://dl.acm.org/loi/taco
rawauthor: Bobin Deng and Bhargava Nadendla and Kun Suo and Yixin Xie and Dan Chia-Tien Lo
rawtitle: Fixed-point Encoding and Architecture Exploration for Residue Number Systems
abstract:
Residue Number Systems (RNS) demonstrate the fascinating potential to serve integer addition / multiplication-intensive applications. The complexity of Artificial Intelligence (AI) models has grown enormously in recent years. From a computer system's perspective, ensuring the training of these large-scale AI models within an adequate time and energy consumption has become a big concern. Matrix multiplication is a dominant subroutine in many prevailing AI models, with an addition / multiplication-intensive attribute. However, the data type of matrix multiplication within machine learning training typically requires real numbers, which indicates that RNS benefits for integer applications cannot be directly gained by AI training. The state-of-the-art RNS real-number encodings, including floating-point and fixed-point, have defects and can be further enhanced. To transform default RNS benefits to the efficiency of large-scale AI training, we propose a low-cost and high-accuracy RNS fixed-point representation: Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling-down Postprocessing Multiplication (SD-Post-Mul). Moreover, we extend the implementation details of the other two RNS fixed-point methods: Double RNS Concatenation and S-RNS-Logic-P representation with Scaling-down Preprocessing Multiplication. We also design the architectures of these three fixed-point multipliers. In empirical experiments, our S-RNS-Logic-P representation with SD-Post-Mul method achieves less latency and energy overhead while maintaining good accuracy. Furthermore, this method can easily extend to the Redundant Residue Number System to raise the efficiency of error-tolerant domains, such as improving the error correction efficiency of quantum computing.

rawabstract:
Residue Number Systems (RNS) demonstrate the fascinating potential to serve integer addition\slash multiplication-intensive applications. The complexity of Artificial Intelligence (AI) models has grown enormously in recent years. From a computer system's perspective, ensuring the training of these large-scale AI models within an adequate time and energy consumption has become a big concern. Matrix multiplication is a dominant subroutine in many prevailing AI models, with an addition\slash multiplication-intensive attribute. However, the data type of matrix multiplication within machine learning training typically requires real numbers, which indicates that RNS benefits for integer applications cannot be directly gained by AI training. The state-of-the-art RNS real-number encodings, including floating-point and fixed-point, have defects and can be further enhanced. To transform default RNS benefits to the efficiency of large-scale AI training, we propose a low-cost and high-accuracy RNS fixed-point representation: Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling-down Postprocessing Multiplication (SD-Post-Mul). Moreover, we extend the implementation details of the other two RNS fixed-point methods: Double RNS Concatenation and S-RNS-Logic-P representation with Scaling-down Preprocessing Multiplication. We also design the architectures of these three fixed-point multipliers. In empirical experiments, our S-RNS-Logic-P representation with SD-Post-Mul method achieves less latency and energy overhead while maintaining good accuracy. Furthermore, this method can easily extend to the Redundant Residue Number System to raise the efficiency of error-tolerant domains, such as improving the error correction efficiency of quantum computing.

entry:
@Article{Deng:2024:FPE,
  author =       "Bobin Deng and Bhargava Nadendla and Kun Suo and Yixin
                 Xie and Dan Chia-Tien Lo",
  title =        "Fixed-point Encoding and Architecture Exploration for
                 Residue Number Systems",
  journal =      j-TACO,
  volume =       "21",
  number =       "3",
  pages =        "53:1--53:??",
  month =        sep,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3664923",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Sat Sep 21 06:05:41 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3664923",
  abstract =     "Residue Number Systems (RNS) demonstrate the
                 fascinating potential to serve integer addition\slash
                 multiplication-intensive applications. The complexity
                 of Artificial Intelligence (AI) models has grown
                 enormously in recent years. From a computer system's
                 perspective, ensuring the training of these large-scale
                 AI models within an adequate time and energy
                 consumption has become a big concern. Matrix
                 multiplication is a dominant subroutine in many
                 prevailing AI models, with an addition\slash
                 multiplication-intensive attribute. However, the data
                 type of matrix multiplication within machine learning
                 training typically requires real numbers, which
                 indicates that RNS benefits for integer applications
                 cannot be directly gained by AI training. The
                 state-of-the-art RNS real-number encodings, including
                 floating-point and fixed-point, have defects and can be
                 further enhanced. To transform default RNS benefits to
                 the efficiency of large-scale AI training, we propose a
                 low-cost and high-accuracy RNS fixed-point
                 representation: Single RNS Logical Partition
                 (S-RNS-Logic-P) representation with Scaling-down
                 Postprocessing Multiplication (SD-Post-Mul). Moreover,
                 we extend the implementation details of the other two
                 RNS fixed-point methods: Double RNS Concatenation and
                 S-RNS-Logic-P representation with Scaling-down
                 Preprocessing Multiplication. We also design the
                 architectures of these three fixed-point multipliers.
                 In empirical experiments, our S-RNS-Logic-P
                 representation with SD-Post-Mul method achieves less
                 latency and energy overhead while maintaining good
                 accuracy. Furthermore, this method can easily extend to
                 the Redundant Residue Number System to raise the
                 efficiency of error-tolerant domains, such as improving
                 the error correction efficiency of quantum computing.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Archit. Code Optim.",
  articleno =    "53",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}


bibtype: inproceedings
filename: fparith.bib
label: deSousa:2024:PFF
author: Jose T. de Sousa and Joao D. Lopes and Micaela Serodio and Horacio C. Neto and Mario P. Vestias
title: PT-Float: a Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes
crossref: IEEE:2024:PIS
pages: 139--146
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00031
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawtitle: {PT-Float}: a Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes
rawauthor:
Jos{\'e} T. de Sousa and Jo{\~a}o D. Lopes and Micaela Ser{\^o}dio and Hor{\'a}cio C. Neto and M{\'a}rio P. V{\'e}stias

entry:
@InProceedings{deSousa:2024:PFF,
  author =       "Jos{\'e} T. de Sousa and Jo{\~a}o D. Lopes and Micaela
                 Ser{\^o}dio and Hor{\'a}cio C. Neto and M{\'a}rio P.
                 V{\'e}stias",
  title =        "{PT-Float}: a Floating-Point Unit with Dynamically
                 Varying Exponent and Fraction Sizes",
  crossref =     "IEEE:2024:PIS",
  pages =        "139--146",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00031",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimitrov:2024:MBL
title: Multiple-base Logarithmic Quantization and Application in Reduced Precision AI Computations
crossref: IEEE:2024:PIS
pages: 48--51
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00017
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawtitle: Multiple-base Logarithmic Quantization and Application in Reduced Precision {AI} Computations
author:
Vassil Dimitrov and Richard Ford and Laurent Imbert and Arjuna Madanayake and Nilan Udayanga and Will Wray

rawauthor:
Vassil Dimitrov and Richard Ford and Laurent Imbert and Arjuna Madanayake and Nilan Udayanga and Will Wray

entry:
@InProceedings{Dimitrov:2024:MBL,
  author =       "Vassil Dimitrov and Richard Ford and Laurent Imbert
                 and Arjuna Madanayake and Nilan Udayanga and Will
                 Wray",
  title =        "Multiple-base Logarithmic Quantization and Application
                 in Reduced Precision {AI} Computations",
  crossref =     "IEEE:2024:PIS",
  pages =        "48--51",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00017",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Drane:2024:SCF
author: Theo Drane and Samuel Coward and Mertcan Temel and Joe Leslie-Hurd
title: On the Systematic Creation of Faithfully Rounded Commutative Truncated Booth Multipliers
crossref: IEEE:2024:PIS
pages: 108--115
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00027
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Theo Drane and Samuel Coward and Mertcan Temel and Joe Leslie-Hurd
rawtitle: On the Systematic Creation of Faithfully Rounded Commutative Truncated {Booth} Multipliers
entry:
@InProceedings{Drane:2024:SCF,
  author =       "Theo Drane and Samuel Coward and Mertcan Temel and Joe
                 Leslie-Hurd",
  title =        "On the Systematic Creation of Faithfully Rounded
                 Commutative Truncated {Booth} Multipliers",
  crossref =     "IEEE:2024:PIS",
  pages =        "108--115",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00027",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Duarte:2024:DNB
booktitle: 2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)
title: Deep Nibble: a 4-bit Number Format for Efficient DNN Training and Inference in FPGA
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2024
DOI: https://doi.org/10.1109/SBCCI62366.2024.10703994
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)}
rawtitle: {Deep Nibble}: a 4-bit Number Format for Efficient {DNN} Training and Inference in {FPGA}
author:
Luiz F. H. Duarte and George B. Nardes and Wesley Grignani and Douglas R. Melo and Cesar A. Zeferino

keywords:
Accuracy; Artificial neural networks; Deep learning; Deep Learning; FPGA; Hardware Acceleration; Integrated circuit modeling; Logarithmic Quantization; Memory management; Performance evaluation; Quantization (signal); Stochastic processes; Stochastic Rounding; Throughput; Training

rawauthor:
Luiz F. H. Duarte and George B. Nardes and Wesley Grignani and Douglas R. Melo and Cesar A. Zeferino

entry:
@InProceedings{Duarte:2024:DNB,
  author =       "Luiz F. H. Duarte and George B. Nardes and Wesley
                 Grignani and Douglas R. Melo and Cesar A. Zeferino",
  booktitle =    "{2024 37th SBC/SBMicro/IEEE Symposium on Integrated
                 Circuits and Systems Design (SBCCI)}",
  title =        "{Deep Nibble}: a 4-bit Number Format for Efficient
                 {DNN} Training and Inference in {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/SBCCI62366.2024.10703994",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Artificial neural networks; Deep learning;
                 Deep Learning; FPGA; Hardware Acceleration; Integrated
                 circuit modeling; Logarithmic Quantization; Memory
                 management; Performance evaluation; Quantization
                 (signal); Stochastic processes; Stochastic Rounding;
                 Throughput; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: DuPont:2024:HAP
author: David Du Pont and Jonas Bertels and Furkan Turan and Michiel Van Beirendonck and Ingrid Verbauwhede
title: Hardware Acceleration of the Prime-Factor and Rader NTT for BGV Fully Homomorphic Encryption
crossref: IEEE:2024:PIS
pages: 1--8
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00011
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawtitle: Hardware Acceleration of the Prime-Factor and Rader {NTT} for {BGV} Fully Homomorphic Encryption
rawauthor:
David {Du Pont} and Jonas Bertels and Furkan Turan and Michiel {Van Beirendonck} and Ingrid Verbauwhede

entry:
@InProceedings{DuPont:2024:HAP,
  author =       "David {Du Pont} and Jonas Bertels and Furkan Turan and
                 Michiel {Van Beirendonck} and Ingrid Verbauwhede",
  title =        "Hardware Acceleration of the Prime-Factor and Rader
                 {NTT} for {BGV} Fully Homomorphic Encryption",
  crossref =     "IEEE:2024:PIS",
  pages =        "1--8",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00011",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: article
filename: fparith.bib
label: ElArar:2024:BNE
author: E-M. El Arar and D. Sohier and P. de Oliveira Castro and E. Petit
title: Bounds on Nonlinear Errors for Variance Computation with Stochastic Rounding
journal: j-SIAM-J-SCI-COMP
volume: 46
number: 5
pages: B579--B599
year: 2024
CODEN: SJOCE3
DOI: https://doi.org/10.1137/23M1563001
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Mon Sep 30 10:38:50 MDT 2024
bibtimestamp: 2024.09.30 10:38:50 MDT
URL: https://epubs.siam.org/doi/10.1137/23M1563001
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; stochastic rounding
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: E-M. {El Arar} and D. Sohier and P. {de Oliveira Castro} and E. Petit
rawtitle: Bounds on Nonlinear Errors for Variance Computation with Stochastic Rounding
bibsource:
http://epubs.siam.org/toc/sjoce3/46/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{ElArar:2024:BNE,
  author =       "E-M. {El Arar} and D. Sohier and P. {de Oliveira
                 Castro} and E. Petit",
  title =        "Bounds on Nonlinear Errors for Variance Computation
                 with Stochastic Rounding",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "46",
  number =       "5",
  pages =        "B579--B599",
  month =        "????",
  year =         "2024",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/23M1563001",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Mon Sep 30 10:38:50 MDT 2024",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/46/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  URL =          "https://epubs.siam.org/doi/10.1137/23M1563001",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; stochastic
                 rounding",
}


bibtype: incollection
filename: fparith.bib
label: Elrefai:2024:CML
author: Hisham M. Elrefai and Sara S. Abou Zeid and Wafaa S. Sayed and Lobna A. Said and Ahmed G. Radwan
booktitle: Advances in Nonlinear Dynamics, Volume III
title: Compact Multiplier-less CORDIC-Based FPGA Implementation of Sine and Modified Sine Chaotic Maps
publisher: pub-SV-CHAM
address: pub-SV-CHAM:adr
pages: 153--161
year: 2024
DOI: https://doi.org/10.1007/978-3-031-50635-2_15
ISBN: 3-031-50634-0; 3-031-50635-9 OR 3031506340; 3031506359
ISBN13: 978-3-031-50634-5; 978-3-031-50635-2 OR 9783031506345; 9783031506352
ISSN: 2730-7697 OR 27307697
MRnumber: 4769607
bibdate: Tue Oct 28 07:04:09 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.28 07:04:09 ???
series: NODYCON Conference Proceedings Series
acknowledgement: ack-nhfb
rawauthor: Hisham M. Elrefai and Sara S. Abou Zeid and Wafaa S. Sayed and Lobna A. Said and Ahmed G. Radwan
rawbooktitle: Advances in Nonlinear Dynamics, Volume {III}
rawtitle: Compact Multiplier-less {CORDIC}-Based {FPGA} Implementation of Sine and Modified Sine Chaotic Maps
entry:
@InCollection{Elrefai:2024:CML,
  author =       "Hisham M. Elrefai and Sara S. Abou Zeid and Wafaa S.
                 Sayed and Lobna A. Said and Ahmed G. Radwan",
  booktitle =    "Advances in Nonlinear Dynamics, Volume {III}",
  title =        "Compact Multiplier-less {CORDIC}-Based {FPGA}
                 Implementation of Sine and Modified Sine Chaotic Maps",
  publisher =    pub-SV-CHAM,
  address =      pub-SV-CHAM:adr,
  pages =        "153--161",
  year =         "2024",
  DOI =          "https://doi.org/10.1007/978-3-031-50635-2_15",
  ISBN =         "3-031-50634-0; 3-031-50635-9",
  ISBN-13 =      "978-3-031-50634-5; 978-3-031-50635-2",
  ISSN =         "2730-7697",
  MRnumber =     "4769607",
  bibdate =      "Tue Oct 28 07:04:09 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "NODYCON Conference Proceedings Series",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Faissole:2024:FVR
author: Florian Faissole
title: Formally-Verified Round-Off Error Analysis of Runge--Kutta Methods
journal: j-J-AUTOM-REASON
volume: 68
number: 1
pages: ??--??
month: mar
monthnumber: 3
year: 2024
CODEN: JAREEW
DOI: https://doi.org/10.1007/s10817-023-09686-y
ISSN: 0168-7433 (print), 1573-0670 (electronic) OR 01687433 (print), 15730670 (electronic)
ISSNL: 0168-7433 OR 01687433
bibdate: Fri May 24 08:31:25 MDT 2024
bibtimestamp: 2024.05.24 08:31:25 MDT
URL: https://link.springer.com/article/10.1007/s10817-023-09686-y
fjournal: Journal of Automated Reasoning
acknowledgement: ack-nhfb
ajournal: J. Autom. Reason.
articleno: 1
journalURL: http://link.springer.com/journal/10817
rawauthor: Florian Faissole
rawtitle: Formally-Verified Round-Off Error Analysis of {Runge--Kutta} Methods
entry:
@Article{Faissole:2024:FVR,
  author =       "Florian Faissole",
  title =        "Formally-Verified Round-Off Error Analysis of
                 {Runge--Kutta} Methods",
  journal =      j-J-AUTOM-REASON,
  volume =       "68",
  number =       "1",
  pages =        "??--??",
  month =        mar,
  year =         "2024",
  CODEN =        "JAREEW",
  DOI =          "https://doi.org/10.1007/s10817-023-09686-y",
  ISSN =         "0168-7433 (print), 1573-0670 (electronic)",
  ISSN-L =       "0168-7433",
  bibdate =      "Fri May 24 08:31:25 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jautomreason.bib",
  URL =          "https://link.springer.com/article/10.1007/s10817-023-09686-y",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Autom. Reason.",
  articleno =    "1",
  fjournal =     "Journal of Automated Reasoning",
  journal-URL =  "http://link.springer.com/journal/10817",
}


bibtype: techreport
filename: fparith.bib
label: Fog:2024:FPE
author: Agner Fog
title: Floating point exception tracking and NAN propagation
type: Report
institution: Technical University of Denmark
address: Lyngby, Denmark
pages: 11
day: 15
month: aug
monthnumber: 8
year: 2024
bibdate: Wed Jan 15 10:06:11 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.01.15 10:06:11 ???
URL: https://www.agner.org/optimize/nan_propagation.pdf
remark: Revision of cite Fog:2020:FPE and cite Fog:2023:FPE.
acknowledgement: ack-nhfb
rawauthor: Agner Fog
rawtitle: Floating point exception tracking and {NAN} propagation
entry:
@TechReport{Fog:2024:FPE,
  author =       "Agner Fog",
  title =        "Floating point exception tracking and {NAN}
                 propagation",
  type =         "Report",
  institution =  "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "11",
  day =          "15",
  month =        aug,
  year =         "2024",
  bibdate =      "Wed Jan 15 10:06:11 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/nan_propagation.pdf",
  abstract =     "The most common methods for detecting floating point
                 errors are based on exception trapping or a global
                 status register. These methods are inefficient in
                 modern systems that use out-of-order parallelism and
                 single-instruction-multiple-data (SIMD) parallelism for
                 improving performance. It is argued that a method based
                 on NAN propagation is more efficient and deterministic.
                 Problems with NAN propagation in current systems are
                 discussed. Examples of implementation in the C++ vector
                 class library and in an experimental instruction set
                 named ForwardCom are presented. The IEEE-754 standard
                 for floating point arithmetic may need adjustment to
                 accommodate the needs of modern forms of parallelism.",
  acknowledgement = ack-nhfb,
  remark =       "Revision of \cite{Fog:2020:FPE} and
                 \cite{Fog:2023:FPE}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Fuengfusin:2024:NAB
author: Ninnart Fuengfusin and Hakaru Tamukoh
booktitle: 2024 1st International Conference on Robotics, Engineering, Science, and Technology (RESTCON)
title: NaN Attacks: Bit-Flipping Deep Neural Network Parameters to NaN or Infinity
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 33--37
year: 2024
DOI: https://doi.org/10.1109/RESTCON60981.2024.10463548
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Ninnart Fuengfusin and Hakaru Tamukoh
rawbooktitle: {2024 1st International Conference on Robotics, Engineering, Science, and Technology (RESTCON)}
rawtitle: {NaN} Attacks: Bit-Flipping Deep Neural Network Parameters to {NaN} or {Infinity}
keywords:
Analytical models; Artificial neural networks; bit-flip attack; bit-flip defense; Computational modeling; Correlation; deep learning; FP32; Image recognition; Infinity; NaN; Performance evaluation; Speech recognition

entry:
@InProceedings{Fuengfusin:2024:NAB,
  author =       "Ninnart Fuengfusin and Hakaru Tamukoh",
  booktitle =    "{2024 1st International Conference on Robotics,
                 Engineering, Science, and Technology (RESTCON)}",
  title =        "{NaN} Attacks: Bit-Flipping Deep Neural Network
                 Parameters to {NaN} or {Infinity}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "33--37",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/RESTCON60981.2024.10463548",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Analytical models; Artificial neural networks;
                 bit-flip attack; bit-flip defense; Computational
                 modeling; Correlation; deep learning; FP32; Image
                 recognition; Infinity; NaN; Performance evaluation;
                 Speech recognition",
}


bibtype: inproceedings
filename: fparith.bib
label: GazzoniFilho:2024:PAA
title: PQC-AMX: Accelerating Saber and FrodoKEM on the Apple M1 and M3 SoCs
crossref: IEEE:2024:PIS
pages: 9--16
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00012
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawtitle: {PQC-AMX}: Accelerating {Saber} and {FrodoKEM} on the {Apple} {M1} and {M3} {SoCs}
author:
Decio Luiz Gazzoni Filho and Guilherme Brandao and Gora Adj and Arwa Alblooshi and Isaac A. Canales-Martinez and Jorge Chavez-Saab and Julio Lopez

rawauthor:
D{\'e}cio Luiz {Gazzoni Filho} and Guilherme Brand{\~a}o and Gora Adj and Arwa Alblooshi and Isaac A. Canales-Mart{\'\i}nez and Jorge Ch{\'a}vez-Saab and Julio L{\'o}pez

entry:
@InProceedings{GazzoniFilho:2024:PAA,
  author =       "D{\'e}cio Luiz {Gazzoni Filho} and Guilherme
                 Brand{\~a}o and Gora Adj and Arwa Alblooshi and Isaac
                 A. Canales-Mart{\'\i}nez and Jorge Ch{\'a}vez-Saab and
                 Julio L{\'o}pez",
  title =        "{PQC-AMX}: Accelerating {Saber} and {FrodoKEM} on the
                 {Apple} {M1} and {M3} {SoCs}",
  crossref =     "IEEE:2024:PIS",
  pages =        "9--16",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00012",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: article
filename: fparith.bib
label: Giles:2024:REU
author: Michael B. Giles and Oliver Sheridan-Methven
title: Rounding Error Using Low Precision Approximate Random Variables
journal: j-SIAM-J-SCI-COMP
volume: 46
number: 4
pages: B502--B526
year: 2024
CODEN: SJOCE3
DOI: https://doi.org/10.1137/23M1552814
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Sat Aug 24 16:22:17 MDT 2024
bibtimestamp: 2024.08.24 16:22:17 MDT
URL: https://epubs.siam.org/doi/10.1137/23M1552814
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
ajournal: SIAM J. Sci. Comput.
journalURL: http://epubs.siam.org/sisc
rawauthor: Michael B. Giles and Oliver Sheridan-Methven
rawtitle: Rounding Error Using Low Precision Approximate Random Variables
bibsource:
http://epubs.siam.org/toc/sjoce3/46/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{Giles:2024:REU,
  author =       "Michael B. Giles and Oliver Sheridan-Methven",
  title =        "Rounding Error Using Low Precision Approximate Random
                 Variables",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "46",
  number =       "4",
  pages =        "B502--B526",
  month =        "????",
  year =         "2024",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/23M1552814",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Sat Aug 24 16:22:17 MDT 2024",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/46/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  URL =          "https://epubs.siam.org/doi/10.1137/23M1552814",
  acknowledgement = ack-nhfb,
  ajournal =     "SIAM J. Sci. Comput.",
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
}


bibtype: techreport
filename: fparith.bib
label: Gladman:2024:AMFa
author: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 25
day: 15
month: feb
monthnumber: 2
year: 2024
bibdate: Thu Feb 15 13:17:22 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.15 13:17:22 ???
URL: https://hal.inria.fr/hal-03141101; https://members.loria.fr/PZimmermann/papers/accuracy.pdf
acknowledgement: ack-nhfb
rawauthor: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
remark:
Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD, GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm, RadeonOpenCompute (ROCm), and RedHat -lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Gladman:2024:AMFa,
  author =       "Brian Gladman and Vincenzo Innocente and John Mather
                 and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "25",
  day =          "15",
  month =        feb,
  year =         "2024",
  bibdate =      "Thu Feb 15 13:17:22 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.inria.fr/hal-03141101;
                 https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD,
                 GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm,
                 RadeonOpenCompute (ROCm), and RedHat -lm libraries for
                 correct rounding, versus results from MPFR.",
}


bibtype: techreport
filename: fparith.bib
label: Gladman:2024:AMFb
author: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
pages: 25
day: 26
month: aug
monthnumber: 8
year: 2024
bibdate: Thu Sep 19 14:49:38 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.09.19 14:49:38 ???
URL: https://members.loria.fr/PZimmermann/papers/accuracy.pdf
acknowledgement: ack-nhfb
rawauthor: Brian Gladman and Vincenzo Innocente and John Mather and Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single, Double, Double Extended, and Quadruple Precision
remark:
Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD, GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm, RadeonOpenCompute (ROCm), and RedHat -lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Gladman:2024:AMFb,
  author =       "Brian Gladman and Vincenzo Innocente and John Mather
                 and Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 Double Extended, and Quadruple Precision",
  institution =  "????",
  pages =        "25",
  day =          "26",
  month =        aug,
  year =         "2024",
  bibdate =      "Thu Sep 19 14:49:38 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, Apple, ARM, CUDA, FreeBSD,
                 GNU, Intel, LLVM, Microsoft Musl, Newlib, OpenLibm,
                 RadeonOpenCompute (ROCm), and RedHat -lm libraries for
                 correct rounding, versus results from MPFR.",
}


bibtype: article
filename: fparith.bib
label: Guthmuller:2024:XRV
title: Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 7
pages: 1683--1697
month: jul
monthnumber: 7
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2024.3383964
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jun 12 15:57:24 2024
bibtimestamp: 2024.06.12 15:57:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: {Xvpfloat}: {RISC-V} {ISA} Extension for Variable Extended Precision Floating Point Computation
author:
Eric Guthmuller and Cesar Fuguet and Andrea Bocco and Jerome Fereyre and Riccardo Alidori and Ihsane Tahir and Yves Durand

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

keywords:
application specific processor; Arithmetic; Computer architecture; Convergence; coprocessor; Field programmable gate arrays; floating point arithmetic; Hardware; high precision arithmetic; Instruction sets; linear algebra; Open area test sites; RISC-V; scientific computing; Software

rawauthor:
Eric Guthmuller and C{\'e}sar Fuguet and Andrea Bocco and J{\'e}r{\^o}me Fereyre and Riccardo Alidori and Ihsane Tahir and Yves Durand

entry:
@Article{Guthmuller:2024:XRV,
  author =       "Eric Guthmuller and C{\'e}sar Fuguet and Andrea Bocco
                 and J{\'e}r{\^o}me Fereyre and Riccardo Alidori and
                 Ihsane Tahir and Yves Durand",
  title =        "{Xvpfloat}: {RISC-V} {ISA} Extension for Variable
                 Extended Precision Floating Point Computation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "7",
  pages =        "1683--1697",
  month =        jul,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2024.3383964",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jun 12 15:57:24 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "application specific processor; Arithmetic; Computer
                 architecture; Convergence; coprocessor; Field
                 programmable gate arrays; floating point arithmetic;
                 Hardware; high precision arithmetic; Instruction sets;
                 linear algebra; Open area test sites; RISC-V;
                 scientific computing; Software",
}


bibtype: inproceedings
filename: fparith.bib
label: Haghi:2024:BGB
booktitle: 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)
title: Bridging the Gap Between LLMs and LNS with Dynamic Data Format and Architecture Codesign
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1617--1631
year: 2024
DOI: https://doi.org/10.1109/MICRO61859.2024.00118
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)}
rawtitle: Bridging the Gap Between {LLMs} and {LNS} with Dynamic Data Format and Architecture Codesign
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Pouya Haghi and Chunshu Wu and Zahra Azad and Yanfei Li and Andrew Gui and Yuchen Hao and Ang Li and Tony Tong Geng

keywords:
Accuracy; Field programmable gate arrays; Hardware; Large Language Models; Logarithmic Number System; Machine Learning Accelerator; Next generation networking; Quantization; Quantization (signal); Runtime; Solids; Systolic arrays; Tensors; Training

rawauthor:
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  author =       "Pouya Haghi and Chunshu Wu and Zahra Azad and Yanfei
                 Li and Andrew Gui and Yuchen Hao and Ang Li and Tony
                 Tong Geng",
  booktitle =    "{2024 57th IEEE/ACM International Symposium on
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  pages =        "1617--1631",
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bibtype: article
filename: fparith.bib
label: Haghiri:2024:MIF
author: Saeed Haghiri and Salah I. Yahya and Abbas Rezaei and Arash Ahmadi
title: Multiplierless Implementation of Fitz-Hugh Nagumo (FHN) Modeling Using CORDIC Approach
journal: IEEE Transactions on Emerging Topics in Computational Intelligence
volume: 8
number: 1
pages: 279--287
year: 2024
DOI: https://doi.org/10.1109/TETCI.2023.3300176
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Saeed Haghiri and Salah I. Yahya and Abbas Rezaei and Arash Ahmadi
rawtitle: Multiplierless Implementation of {Fitz-Hugh Nagumo (FHN)} Modeling Using {CORDIC} Approach
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entry:
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  author =       "Saeed Haghiri and Salah I. Yahya and Abbas Rezaei and
                 Arash Ahmadi",
  title =        "Multiplierless Implementation of {Fitz-Hugh Nagumo
                 (FHN)} Modeling Using {CORDIC} Approach",
  journal =      "IEEE Transactions on Emerging Topics in Computational
                 Intelligence",
  volume =       "8",
  number =       "1",
  pages =        "279--287",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/TETCI.2023.3300176",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
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  acknowledgement = ack-nhfb,
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                 Computational modeling; FHN; Field programmable gate
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bibtype: article
filename: fparith.bib
label: Haider:2024:DRA
author: Muhammad Hamis Haider and Hao Zhang and Seok-Bum Ko
title: Decoder Reduction Approximation Scheme for Booth Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 3
pages: 735--746
month: mar
monthnumber: 3
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3343093
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Feb 16 07:37:44 2024
bibtimestamp: 2024.02.16 07:37:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Muhammad Hamis Haider and Hao Zhang and Seok-Bum Ko
rawtitle: Decoder Reduction Approximation Scheme for {Booth} Multipliers
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entry:
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  author =       "Muhammad Hamis Haider and Hao Zhang and Seok-Bum Ko",
  title =        "Decoder Reduction Approximation Scheme for {Booth}
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "3",
  pages =        "735--746",
  month =        mar,
  year =         "2024",
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  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 16 07:37:44 2024",
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bibtype: article
filename: fparith.bib
label: Harris:2024:UDS
title: Unified Digit Selection for Radix-4 Recurrence Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 73
number: 1
pages: 292--300
month: jan
monthnumber: 1
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2023.3305760
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Dec 27 15:37:27 2023
bibtimestamp: 2023.12.27 15:37:27 ???
fjournal: IEEE Transactions on Computers
keywords: division; minimally-redundant radix-4; RISC-V; square root; SRT
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Unified Digit Selection for Radix-4 Recurrence Division and Square Root
author:
David Harris and James Stine and Milo Ercegovac and Alberto Nannarelli and Katherine Parry and Cedar Turek

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib

rawauthor:
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                 Alberto Nannarelli and Katherine Parry and Cedar
                 Turek",
  title =        "Unified Digit Selection for Radix-4 Recurrence
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  volume =       "73",
  number =       "1",
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bibtype: article
filename: fparith.bib
label: Harvey:2024:FTI
author: David Harvey
title: Faster truncated integer multiplication
journal: j-MATH-COMPUT
volume: 93
number: 347
pages: 1265--1296
month: jul
monthnumber: 7
year: 2024
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3939
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Mon May 27 15:56:44 MDT 2024
bibtimestamp: 2024.05.27 15:56:44 MDT
URL: https://www.ams.org/journals/mcom/2024-93-347/S0025-5718-2024-03939-X
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
journalURL: https://www.ams.org/mcom/
rawauthor: David Harvey
rawtitle: Faster truncated integer multiplication
bibsource:
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entry:
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  author =       "David Harvey",
  title =        "Faster truncated integer multiplication",
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  number =       "347",
  pages =        "1265--1296",
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  acknowledgement = ack-nhfb,
  fjournal =     "Mathematics of Computation",
  journal-URL =  "https://www.ams.org/mcom/",
  pubdate =      "2 February 2024",
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bibtype: article
filename: fparith.bib
label: He:2024:RFP
title: A Reconfigurable Floating-Point Compute-in-Memory With Analog Exponent Preprocesses
journal: IEEE Solid-State Circuits Letters
volume: 7
pages: 271--274
year: 2024
DOI: https://doi.org/10.1109/LSSC.2024.3463208
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawtitle: A Reconfigurable Floating-Point Compute-in-Memory With Analog Exponent Preprocesses
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Pengyu He and Yuanzhe Zhao and Heng Xie and Yang Wang and Shouyi Yin and Li Li and Yan Zhu and Rui P. Martins and Chi-Hang Chan and Minglei Zhang

keywords:
Accuracy; Common Information Model (computing); Compute-in-memory (CIM) macro; Energy efficiency; exponent preprocess; floating point (FP); Gain; MOS devices; Quantization (signal); reconfigurable; Registers; segmented computation

rawauthor:
Pengyu He and Yuanzhe Zhao and Heng Xie and Yang Wang and Shouyi Yin and Li Li and Yan Zhu and Rui P. Martins and Chi-Hang Chan and Minglei Zhang

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  author =       "Pengyu He and Yuanzhe Zhao and Heng Xie and Yang Wang
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  title =        "A Reconfigurable Floating-Point Compute-in-Memory With
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  volume =       "7",
  pages =        "271--274",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/LSSC.2024.3463208",
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bibtype: inproceedings
filename: fparith.bib
label: Henriksson:2024:AAD
author: Mikael Henriksson and Theodor Lindberg and Oscar Gustafsson
title: APyTypes: Algorithmic Data Types in Python for Efficient Simulation of Finite Word-Length Effects
crossref: IEEE:2024:PIS
pages: 72--75
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00021
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/python.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Mikael Henriksson and Theodor Lindberg and Oscar Gustafsson
rawtitle:
{APyTypes}: Algorithmic Data Types in {Python} for Efficient Simulation of Finite Word-Length Effects

entry:
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  author =       "Mikael Henriksson and Theodor Lindberg and Oscar
                 Gustafsson",
  title =        "{APyTypes}: Algorithmic Data Types in {Python} for
                 Efficient Simulation of Finite Word-Length Effects",
  crossref =     "IEEE:2024:PIS",
  pages =        "72--75",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00021",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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bibtype: article
filename: fparith.bib
label: Hingu:2024:BFF
author: Chanakya Hingu and Xingang Fu and Praneeth Vangala and Ramkrishna Mishan and Poria Fajri
journal: j-IEEE-ACCESS
volume: 12
pages: 111097--111110
year: 2024
DOI: https://doi.org/10.1109/ACCESS.2024.3441512
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
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rawauthor: Chanakya Hingu and Xingang Fu and Praneeth Vangala and Ramkrishna Mishan and Poria Fajri
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32-Bit Fixed and Floating-Point Hardware Implementation for Enhanced Inverter Control: Leveraging FPGA in Recurrent Neural Network Applications

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rawtitle:
32-Bit Fixed and Floating-Point Hardware Implementation for Enhanced Inverter Control: Leveraging {FPGA} in Recurrent Neural Network Applications

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bibtype: inproceedings
filename: fparith.bib
label: Hsieh:2024:MAP
author: Mong-Yung Hsieh and Alan Liu and Zih-Jyun Chen
booktitle: 2024 IEEE International Conference on Systems, Man, and Cybernetics (SMC)
title: Multi-Agent Pruning and Quantization in Mixed-Precision Models
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 5367--5372
year: 2024
DOI: https://doi.org/10.1109/SMC54092.2024.10831664
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
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  author =       "Mong-Yung Hsieh and Alan Liu and Zih-Jyun Chen",
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  title =        "Multi-Agent Pruning and Quantization in
                 Mixed-Precision Models",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "5367--5372",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/SMC54092.2024.10831664",
  bibdate =      "Wed Oct 1 06:40:18 2025",
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bibtype: article
filename: fparith.bib
label: Huang:2024:IPF
author: Paul Xuanyuanliang Huang and Yannis Tsividis and Mingoo Seok
title: INTIACC: a Programmable Floating-Point Accelerator for Partial Differential Equations
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 59
number: 9
pages: 3058--3069
year: 2024
CODEN: IJSCBC
DOI: https://doi.org/10.1109/JSSC.2024.3379308
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawauthor: Paul Xuanyuanliang Huang and Yannis Tsividis and Mingoo Seok
rawtitle: {INTIACC}: a Programmable Floating-Point Accelerator for Partial Differential Equations
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  author =       "Paul Xuanyuanliang Huang and Yannis Tsividis and
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  title =        "{INTIACC}: a Programmable Floating-Point Accelerator
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  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "59",
  number =       "9",
  pages =        "3058--3069",
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  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
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  bibdate =      "Wed Oct 1 06:40:18 2025",
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bibtype: techreport
filename: fparith.bib
label: Hubrecht:2024:TCR
author: Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann and Laurence Rideau and Laurent Thery
title: Towards a correctly-rounded and fast power function in binary64 arithmetic
type: Report
institution: DI-ENS --- Departement d'informatique --- ENS Paris
address: Paris, France
pages: 3058--3069
day: 8
month: feb
monthnumber: 2
year: 2024
bibdate: Mon May 13 12:00:21 2024
bibtimestamp: 2024.05.13 12:00:21 ???
URL: https://inria.hal.science/hal-04159652v2/
acknowledgement: ack-nhfb
rawtitle: Towards a correctly-rounded and fast power function in binary64 arithmetic
abstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed and have been formally verified. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

remark:
This is a longer version of cite Hubrecht:2023:TCRb with proofs and remarks by the final two authors on the formal verification.

rawabstract:
We design algorithms for the correct rounding of the power function $ x^y $ in the binary64 IEEE 754 format, for all rounding modes, modulo the knowledge of hardest-to-round cases. Our implementation of these algorithms largely outperforms previous correctly-rounded implementations and is not far from the efficiency of current mathematical libraries, which are not correctly-rounded. Still, we expect our algorithms can be further improved for speed. The proofs of correctness are fully detailed and have been formally verified. We hope this work will motivate the next IEEE 754 revision committee to require correct rounding for mathematical functions.

rawauthor:
Tom Hubrecht and Claude-Pierre Jeannerod and Paul Zimmermann and Laurence Rideau and Laurent Th{\'e}ry

entry:
@TechReport{Hubrecht:2024:TCR,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and Paul
                 Zimmermann and Laurence Rideau and Laurent Th{\'e}ry",
  title =        "Towards a correctly-rounded and fast power function in
                 binary64 arithmetic",
  type =         "Report",
  institution =  "DI-ENS --- D{\'e}partement d'informatique --- ENS
                 Paris",
  address =      "Paris, France",
  day =          "8",
  month =        feb,
  year =         "2024",
  bibdate =      "Mon May 13 12:00:21 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04159652v2/",
  abstract =     "We design algorithms for the correct rounding of the
                 power function $ x^y $ in the binary64 IEEE 754 format,
                 for all rounding modes, modulo the knowledge of
                 hardest-to-round cases. Our implementation of these
                 algorithms largely outperforms previous
                 correctly-rounded implementations and is not far from
                 the efficiency of current mathematical libraries, which
                 are not correctly-rounded. Still, we expect our
                 algorithms can be further improved for speed. The
                 proofs of correctness are fully detailed and have been
                 formally verified. We hope this work will motivate the
                 next IEEE 754 revision committee to require correct
                 rounding for mathematical functions.",
  acknowledgement = ack-nhfb,
  remark =       "This is a longer version of \cite{Hubrecht:2023:TCRb}
                 with proofs and remarks by the final two authors on the
                 formal verification.",
}


bibtype: techreport
filename: fparith.bib
label: Hubrecht:2024:UACa
author: Tom Hubrecht and Claude-Pierre Jeannerod and Jean-Michel Muller
title: Useful applications of correctly-rounded operators of the form $ a b + c d + e $
type: Report
number: hal-04461089
institution: DI-ENS (Department d'informatique --- ENS Paris) and Universite de Lyon
address: Paris, France and Lyon France
pages: 3058--3069
day: 16
month: feb
monthnumber: 2
year: 2024
bibdate: Thu Feb 22 05:37:30 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.22 05:37:30 ???
URL: https://inria.hal.science/hal-04461089
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Jean-Michel Muller
rawtitle: Useful applications of correctly-rounded operators of the form $ a b + c d + e $
abstract:
We show that the availability of fused arithmetic operators that evaluate expressions of the form $ a b + c d $ (FD2 instruction) or $ a b + c d + e $ (FD2A instruction) in floating-point arithmetic with one final rounding only would significantly facilitate many calculations that are hard to perform with high accuracy at small cost using only the traditional operations $+$, $-$, $ div $, $ times $, $ sqrt $, and fused multiply-add (FMA).

rawabstract:
We show that the availability of fused arithmetic operators that evaluate expressions of the form $ a b + c d $ (FD2 instruction) or $ a b + c d + e $ (FD2A instruction) in floating-point arithmetic with one final rounding only would significantly facilitate many calculations that are hard to perform with high accuracy at small cost using only the traditional operations $+$, $-$, $ \div $, $ \times $, $ \sqrt {} $, and fused multiply-add (FMA).

entry:
@TechReport{Hubrecht:2024:UACa,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and
                 Jean-Michel Muller",
  title =        "Useful applications of correctly-rounded operators of
                 the form $ a b + c d + e $",
  type =         "Report",
  number =       "hal-04461089",
  institution =  "DI-ENS (D{\'e}partment d'informatique --- ENS Paris)
                 and Universit{\'e} de Lyon",
  address =      "Paris, France and Lyon France",
  day =          "16",
  month =        feb,
  year =         "2024",
  bibdate =      "Thu Feb 22 05:37:30 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-04461089",
  abstract =     "We show that the availability of fused arithmetic
                 operators that evaluate expressions of the form $ a b +
                 c d $ (FD2 instruction) or $ a b + c d + e $ (FD2A
                 instruction) in floating-point arithmetic with one
                 final rounding only would significantly facilitate many
                 calculations that are hard to perform with high
                 accuracy at small cost using only the traditional
                 operations $+$, $-$, $ \div $, $ \times $, $ \sqrt {}
                 $, and fused multiply-add (FMA).",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Hubrecht:2024:UACb
author: Tom Hubrecht and Claude-Pierre Jeannerod and Jean-Michel Muller
title: Useful applications of correctly-rounded operators of the form $ a b + c d + e $
crossref: IEEE:2024:PIS
pages: 32--39
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00015
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Tom Hubrecht and Claude-Pierre Jeannerod and Jean-Michel Muller
rawtitle: Useful applications of correctly-rounded operators of the form $ a b + c d + e $
entry:
@InProceedings{Hubrecht:2024:UACb,
  author =       "Tom Hubrecht and Claude-Pierre Jeannerod and
                 Jean-Michel Muller",
  title =        "Useful applications of correctly-rounded operators of
                 the form $ a b + c d + e $",
  crossref =     "IEEE:2024:PIS",
  pages =        "32--39",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00015",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: article
filename: fparith.bib
label: Jabbarpour:2024:FEE
journal: IEEE Transactions on Services Computing
volume: 17
number: 6
pages: 3657--3671
year: 2024
DOI: https://doi.org/10.1109/TSC.2024.3478768
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
author:
Mohammad Reza Jabbarpour and Bahman Javadi and Philip H. W. Leong and Rodrigo N. Calheiros and David Boland

title:
FedOrbit: Energy Efficient Federated Learning for Orbital Edge Computing Using Block Minifloat Arithmetic

keywords:
Arithmetic; Block minifloat; Clustering algorithms; Computational modeling; energy consumption; federated learning; Low earth orbit satellites; low-earth orbit; orbital edge computing; Orbits; Power demand; Quantization (signal); Satellites; Servers; Training

rawauthor:
Mohammad Reza Jabbarpour and Bahman Javadi and Philip H. W. Leong and Rodrigo N. Calheiros and David Boland

rawtitle:
{FedOrbit}: Energy Efficient Federated Learning for Orbital Edge Computing Using Block Minifloat Arithmetic

entry:
@Article{Jabbarpour:2024:FEE,
  author =       "Mohammad Reza Jabbarpour and Bahman Javadi and Philip
                 H. W. Leong and Rodrigo N. Calheiros and David Boland",
  title =        "{FedOrbit}: Energy Efficient Federated Learning for
                 Orbital Edge Computing Using Block Minifloat
                 Arithmetic",
  journal =      "IEEE Transactions on Services Computing",
  volume =       "17",
  number =       "6",
  pages =        "3657--3671",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/TSC.2024.3478768",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Arithmetic; Block minifloat; Clustering algorithms;
                 Computational modeling; energy consumption; federated
                 learning; Low earth orbit satellites; low-earth orbit;
                 orbital edge computing; Orbits; Power demand;
                 Quantization (signal); Satellites; Servers; Training",
}


bibtype: article
filename: fparith.bib
label: Jonnalagadda:2024:ADP
title: ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks
journal: j-IEEE-ACCESS
volume: 12
pages: 31036--31046
year: 2024
DOI: https://doi.org/10.1109/ACCESS.2024.3369695
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:08:36 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:08:36 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawtitle: {ADEPNET}: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks
author:
Aditya Anirudh Jonnalagadda and Uppugunduru Anil Kumar and Rishi Thotli and Satvik Sardesai and Sreehari Veeramachaneni and Syed Ershad Ahmed

keywords:
Approximate posit multipliers; Artificial neural networks; Decoding; Deep learning; deep neural networks; Encoding; Energy efficiency; energy-efficient; Floating-point arithmetic; Hardware; IEEE Standards; Power dissipation

rawauthor:
Aditya Anirudh Jonnalagadda and Uppugunduru Anil Kumar and Rishi Thotli and Satvik Sardesai and Sreehari Veeramachaneni and Syed Ershad Ahmed

entry:
@Article{Jonnalagadda:2024:ADP,
  author =       "Aditya Anirudh Jonnalagadda and Uppugunduru Anil Kumar
                 and Rishi Thotli and Satvik Sardesai and Sreehari
                 Veeramachaneni and Syed Ershad Ahmed",
  title =        "{ADEPNET}: A Dynamic-Precision Efficient Posit
                 Multiplier for Neural Networks",
  journal =      j-IEEE-ACCESS,
  volume =       "12",
  pages =        "31036--31046",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ACCESS.2024.3369695",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:08:36 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Approximate posit multipliers; Artificial neural
                 networks; Decoding; Deep learning; deep neural
                 networks; Encoding; Energy efficiency;
                 energy-efficient; Floating-point arithmetic; Hardware;
                 IEEE Standards; Power dissipation",
}


bibtype: inproceedings
filename: fparith.bib
label: K:2024:FPC
author: Padmakumar K and Lalu V and Shiny G
title: Floating-point CORDIC Coprocessor with Dynamic Iterations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2024
DOI: https://doi.org/10.1109/APCI61480.2024.10616948
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Padmakumar K and Lalu V and Shiny G
rawtitle: Floating-point {CORDIC} Coprocessor with Dynamic Iterations
booktitle:
2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI)

keywords:
CORDIC; Dynamic iteration; Ecosystems; floating-point; Hardware; Heuristic algorithms; Process control; Software algorithms; Taylor series; VHDL

rawbooktitle:
{2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI)}

entry:
@InProceedings{K:2024:FPC,
  author =       "Padmakumar K and Lalu V and Shiny G",
  booktitle =    "{2024 International Conference on Advancements in
                 Power, Communication and Intelligent Systems (APCI)}",
  title =        "Floating-point {CORDIC} Coprocessor with Dynamic
                 Iterations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/APCI61480.2024.10616948",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "CORDIC; Dynamic iteration; Ecosystems; floating-point;
                 Hardware; Heuristic algorithms; Process control;
                 Software algorithms; Taylor series; VHDL",
}


bibtype: inproceedings
filename: fparith.bib
label: Kaya:2024:NAP
author: Zeynep Kaya and Mario Garrido
crossref: IEEE:2024:PIS
pages: 52--59
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00018
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Zeynep Kaya and Mario Garrido
title:
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs

rawtitle:
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based {FFTs}

entry:
@InProceedings{Kaya:2024:NAP,
  author =       "Zeynep Kaya and Mario Garrido",
  title =        "Novel Access Patterns Based on Overlapping Loading and
                 Processing Times to Reduce Latency and Increase
                 Throughput in Memory-based {FFTs}",
  crossref =     "IEEE:2024:PIS",
  pages =        "52--59",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00018",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: inproceedings
filename: fparith.bib
label: Khwa:2024:IFP
booktitle: 2024 IEEE International Solid-State Circuits Conference (ISSCC)
volume: 67
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 568--570
year: 2024
DOI: https://doi.org/10.1109/ISSCC49657.2024.10454447
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 IEEE International Solid-State Circuits Conference (ISSCC)}
author:
Win-San Khwa and Ping-Chun Wu and Jui-Jen Wu and Jian-Wei Su and Ho-Yu Chen and Zhao-En Ke and Ting-Chien Chiu and Jun-Ming Hsu and Chiao-Yen Cheng and Yu-Chen Chen and Chung-Chuan Lo and Ren-Shuo Liu and Chih-Cheng Hsieh and Kea-Tiong Tang and Meng-Fan Chang

title:
34.2 A 16nm 96Kb Integer / Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI--Edge Devices

keywords:
Arrays; Artificial neural networks; Common Information Model (computing); Computational efficiency; Data transfer; In-memory computing; Solid state circuits

rawauthor:
Win-San Khwa and Ping-Chun Wu and Jui-Jen Wu and Jian-Wei Su and Ho-Yu Chen and Zhao-En Ke and Ting-Chien Chiu and Jun-Ming Hsu and Chiao-Yen Cheng and Yu-Chen Chen and Chung-Chuan Lo and Ren-Shuo Liu and Chih-Cheng Hsieh and Kea-Tiong Tang and Meng-Fan Chang

rawtitle:
34.2 A 16nm {96Kb} Integer\slash Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving {73.3-163.3TOPS/W} and {33.2-91.2TFLOPS/W} for {AI--Edge} Devices

entry:
@InProceedings{Khwa:2024:IFP,
  author =       "Win-San Khwa and Ping-Chun Wu and Jui-Jen Wu and
                 Jian-Wei Su and Ho-Yu Chen and Zhao-En Ke and
                 Ting-Chien Chiu and Jun-Ming Hsu and Chiao-Yen Cheng
                 and Yu-Chen Chen and Chung-Chuan Lo and Ren-Shuo Liu
                 and Chih-Cheng Hsieh and Kea-Tiong Tang and Meng-Fan
                 Chang",
  booktitle =    "{2024 IEEE International Solid-State Circuits
                 Conference (ISSCC)}",
  title =        "34.2 A 16nm {96Kb} Integer\slash Floating-Point
                 Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving
                 {73.3-163.3TOPS/W} and {33.2-91.2TFLOPS/W} for
                 {AI--Edge} Devices",
  volume =       "67",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "568--570",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ISSCC49657.2024.10454447",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Arrays; Artificial neural networks; Common Information
                 Model (computing); Computational efficiency; Data
                 transfer; In-memory computing; Solid state circuits",
}


bibtype: article
filename: fparith.bib
label: Kim:2024:MCA
author: Kwang Ho Kim and Sihem Mesnager and Kyong Il Pak
title: Montgomery curve arithmetic revisited
journal: j-J-CRYPTO-ENG
volume: 14
number: 2
pages: 343--362
month: jun
monthnumber: 6
year: 2024
DOI: https://doi.org/10.1007/s13389-024-00353-5
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Thu Aug 8 07:34:12 MDT 2024
bibtimestamp: 2024.08.08 07:34:12 MDT
note: See cite Montgomery:1987:SPE.
URL: https://link.springer.com/article/10.1007/s13389-024-00353-5
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
ajournal: J. Crypto. Eng.
journalURL: http://link.springer.com/journal/13389
rawauthor: Kwang Ho Kim and Sihem Mesnager and Kyong Il Pak
rawnote: See \cite{Montgomery:1987:SPE}.
rawtitle: {Montgomery} curve arithmetic revisited
entry:
@Article{Kim:2024:MCA,
  author =       "Kwang Ho Kim and Sihem Mesnager and Kyong Il Pak",
  title =        "{Montgomery} curve arithmetic revisited",
  journal =      j-J-CRYPTO-ENG,
  volume =       "14",
  number =       "2",
  pages =        "343--362",
  month =        jun,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-024-00353-5",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Thu Aug 8 07:34:12 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  note =         "See \cite{Montgomery:1987:SPE}.",
  URL =          "https://link.springer.com/article/10.1007/s13389-024-00353-5",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Crypto. Eng.",
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: inproceedings
filename: fparith.bib
label: Kluska:2024:QEG
booktitle: 2024 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)
title: QAttn: Efficient GPU Kernels for mixed-precision Vision Transformers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 3648--3657
year: 2024
DOI: https://doi.org/10.1109/CVPRW63382.2024.00368
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)}
rawtitle: {QAttn}: Efficient {GPU} Kernels for mixed-precision {Vision Transformers}
author:
Piotr Kluska and Adrian Castello and Florian Scheidegger and A. Cristiano I. Malossi and Enrique S. Quintana-Orti

keywords:
compression; Computational modeling; Computer vision; Graphics processing units; Image segmentation; instance segmentation; object classification; Prototypes; quantization; Quantization (signal); Transformers; vision transformers

rawauthor:
Piotr Kluska and Adri{\'a}n Castell{\'o} and Florian Scheidegger and A. Cristiano I. Malossi and Enrique S. Quintana-Ort{\'\i}

entry:
@InProceedings{Kluska:2024:QEG,
  author =       "Piotr Kluska and Adri{\'a}n Castell{\'o} and Florian
                 Scheidegger and A. Cristiano I. Malossi and Enrique S.
                 Quintana-Ort{\'\i}",
  booktitle =    "{2024 IEEE/CVF Conference on Computer Vision and
                 Pattern Recognition Workshops (CVPRW)}",
  title =        "{QAttn}: Efficient {GPU} Kernels for mixed-precision
                 {Vision Transformers}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "3648--3657",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/CVPRW63382.2024.00368",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "compression; Computational modeling; Computer vision;
                 Graphics processing units; Image segmentation; instance
                 segmentation; object classification; Prototypes;
                 quantization; Quantization (signal); Transformers;
                 vision transformers",
}


bibtype: article
filename: fparith.bib
label: Kohl:2024:MMU
author: Nils Kohl and Stephen F. McCormick and Rasmus Tamstorf
title: Multigrid Methods Using Block Floating Point Arithmetic
journal: j-SIAM-J-SCI-COMP
volume: 46
number: 5
pages: S202--S224
year: 2024
CODEN: SJOCE3
DOI: https://doi.org/10.1137/23M1581819
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Sat Apr 12 07:31:17 MDT 2025
bibtimestamp: 2025.04.12 07:31:17 MDT
URL: https://epubs.siam.org/doi/10.1137/23M1581819
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Nils Kohl and Stephen F. McCormick and Rasmus Tamstorf
rawtitle: Multigrid Methods Using Block Floating Point Arithmetic
bibsource:
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entry:
@Article{Kohl:2024:MMU,
  author =       "Nils Kohl and Stephen F. McCormick and Rasmus
                 Tamstorf",
  title =        "Multigrid Methods Using Block Floating Point
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  journal =      j-SIAM-J-SCI-COMP,
  volume =       "46",
  number =       "5",
  pages =        "S202--S224",
  month =        "????",
  year =         "2024",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/23M1581819",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Sat Apr 12 07:31:17 MDT 2025",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/46/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  URL =          "https://epubs.siam.org/doi/10.1137/23M1581819",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
}


bibtype: inproceedings
filename: fparith.bib
label: Langhammer:2024:MAC
author: Martin Langhammer and Bogdan Pasca and Igor Kucherenko
title: Multiplier Architecture with a Carry-Based Partial Product Encoding
crossref: IEEE:2024:PIS
pages: 104--107
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00026
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Martin Langhammer and Bogdan Pasca and Igor Kucherenko
rawtitle: Multiplier Architecture with a Carry-Based Partial Product Encoding
entry:
@InProceedings{Langhammer:2024:MAC,
  author =       "Martin Langhammer and Bogdan Pasca and Igor
                 Kucherenko",
  title =        "Multiplier Architecture with a Carry-Based Partial
                 Product Encoding",
  crossref =     "IEEE:2024:PIS",
  pages =        "104--107",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00026",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: article
filename: fparith.bib
label: Laudadio:2024:CIE
author: Teresa Laudadio and Nicola Mastronardi and Donatella Occorsio
title: Computing integrals with an exponential weight on the real axis in floating point arithmetic
journal: j-APPL-NUM-MATH
volume: 200
pages: 309--317
month: jun
monthnumber: 6
year: 2024
CODEN: ANMAEL
DOI: https://doi.org/10.1016/j.apnum.2023.05.025
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Thu Apr 11 08:18:17 MDT 2024
bibtimestamp: 2024.04.11 08:18:17 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0168927423001551
fjournal: Applied Numerical Mathematics: Transactions of IMACS
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274
rawauthor: Teresa Laudadio and Nicola Mastronardi and Donatella Occorsio
rawtitle: Computing integrals with an exponential weight on the real axis in floating point arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/applnummath.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Laudadio:2024:CIE,
  author =       "Teresa Laudadio and Nicola Mastronardi and Donatella
                 Occorsio",
  title =        "Computing integrals with an exponential weight on the
                 real axis in floating point arithmetic",
  journal =      j-APPL-NUM-MATH,
  volume =       "200",
  number =       "??",
  pages =        "309--317",
  month =        jun,
  year =         "2024",
  CODEN =        "ANMAEL",
  DOI =          "https://doi.org/10.1016/j.apnum.2023.05.025",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Thu Apr 11 08:18:17 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applnummath.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0168927423001551",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics: Transactions of IMACS",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274",
}


bibtype: article
filename: fparith.bib
label: Lee:2024:ODF
author: Seunghwan Lee and Dong-Joon Shin
title: Overflow-Detectable Floating-Point Fully Homomorphic Encryption
journal: j-IEEE-ACCESS
volume: 12
pages: 6160--6180
year: 2024
DOI: https://doi.org/10.1109/ACCESS.2024.3351738
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Seunghwan Lee and Dong-Joon Shin
rawtitle: Overflow-Detectable Floating-Point Fully Homomorphic Encryption
keywords:
Deep learning; Encoding; Error analysis; Floating-point arithmetic; Fully homomorphic encryption; Gaussian processes; Homomorphic encryption; homomorphic floating-point arithmetic; homomorphic overflow detection; Random variables; subgaussian error analysis; Transforms

entry:
@Article{Lee:2024:ODF,
  author =       "Seunghwan Lee and Dong-Joon Shin",
  title =        "Overflow-Detectable Floating-Point Fully Homomorphic
                 Encryption",
  journal =      j-IEEE-ACCESS,
  volume =       "12",
  pages =        "6160--6180",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ACCESS.2024.3351738",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Deep learning; Encoding; Error analysis;
                 Floating-point arithmetic; Fully homomorphic
                 encryption; Gaussian processes; Homomorphic encryption;
                 homomorphic floating-point arithmetic; homomorphic
                 overflow detection; Random variables; subgaussian error
                 analysis; Transforms",
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2024:ECS
author: Vincent Lefevre
title: An Emacs--Cairo Scrolling Bug due to Floating-Point Inaccuracy
crossref: IEEE:2024:PIS
pages: 76--79
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00022
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
rawtitle: An {Emacs--Cairo} Scrolling Bug due to Floating-Point Inaccuracy
entry:
@InProceedings{Lefevre:2024:ECS,
  author =       "Vincent Lef{\`e}vre",
  title =        "An {Emacs--Cairo} Scrolling Bug due to Floating-Point
                 Inaccuracy",
  crossref =     "IEEE:2024:PIS",
  pages =        "76--79",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00022",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
}


bibtype: misc
filename: fparith.bib
label: Lefevre:2024:TMF
author: Vincent Lefevre
title: Test of Mathematical Functions of the Standard C Library
pages: 76--79
day: 27
month: sep
monthnumber: 9
year: 2024
bibdate: Mon Oct 21 11:32:37 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.10.21 11:32:37 ???
URL: https://www.vinc17.net/research/testlibm/; https://www.vinc17.net/research/testlibm/hrcases/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Vincent Lef{\`e}vre
rawtitle: Test of Mathematical Functions of the {Standard C Library}
remark:
Contains link to collection of data files with worst-case (or hard-to-round) arguments for common elementary functions. See also cite Lefevre:2003:WCC.

entry:
@Misc{Lefevre:2024:TMF,
  author =       "Vincent Lef{\`e}vre",
  title =        "Test of Mathematical Functions of the {Standard C
                 Library}",
  howpublished = "Web site.",
  day =          "27",
  month =        sep,
  year =         "2024",
  bibdate =      "Mon Oct 21 11:32:37 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.vinc17.net/research/testlibm/;
                 https://www.vinc17.net/research/testlibm/hrcases/",
  acknowledgement = ack-nhfb,
  remark =       "Contains link to collection of data files with
                 worst-case (or hard-to-round) arguments for common
                 elementary functions. See also
                 \cite{Lefevre:2003:WCC}.",
}


bibtype: article
filename: fparith.bib
label: Lemire:2024:ESP
author: Daniel Lemire
title: Exact Short Products From Truncated Multipliers
journal: j-COMP-J
volume: 67
number: 4
pages: 1514--1520
month: apr
monthnumber: 4
year: 2024
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxad077
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Fri Apr 26 12:13:08 MDT 2024
bibtimestamp: 2024.04.26 12:13:08 MDT
URL: http://academic.oup.com/comjnl/article/67/4/1514/7306807; https://arxiv.org/abs/2303.14321v1
fjournal: Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Daniel Lemire
rawtitle: Exact Short Products From Truncated Multipliers
bibsource:
https://www.math.utah.edu/pub/tex/bib/compj2020.bib; https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We sometimes need to compute the most significant digits of the product of small integers with a multiplier requiring much storage: e.g., a large integer (e.g., $ 5^100 $) or an irrational number ($ pi $). We only need to access the most significant digits of the multiplier --- as long as the integers are sufficiently small. We provide an efficient algorithm to compute the range of integers given a truncated multiplier and a desired number of digits.

rawabstract:
We sometimes need to compute the most significant digits of the product of small integers with a multiplier requiring much storage: e.g., a large integer (e.g., $ 5^{100} $) or an irrational number ($ \pi $). We only need to access the most significant digits of the multiplier --- as long as the integers are sufficiently small. We provide an efficient algorithm to compute the range of integers given a truncated multiplier and a desired number of digits.

entry:
@Article{Lemire:2024:ESP,
  author =       "Daniel Lemire",
  title =        "Exact Short Products From Truncated Multipliers",
  journal =      j-COMP-J,
  volume =       "67",
  number =       "4",
  pages =        "1514--1520",
  month =        apr,
  year =         "2024",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxad077",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Fri Apr 26 12:13:08 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compj2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://academic.oup.com/comjnl/article/67/4/1514/7306807;
                 https://arxiv.org/abs/2303.14321v1",
  abstract =     "We sometimes need to compute the most significant
                 digits of the product of small integers with a
                 multiplier requiring much storage: e.g., a large
                 integer (e.g., $ 5^{100} $) or an irrational number ($
                 \pi $). We only need to access the most significant
                 digits of the multiplier --- as long as the integers
                 are sufficiently small. We provide an efficient
                 algorithm to compute the range of integers given a
                 truncated multiplier and a desired number of digits.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2024:DFPa
booktitle: 2024 IEEE 24th International Symposium on Cluster, Cloud and Internet Computing (CCGrid)
title: Discovery of Floating-Point Differences Between NVIDIA and AMD GPUs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 663--666
year: 2024
DOI: https://doi.org/10.1109/CCGrid59990.2024.00083
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 IEEE 24th International Symposium on Cluster, Cloud and Internet Computing (CCGrid)}
rawtitle: Discovery of Floating-Point Differences Between {NVIDIA} and {AMD} {GPUs}
author:
Xinyi Li and Ang Li and Bo Fang and Katarzyna Swirydowicz and Ignacio Laguna and Ganesh Gopalakrishnan

keywords:
AMD GPU; Complexity theory; Computational modeling; correctness-portability; floating-point arithmetic; Graphics processing units; Hardware; high performance computing; Libraries; machine learning; Numerical models; NVIDIA GPU; performance-portability; Software development management; Standards; Tensors; Testing

rawauthor:
Xinyi Li and Ang Li and Bo Fang and Katarzyna Swirydowicz and Ignacio Laguna and Ganesh Gopalakrishnan

entry:
@InProceedings{Li:2024:DFPa,
  author =       "Xinyi Li and Ang Li and Bo Fang and Katarzyna
                 Swirydowicz and Ignacio Laguna and Ganesh
                 Gopalakrishnan",
  booktitle =    "{2024 IEEE 24th International Symposium on Cluster,
                 Cloud and Internet Computing (CCGrid)}",
  title =        "Discovery of Floating-Point Differences Between
                 {NVIDIA} and {AMD} {GPUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "663--666",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/CCGrid59990.2024.00083",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AMD GPU; Complexity theory; Computational modeling;
                 correctness-portability; floating-point arithmetic;
                 Graphics processing units; Hardware; high performance
                 computing; Libraries; machine learning; Numerical
                 models; NVIDIA GPU; performance-portability; Software
                 development management; Standards; Tensors; Testing",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2024:DFPb
booktitle: 2024 IEEE International Electron Devices Meeting (IEDM)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2024
DOI: https://doi.org/10.1109/IEDM50854.2024.10873550
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 IEEE International Electron Devices Meeting (IEDM)}
author:
Jiancong Li and Shengguang Ren and Yi Li and Wenlong Peng and Zhiwei Zhou and Yibai Xue and Yu Zhang and Zhiwen Cao and Jiayi Sun and Yuhui He and Xiangshui Miao

title:
Demonstration of a Floating-point Deep Neural Matrix Equation Solver using 3D Vertical ReRAM with High Energy- and Area-Efficiency

keywords:
Arrays; In-memory computing; Mathematical models; Resistance; Scientific computing; Silicon compounds; Three-dimensional displays; Training; Transmission line matrix methods; Voltage measurement

rawauthor:
Jiancong Li and Shengguang Ren and Yi Li and Wenlong Peng and Zhiwei Zhou and Yibai Xue and Yu Zhang and Zhiwen Cao and Jiayi Sun and Yuhui He and Xiangshui Miao

rawtitle:
Demonstration of a Floating-point Deep Neural Matrix Equation Solver using {3D} Vertical {ReRAM} with High Energy- and Area-Efficiency

entry:
@InProceedings{Li:2024:DFPb,
  author =       "Jiancong Li and Shengguang Ren and Yi Li and Wenlong
                 Peng and Zhiwei Zhou and Yibai Xue and Yu Zhang and
                 Zhiwen Cao and Jiayi Sun and Yuhui He and Xiangshui
                 Miao",
  booktitle =    "{2024 IEEE International Electron Devices Meeting
                 (IEDM)}",
  title =        "Demonstration of a Floating-point Deep Neural Matrix
                 Equation Solver using {3D} Vertical {ReRAM} with High
                 Energy- and Area-Efficiency",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/IEDM50854.2024.10873550",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Arrays; In-memory computing; Mathematical models;
                 Resistance; Scientific computing; Silicon compounds;
                 Three-dimensional displays; Training; Transmission line
                 matrix methods; Voltage measurement",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2024:LLB
author: Yike Li and Zheng Wang and Wenhui Ou and Chen Liang and Weiyu Zhou and Yongkui Yang and Chao Chen
booktitle: 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Low-latency Buffering for Mixed-precision Neural Network Accelerator with MulTAP and FQPipe
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2024
DOI: https://doi.org/10.1109/ISCAS58744.2024.10558641
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Yike Li and Zheng Wang and Wenhui Ou and Chen Liang and Weiyu Zhou and Yongkui Yang and Chao Chen
rawbooktitle: {2024 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: Low-latency Buffering for Mixed-precision Neural Network Accelerator with {MulTAP} and {FQPipe}
keywords:
activation buffering; Arithmetic; Arrays; Artificial neural networks; Circuits and systems; IP networks; Low latency communication; mixed-precision; NN accelerator; Pipelines; quantization pipeline

entry:
@InProceedings{Li:2024:LLB,
  author =       "Yike Li and Zheng Wang and Wenhui Ou and Chen Liang
                 and Weiyu Zhou and Yongkui Yang and Chao Chen",
  booktitle =    "{2024 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Low-latency Buffering for Mixed-precision Neural
                 Network Accelerator with {MulTAP} and {FQPipe}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ISCAS58744.2024.10558641",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "activation buffering; Arithmetic; Arrays; Artificial
                 neural networks; Circuits and systems; IP networks; Low
                 latency communication; mixed-precision; NN accelerator;
                 Pipelines; quantization pipeline",
}


bibtype: article
filename: fparith.bib
label: Li:2024:MFM
author: Hongyan Li and Hang Lu and Xiaowei Li
journal: j-IEEE-TRANS-CAD-ICS
volume: 43
number: 3
pages: 878--891
year: 2024
CODEN: ITCSDI
DOI: https://doi.org/10.1109/TCAD.2023.3329778
ISSN: 0278-0070 (print), 1937-4151 (electronic) OR 02780070 (print), 19374151 (electronic)
ISSNL: 0278-0070 OR 02780070
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43
rawauthor: Hongyan Li and Hang Lu and Xiaowei Li
title:
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration

keywords:
Artificial neural networks; Computational efficiency; Deep learning; Deep learning accelerator; deep neural network (DNN); fp8 format; Hardware acceleration; Inference algorithms; Software algorithms

rawtitle:
{Mortar-FP8}: Morphing the Existing {FP32} Infrastructure for High-Performance Deep Learning Acceleration

entry:
@Article{Li:2024:MFM,
  author =       "Hongyan Li and Hang Lu and Xiaowei Li",
  title =        "{Mortar-FP8}: Morphing the Existing {FP32}
                 Infrastructure for High-Performance Deep Learning
                 Acceleration",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "43",
  number =       "3",
  pages =        "878--891",
  year =         "2024",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2023.3329778",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
  keywords =     "Artificial neural networks; Computational efficiency;
                 Deep learning; Deep learning accelerator; deep neural
                 network (DNN); fp8 format; Hardware acceleration;
                 Inference algorithms; Software algorithms",
}


bibtype: article
filename: fparith.bib
label: Li:2024:RPE
author: Boyu Li and Kai Li and Jiajun Zhou and Yuan Ren and Wei Mao and Hao Yu and Ngai Wong
title: A Reconfigurable Processing Element for Multiple-Precision Floating / Fixed-Point HPC
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 71
number: 3
pages: 1401--1405
year: 2024
DOI: https://doi.org/10.1109/TCSII.2023.3322259
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Boyu Li and Kai Li and Jiajun Zhou and Yuan Ren and Wei Mao and Hao Yu and Ngai Wong
rawtitle: A Reconfigurable Processing Element for Multiple-Precision Floating\slash Fixed-Point {HPC}
keywords:
Artificial neural networks; Clocks; Deep learning; Energy efficiency; fixed-point; floating-point; Hardware; HPC; MAC; Multiple-precision; PE; Random access memory; Training

entry:
@Article{Li:2024:RPE,
  author =       "Boyu Li and Kai Li and Jiajun Zhou and Yuan Ren and
                 Wei Mao and Hao Yu and Ngai Wong",
  title =        "A Reconfigurable Processing Element for
                 Multiple-Precision Floating\slash Fixed-Point {HPC}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "71",
  number =       "3",
  pages =        "1401--1405",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3322259",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "Artificial neural networks; Clocks; Deep learning;
                 Energy efficiency; fixed-point; floating-point;
                 Hardware; HPC; MAC; Multiple-precision; PE; Random
                 access memory; Training",
}


bibtype: article
filename: fparith.bib
label: Lin:2024:FHP
author: Xian Lin and Heming Liu and Xin Zheng and Huaien Gao and Shuting Cai and Xiaoming Xiong
title: FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores
journal: j-IEEE-TRANS-VLSI-SYST
volume: 32
number: 10
pages: 1945--1949
year: 2024
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2024.3399221
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Xian Lin and Heming Liu and Xin Zheng and Huaien Gao and Shuting Cai and Xiaoming Xiong
rawtitle: {FPUx}: High-Performance Floating-Point Support for Cost-Constrained {RISC-V} Cores
keywords:
Arithmetic; Floating-point units (FPUs); Hardware; Internet of Things; Internet of Things (IoT); IP networks; Pipelines; RISC-V; single-precision floating-point (FP) arithmetic IPs; Standards; Timing

entry:
@Article{Lin:2024:FHP,
  author =       "Xian Lin and Heming Liu and Xin Zheng and Huaien Gao
                 and Shuting Cai and Xiaoming Xiong",
  title =        "{FPUx}: High-Performance Floating-Point Support for
                 Cost-Constrained {RISC-V} Cores",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "32",
  number =       "10",
  pages =        "1945--1949",
  year =         "2024",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2024.3399221",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
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  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  keywords =     "Arithmetic; Floating-point units (FPUs); Hardware;
                 Internet of Things; Internet of Things (IoT); IP
                 networks; Pipelines; RISC-V; single-precision
                 floating-point (FP) arithmetic IPs; Standards; Timing",
}


bibtype: inproceedings
filename: fparith.bib
label: Liu:2024:ACA
author: Haobo Liu and Zhengyang Qian and Wei Wu and Hongwei Ren and Zhiwei Liu and Leibin Ni
booktitle: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2024
DOI: https://doi.org/10.23919/DATE58400.2024.10546882
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Haobo Liu and Zhengyang Qian and Wei Wu and Hongwei Ren and Zhiwei Liu and Leibin Ni
rawbooktitle: {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
title:
AFPR-CIM: an Analog-Domain Floating-Point RRAM-based Compute-In-Memory Architecture with Dynamic Range Adaptive FP-ADC

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adaptive; analog domain; Codes; computing in memory; dynamic range; floating-point; In-memory computing; Neural networks; Nonvolatile memory; Power demand; RRAM; Throughput; Voltage

rawtitle:
{AFPR-CIM}: an Analog-Domain Floating-Point {RRAM}-based Compute-In-Memory Architecture with Dynamic Range Adaptive {FP-ADC}

entry:
@InProceedings{Liu:2024:ACA,
  author =       "Haobo Liu and Zhengyang Qian and Wei Wu and Hongwei
                 Ren and Zhiwei Liu and Leibin Ni",
  booktitle =    "{2024 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{AFPR-CIM}: an Analog-Domain Floating-Point
                 {RRAM}-based Compute-In-Memory Architecture with
                 Dynamic Range Adaptive {FP-ADC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2024",
  DOI =          "https://doi.org/10.23919/DATE58400.2024.10546882",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "adaptive; analog domain; Codes; computing in memory;
                 dynamic range; floating-point; In-memory computing;
                 Neural networks; Nonvolatile memory; Power demand;
                 RRAM; Throughput; Voltage",
}


bibtype: inproceedings
filename: fparith.bib
label: Ltaief:2024:TCG
booktitle: SC24: International Conference for High Performance Computing, Networking, Storage and Analysis
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--12
year: 2024
DOI: https://doi.org/10.1109/SC41406.2024.00012
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {SC24: International Conference for High Performance Computing, Networking, Storage and Analysis}
author:
Hatem Ltaief and Rabab Alomairy and Qinglei Cao and Jie Ren and Lotfi Slim and Thorsten Kurth and Benedikt Dorschner and Salim Bougouffa and Rached Abdelkhalak and David E. Keyes

title:
Toward Capturing Genetic Epistasis from Multivariate Genome-Wide Association Studies Using Mixed-Precision Kernel Ridge Regression

keywords:
Bioinformatics; Dynamic runtime system; Genomics; Genotypes; GPU accelerators; Graphics processing units; High performance computing; Kernel; Kernel Ridge Regression; Mixed precision; Multivariate Genome-wide Association Studies; Nonlinear genotype-phenotype relationships; Phenotypes; Runtime; Software; Tensors; Tile-centric matrix computations; UK BioBank data

rawauthor:
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rawtitle:
Toward Capturing Genetic Epistasis from Multivariate Genome-Wide Association Studies Using Mixed-Precision Kernel Ridge Regression

entry:
@InProceedings{Ltaief:2024:TCG,
  author =       "Hatem Ltaief and Rabab Alomairy and Qinglei Cao and
                 Jie Ren and Lotfi Slim and Thorsten Kurth and Benedikt
                 Dorschner and Salim Bougouffa and Rached Abdelkhalak
                 and David E. Keyes",
  booktitle =    "{SC24: International Conference for High Performance
                 Computing, Networking, Storage and Analysis}",
  title =        "Toward Capturing Genetic Epistasis from Multivariate
                 Genome-Wide Association Studies Using Mixed-Precision
                 Kernel Ridge Regression",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--12",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/SC41406.2024.00012",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Bioinformatics; Dynamic runtime system; Genomics;
                 Genotypes; GPU accelerators; Graphics processing units;
                 High performance computing; Kernel; Kernel Ridge
                 Regression; Mixed precision; Multivariate Genome-wide
                 Association Studies; Nonlinear genotype-phenotype
                 relationships; Phenotypes; Runtime; Software; Tensors;
                 Tile-centric matrix computations; UK BioBank data",
}


bibtype: inproceedings
filename: fparith.bib
label: Luo:2024:BDN
author: Weile Luo and Ruibo Fan and Zeyu Li and Dayou Du and Qiang Wang and Xiaowen Chu
booktitle: 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
title: Benchmarking and Dissecting the Nvidia Hopper GPU Architecture
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 656--667
year: 2024
DOI: https://doi.org/10.1109/IPDPS57955.2024.00064
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Weile Luo and Ruibo Fan and Zeyu Li and Dayou Du and Qiang Wang and Xiaowen Chu
rawbooktitle: {2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}
rawtitle: Benchmarking and Dissecting the {Nvidia Hopper GPU} Architecture
keywords:
Asynchronous Execution; Benchmark testing; Computer architecture; Distributed Shared Memory; DPX; Graphics processing units; Hopper; Instruction Latency; Instruction sets; Microarchitecture; Performance evaluation; PTX; Tensor Core; Tensors

entry:
@InProceedings{Luo:2024:BDN,
  author =       "Weile Luo and Ruibo Fan and Zeyu Li and Dayou Du and
                 Qiang Wang and Xiaowen Chu",
  booktitle =    "{2024 IEEE International Parallel and Distributed
                 Processing Symposium (IPDPS)}",
  title =        "Benchmarking and Dissecting the {Nvidia Hopper GPU}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "656--667",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/IPDPS57955.2024.00064",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Asynchronous Execution; Benchmark testing; Computer
                 architecture; Distributed Shared Memory; DPX; Graphics
                 processing units; Hopper; Instruction Latency;
                 Instruction sets; Microarchitecture; Performance
                 evaluation; PTX; Tensor Core; Tensors",
}


bibtype: inproceedings
filename: fparith.bib
label: Lutz:2024:FFW
author: David R. Lutz and Anisha Saini and Mairin Kroes and Thomas Elmer and Harsha Valsaraju
title: Fused FP8 4-way Dot Product With Scaling and FP32 Accumulation
crossref: IEEE:2024:PIS
pages: 40--47
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00016
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: David R. Lutz and Anisha Saini and Mairin Kroes and Thomas Elmer and Harsha Valsaraju
rawtitle: Fused {FP8} 4-way Dot Product With Scaling and {FP32} Accumulation
keywords:
Adders; ARITH 2024; ARITH-31; Computational efficiency; Costs; Digital arithmetic; Dynamic range; Microarchitecture; US Department of Transportation

entry:
@InProceedings{Lutz:2024:FFW,
  author =       "David R. Lutz and Anisha Saini and Mairin Kroes and
                 Thomas Elmer and Harsha Valsaraju",
  title =        "Fused {FP8} 4-way Dot Product With Scaling and {FP32}
                 Accumulation",
  crossref =     "IEEE:2024:PIS",
  pages =        "40--47",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00016",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH 2024; ARITH-31; Computational
                 efficiency; Costs; Digital arithmetic; Dynamic range;
                 Microarchitecture; US Department of Transportation",
}


bibtype: article
filename: fparith.bib
label: Mackie:2024:RFM
author: Maximilien Mackie
title: Recursion-free modular arithmetic in the lambda-calculus
journal: j-INFO-PROC-LETT
volume: 183
pages: Article 106408
month: jan
monthnumber: 1
year: 2024
CODEN: IFPLAT
DOI: https://doi.org/10.1016/j.ipl.2023.106408
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Tue Sep 19 07:09:51 MDT 2023
bibtimestamp: 2023.09.19 07:09:51 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0020019023000510
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Maximilien Mackie
rawtitle: Recursion-free modular arithmetic in the lambda-calculus
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2020.bib

entry:
@Article{Mackie:2024:RFM,
  author =       "Maximilien Mackie",
  title =        "Recursion-free modular arithmetic in the
                 lambda-calculus",
  journal =      j-INFO-PROC-LETT,
  volume =       "183",
  number =       "??",
  pages =        "Article 106408",
  month =        jan,
  year =         "2024",
  CODEN =        "IFPLAT",
  DOI =          "https://doi.org/10.1016/j.ipl.2023.106408",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Tue Sep 19 07:09:51 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0020019023000510",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: McCormick:2024:REA
author: Stephen F. McCormick and Rasmus Tamstorf
title: Rounding-Error Analysis of Multigrid V-Cycles
journal: j-SIAM-J-SCI-COMP
volume: 46
number: 5
pages: S88--S95
year: 2024
CODEN: SJOCE3
DOI: https://doi.org/10.1137/23M1582898
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Sat Apr 12 07:31:17 MDT 2025
bibtimestamp: 2025.04.12 07:31:17 MDT
URL: https://epubs.siam.org/doi/10.1137/23M1582898
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Stephen F. McCormick and Rasmus Tamstorf
rawtitle: Rounding-Error Analysis of Multigrid {V}-Cycles
bibsource:
http://epubs.siam.org/toc/sjoce3/46/5; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{McCormick:2024:REA,
  author =       "Stephen F. McCormick and Rasmus Tamstorf",
  title =        "Rounding-Error Analysis of Multigrid {V}-Cycles",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "46",
  number =       "5",
  pages =        "S88--S95",
  month =        "????",
  year =         "2024",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/23M1582898",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Sat Apr 12 07:31:17 MDT 2025",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/46/5;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
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  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
}


bibtype: article
filename: fparith.bib
label: Mikaitis:2024:MMT
author: Mantas Mikaitis
title: Monotonicity of Multi-Term Floating-Point Adders
journal: j-IEEE-TRANS-COMPUT
pages: 1--13
year: 2024
CODEN: ITCOB4
DOI: https://doi.org/10.1109/tc.2024.3371783
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Mar 11 11:33:29 2024
bibtimestamp: 2024.03.11 11:33:29 ???
fjournal: IEEE Transactions on Computers
keywords: accurate floating-point summation
remark: Online on 11 March 2024, but not yet assigned to an issue.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Mantas Mikaitis
rawtitle: Monotonicity of Multi-Term Floating-Point Adders
entry:
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  volume =       "??",
  number =       "??",
  pages =        "1--13",
  month =        "????",
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  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Mar 11 11:33:29 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
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  keywords =     "accurate floating-point summation",
  remark =       "Online on 11 March 2024, but not yet assigned to an
                 issue.",
}


bibtype: inproceedings
filename: fparith.bib
label: Mikaitis:2024:MSL
author: Mantas Mikaitis
title: MATLAB Simulator of Level-Index Arithmetic
crossref: IEEE:2024:PIS
pages: 68--71
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00020
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31
acknowledgement: ack-nhfb
rawauthor: Mantas Mikaitis
rawtitle: {MATLAB} Simulator of Level-Index Arithmetic
entry:
@InProceedings{Mikaitis:2024:MSL,
  author =       "Mantas Mikaitis",
  title =        "{MATLAB} Simulator of Level-Index Arithmetic",
  crossref =     "IEEE:2024:PIS",
  pages =        "68--71",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00020",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31",
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bibtype: inproceedings
filename: fparith.bib
label: Mirsalari:2024:UBF
author: Seyed Ahmad Mirsalari and Saba Yousefzadeh and Ahmed Hemani and Giuseppe Tagliavini
booktitle: 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
title: Unleashing 8-Bit Floating Point Formats Out of the Deep-Learning Domain
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2024
DOI: https://doi.org/10.1109/ICECS61496.2024.10848785
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Seyed Ahmad Mirsalari and Saba Yousefzadeh and Ahmed Hemani and Giuseppe Tagliavini
rawbooktitle: {2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)}
rawtitle: Unleashing 8-Bit Floating Point Formats Out of the Deep-Learning Domain
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entry:
@InProceedings{Mirsalari:2024:UBF,
  author =       "Seyed Ahmad Mirsalari and Saba Yousefzadeh and Ahmed
                 Hemani and Giuseppe Tagliavini",
  booktitle =    "{2024 31st IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "Unleashing 8-Bit Floating Point Formats Out of the
                 Deep-Learning Domain",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/ICECS61496.2024.10848785",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; approximate computing; Deep learning; Energy
                 conservation; Energy efficiency; float8; Hardware;
                 Instruction sets; Kernel; Market research; Parallel
                 ultra-low-power platform; Resource management; RISC-V;
                 smallFloat data types; Sustainable development",
}


bibtype: misc
filename: fparith.bib
label: MPFRTeam:2024:MLA
author: MPFR Team
title: The MPFR Library: Algorithms and Proofs
pages: 69
day: 25
month: jan
monthnumber: 1
year: 2024
bibdate: Thu Oct 16 06:58:53 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.16 06:58:53 ???
URL: https://mpfr.org/algorithms.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: {MPFR Team}
rawtitle: The {MPFR} Library: Algorithms and Proofs
entry:
@Misc{MPFRTeam:2024:MLA,
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  title =        "The {MPFR} Library: Algorithms and Proofs",
  howpublished = "Web document",
  pages =        "69",
  day =          "25",
  month =        jan,
  year =         "2024",
  bibdate =      "Thu Oct 16 06:58:53 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://mpfr.org/algorithms.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Muller:2024:SNC
author: Jean-Michel Muller
title: Some notes on correct rounding of functions
pages: 31
day: 18
month: sep
monthnumber: 9
year: 2024
bibdate: Thu Sep 19 15:27:07 2024
bibtimestamp: 2024.09.19 15:27:07 ???
acknowledgement: ack-nhfb
howpublished: Attachment to STDS-754 mailing list
rawauthor: Jean-Michel Muller
rawtitle: Some notes on correct rounding of functions
entry:
@Misc{Muller:2024:SNC,
  author =       "Jean-Michel Muller",
  title =        "Some notes on correct rounding of functions",
  howpublished = "Attachment to STDS-754 mailing list",
  pages =        "31",
  day =          "18",
  month =        sep,
  year =         "2024",
  bibdate =      "Thu Sep 19 15:27:07 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2024:SRU
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella
title: Square Root Unit with Minimum Iterations for Posit Arithmetic
crossref: IEEE:2024:PIS
pages: 132--138
year: 2024
DOI: https://doi.org/10.1109/arith61463.2024.00030
bibdate: Thu Nov 13 11:37:34 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.13 11:37:34 ???
keywords: ARITH 2024; ARITH-31; posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella
rawtitle: Square Root Unit with Minimum Iterations for Posit Arithmetic
entry:
@InProceedings{Murillo:2024:SRU,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella",
  title =        "Square Root Unit with Minimum Iterations for Posit
                 Arithmetic",
  crossref =     "IEEE:2024:PIS",
  pages =        "132--138",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/arith61463.2024.00030",
  bibdate =      "Thu Nov 13 11:37:34 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2024; ARITH-31; posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Navimipour:2024:NSA
author: Nima Jafari Navimipour and Seyed-Sajad Ahmadpour and Senay Yalcin
title: A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots
journal: j-J-SUPERCOMPUTING
volume: 80
number: 1
pages: 395--412
month: jan
monthnumber: 1
year: 2024
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-023-05491-x
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Feb 15 10:23:12 MST 2024
bibtimestamp: 2024.02.15 10:23:12 MST
URL: https://link.springer.com/article/10.1007/s11227-023-05491-x
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Nima Jafari Navimipour and Seyed-Sajad Ahmadpour and Senay Yalcin
rawtitle: A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots
entry:
@Article{Navimipour:2024:NSA,
  author =       "Nima Jafari Navimipour and Seyed-Sajad Ahmadpour and
                 Senay Yalcin",
  title =        "A nano-scale arithmetic and logic unit using a
                 reversible logic and quantum-dots",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "80",
  number =       "1",
  pages =        "395--412",
  month =        jan,
  year =         "2024",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-023-05491-x",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Feb 15 10:23:12 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-023-05491-x",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Noyez:2024:MMS
author: Louis Noyez and Nadia El Mrabet and Olivier Potin and Pascal Veron
title: Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2
journal: j-TRETS
volume: 17
number: 1
pages: 9:1--9:??
month: mar
monthnumber: 3
year: 2024
DOI: https://doi.org/10.1145/3624571
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Wed Mar 20 07:25:09 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib
bibtimestamp: 2024.03.20 07:25:09 MDT
URL: https://dl.acm.org/doi/10.1145/3624571
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Reconfigurable Technol. Syst.
articleno: 9
journalURL: https://dl.acm.org/loi/trets
rawauthor: Louis Noyez and Nadia {El Mrabet} and Olivier Potin and Pascal Veron
rawtitle: {Montgomery} Multiplication Scalable Systolic Designs Optimized for {DSP48E2}
abstract:
This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic ldots 

rawabstract:
This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic \ldots{}

entry:
@Article{Noyez:2024:MMS,
  author =       "Louis Noyez and Nadia {El Mrabet} and Olivier Potin
                 and Pascal Veron",
  title =        "{Montgomery} Multiplication Scalable Systolic Designs
                 Optimized for {DSP48E2}",
  journal =      j-TRETS,
  volume =       "17",
  number =       "1",
  pages =        "9:1--9:??",
  month =        mar,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3624571",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Wed Mar 20 07:25:09 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3624571",
  abstract =     "This article describes an extensive study of the use
                 of DSP48E2 Slices in Ultrascale FPGAs to design
                 hardware versions of the Montgomery Multiplication
                 algorithm for the hardware acceleration of modular
                 multiplications. Our fully scalable systolic \ldots{}",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Reconfigurable Technol. Syst.",
  articleno =    "9",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "https://dl.acm.org/loi/trets",
}


bibtype: inproceedings
filename: fparith.bib
label: Okoshi:2024:WTW
booktitle: 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--3
year: 2024
DOI: https://doi.org/10.1109/A-SSCC60305.2024.10849314
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)}
author:
Yasuyuki Okoshi and Angel Lopez Garcia-Arias and Jaehoon Yu and Junnnosuke Suzuki and Hikari Otsuka and Thiem Van Chu and Kazushi Kawamura and Daichi Fujiki and Masato Motomura

title:
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression

keywords:
Accuracy; Computational modeling; Engines; Image coding; Neural networks; Process control; Quantization (signal); Solid state circuits; Tensors; Training

rawauthor:
Yasuyuki Okoshi and {\'A}ngel L{\'o}pez Garc{\'\i}a-Arias and Jaehoon Yu and Junnnosuke Suzuki and Hikari Otsuka and Thiem Van Chu and Kazushi Kawamura and Daichi Fujiki and Masato Motomura

rawtitle:
{WhiteDwarf: 12.24} {TFLOPS/W 40} nm Versatile Neural Inference Engine for Ultra-Compact Execution of {CNNs} and {MLPs} Through Triple Unstructured Sparsity Exploitation and Triple Model Compression

entry:
@InProceedings{Okoshi:2024:WTW,
  author =       "Yasuyuki Okoshi and {\'A}ngel L{\'o}pez
                 Garc{\'\i}a-Arias and Jaehoon Yu and Junnnosuke Suzuki
                 and Hikari Otsuka and Thiem Van Chu and Kazushi
                 Kawamura and Daichi Fujiki and Masato Motomura",
  booktitle =    "{2024 IEEE Asian Solid-State Circuits Conference
                 (A-SSCC)}",
  title =        "{WhiteDwarf: 12.24} {TFLOPS/W 40} nm Versatile Neural
                 Inference Engine for Ultra-Compact Execution of {CNNs}
                 and {MLPs} Through Triple Unstructured Sparsity
                 Exploitation and Triple Model Compression",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/A-SSCC60305.2024.10849314",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Computational modeling; Engines; Image
                 coding; Neural networks; Process control; Quantization
                 (signal); Solid state circuits; Tensors; Training",
}


bibtype: manual
filename: fparith.bib
label: Oracle:2024:SLR
title: SQL Language Reference
organization: Oracle Corporation
publisher: pub-ORACLE
address: pub-ORACLE:adr
edition: 19c (E96310-27)
pages: 1--3
month: jul
monthnumber: 7
year: 2024
bibdate: Tue Sep 10 15:24:10 2024
bibtimestamp: 2024.09.10 15:24:10 ???
acknowledgement: ack-nhfb
rawtitle: {SQL} Language Reference
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sqlbooks.bib

note:
The Data Types section describes the (non-IEEE 754) decimal number encoding. The precision is about 39 decimal digits, with a nonzero range of [1e-130, 1e126).

URL:
https://docs.oracle.com/en/database/oracle/oracle-database/19/sqlrf/Data-Types.html#GUID-A3C0D836-BADB-44E5-A5D4-265BA5968483

rawnote:
The Data Types section describes the (non-IEEE 754) decimal number encoding. The precision is about 39 decimal digits, with a nonzero range of [1e-130, 1e126).

entry:
@Manual{Oracle:2024:SLR,
  title =        "{SQL} Language Reference",
  organization = "{Oracle Corporation}",
  publisher =    pub-ORACLE,
  address =      pub-ORACLE:adr,
  edition =      "19c (E96310-27)",
  month =        jul,
  year =         "2024",
  bibdate =      "Tue Sep 10 15:24:10 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sqlbooks.bib",
  note =         "The Data Types section describes the (non-IEEE 754)
                 decimal number encoding. The precision is about 39
                 decimal digits, with a nonzero range of [1e-130,
                 1e126).",
  URL =          "https://docs.oracle.com/en/database/oracle/oracle-database/19/sqlrf/Data-Types.html#GUID-A3C0D836-BADB-44E5-A5D4-265BA5968483",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Palchaudhuri:2024:FSS
author: Ayan Palchaudhuri and Anindya Sundar Dhar
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 617--622
year: 2024
DOI: https://doi.org/10.1109/VLSID60093.2024.00109
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Ayan Palchaudhuri and Anindya Sundar Dhar
booktitle:
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)

title:
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation

keywords:
absolute difference; carry chain; CORDIC; Finite element analysis; FPGA; Look-Up Table; Minimization; Philosophical considerations; Registers; Scalability; scan register; Table lookup; ternary accumulator; Very large scale integration

rawbooktitle:
{2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)}

rawtitle:
{FPGA} Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation

entry:
@InProceedings{Palchaudhuri:2024:FSS,
  author =       "Ayan Palchaudhuri and Anindya Sundar Dhar",
  booktitle =    "{2024 37th International Conference on VLSI Design and
                 2024 23rd International Conference on Embedded Systems
                 (VLSID)}",
  title =        "{FPGA} Specific Speed-Area Optimized Architectures of
                 Arithmetic Cores with Scan Insertion for Carry Chain
                 Based Multi-level Logic Implementation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "617--622",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/VLSID60093.2024.00109",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "absolute difference; carry chain; CORDIC; Finite
                 element analysis; FPGA; Look-Up Table; Minimization;
                 Philosophical considerations; Registers; Scalability;
                 scan register; Table lookup; ternary accumulator; Very
                 large scale integration",
}


bibtype: inproceedings
filename: fparith.bib
label: Paulin:2024:OCD
booktitle: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--2
year: 2024
DOI: https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631529
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}
author:
Gianna Paulin and Paul Scheffler and Thomas Benz and Matheus Cavalcante and Tim Fischer and Manuel Eggimann and Yichao Zhang and Nils Wistoff and Luca Bertaccini and Luca Colagrande and Gianmarco Ottavi and Frank K. Gurkaynak and Davide Rossi and Luca Benini

title:
Occamy: a 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

keywords:
2.5D Integration; Chiplet; Computational efficiency; FinFETs; General Sparse Acceleration; Integrated circuit interconnections; Interposer; Linear algebra; Multi-Precision; Single instruction multiple data; Sparse matrices; Stencil Acceleration; Very large scale integration

rawauthor:
Gianna Paulin and Paul Scheffler and Thomas Benz and Matheus Cavalcante and Tim Fischer and Manuel Eggimann and Yichao Zhang and Nils Wistoff and Luca Bertaccini and Luca Colagrande and Gianmarco Ottavi and Frank K. G{\"u}rkaynak and Davide Rossi and Luca Benini

rawtitle:
{Occamy}: a 432-Core 28.1 {DP-GFLOP/s/W} 83\% {FPU} Utilization Dual-Chiplet, {Dual-HBM2E} {RISC-V}-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm {FinFET}

entry:
@InProceedings{Paulin:2024:OCD,
  author =       "Gianna Paulin and Paul Scheffler and Thomas Benz and
                 Matheus Cavalcante and Tim Fischer and Manuel Eggimann
                 and Yichao Zhang and Nils Wistoff and Luca Bertaccini
                 and Luca Colagrande and Gianmarco Ottavi and Frank K.
                 G{\"u}rkaynak and Davide Rossi and Luca Benini",
  booktitle =    "{2024 IEEE Symposium on VLSI Technology and Circuits
                 (VLSI Technology and Circuits)}",
  title =        "{Occamy}: a 432-Core 28.1 {DP-GFLOP/s/W} 83\% {FPU}
                 Utilization Dual-Chiplet, {Dual-HBM2E} {RISC-V}-Based
                 Accelerator for Stencil and Sparse Linear Algebra
                 Computations with 8-to-64-bit Floating-Point Support in
                 12nm {FinFET}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631529",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "2.5D Integration; Chiplet; Computational efficiency;
                 FinFETs; General Sparse Acceleration; Integrated
                 circuit interconnections; Interposer; Linear algebra;
                 Multi-Precision; Single instruction multiple data;
                 Sparse matrices; Stencil Acceleration; Very large scale
                 integration",
}


bibtype: article
filename: fparith.bib
label: Perez:2024:HAF
author: J. Ayuso Perez
title: Hardware Addition Over Finite Fields Based On Booth--Karatsuba Algorithm
journal: j-COMP-J
volume: 67
number: 8
pages: 2643--2666
month: aug
monthnumber: 8
year: 2024
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxae034
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Mon Aug 19 11:43:29 MDT 2024
bibtimestamp: 2024.08.19 11:43:29 MDT
URL: http://academic.oup.com/comjnl/article/67/8/2643/7667243
fjournal: Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: J. Ayuso Perez
rawtitle: Hardware Addition Over Finite Fields Based On {Booth--Karatsuba} Algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/compj2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Perez:2024:HAF,
  author =       "J. Ayuso Perez",
  title =        "Hardware Addition Over Finite Fields Based On
                 {Booth--Karatsuba} Algorithm",
  journal =      j-COMP-J,
  volume =       "67",
  number =       "8",
  pages =        "2643--2666",
  month =        aug,
  year =         "2024",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxae034",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Mon Aug 19 11:43:29 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compj2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://academic.oup.com/comjnl/article/67/8/2643/7667243",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: article
filename: fparith.bib
label: Rashidi:2024:AFE
author: Bahram Rashidi
title: APPAs: fast and efficient approximate parallel prefix adders and multipliers
journal: j-J-SUPERCOMPUTING
volume: 80
number: 16
pages: 24269--24296
month: nov
monthnumber: 11
year: 2024
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-024-06356-7
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Aug 22 13:34:29 MDT 2024
bibtimestamp: 2024.08.22 13:34:29 MDT
URL: https://link.springer.com/article/10.1007/s11227-024-06356-7
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
ajournal: J. Supercomputing
journalURL: http://link.springer.com/journal/11227
rawauthor: Bahram Rashidi
rawtitle: {APPAs}: fast and efficient approximate parallel prefix adders and multipliers
entry:
@Article{Rashidi:2024:AFE,
  author =       "Bahram Rashidi",
  title =        "{APPAs}: fast and efficient approximate parallel
                 prefix adders and multipliers",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "80",
  number =       "16",
  pages =        "24269--24296",
  month =        nov,
  year =         "2024",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-024-06356-7",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Aug 22 13:34:29 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-024-06356-7",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: inproceedings
filename: fparith.bib
label: Rayapati:2024:EEB
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 605--610
year: 2024
DOI: https://doi.org/10.1109/VLSID60093.2024.00107
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
author:
Vinay Rayapati and Sanampudi GopalaKrishna Reddy and Gandi Ajay Kumar and Gogireddy Ravikiran Reddy and Madhav Rao

booktitle:
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)

title:
EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture

keywords:
BFloat16; CNN; CORDIC; Embedded systems; Hardware; Inference algorithms; Libraries; Low Power; Neural networks; Performance evaluation; Sigmoid; Softmax; Tanh; Very large scale integration

rawauthor:
Vinay Rayapati and Sanampudi GopalaKrishna Reddy and Gandi Ajay Kumar and Gogireddy Ravikiran Reddy and Madhav Rao

rawbooktitle:
{2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)}

rawtitle:
{EBACA}: Efficient {Bfloat16}-based Activation Function Implementation Using Enhanced {CORDIC} Architecture

entry:
@InProceedings{Rayapati:2024:EEB,
  author =       "Vinay Rayapati and Sanampudi GopalaKrishna Reddy and
                 Gandi Ajay Kumar and Gogireddy Ravikiran Reddy and
                 Madhav Rao",
  booktitle =    "{2024 37th International Conference on VLSI Design and
                 2024 23rd International Conference on Embedded Systems
                 (VLSID)}",
  title =        "{EBACA}: Efficient {Bfloat16}-based Activation
                 Function Implementation Using Enhanced {CORDIC}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "605--610",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/VLSID60093.2024.00107",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "BFloat16; CNN; CORDIC; Embedded systems; Hardware;
                 Inference algorithms; Libraries; Low Power; Neural
                 networks; Performance evaluation; Sigmoid; Softmax;
                 Tanh; Very large scale integration",
}


bibtype: inproceedings
filename: fparith.bib
label: Remke:2024:HSG
author: Stefan Remke and Alexander Breuer
title: Hello SME! Generating Fast Matrix Multiplication Kernels Using the Scalable Matrix Extension
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1443--1454
year: 2024
DOI: https://doi.org/10.1109/SCW63240.2024.00185
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Stefan Remke and Alexander Breuer
rawtitle: {Hello SME}! {Generating} Fast Matrix Multiplication Kernels Using the Scalable Matrix Extension
booktitle:
SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis

keywords:
Bandwidth; code generation; Computer architecture; Instruction sets; Kernel; Loading; M4; microbenchmarks; Parallel processing; Pipelines; Registers; Scalable Matrix Extension (SME); small GEMMs; Throughput; Vectors

rawbooktitle:
{SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis}

entry:
@InProceedings{Remke:2024:HSG,
  author =       "Stefan Remke and Alexander Breuer",
  booktitle =    "{SC24-W: Workshops of the International Conference for
                 High Performance Computing, Networking, Storage and
                 Analysis}",
  title =        "{Hello SME}! {Generating} Fast Matrix Multiplication
                 Kernels Using the Scalable Matrix Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1443--1454",
  year =         "2024",
  DOI =          "https://doi.org/10.1109/SCW63240.2024.00185",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Bandwidth; code generation; Computer architecture;
                 Instruction sets; Kernel; Loading; M4; microbenchmarks;
                 Parallel processing; Pipelines; Registers; Scalable
                 Matrix Extension (SME); small GEMMs; Throughput;
                 Vectors",
}


bibtype: article
filename: fparith.bib
label: Sahoo:2024:ADF
author: Siva Satyendra Sahoo and Salim Ullah and Akash Kumar
title: AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming
journal: j-TRETS
volume: 17
number: 2
pages: 31:1--31:??
month: jun
monthnumber: 6
year: 2024
DOI: https://doi.org/10.1145/3648694
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Tue Jun 4 06:09:07 MDT 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib
bibtimestamp: 2024.06.04 06:09:07 MDT
URL: https://dl.acm.org/doi/10.1145/3648694
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
ajournal: ACM Trans. Reconfigurable Technol. Syst.
articleno: 31
journalURL: https://dl.acm.org/loi/trets
rawauthor: Siva Satyendra Sahoo and Salim Ullah and Akash Kumar
rawtitle: {AxOMaP}: Designing {FPGA}-based Approximate Arithmetic Operators using Mathematical Programming
abstract:
With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resource-constrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, the design of platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported the use of AI / ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit the use of AI/ML to designing ML-based surrogate functions that are used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers. Further, we report up to 27% better hypervolume than other state-of-the-art approaches to DSE for FPGA-based application-specific AxOs.

rawabstract:
With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resource-constrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, the design of platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported the use of AI\slash ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit the use of AI/ML to designing ML-based surrogate functions that are used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21\% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers. Further, we report up to 27\% better hypervolume than other state-of-the-art approaches to DSE for FPGA-based application-specific AxOs.

entry:
@Article{Sahoo:2024:ADF,
  author =       "Siva Satyendra Sahoo and Salim Ullah and Akash Kumar",
  title =        "{AxOMaP}: Designing {FPGA}-based Approximate
                 Arithmetic Operators using Mathematical Programming",
  journal =      j-TRETS,
  volume =       "17",
  number =       "2",
  pages =        "31:1--31:??",
  month =        jun,
  year =         "2024",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3648694",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Tue Jun 4 06:09:07 MDT 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3648694",
  abstract =     "With the increasing application of machine learning
                 (ML) algorithms in embedded systems, there is a rising
                 necessity to design low-cost computer arithmetic for
                 these resource-constrained systems. As a result,
                 emerging models of computation, such as approximate and
                 stochastic computing, that leverage the inherent
                 error-resilience of such algorithms are being actively
                 explored for implementing ML inference on
                 resource-constrained systems. Approximate computing
                 (AxC) aims to provide disproportionate gains in the
                 power, performance, and area (PPA) of an application by
                 allowing some level of reduction in its behavioral
                 accuracy (BEHAV). Using approximate operators (AxOs)
                 for computer arithmetic forms one of the more prevalent
                 methods of implementing AxC. AxOs provide the
                 additional scope for finer granularity of optimization,
                 compared to only precision scaling of computer
                 arithmetic. To this end, the design of
                 platform-specific and cost-efficient approximate
                 operators forms an important research goal. Recently,
                 multiple works have reported the use of AI\slash
                 ML-based approaches for synthesizing novel FPGA-based
                 AxOs. However, most of such works limit the use of
                 AI/ML to designing ML-based surrogate functions that
                 are used during iterative optimization processes. To
                 this end, we propose a novel data analysis-driven
                 mathematical programming-based approach to synthesizing
                 approximate operators for FPGAs. Specifically, we
                 formulate mixed integer quadratically constrained
                 programs based on the results of correlation analysis
                 of the characterization data and use the solutions to
                 enable a more directed search approach for evolutionary
                 optimization algorithms. Compared to traditional
                 evolutionary algorithms-based optimization, we report
                 up to 21\% improvement in the hypervolume, for joint
                 optimization of PPA and BEHAV, in the design of signed
                 8-bit multipliers. Further, we report up to 27\% better
                 hypervolume than other state-of-the-art approaches to
                 DSE for FPGA-based application-specific AxOs.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Trans. Reconfigurable Technol. Syst.",
  articleno =    "31",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "https://dl.acm.org/loi/trets",
}


