# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:2018:TFP
author: Alberto Nannarelli
title: Tunable Floating-Point for Energy Efficient Accelerators
crossref: Tenca:2018:PIS
pages: 29--36
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464797
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli
rawtitle: Tunable Floating-Point for Energy Efficient Accelerators
abstract:
In this work, we address the design of an on-chip accelerator for Machine Learning and other computation-demanding applications with a Tunable Floating-Point (TFP) precision. The precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of a given algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient. We focus on floating-point multiplication, which is the most power demanding arithmetic operation.

keywords:
Adders; ARITH 2018; ARITH-25; computation-demanding applications; Decoding; Dynamic range; electronic engineering computing; energy efficient accelerators; floating point arithmetic; floating-point multiplication; floating-point representation; Hardware; learning (artificial intelligence); Machine Learning; Machine learning; on-chip accelerator; Standards; System-on-chip; TFP precision; Tunable Floating-Point precision

rawabstract:
In this work, we address the design of an on-chip accelerator for Machine Learning and other computation-demanding applications with a Tunable Floating-Point (TFP) precision. The precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of a given algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient. We focus on floating-point multiplication, which is the most power demanding arithmetic operation.

entry:
@InProceedings{Nannarelli:2018:TFP,
  author =       "Alberto Nannarelli",
  title =        "Tunable Floating-Point for Energy Efficient
                 Accelerators",
  crossref =     "Tenca:2018:PIS",
  pages =        "29--36",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464797",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this work, we address the design of an on-chip
                 accelerator for Machine Learning and other
                 computation-demanding applications with a Tunable
                 Floating-Point (TFP) precision. The precision can be
                 chosen for a single operation by selecting a specific
                 number of bits for significand and exponent in the
                 floating-point representation. By tuning the precision
                 of a given algorithm to the minimum precision achieving
                 an acceptable target error, we can make the computation
                 more power efficient. We focus on floating-point
                 multiplication, which is the most power demanding
                 arithmetic operation.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH 2018; ARITH-25; computation-demanding
                 applications; Decoding; Dynamic range; electronic
                 engineering computing; energy efficient accelerators;
                 floating point arithmetic; floating-point
                 multiplication; floating-point representation;
                 Hardware; learning (artificial intelligence); Machine
                 Learning; Machine learning; on-chip accelerator;
                 Standards; System-on-chip; TFP precision; Tunable
                 Floating-Point precision",
}


bibtype: inproceedings
filename: fparith.bib
label: Nguyen:2018:EFP
author: Hong-Thu Nguyen and Xuan-Thuan Nguyen and Cong-Kha Pham
booktitle: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
title: An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 327--328
year: 2018
DOI: https://doi.org/10.1109/ASPDAC.2018.8297343
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Hong-Thu Nguyen and Xuan-Thuan Nguyen and Cong-Kha Pham
rawbooktitle: {2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)}
rawtitle: An efficient fixed-point arithmetic processor using a hybrid {CORDIC} algorithm
keywords:
Adders; Approximation algorithms; CMOS technology; Complexity theory; Hardware; Logic gates; Power demand

entry:
@InProceedings{Nguyen:2018:EFP,
  author =       "Hong-Thu Nguyen and Xuan-Thuan Nguyen and Cong-Kha
                 Pham",
  booktitle =    "{2018 23rd Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "An efficient fixed-point arithmetic processor using a
                 hybrid {CORDIC} algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "327--328",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ASPDAC.2018.8297343",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; Approximation algorithms; CMOS technology;
                 Complexity theory; Hardware; Logic gates; Power
                 demand",
}


bibtype: article
filename: fparith.bib
label: Numahata:2018:RAS
author: Dai Numahata and Hiroshi Sekigawa
title: Robust algorithms for sparse interpolation of multivariate polynomials
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 52
number: 4
pages: 145--147
month: dec
monthnumber: 12
year: 2018
DOI: https://doi.org/10.1145/3338637.3338648
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Wed Oct 23 07:34:18 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigsam.bib
bibtimestamp: 2019.10.23 07:34:18 MDT
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: Dai Numahata and Hiroshi Sekigawa
rawtitle: Robust algorithms for sparse interpolation of multivariate polynomials
abstract:
We consider the problem of symbolic-numeric sparse interpolation of multivariate polynomials. The problem is to find the coefficients and the exponents of a given black-box polynomial $ f(x_1, ldots , x_n) = sum _j = 1^t c_j x_1^d_j, 1 ldots x_n^d_j, n in mathbb C[x_1, ldots , x_n] (c_j neq 0) $ by evaluating the value of $ f(x_1, ldots , x_n) $ at any point in $ mathbb C^n $ in floating-point arithmetic and by using the conditions of the input.

rawabstract:
We consider the problem of symbolic-numeric sparse interpolation of multivariate polynomials. The problem is to find the coefficients and the exponents of a given black-box polynomial $ f(x_1, \ldots, x_n) = \sum_{j = 1}^t c_j x_1^{d_{j, 1}} \ldots {} x_n^{d_{j, n}} \in \mathbb {C}[x_1, \ldots, x_n] (c_j \neq 0) $ by evaluating the value of $ f(x_1, \ldots, x_n) $ at any point in $ \mathbb {C}^n $ in floating-point arithmetic and by using the conditions of the input.

entry:
@Article{Numahata:2018:RAS,
  author =       "Dai Numahata and Hiroshi Sekigawa",
  title =        "Robust algorithms for sparse interpolation of
                 multivariate polynomials",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "52",
  number =       "4",
  pages =        "145--147",
  month =        dec,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3338637.3338648",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Wed Oct 23 07:34:18 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  abstract =     "We consider the problem of symbolic-numeric sparse
                 interpolation of multivariate polynomials. The problem
                 is to find the coefficients and the exponents of a
                 given black-box polynomial $ f(x_1, \ldots, x_n) =
                 \sum_{j = 1}^t c_j x_1^{d_{j, 1}} \ldots {} x_n^{d_{j,
                 n}} \in \mathbb {C}[x_1, \ldots, x_n] (c_j \neq 0) $ by
                 evaluating the value of $ f(x_1, \ldots, x_n) $ at any
                 point in $ \mathbb {C}^n $ in floating-point arithmetic
                 and by using the conditions of the input.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Oliveira:2018:MLB
author: Thomaz Oliveira and Julio Lopez and Francisco Rodriguez-Henriquez
title: The Montgomery ladder on binary elliptic curves
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 241--258
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0163-8
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0163-8
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Thomaz Oliveira and Julio L{\'o}pez and Francisco Rodr{\'{\i}}guez-Henr{\'{\i}}quez
rawtitle: The {Montgomery} ladder on binary elliptic curves
entry:
@Article{Oliveira:2018:MLB,
  author =       "Thomaz Oliveira and Julio L{\'o}pez and Francisco
                 Rodr{\'{\i}}guez-Henr{\'{\i}}quez",
  title =        "The {Montgomery} ladder on binary elliptic curves",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "241--258",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0163-8",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0163-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Omari:2018:ICB
author: Mohammed Omari and Salah Yaichi
title: Image Compression Based on Mapping Image Fractals to Rational Numbers
journal: j-IEEE-ACCESS
volume: 6
pages: 47062--47074
year: 2018
DOI: https://doi.org/10.1109/ACCESS.2018.2865784
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:08:36 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:08:36 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Mohammed Omari and Salah Yaichi
rawtitle: Image Compression Based on Mapping Image Fractals to Rational Numbers
keywords:
Discrete transforms; Fractal image; Fractals; Genetic algorithms; genetic algorithms; Image coding; lossy compression; Mersenne numbers; rational numbers; Sociology; Statistics

entry:
@Article{Omari:2018:ICB,
  author =       "Mohammed Omari and Salah Yaichi",
  title =        "Image Compression Based on Mapping Image Fractals to
                 Rational Numbers",
  journal =      j-IEEE-ACCESS,
  volume =       "6",
  pages =        "47062--47074",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ACCESS.2018.2865784",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:08:36 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Discrete transforms; Fractal image; Fractals; Genetic
                 algorithms; genetic algorithms; Image coding; lossy
                 compression; Mersenne numbers; rational numbers;
                 Sociology; Statistics",
}


bibtype: inproceedings
filename: fparith.bib
label: Pendem:2018:ECA
author: Suganda Pendem and Rajshekar B. Shettar
booktitle: 2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2018
DOI: https://doi.org/10.1109/ICNEWS.2018.8903935
bibdate: Mon Oct 27 10:32:44 2025
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Suganda Pendem and Rajshekar B. Shettar
rawbooktitle: {2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS)}
title:
Enhancing Computational Accuracy and Performance of Interval Arithmetic Double Rotation CORDIC algorithm

bibsource:
https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib

keywords:
Accuracy; Arithmetic; Computer architecture; Cordic; Digital signal processing; DSP; Interval arithmetic; MATLAB; MATLAB and INTLAB; Monitoring; Real-time systems; Signal processing algorithms; Very large scale integration; Wireless communication

rawtitle:
Enhancing Computational Accuracy and Performance of Interval Arithmetic Double Rotation {CORDIC} algorithm

entry:
@InProceedings{Pendem:2018:ECA,
  author =       "Suganda Pendem and Rajshekar B. Shettar",
  booktitle =    "{2018 International Conference on Networking, Embedded
                 and Wireless Systems (ICNEWS)}",
  title =        "Enhancing Computational Accuracy and Performance of
                 Interval Arithmetic Double Rotation {CORDIC}
                 algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ICNEWS.2018.8903935",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Arithmetic; Computer architecture; Cordic;
                 Digital signal processing; DSP; Interval arithmetic;
                 MATLAB; MATLAB and INTLAB; Monitoring; Real-time
                 systems; Signal processing algorithms; Very large scale
                 integration; Wireless communication",
}


bibtype: inproceedings
filename: fparith.bib
label: Peou:2018:CSO
author: Kenny Peou and Alan Kelly and Joel Falcou and Cecile Germain
editor: IEEE
title: A Case Study on Optimizing Accurate Half Precision Average
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 356--363
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1109/cahpc.2018.8645923
ISBN: 1-5386-7769-5 OR 1538677695
ISBN13: 978-1-5386-7769-8 OR 9781538677698
bibdate: Fri Apr 11 08:36:46 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.04.11 08:36:46 ???
acknowledgement: ack-nhfb
rawauthor: Kenny Peou and Alan Kelly and Joel Falcou and Cecile Germain
raweditor: {IEEE}
rawtitle: A Case Study on Optimizing Accurate Half Precision Average
booktitle:
2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD): Lyon, France, 24--27 September 2018

abstract:
In this work, we study the numerical performance of various common algorithms used to calculate the average of an array of half precision (FP16) floating point values. While the current generation of CPUs does not support native FP16 arithmetic, it is a planned feature in a number of next-generation CPUs. FP16 arithmetic was emulated via the half software library. Due to the limitations of the FP16 data type, some algorithms proved insufficient for arrays as small as 100 elements. We propose an algorithm that allows numerically stable FP16 computation of the average and compare it to the naive floating point (FP32) algorithm in terms of both numerical precision and runtime performance. We find that our algorithm offers comparable robustness, numerical precision, and SIMD performance to the higher precision computation.

keywords:
Clustering algorithms; Half-Precision; Machine learning algorithms; Memory management; Numerical Precision; Program processors; Random access memory; Registers; SIMD; Software algorithms

rawabstract:
In this work, we study the numerical performance of various common algorithms used to calculate the average of an array of half precision (FP16) floating point values. While the current generation of CPUs does not support native FP16 arithmetic, it is a planned feature in a number of next-generation CPUs. FP16 arithmetic was emulated via the half software library. Due to the limitations of the FP16 data type, some algorithms proved insufficient for arrays as small as 100 elements. We propose an algorithm that allows numerically stable FP16 computation of the average and compare it to the naive floating point (FP32) algorithm in terms of both numerical precision and runtime performance. We find that our algorithm offers comparable robustness, numerical precision, and SIMD performance to the higher precision computation.

rawbooktitle:
{2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD): Lyon, France, 24--27 September 2018}

entry:
@InProceedings{Peou:2018:CSO,
  author =       "Kenny Peou and Alan Kelly and Joel Falcou and Cecile
                 Germain",
  editor =       "{IEEE}",
  booktitle =    "{2018 30th International Symposium on Computer
                 Architecture and High Performance Computing (SBAC-PAD):
                 Lyon, France, 24--27 September 2018}",
  title =        "A Case Study on Optimizing Accurate Half Precision
                 Average",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "356--363",
  month =        sep,
  year =         "2018",
  DOI =          "https://doi.org/10.1109/cahpc.2018.8645923",
  ISBN =         "1-5386-7769-5",
  ISBN-13 =      "978-1-5386-7769-8",
  bibdate =      "Fri Apr 11 08:36:46 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this work, we study the numerical performance of
                 various common algorithms used to calculate the average
                 of an array of half precision (FP16) floating point
                 values. While the current generation of CPUs does not
                 support native FP16 arithmetic, it is a planned feature
                 in a number of next-generation CPUs. FP16 arithmetic
                 was emulated via the half software library. Due to the
                 limitations of the FP16 data type, some algorithms
                 proved insufficient for arrays as small as 100
                 elements. We propose an algorithm that allows
                 numerically stable FP16 computation of the average and
                 compare it to the naive floating point (FP32) algorithm
                 in terms of both numerical precision and runtime
                 performance. We find that our algorithm offers
                 comparable robustness, numerical precision, and SIMD
                 performance to the higher precision computation.",
  acknowledgement = ack-nhfb,
  keywords =     "Clustering algorithms; Half-Precision; Machine
                 learning algorithms; Memory management; Numerical
                 Precision; Program processors; Random access memory;
                 Registers; SIMD; Software algorithms",
}


bibtype: inproceedings
filename: fparith.bib
label: Podobas:2018:HIP
author: Artur Podobas and Satoshi Matsuoka
editor: IEEE
booktitle: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
title: Hardware Implementation of POSITs and Their Application in FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 138--145
year: 2018
DOI: https://doi.org/10.1109/IPDPSW.2018.00029
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Artur Podobas and Satoshi Matsuoka
rawbooktitle: {2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}
raweditor: {IEEE}
rawtitle: Hardware Implementation of {POSITs} and Their Application in {FPGAs}
entry:
@InProceedings{Podobas:2018:HIP,
  author =       "Artur Podobas and Satoshi Matsuoka",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Parallel and Distributed
                 Processing Symposium Workshops (IPDPSW)}",
  title =        "Hardware Implementation of {POSITs} and Their
                 Application in {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "138--145",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/IPDPSW.2018.00029",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Popescu:2018:FPN
author: Valentina Popescu and Marcel Nassar and Xin Wang and Evren Tumer and Tristania Webb
title: Flexpoint: Predictive Numerics for Deep Learning
crossref: Tenca:2018:PIS
pages: 1--4
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464801
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Valentina Popescu and Marcel Nassar and Xin Wang and Evren Tumer and Tristania Webb
rawtitle: {Flexpoint}: Predictive Numerics for Deep Learning
abstract:
Deep learning has been undergoing rapid growth in recent years thanks to its state-of-the-art performance across a wide range of real-world applications. Traditionally neural networks were trained in IEEE-754 binary64 or binary32 format, a common practice in general scientific computing. However, the unique computational requirements of deep neural network training workloads allow for much more efficient and inexpensive alternatives, unleashing a new wave of numerical innovations powering specialized computing hardware. We previously presented Flexpoint, a blocked fixed-point data type combined with a novel predictive exponent management algorithm designed to support training of deep networks without modifications, aiming at a seamless replacement of the binary32 widely in practice today. We showed that Flexpoint with 16-bit mantissa and 5-bit shared exponent (flex16+S) achieved numerical parity to binary32 in training a number of convolutional neural networks. In the current paper we review the continuing trend of predictive numerics enhancing deep neural network training in specialized computing devices such as the Intel Nervana Neural Network Processor.

keywords:
ARITH 2018; ARITH-25; blocked fixed-point data type; convolution; convolutional neural networks; deep learning; Deep Learning; deep neural network training; feedforward neural nets; Flexpoint; floating point arithmetic; general scientific computing; Hardware; learning (artificial intelligence); Machine learning; Market research; Neural networks; Neural Networks; Prediction algorithms; predictive exponent management algorithm; Tensile stress; Training

rawabstract:
Deep learning has been undergoing rapid growth in recent years thanks to its state-of-the-art performance across a wide range of real-world applications. Traditionally neural networks were trained in IEEE-754 binary64 or binary32 format, a common practice in general scientific computing. However, the unique computational requirements of deep neural network training workloads allow for much more efficient and inexpensive alternatives, unleashing a new wave of numerical innovations powering specialized computing hardware. We previously presented Flexpoint, a blocked fixed-point data type combined with a novel predictive exponent management algorithm designed to support training of deep networks without modifications, aiming at a seamless replacement of the binary32 widely in practice today. We showed that Flexpoint with 16-bit mantissa and 5-bit shared exponent (flex16+S) achieved numerical parity to binary32 in training a number of convolutional neural networks. In the current paper we review the continuing trend of predictive numerics enhancing deep neural network training in specialized computing devices such as the Intel Nervana Neural Network Processor.

entry:
@InProceedings{Popescu:2018:FPN,
  author =       "Valentina Popescu and Marcel Nassar and Xin Wang and
                 Evren Tumer and Tristania Webb",
  title =        "{Flexpoint}: Predictive Numerics for Deep Learning",
  crossref =     "Tenca:2018:PIS",
  pages =        "1--4",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464801",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Deep learning has been undergoing rapid growth in
                 recent years thanks to its state-of-the-art performance
                 across a wide range of real-world applications.
                 Traditionally neural networks were trained in IEEE-754
                 binary64 or binary32 format, a common practice in
                 general scientific computing. However, the unique
                 computational requirements of deep neural network
                 training workloads allow for much more efficient and
                 inexpensive alternatives, unleashing a new wave of
                 numerical innovations powering specialized computing
                 hardware. We previously presented Flexpoint, a blocked
                 fixed-point data type combined with a novel predictive
                 exponent management algorithm designed to support
                 training of deep networks without modifications, aiming
                 at a seamless replacement of the binary32 widely in
                 practice today. We showed that Flexpoint with 16-bit
                 mantissa and 5-bit shared exponent (flex16+S) achieved
                 numerical parity to binary32 in training a number of
                 convolutional neural networks. In the current paper we
                 review the continuing trend of predictive numerics
                 enhancing deep neural network training in specialized
                 computing devices such as the Intel Nervana Neural
                 Network Processor.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2018; ARITH-25; blocked fixed-point data type;
                 convolution; convolutional neural networks; deep
                 learning; Deep Learning; deep neural network training;
                 feedforward neural nets; Flexpoint; floating point
                 arithmetic; general scientific computing; Hardware;
                 learning (artificial intelligence); Machine learning;
                 Market research; Neural networks; Neural Networks;
                 Prediction algorithms; predictive exponent management
                 algorithm; Tensile stress; Training",
}


bibtype: article
filename: fparith.bib
label: Radford:2018:FIF
author: Peter Radford
title: A ``Feature'' of IBM 360 Floating Point
journal: Resurrection: The Journal of the Computer Conservation Society
number: 82
pages: ??--??
month: Summer
year: 2018
ISSN: 0958-7403 OR 09587403
ISSNL: 0958-7403 OR 09587403
bibdate: Mon Jul 27 18:19:06 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.07.27 18:19:06 ???
URL: https://computerconservationsociety.org/resurrection/res82.htm#f
acknowledgement: ack-nhfb
rawauthor: Peter Radford
rawtitle: A {``Feature''} of {IBM 360} Floating Point
remark:
The short article discusses the impact of hexadecimal normalization on representation of decimal input values, and ends with the statement: ``32-bit floating point remains an elephant trap for programmers to this day.''.

entry:
@Article{Radford:2018:FIF,
  author =       "Peter Radford",
  title =        "A {``Feature''} of {IBM 360} Floating Point",
  journal =      "Resurrection: The Journal of the Computer Conservation
                 Society",
  volume =       "??",
  number =       "82",
  pages =        "??--??",
  month =        "Summer",
  year =         "2018",
  ISSN =         "0958-7403",
  ISSN-L =       "0958-7403",
  bibdate =      "Mon Jul 27 18:19:06 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://computerconservationsociety.org/resurrection/res82.htm#f",
  acknowledgement = ack-nhfb,
  remark =       "The short article discusses the impact of hexadecimal
                 normalization on representation of decimal input
                 values, and ends with the statement: ``32-bit floating
                 point remains an elephant trap for programmers to this
                 day.''.",
}


bibtype: inproceedings
filename: fparith.bib
label: Ram:2018:FVF
author: Ravi Ram and Adam Elkins and Adnan Pratama and Sasa Stamenkovic and Sven Beyer and Sergio Marchese
booktitle: Proceedings of DVCon US 2018
title: Formal Verification of Floating-Point Hardware with Assertion-Based VIP
pages: 1--9
day: 5
month: jun
monthnumber: 6
year: 2018
bibdate: Fri Sep 28 06:20:43 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:20:43 ???
acknowledgement: ack-nhfb
rawauthor: Ravi Ram and Adam Elkins and Adnan Pratama and Sasa Stamenkovic and Sven Beyer and Sergio Marchese
rawbooktitle: Proceedings of {DVCon US 2018}
rawtitle: Formal Verification of Floating-Point Hardware with Assertion-Based {VIP}
URL:
https://www.onespin.com/fileadmin/user_upload/pdf/whitepapers/Formal_Verification_of_Floating_Point_Hardware.pdf

abstract:
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.

rawabstract:
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.

entry:
@InProceedings{Ram:2018:FVF,
  author =       "Ravi Ram and Adam Elkins and Adnan Pratama and Sasa
                 Stamenkovic and Sven Beyer and Sergio Marchese",
  editor =       "????",
  booktitle =    "Proceedings of {DVCon US 2018}",
  title =        "Formal Verification of Floating-Point Hardware with
                 Assertion-Based {VIP}",
  publisher =    "????",
  address =      "????",
  pages =        "1--9",
  day =          "5",
  month =        jun,
  year =         "2018",
  bibdate =      "Fri Sep 28 06:20:43 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.onespin.com/fileadmin/user_upload/pdf/whitepapers/Formal_Verification_of_Floating_Point_Hardware.pdf",
  abstract =     "Hardware for integer or fixed-point arithmetic is
                 relatively simple to design, at least at the
                 register-transfer level. If the range of values and
                 precision that can be represented with these formats is
                 not sufficient for the target application,
                 floating-point hardware might be required.
                 Unfortunately, floating-point units are complex to
                 design, and notoriously challenging to verify. Since
                 the famous 1994 Intel Pentium bug, many companies have
                 investigated and successfully applied formal methods to
                 this task. However, solutions often rely on a mix of
                 the following: hard-to-use formal tools; highly
                 specialized engineering skills; availability of a
                 suitable executable model of the hardware; and
                 significant, design-specific engineering effort. In
                 this paper, we present an alternative floating-point
                 hardware verification approach based on a reusable,
                 IEEE 754 compliant SystemVerilog arithmetic library.
                 While not addressing all verification challenges, this
                 method enables engineers to set up a formal testbench
                 and uncover deep corner-case bugs with minimal effort.
                 Results from industrial applications are reported.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Reddy:2018:DAD
author: K. Manikantta Reddy and M. H. Vasantha and Y. B. Nithin Kumar and Devesh Dwivedi
booktitle: 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
title: Design of Approximate Dividers for Error Tolerant Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--9
month: aug
monthnumber: 8
year: 2018
DOI: https://doi.org/10.1109/mwscas.2018.8623909
bibdate: Wed Dec 20 07:39:14 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:39:14 ???
acknowledgement: ack-nhfb
rawauthor: K. Manikantta Reddy and M. H. Vasantha and Y. B. Nithin Kumar and Devesh Dwivedi
rawbooktitle: {2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)}
rawtitle: Design of Approximate Dividers for Error Tolerant Applications
entry:
@InProceedings{Reddy:2018:DAD,
  author =       "K. Manikantta Reddy and M. H. Vasantha and Y. B.
                 Nithin Kumar and Devesh Dwivedi",
  booktitle =    "{2018 IEEE 61st International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "Design of Approximate Dividers for Error Tolerant
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  month =        aug,
  year =         "2018",
  DOI =          "https://doi.org/10.1109/mwscas.2018.8623909",
  bibdate =      "Wed Dec 20 07:39:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Reyhani-Masoleh:2018:NAR
author: Arash Reyhani-Masoleh and Mostafa Taha and Doaa Ashmawy
title: New Area Record for the AES Combined S-Box / Inverse S-Box
crossref: Tenca:2018:PIS
pages: 145--152
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464780
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Arash Reyhani-Masoleh and Mostafa Taha and Doaa Ashmawy
rawtitle: New Area Record for the {AES} Combined {S}-Box\slash Inverse {S}-Box
abstract:
The AES combined S-box/inverse S-box is a single construction that is shared between the encryption and decryption data paths of the AES. The currently most compact implementation of the AES combined S-box/inverse S-box is Canright's design, introduced back in 2005. Since then, the research community has introduced several optimizations over the S-box only, however the combined S-boxlinverse S-box received little attention. In this paper, we propose a new AES combined S-boxlinverse S-box design that is both smaller and faster than Canright's design. We achieve this goal by proposing to use new tower field and optimizing each and every block inside the combined architecture for this field. Our complexity analysis and ASIC implementation results in the CMOS STM 65nm and NanGate 15nm technologies show that our design outperforms the counterparts in terms of area and speed.

keywords:
AES combined S-box-inverse S-box; application specific integrated circuits; ARITH 2018; ARITH-25; Canright design; circuit optimisation; CMOS STM; Complexity theory; Computer architecture; cryptography; decryption data paths; Encryption; encryption data paths; Generators; Logic gates; Multiplexing; NanGate; Poles and towers; size 15.0 nm; size 65.0 nm

rawabstract:
The AES combined S-box/inverse S-box is a single construction that is shared between the encryption and decryption data paths of the AES. The currently most compact implementation of the AES combined S-box/inverse S-box is Canright's design, introduced back in 2005. Since then, the research community has introduced several optimizations over the S-box only, however the combined S-boxlinverse S-box received little attention. In this paper, we propose a new AES combined S-boxlinverse S-box design that is both smaller and faster than Canright's design. We achieve this goal by proposing to use new tower field and optimizing each and every block inside the combined architecture for this field. Our complexity analysis and ASIC implementation results in the CMOS STM 65nm and NanGate 15nm technologies show that our design outperforms the counterparts in terms of area and speed.

entry:
@InProceedings{Reyhani-Masoleh:2018:NAR,
  author =       "Arash Reyhani-Masoleh and Mostafa Taha and Doaa
                 Ashmawy",
  title =        "New Area Record for the {AES} Combined {S}-Box\slash
                 Inverse {S}-Box",
  crossref =     "Tenca:2018:PIS",
  pages =        "145--152",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464780",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The AES combined S-box/inverse S-box is a single
                 construction that is shared between the encryption and
                 decryption data paths of the AES. The currently most
                 compact implementation of the AES combined
                 S-box/inverse S-box is Canright's design, introduced
                 back in 2005. Since then, the research community has
                 introduced several optimizations over the S-box only,
                 however the combined S-boxlinverse S-box received
                 little attention. In this paper, we propose a new AES
                 combined S-boxlinverse S-box design that is both
                 smaller and faster than Canright's design. We achieve
                 this goal by proposing to use new tower field and
                 optimizing each and every block inside the combined
                 architecture for this field. Our complexity analysis
                 and ASIC implementation results in the CMOS STM 65nm
                 and NanGate 15nm technologies show that our design
                 outperforms the counterparts in terms of area and
                 speed.",
  acknowledgement = ack-nhfb,
  keywords =     "AES combined S-box-inverse S-box; application specific
                 integrated circuits; ARITH 2018; ARITH-25; Canright
                 design; circuit optimisation; CMOS STM; Complexity
                 theory; Computer architecture; cryptography; decryption
                 data paths; Encryption; encryption data paths;
                 Generators; Logic gates; Multiplexing; NanGate; Poles
                 and towers; size 15.0 nm; size 65.0 nm",
}


bibtype: inproceedings
filename: fparith.bib
label: Riedy:2018:AAO
author: Jason Riedy and James Demmel
title: Augmented Arithmetic Operations Proposed for IEEE-754 2018
crossref: Tenca:2018:PIS
pages: 45--52
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464813
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Jason Riedy and James Demmel
rawtitle: Augmented Arithmetic Operations Proposed for {IEEE-754 2018}
abstract:
Algorithms for extending arithmetic precision through compensated summation or arithmetics like double-double rely on operations commonly called twoSum and twoProduct. The current draft of the IEEE 754 standard specifies these operations under the names augmentedAddition and augmentedMultiplication. These operations were included after three decades of experience because of a motivating new use: bitwise reproducible arithmetic. Standardizing the operations provides a hardware acceleration target that can provide at least a 33% speed improvements in reproducible dot product, placing reproducible dot product almost within a factor of two of common dot product. This paper provides history and motivation for standardizing these operations. We also define the operations, explain the rationale for all the specific choices, and provide parameterized test cases for new boundary behaviors.

keywords:
Acceleration; ARITH 2018; ARITH-25; arithmetic precision; augmented arithmetic operations; bitwise reproducible arithmetic; common dot product; floating point arithmetic; Hardware; hardware acceleration target; History; IEEE 754 standard; IEEE standards; IEEE-754 2018; Libraries; Magnetic heads; reproducible dot product; Software; Standards

rawabstract:
Algorithms for extending arithmetic precision through compensated summation or arithmetics like double-double rely on operations commonly called twoSum and twoProduct. The current draft of the IEEE 754 standard specifies these operations under the names augmentedAddition and augmentedMultiplication. These operations were included after three decades of experience because of a motivating new use: bitwise reproducible arithmetic. Standardizing the operations provides a hardware acceleration target that can provide at least a 33\% speed improvements in reproducible dot product, placing reproducible dot product almost within a factor of two of common dot product. This paper provides history and motivation for standardizing these operations. We also define the operations, explain the rationale for all the specific choices, and provide parameterized test cases for new boundary behaviors.

entry:
@InProceedings{Riedy:2018:AAO,
  author =       "Jason Riedy and James Demmel",
  title =        "Augmented Arithmetic Operations Proposed for {IEEE-754
                 2018}",
  crossref =     "Tenca:2018:PIS",
  pages =        "45--52",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464813",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Algorithms for extending arithmetic precision through
                 compensated summation or arithmetics like double-double
                 rely on operations commonly called twoSum and
                 twoProduct. The current draft of the IEEE 754 standard
                 specifies these operations under the names
                 augmentedAddition and augmentedMultiplication. These
                 operations were included after three decades of
                 experience because of a motivating new use: bitwise
                 reproducible arithmetic. Standardizing the operations
                 provides a hardware acceleration target that can
                 provide at least a 33\% speed improvements in
                 reproducible dot product, placing reproducible dot
                 product almost within a factor of two of common dot
                 product. This paper provides history and motivation for
                 standardizing these operations. We also define the
                 operations, explain the rationale for all the specific
                 choices, and provide parameterized test cases for new
                 boundary behaviors.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; ARITH 2018; ARITH-25; arithmetic
                 precision; augmented arithmetic operations; bitwise
                 reproducible arithmetic; common dot product; floating
                 point arithmetic; Hardware; hardware acceleration
                 target; History; IEEE 754 standard; IEEE standards;
                 IEEE-754 2018; Libraries; Magnetic heads; reproducible
                 dot product; Software; Standards",
}


bibtype: article
filename: fparith.bib
label: Rodriguez-Henriquez:2018:SIH
author: Francisco Rodriguez-Henriquez and Erkay Savas
title: Special issue in honor of Peter Lawrence Montgomery
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 185--187
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0168-3
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Francisco Rodr{\'\i}guez-Henr{\'\i}quez and Erkay Savas
rawtitle: Special issue in honor of {Peter Lawrence Montgomery}
URL:
http://link.springer.com/article/10.1007/s13389-017-0168-3; https://link.springer.com/content/pdf/10.1007/s13389-017-0168-3.pdf

entry:
@Article{Rodriguez-Henriquez:2018:SIH,
  author =       "Francisco Rodr{\'\i}guez-Henr{\'\i}quez and Erkay
                 Savas",
  title =        "Special issue in honor of {Peter Lawrence
                 Montgomery}",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "185--187",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0168-3",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0168-3;
                 https://link.springer.com/content/pdf/10.1007/s13389-017-0168-3.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Saadat:2018:MBM
author: Hassaan Saadat and Haseeb Bokhari and Sri Parameswaran
title: Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
journal: j-IEEE-TRANS-CAD-ICS
volume: 37
number: 11
pages: 2623--2635
month: nov
monthnumber: 11
year: 2018
CODEN: ITCSDI
DOI: https://doi.org/10.1109/tcad.2018.2857262
ISSN: 0278-0070 (print), 1937-4151 (electronic) OR 02780070 (print), 19374151 (electronic)
ISSNL: 0278-0070 OR 02780070
bibdate: Wed Dec 20 07:46:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:46:25 ???
fjournal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43
rawauthor: Hassaan Saadat and Haseeb Bokhari and Sri Parameswaran
rawtitle: Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
entry:
@Article{Saadat:2018:MBM,
  author =       "Hassaan Saadat and Haseeb Bokhari and Sri
                 Parameswaran",
  title =        "Minimally Biased Multipliers for Approximate Integer
                 and Floating-Point Multiplication",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "37",
  number =       "11",
  pages =        "2623--2635",
  month =        nov,
  year =         "2018",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/tcad.2018.2857262",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Wed Dec 20 07:46:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}


bibtype: article
filename: fparith.bib
label: Sanchez-Stern:2018:FRC
author: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
title: Finding root causes of floating point error
journal: j-SIGPLAN
volume: 53
number: 4
pages: 256--269
month: apr
monthnumber: 4
year: 2018
CODEN: SINODQ
DOI: https://doi.org/10.1145/3296979.3192411
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Wed Oct 16 14:12:57 MDT 2019
bibtimestamp: 2019.10.16 14:12:57 MDT
fjournal: ACM SIGPLAN Notices
remark: PLDI '18 proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
rawtitle: Finding root causes of floating point error
abstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level languages like C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to simplified program fragments whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries and tracking error across function boundaries and through the heap.

rawabstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level languages like C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to simplified program fragments whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries and tracking error across function boundaries and through the heap.

entry:
@Article{Sanchez-Stern:2018:FRC,
  author =       "Alex Sanchez-Stern and Pavel Panchekha and Sorin
                 Lerner and Zachary Tatlock",
  title =        "Finding root causes of floating point error",
  journal =      j-SIGPLAN,
  volume =       "53",
  number =       "4",
  pages =        "256--269",
  month =        apr,
  year =         "2018",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3296979.3192411",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Wed Oct 16 14:12:57 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Floating-point arithmetic plays a central role in
                 science, engineering, and finance by enabling
                 developers to approximate real arithmetic. To address
                 numerical issues in large floating-point applications,
                 developers must identify root causes, which is
                 difficult because floating-point errors are generally
                 non-local, non-compositional, and non-uniform. This
                 paper presents Herbgrind, a tool to help developers
                 identify and address root causes in numerical code
                 written in low-level languages like C/C++ and Fortran.
                 Herbgrind dynamically tracks dependencies between
                 operations and program outputs to avoid false positives
                 and abstracts erroneous computations to simplified
                 program fragments whose improvement can reduce output
                 error. We perform several case studies applying
                 Herbgrind to large, expert-crafted numerical programs
                 and show that it scales to applications spanning
                 hundreds of thousands of lines, correctly handling the
                 low-level details of modern floating point hardware and
                 mathematical libraries and tracking error across
                 function boundaries and through the heap.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "PLDI '18 proceedings.",
}


bibtype: article
filename: fparith.bib
label: Savas:2018:MI
author: Erkay Savas and Cetin Kaya Koc
title: Montgomery inversion
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 201--210
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0161-x
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0161-x
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Erkay Savas and {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: {Montgomery} inversion
entry:
@Article{Savas:2018:MI,
  author =       "Erkay Savas and {\c{C}}etin Kaya Ko{\c{c}}",
  title =        "{Montgomery} inversion",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "201--210",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0161-x",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0161-x",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Schneider:2018:USS
author: D. Schneider
title: U.S. supercomputing strikes back
journal: j-IEEE-SPECTRUM
volume: 55
number: 1
pages: 52--53
month: jan
monthnumber: 1
year: 2018
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2018.8241739
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Sat Jan 18 07:02:09 2020
bibtimestamp: 2020.01.18 07:02:09 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: D. Schneider
rawtitle: {U.S.} supercomputing strikes back
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib; https://www.math.utah.edu/pub/tex/bib/super.bib

keywords:
Companies; Computational modeling; floating-point operations; Games; Hardware; parallel machines; Payloads; petaflops; Rockets; Supercomputers; Titan machine; U.S. high-performance computing community; U.S. supercomputing

entry:
@Article{Schneider:2018:USS,
  author =       "D. Schneider",
  title =        "{U.S.} supercomputing strikes back",
  journal =      j-IEEE-SPECTRUM,
  volume =       "55",
  number =       "1",
  pages =        "52--53",
  month =        jan,
  year =         "2018",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2018.8241739",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Sat Jan 18 07:02:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/super.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "Companies; Computational modeling; floating-point
                 operations; Games; Hardware; parallel machines;
                 Payloads; petaflops; Rockets; Supercomputers; Titan
                 machine; U.S. high-performance computing community;
                 U.S. supercomputing",
}


bibtype: article
filename: fparith.bib
label: Seo:2018:FBM
author: Jungjoo Seo and Kunsoo Park
title: Fast batch modular exponentiation with common-multiplicand multiplication
journal: j-INFO-PROC-LETT
volume: 129
pages: 5--10
month: jan
monthnumber: 1
year: 2018
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Mon Oct 30 08:48:26 MDT 2017
bibtimestamp: 2017.10.30 08:48:26 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0020019017301527
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Jungjoo Seo and Kunsoo Park
rawtitle: Fast batch modular exponentiation with common-multiplicand multiplication
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib

entry:
@Article{Seo:2018:FBM,
  author =       "Jungjoo Seo and Kunsoo Park",
  title =        "Fast batch modular exponentiation with
                 common-multiplicand multiplication",
  journal =      j-INFO-PROC-LETT,
  volume =       "129",
  number =       "??",
  pages =        "5--10",
  month =        jan,
  year =         "2018",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Mon Oct 30 08:48:26 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0020019017301527",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: misc
filename: fparith.bib
label: Shirriff:2018:TBP
author: Ken Shirriff
title: Two bits per transistor: high-density ROM in Intel's 8087 floating point chip
pages: 16
month: sep
monthnumber: 9
year: 2018
bibdate: Sat Aug 23 07:23:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.08.23 07:23:18 ???
acknowledgement: ack-nhfb
howpublished: Blog posting
rawauthor: Ken Shirriff
rawtitle: Two bits per transistor: high-density {ROM} in {Intel}'s 8087 floating point chip
note:
Analysis of the transistors invented by the 8087 team in order to reduce the footprint of the microcode ROM on the die. See patent cite Stark:1981:MBR.

URL:
https://ieeemilestones.ethw.org/w/images/6/66/Shirriff_8087_two_bit_transistors.pdf; https://www.righto.com/2018/09/two-bits-per-transistor-high-density.html

rawnote:
Analysis of the transistors invented by the 8087 team in order to reduce the footprint of the microcode ROM on the die. See patent \cite{Stark:1981:MBR}.

entry:
@Misc{Shirriff:2018:TBP,
  author =       "Ken Shirriff",
  title =        "Two bits per transistor: high-density {ROM} in
                 {Intel}'s 8087 floating point chip",
  howpublished = "Blog posting",
  pages =        "16",
  month =        sep,
  year =         "2018",
  bibdate =      "Sat Aug 23 07:23:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Analysis of the transistors invented by the 8087 team
                 in order to reduce the footprint of the microcode ROM
                 on the die. See patent \cite{Stark:1981:MBR}.",
  URL =          "https://ieeemilestones.ethw.org/w/images/6/66/Shirriff_8087_two_bit_transistors.pdf;
                 https://www.righto.com/2018/09/two-bits-per-transistor-high-density.html",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Trader:2018:ICS
author: Tiffany Trader
title: Inventor Claims to Have Solved Floating Point Error Problem
pages: 16
day: 17
month: jan
monthnumber: 1
year: 2018
bibdate: Fri Mar 23 19:13:03 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.23 19:13:03 ???
URL: https://www.hpcwire.com/2018/01/17/inventor-claims-solved-floating-point-error-problem/
acknowledgement: ack-nhfb
howpublished: HPC Web site.
rawauthor: Tiffany Trader
rawtitle: Inventor Claims to Have Solved Floating Point Error Problem
note:
From the HPC editor: ``After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, booktitle The End of Error, which was published 19 months before Jorgensen's patent application was filed. ''

rawnote:
From the HPC editor: ``After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, \booktitle{The End of Error}, which was published 19 months before Jorgensen's patent application was filed. ''

entry:
@Misc{Trader:2018:ICS,
  author =       "Tiffany Trader",
  title =        "Inventor Claims to Have Solved Floating Point Error
                 Problem",
  howpublished = "HPC Web site.",
  day =          "17",
  month =        jan,
  year =         "2018",
  bibdate =      "Fri Mar 23 19:13:03 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "From the HPC editor: ``After this article was
                 published, a number of readers raised concerns about
                 the originality of Jorgensen's techniques, noting the
                 existence of prior art going back years. Specifically,
                 there is precedent in John Gustafson's work on unums
                 and interval arithmetic both at Sun and in his 2015
                 book, \booktitle{The End of Error}, which was published
                 19 months before Jorgensen's patent application was
                 filed. ''",
  URL =          "https://www.hpcwire.com/2018/01/17/inventor-claims-solved-floating-point-error-problem/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Villalba-Moreno:2018:FHF
author: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonzalez-Navarro
title: Fast HUB Floating-point Adder for FPGA
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 66
number: 6
pages: 1028--1032
month: jun
monthnumber: 6
year: 2018
DOI: https://doi.org/10.1109/TCSII.2018.2873194
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Mon Feb 10 08:25:14 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 08:25:14 ???
URL: https://ieeexplore.ieee.org/document/8477084
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
keywords: HUB (Half-Unit-Biased) floating-point format
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Circuits Syst., II Express Briefs
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonz{\'a}lez-Navarro
rawtitle: Fast {HUB} Floating-point Adder for {FPGA}
entry:
@Article{Villalba-Moreno:2018:FHF,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Sonia
                 Gonz{\'a}lez-Navarro",
  title =        "Fast {HUB} Floating-point Adder for {FPGA}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "66",
  number =       "6",
  pages =        "1028--1032",
  month =        jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/TCSII.2018.2873194",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Mon Feb 10 08:25:14 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/8477084",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Circuits Syst., II Express Briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "HUB (Half-Unit-Biased) floating-point format",
}


bibtype: article
filename: fparith.bib
label: Villalba-Moreno:2018:URH
author: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonzalez-Navarro
title: Unbiased Rounding for HUB Floating-Point Addition
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 9
pages: 1359--1365
month: sep
monthnumber: 9
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2807429
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Mar 15 08:10:13 2019
bibtimestamp: 2019.03.15 08:10:13 ???
URL: https://ieeexplore.ieee.org/document/8300633/
fjournal: IEEE Transactions on Computers
keywords: HUB (Half-Unit-Biased) floating-point format
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonz{\'a}lez-Navarro
rawtitle: Unbiased Rounding for {HUB} Floating-Point Addition
entry:
@Article{Villalba-Moreno:2018:URH,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Sonia
                 Gonz{\'a}lez-Navarro",
  title =        "Unbiased Rounding for {HUB} Floating-Point Addition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "9",
  pages =        "1359--1365",
  month =        sep,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2807429",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Mar 15 08:10:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8300633/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "HUB (Half-Unit-Biased) floating-point format",
}


bibtype: article
filename: fparith.bib
label: Walczyk:2018:IAF
author: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cieslinski
title: Improving the accuracy of the fast inverse square root algorithm
journal: arXiv.org
pages: 1--21
day: 17
month: feb
monthnumber: 2
year: 2018
DOI: https://doi.org/10.48550/arXiv.1802.06302
bibdate: Wed Dec 20 07:55:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:55:45 ???
URL: https://arxiv.org/abs/1802.06302
acknowledgement: ack-nhfb
rawauthor: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cie{\'s}li{\'n}ski
rawtitle: Improving the accuracy of the fast inverse square root algorithm
abstract:
We present improved algorithms for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithms are much more accurate than the famous fast inverse square root algorithm and have the same or similar computational cost. The main idea of our work consists in modifying the Newton-Raphson method and demanding that the maximal error is as small as possible. Such modification is possible when the distribution of Newton-Raphson corrections is not symmetric (e.g., if they are non-positive functions).

rawabstract:
We present improved algorithms for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithms are much more accurate than the famous fast inverse square root algorithm and have the same or similar computational cost. The main idea of our work consists in modifying the Newton-Raphson method and demanding that the maximal error is as small as possible. Such modification is possible when the distribution of Newton-Raphson corrections is not symmetric (e.g., if they are non-positive functions).

entry:
@Article{Walczyk:2018:IAF,
  author =       "Cezary J. Walczyk and Leonid V. Moroz and Jan L.
                 Cie{\'s}li{\'n}ski",
  title =        "Improving the accuracy of the fast inverse square root
                 algorithm",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--21",
  day =          "17",
  month =        feb,
  year =         "2018",
  DOI =          "https://doi.org/10.48550/arXiv.1802.06302",
  bibdate =      "Wed Dec 20 07:55:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1802.06302",
  abstract =     "We present improved algorithms for fast calculation of
                 the inverse square root for single-precision
                 floating-point numbers. The algorithms are much more
                 accurate than the famous fast inverse square root
                 algorithm and have the same or similar computational
                 cost. The main idea of our work consists in modifying
                 the Newton-Raphson method and demanding that the
                 maximal error is as small as possible. Such
                 modification is possible when the distribution of
                 Newton-Raphson corrections is not symmetric (e.g., if
                 they are non-positive functions).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2018:TDN
author: Naigang Wang and Jungwook Choi and Daniel Brand and Chia-Yu Chen and Kailash Gopalakrishnan
editor: S. Bengio and others
title: Training Deep Neural Networks with 8-bit Floating Point Numbers
publisher: Curran Associates, Inc.
pages: 7675--7684
year: 2018
bibdate: Wed Dec 19 19:17:48 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.12.19 19:17:48 ???
acknowledgement: ack-nhfb
rawauthor: Naigang Wang and Jungwook Choi and Daniel Brand and Chia-Yu Chen and Kailash Gopalakrishnan
raweditor: S. Bengio and others
rawtitle: Training {Deep Neural Networks} with 8-bit Floating Point Numbers
booktitle:
Proceedings of the 32nd Conference on Neural Information Processing Systems (NeurIPS 2018), Montreal, Canada

URL:
https://arxiv.org/abs/1812.08011; https://papers.nips.cc/paper/7994-training-deep-neural-networks-with-8-bit-floating-point-numbers.pdf

abstract:
The state-of-the-art hardware platforms for training Deep Neural Networks (DNNs) are moving from traditional single precision (32-bit) computations towards 16 bits of precision in large part due to the high energy efficiency and smaller bit storage associated with using reduced-precision representations. However, unlike inference, training with numbers represented with less than 16 bits has been challenging due to the need to maintain fidelity of the gradient computations during back-propagation. Here we demonstrate, for the first time, the successful training of DNNs using 8-bit floating point numbers while fully maintaining the accuracy on a spectrum of Deep Learning models and datasets. In addition to reducing the data and computation precision to 8 bits, we also successfully reduce the arithmetic precision for additions (used in partial product accumulation and weight updates) from 32 bits to 16 bits through the introduction of a number of key ideas including chunk-based accumulation and floating point stochastic rounding. The use of these novel techniques lays the foundation for a new generation of hardware training platforms with the potential for 2--4 $ times $ improved throughput over today's systems.

remark:
The 8-bit floating-point format, FP8, has 1 sign bit, 5 exponent bits, and 2 significand bits (1,5,2); the 16-bit format, FP16, has 1 sign bit, 6 exponent bits, and 9 significand bits (1,6,9). There is no mention of Infinity, NaN, signed zeros, or FMA operations

rawabstract:
The state-of-the-art hardware platforms for training Deep Neural Networks (DNNs) are moving from traditional single precision (32-bit) computations towards 16 bits of precision in large part due to the high energy efficiency and smaller bit storage associated with using reduced-precision representations. However, unlike inference, training with numbers represented with less than 16 bits has been challenging due to the need to maintain fidelity of the gradient computations during back-propagation. Here we demonstrate, for the first time, the successful training of DNNs using 8-bit floating point numbers while fully maintaining the accuracy on a spectrum of Deep Learning models and datasets. In addition to reducing the data and computation precision to 8 bits, we also successfully reduce the arithmetic precision for additions (used in partial product accumulation and weight updates) from 32 bits to 16 bits through the introduction of a number of key ideas including chunk-based accumulation and floating point stochastic rounding. The use of these novel techniques lays the foundation for a new generation of hardware training platforms with the potential for 2--4 $ \times $ improved throughput over today's systems.

rawbooktitle:
{Proceedings of the 32nd Conference on Neural Information Processing Systems (NeurIPS 2018), Montr{\'e}al, Canada}

entry:
@InProceedings{Wang:2018:TDN,
  author =       "Naigang Wang and Jungwook Choi and Daniel Brand and
                 Chia-Yu Chen and Kailash Gopalakrishnan",
  editor =       "S. Bengio and others",
  booktitle =    "{Proceedings of the 32nd Conference on Neural
                 Information Processing Systems (NeurIPS 2018),
                 Montr{\'e}al, Canada}",
  title =        "Training {Deep Neural Networks} with 8-bit Floating
                 Point Numbers",
  publisher =    "Curran Associates, Inc.",
  address =      "????",
  pages =        "7675--7684",
  year =         "2018",
  bibdate =      "Wed Dec 19 19:17:48 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1812.08011;
                 https://papers.nips.cc/paper/7994-training-deep-neural-networks-with-8-bit-floating-point-numbers.pdf",
  abstract =     "The state-of-the-art hardware platforms for training
                 Deep Neural Networks (DNNs) are moving from traditional
                 single precision (32-bit) computations towards 16 bits
                 of precision in large part due to the high energy
                 efficiency and smaller bit storage associated with
                 using reduced-precision representations. However,
                 unlike inference, training with numbers represented
                 with less than 16 bits has been challenging due to the
                 need to maintain fidelity of the gradient computations
                 during back-propagation. Here we demonstrate, for the
                 first time, the successful training of DNNs using 8-bit
                 floating point numbers while fully maintaining the
                 accuracy on a spectrum of Deep Learning models and
                 datasets. In addition to reducing the data and
                 computation precision to 8 bits, we also successfully
                 reduce the arithmetic precision for additions (used in
                 partial product accumulation and weight updates) from
                 32 bits to 16 bits through the introduction of a number
                 of key ideas including chunk-based accumulation and
                 floating point stochastic rounding. The use of these
                 novel techniques lays the foundation for a new
                 generation of hardware training platforms with the
                 potential for 2--4 $ \times $ improved throughput over
                 today's systems.",
  acknowledgement = ack-nhfb,
  remark =       "The 8-bit floating-point format, FP8, has 1 sign bit,
                 5 exponent bits, and 2 significand bits (1,5,2); the
                 16-bit format, FP16, has 1 sign bit, 6 exponent bits,
                 and 9 significand bits (1,6,9). There is no mention of
                 Infinity, NaN, signed zeros, or FMA operations",
  xxpages =      "1--10",
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:2018:OMP
editor: IEEE
booktitle: 2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR)
title: An Omnidirectional and Movable Palletizing Robot based on Computer Vision Positing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 423--428
year: 2018
DOI: https://doi.org/10.1109/IISR.2018.8535688
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR)}
raweditor: {IEEE}
rawtitle: An Omnidirectional and Movable Palletizing Robot based on Computer Vision Positing
author:
Xiong Yang and Hongbin Zhang and Tianyou Cheng and Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian Lu and Zhiguo Lu and Yajing Shen

rawauthor:
Xiong Yang and Hongbin Zhang and Tianyou Cheng and Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian Lu and Zhiguo Lu and Yajing Shen

entry:
@InProceedings{Yang:2018:OMP,
  author =       "Xiong Yang and Hongbin Zhang and Tianyou Cheng and
                 Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian
                 Lu and Zhiguo Lu and Yajing Shen",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Conference on Intelligence
                 and Safety for Robotics (ISR)}",
  title =        "An Omnidirectional and Movable Palletizing Robot based
                 on Computer Vision Positing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "423--428",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/IISR.2018.8535688",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Yeshwanth:2018:HSS
author: Balaji Yeshwanth and Vutukuri Venkatesh and Repala Akhil
title: High-Speed Single Precision Floating Point Multiplier using CORDIC Algorithm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 135--141
year: 2018
DOI: https://doi.org/10.1109/ICEECCOT43722.2018.9001506
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Balaji Yeshwanth and Vutukuri Venkatesh and Repala Akhil
rawtitle: High-Speed Single Precision Floating Point Multiplier using {CORDIC} Algorithm
booktitle:
2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)

keywords:
Adders; Clocks; Computer architecture; CORDIC algorithm; Delays; Kogge-Stone adder; Parallel Prefixadder; Pipelines; Routing; Signal processing algorithms; Single precision floating point multiplier; Vedic multiplier

rawbooktitle:
{2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)}

entry:
@InProceedings{Yeshwanth:2018:HSS,
  author =       "Balaji Yeshwanth and Vutukuri Venkatesh and Repala
                 Akhil",
  booktitle =    "{2018 International Conference on Electrical,
                 Electronics, Communication, Computer, and Optimization
                 Techniques (ICEECCOT)}",
  title =        "High-Speed Single Precision Floating Point Multiplier
                 using {CORDIC} Algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "135--141",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ICEECCOT43722.2018.9001506",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; Clocks; Computer architecture; CORDIC
                 algorithm; Delays; Kogge-Stone adder; Parallel
                 Prefixadder; Pipelines; Routing; Signal processing
                 algorithms; Single precision floating point multiplier;
                 Vedic multiplier",
}


bibtype: article
filename: fparith.bib
label: Zhang:2018:HSA
author: Yunxiang Zhang and Xiaokun Yang and Lei Wu and Archit Gajjar and Han He
journal: j-INT-J-COMP-APPL
volume: 180
pages: 1--7
month: feb
monthnumber: 2
year: 2018
DOI: https://doi.org/10.5120/ijca2018916380
ISSN: 0975-8887 OR 09758887
ISSNL: 0975-8887 OR 09758887
bibdate: Fri Jan 24 09:43:10 MST 2025
bibtimestamp: 2025.01.24 09:43:10 MST
URL: https://www.ijcaonline.org/archives/volume180/number17/29021-2018916380/
fjournal: International Journal of Computer Applications
acknowledgement: ack-nhfb
ajournal: Intern. J. of Computer Applications
articleno: 17
journalURL: https://www.ijcaonline.org/
rawauthor: Yunxiang Zhang and Xiaokun Yang and Lei Wu and Archit Gajjar and Han He
title:
Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System

rawtitle:
Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays {(FPGA)-CSRmesh} System

entry:
@Article{Zhang:2018:HSA,
  author =       "Yunxiang Zhang and Xiaokun Yang and Lei Wu and Archit
                 Gajjar and Han He",
  title =        "Hierarchical Synthesis of Approximate Multiplier
                 Design for Field-programmable Gate Arrays
                 {(FPGA)-CSRmesh} System",
  journal =      j-INT-J-COMP-APPL,
  volume =       "180",
  number =       "??",
  pages =        "1--7",
  month =        feb,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.5120/ijca2018916380",
  ISSN =         "0975-8887",
  ISSN-L =       "0975-8887",
  bibdate =      "Fri Jan 24 09:43:10 MST 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/intjcompappl.bib",
  URL =          "https://www.ijcaonline.org/archives/volume180/number17/29021-2018916380/",
  acknowledgement = ack-nhfb,
  ajournal =     "Intern. J. of Computer Applications",
  articleno =    "17",
  fjournal =     "International Journal of Computer Applications",
  journal-URL =  "https://www.ijcaonline.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Abdelfattah:2019:THP
author: Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 17--24
year: 2019
DOI: https://doi.org/10.1109/ScalA49573.2019.00008
bibdate: Wed Oct 1 06:40:18 2025
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra
booktitle:
2019 IEEE/ACM 10th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA)

title:
Towards Half-Precision Computation for Complex Matrices: a Case Study for Mixed Precision Solvers on GPUs

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
Acceleration; Computer architecture; Graphics processing units; Half precision; Kernel; Libraries; mixed-precision solvers; Standards; Tensor cores FP16 arithmetic; Tensors

rawbooktitle:
{2019 IEEE/ACM 10th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA)}

rawtitle:
Towards Half-Precision Computation for Complex Matrices: a Case Study for Mixed Precision Solvers on {GPUs}

entry:
@InProceedings{Abdelfattah:2019:THP,
  author =       "Ahmad Abdelfattah and Stanimire Tomov and Jack
                 Dongarra",
  booktitle =    "{2019 IEEE/ACM 10th Workshop on Latest Advances in
                 Scalable Algorithms for Large-Scale Systems (ScalA)}",
  title =        "Towards Half-Precision Computation for Complex
                 Matrices: a Case Study for Mixed Precision Solvers on
                 {GPUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "17--24",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ScalA49573.2019.00008",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; Computer architecture; Graphics
                 processing units; Half precision; Kernel; Libraries;
                 mixed-precision solvers; Standards; Tensor cores FP16
                 arithmetic; Tensors",
}


bibtype: article
filename: fparith.bib
label: Adams:2019:RRP
author: Ulf Adams
title: Ryu revisited: tt printf floating point conversion
journal: j-PACMPL
volume: 3
number: OOPSLA
pages: 169:1--169:23
month: oct
monthnumber: 10
year: 2019
DOI: https://doi.org/10.1145/3360595
ISSN: 2475-1421 OR 24751421
bibdate: Fri Aug 7 19:22:30 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2020.08.07 19:22:30 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3360595
fjournal: Proceedings of the ACM on Programming Languages
keywords: base conversion
acknowledgement: ack-nhfb
articleno: 169
journalURL: https://pacmpl.acm.org/
rawauthor: Ulf Adams
rawtitle: {Ry{\=u}} revisited: {\tt printf} floating point conversion
abstract:
Ryu Printf is a new algorithm to convert floating-point numbers to decimal strings according to the tt printf tt %f, tt %e, and tt %g formats: tt %f generates `full' output (integer part of the input, dot, configurable number of digits), tt %e generates scientific output (one leading digit, dot, configurable number of digits, exponent), and tt %g generates the shorter of the two. Ryu's Printf is based on the Ryu algorithm, which converts binary floating-point numbers to the shortest equivalent decimal floating-point representation. We provide quantitative evidence that Ryu Printf is between 3.8 and 55 times faster than existing tt printf implementations.par Furthermore, we show that both Ryu and Ryu Printf generalize to arbitrary number bases. This finding implies the existence of a fast algorithm to convert from base-10 to base-2, as long as the maximum precision of the input is known a priori.

rawabstract:
Ry{\=u} Printf is a new algorithm to convert floating-point numbers to decimal strings according to the {\tt printf} {\tt \%f}, {\tt \%e}, and {\tt \%g} formats: {\tt \%f} generates `full' output (integer part of the input, dot, configurable number of digits), {\tt \%e} generates scientific output (one leading digit, dot, configurable number of digits, exponent), and {\tt \%g} generates the shorter of the two. Ry{\=u}'s Printf is based on the Ry{\=u} algorithm, which converts binary floating-point numbers to the shortest equivalent decimal floating-point representation. We provide quantitative evidence that Ry{\=u} Printf is between 3.8 and 55 times faster than existing {\tt printf} implementations.\par Furthermore, we show that both Ry{\=u} and Ry{\=u} Printf generalize to arbitrary number bases. This finding implies the existence of a fast algorithm to convert from base-10 to base-2, as long as the maximum precision of the input is known a priori.

entry:
@Article{Adams:2019:RRP,
  author =       "Ulf Adams",
  title =        "{Ry{\=u}} revisited: {\tt printf} floating point
                 conversion",
  journal =      j-PACMPL,
  volume =       "3",
  number =       "OOPSLA",
  pages =        "169:1--169:23",
  month =        oct,
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3360595",
  ISSN =         "2475-1421",
  bibdate =      "Fri Aug 7 19:22:30 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3360595",
  abstract =     "Ry{\=u} Printf is a new algorithm to convert
                 floating-point numbers to decimal strings according to
                 the {\tt printf} {\tt \%f}, {\tt \%e}, and {\tt \%g}
                 formats: {\tt \%f} generates `full' output (integer
                 part of the input, dot, configurable number of digits),
                 {\tt \%e} generates scientific output (one leading
                 digit, dot, configurable number of digits, exponent),
                 and {\tt \%g} generates the shorter of the two.
                 Ry{\=u}'s Printf is based on the Ry{\=u} algorithm,
                 which converts binary floating-point numbers to the
                 shortest equivalent decimal floating-point
                 representation. We provide quantitative evidence that
                 Ry{\=u} Printf is between 3.8 and 55 times faster than
                 existing {\tt printf} implementations.\par

                 Furthermore, we show that both Ry{\=u} and Ry{\=u}
                 Printf generalize to arbitrary number bases. This
                 finding implies the existence of a fast algorithm to
                 convert from base-10 to base-2, as long as the maximum
                 precision of the input is known a priori.",
  acknowledgement = ack-nhfb,
  articleno =    "169",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
  keywords =     "base conversion",
}


bibtype: misc
filename: fparith.bib
label: Adams:2019:URP
title: ulfjack / ryu: Printf Support
pages: 169:1--169:23
day: 12
month: aug
monthnumber: 8
year: 2019
DOI: https://doi.org/10.5281/zenodo.3366212
bibdate: Sun Aug 16 18:37:00 2020
bibtimestamp: 2020.08.16 18:37:00 ???
URL: https://github.com/ulfjack/ryu/tree/v2.0; https://zenodo.org/record/3366212
acknowledgement: ack-nhfb
howpublished: Web site
rawtitle: {ulfjack\slash ryu}: Printf Support
author:
Ulf Adams and Stephan T. Lavavej and Alexander Bolz and Vinnie Falco and David Tolnay and Mitchell Blank, Jr. and Mara Bos and Caleb Spare and Alexander Iljin

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/java2010.bib

abstract:
This project contains C and Java implementation of Ryu, as well as a C implementation of Ryu Printf. Ryu converts a floating point number to its shortest decimal representation, whereas Ryu Printf converts a floating point number according to the printf %f or %e format. At the time of this writing, these are the fastest known float-to-string conversion algorithms. We have tested the code on Ubuntu 19.04, MacOS Mojave, and Windows 10.

rawabstract:
This project contains C and Java implementation of Ryu, as well as a C implementation of Ryu Printf. Ryu converts a floating point number to its shortest decimal representation, whereas Ryu Printf converts a floating point number according to the printf \%f or \%e format. At the time of this writing, these are the fastest known float-to-string conversion algorithms. We have tested the code on Ubuntu 19.04, MacOS Mojave, and Windows 10.

rawauthor:
Ulf Adams and Stephan T. Lavavej and Alexander Bolz and Vinnie Falco and David Tolnay and Mitchell {Blank, Jr.} and Mara Bos and Caleb Spare and Alexander Iljin

entry:
@Misc{Adams:2019:URP,
  author =       "Ulf Adams and Stephan T. Lavavej and Alexander Bolz
                 and Vinnie Falco and David Tolnay and Mitchell {Blank,
                 Jr.} and Mara Bos and Caleb Spare and Alexander Iljin",
  title =        "{ulfjack\slash ryu}: Printf Support",
  howpublished = "Web site",
  day =          "12",
  month =        aug,
  year =         "2019",
  DOI =          "https://doi.org/10.5281/zenodo.3366212",
  bibdate =      "Sun Aug 16 18:37:00 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/java2010.bib",
  URL =          "https://github.com/ulfjack/ryu/tree/v2.0;
                 https://zenodo.org/record/3366212",
  abstract =     "This project contains C and Java implementation of
                 Ryu, as well as a C implementation of Ryu Printf. Ryu
                 converts a floating point number to its shortest
                 decimal representation, whereas Ryu Printf converts a
                 floating point number according to the printf \%f or
                 \%e format. At the time of this writing, these are the
                 fastest known float-to-string conversion algorithms. We
                 have tested the code on Ubuntu 19.04, MacOS Mojave, and
                 Windows 10.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Agrawal:2019:DBF
title: DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference
crossref: Takagi:2019:ISC
pages: 92--95
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00023
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawtitle: {DLFloat}: A 16-b Floating Point Format Designed for Deep Learning Training and Inference
author:
Ankur Agrawal and Silvia M. Mueller and Bruce M. Fleischer and Xiao Sun and Naigang Wang and Jungwook Choi and Kailash Gopalakrishnan

abstract:
The resilience of Deep Learning (DL) training and inference workloads to low-precision computations, coupled with the demand for power-and area-efficient hardware accelerators for these workloads, has led to the emergence of 16-bit floating point formats as the precision of choice for DL hardware accelerators. This paper describes our optimized 16-bit format that has 6 exponent bits and 9 fraction bits, derived from a study of the range of values encountered in DL applications. We demonstrate that our format preserves the accuracy of DL networks, and we compare its ease-of-use for DL against IEEE-754 half-precision (5 exponent bits and 10 fraction bits) and bfloat16 (8 exponent bits and 7 fraction bits). Further, our format eliminated sub-normals and simplifies rounding modes and handling of corner cases. This streamlines floating-point unit logic and enables realization of a compact power-efficient computation engine.

keywords:
16-b floating point format; 16-bit floating point formats; Adders; ARITH-26; compact power-efficient computation engine; Deep learning; deep learning training; DL hardware accelerators; Dynamic range; Engines; floating point arithmetic; floating-point unit logic; Hardware; IEEE-754 half-precision; Image recognition; learning (artificial intelligence); low-precision computations; neural nets; power-and area-efficient hardware accelerators; reduced precision computation, floating point, machine learning, deep learning; streamlines floating-point unit logic; Training

remark:
The DLFloat format has a 1-bit sign, 6-bit exponent, and 10-bit normalized significand including the hidden leading one-bit. Subnormals are not supported, and underflows flush to zero. Infinity and NaN are fused into a single value with the largest exponent and significand; other significands with that exponent are normal numbers. Zero and Inf-NaN are considered to be unsigned. There is only one rounding mode: round-nearest-up. Fused multiply-add (FMA) is supported.

rawabstract:
The resilience of Deep Learning (DL) training and inference workloads to low-precision computations, coupled with the demand for power-and area-efficient hardware accelerators for these workloads, has led to the emergence of 16-bit floating point formats as the precision of choice for DL hardware accelerators. This paper describes our optimized 16-bit format that has 6 exponent bits and 9 fraction bits, derived from a study of the range of values encountered in DL applications. We demonstrate that our format preserves the accuracy of DL networks, and we compare its ease-of-use for DL against IEEE-754 half-precision (5 exponent bits and 10 fraction bits) and bfloat16 (8 exponent bits and 7 fraction bits). Further, our format eliminated sub-normals and simplifies rounding modes and handling of corner cases. This streamlines floating-point unit logic and enables realization of a compact power-efficient computation engine.

rawauthor:
Ankur Agrawal and Silvia M. Mueller and Bruce M. Fleischer and Xiao Sun and Naigang Wang and Jungwook Choi and Kailash Gopalakrishnan

entry:
@InProceedings{Agrawal:2019:DBF,
  author =       "Ankur Agrawal and Silvia M. Mueller and Bruce M.
                 Fleischer and Xiao Sun and Naigang Wang and Jungwook
                 Choi and Kailash Gopalakrishnan",
  title =        "{DLFloat}: A 16-b Floating Point Format Designed for
                 Deep Learning Training and Inference",
  crossref =     "Takagi:2019:ISC",
  pages =        "92--95",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00023",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The resilience of Deep Learning (DL) training and
                 inference workloads to low-precision computations,
                 coupled with the demand for power-and area-efficient
                 hardware accelerators for these workloads, has led to
                 the emergence of 16-bit floating point formats as the
                 precision of choice for DL hardware accelerators. This
                 paper describes our optimized 16-bit format that has 6
                 exponent bits and 9 fraction bits, derived from a study
                 of the range of values encountered in DL applications.
                 We demonstrate that our format preserves the accuracy
                 of DL networks, and we compare its ease-of-use for DL
                 against IEEE-754 half-precision (5 exponent bits and 10
                 fraction bits) and bfloat16 (8 exponent bits and 7
                 fraction bits). Further, our format eliminated
                 sub-normals and simplifies rounding modes and handling
                 of corner cases. This streamlines floating-point unit
                 logic and enables realization of a compact
                 power-efficient computation engine.",
  acknowledgement = ack-nhfb,
  keywords =     "16-b floating point format; 16-bit floating point
                 formats; Adders; ARITH-26; compact power-efficient
                 computation engine; Deep learning; deep learning
                 training; DL hardware accelerators; Dynamic range;
                 Engines; floating point arithmetic; floating-point unit
                 logic; Hardware; IEEE-754 half-precision; Image
                 recognition; learning (artificial intelligence);
                 low-precision computations; neural nets; power-and
                 area-efficient hardware accelerators; reduced precision
                 computation, floating point, machine learning, deep
                 learning; streamlines floating-point unit logic;
                 Training",
  remark =       "The DLFloat format has a 1-bit sign, 6-bit exponent,
                 and 10-bit normalized significand including the hidden
                 leading one-bit. Subnormals are not supported, and
                 underflows flush to zero. Infinity and NaN are fused
                 into a single value with the largest exponent and
                 significand; other significands with that exponent are
                 normal numbers. Zero and Inf-NaN are considered to be
                 unsigned. There is only one rounding mode:
                 round-nearest-up. Fused multiply-add (FMA) is
                 supported.",
}


bibtype: inproceedings
filename: fparith.bib
label: Anderson:2019:SAM
author: Andrew Anderson and Michael Doyle and David Gregg
title: Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks
crossref: Takagi:2019:ISC
pages: 61--68
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00018
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrew Anderson and Michael Doyle and David Gregg
rawtitle: Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks
abstract:
Quantization of weights and activations in Deep Neural Networks (DNNs) is a powerful technique for network compression, and has enjoyed significant attention and success. However, much of the inference-time benefit of quantization is accessible only through customized hardware accelerators or with an FPGA implementation of quantized arithmetic. Building on prior work, we show how to construct very fast implementations of arbitrary bit-precise signed and unsigned integer operations using a software technique which logically embeds a vector architecture with custom bit-width lanes in fixed-width scalar arithmetic. At the strongest level of quantization, our approach yields a maximum speedup of $ approx 6 % $ on an x86 platform, and $ approx 10 % $ on an ARM platform versus quantization to native 8-bit integers.

keywords:
ARITH-26; bit-width lanes; Computer architecture; Custom Arithmetic; Deep Neural Networks; digital arithmetic; Field programmable gate arrays; field programmable gate arrays; fixed-width scalar arithmetic; FPGA implementation; Hardware; hardware accelerators; Machine Learning; network compression; neural nets; Program processors; quantisation (signal); quantization; Quantization (signal); quantized arithmetic; Registers; scalar arithmetic multiple data; Software Performance; software technique; vectors

rawabstract:
Quantization of weights and activations in Deep Neural Networks (DNNs) is a powerful technique for network compression, and has enjoyed significant attention and success. However, much of the inference-time benefit of quantization is accessible only through customized hardware accelerators or with an FPGA implementation of quantized arithmetic. Building on prior work, we show how to construct very fast implementations of arbitrary bit-precise signed and unsigned integer operations using a software technique which logically embeds a vector architecture with custom bit-width lanes in fixed-width scalar arithmetic. At the strongest level of quantization, our approach yields a maximum speedup of $ \approx 6 \% $ on an x86 platform, and $ \approx 10 \% $ on an ARM platform versus quantization to native 8-bit integers.

entry:
@InProceedings{Anderson:2019:SAM,
  author =       "Andrew Anderson and Michael Doyle and David Gregg",
  title =        "Scalar Arithmetic Multiple Data: Customizable
                 Precision for Deep Neural Networks",
  crossref =     "Takagi:2019:ISC",
  pages =        "61--68",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00018",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Quantization of weights and activations in Deep Neural
                 Networks (DNNs) is a powerful technique for network
                 compression, and has enjoyed significant attention and
                 success. However, much of the inference-time benefit of
                 quantization is accessible only through customized
                 hardware accelerators or with an FPGA implementation of
                 quantized arithmetic. Building on prior work, we show
                 how to construct very fast implementations of arbitrary
                 bit-precise signed and unsigned integer operations
                 using a software technique which logically embeds a
                 vector architecture with custom bit-width lanes in
                 fixed-width scalar arithmetic. At the strongest level
                 of quantization, our approach yields a maximum speedup
                 of $ \approx 6 \% $ on an x86 platform, and $ \approx
                 10 \% $ on an ARM platform versus quantization to
                 native 8-bit integers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; bit-width lanes; Computer architecture;
                 Custom Arithmetic; Deep Neural Networks; digital
                 arithmetic; Field programmable gate arrays; field
                 programmable gate arrays; fixed-width scalar
                 arithmetic; FPGA implementation; Hardware; hardware
                 accelerators; Machine Learning; network compression;
                 neural nets; Program processors; quantisation (signal);
                 quantization; Quantization (signal); quantized
                 arithmetic; Registers; scalar arithmetic multiple data;
                 Software Performance; software technique; vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Andrlon:2019:OBF
author: Mak Andrlon and Peter Schachte and Harald Sondergaard and Peter J. Stuckey
title: Optimal Bounds for Floating-Point Addition in Constant Time
crossref: Takagi:2019:ISC
pages: 159--166
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00038
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Mak Andrlon and Peter Schachte and Harald S{\o}ndergaard and Peter J. Stuckey
rawtitle: Optimal Bounds for Floating-Point Addition in Constant Time
abstract:
Reasoning about floating-point numbers is notoriously difficult, owing to the lack of convenient algebraic properties such as associativity. This poses a substantial challenge for program analysis and verification tools which rely on precise floating-point constraint solving. Currently, interval methods in this domain often exhibit slow convergence even on simple examples. We present a new theorem supporting efficient computation of exact bounds of the intersection of a rectangle with the preimage of an interval under floating-point addition, in any radix or rounding mode. We thus give an efficient method of deducing optimal bounds on the components of an addition, solving the convergence problem.

keywords:
addition; arbitrary radix; ARITH-26; Australia; bound analysis; constant time; constraint handling; convenient algebraic properties; Convergence; Digital arithmetic; exact bounds; floating point arithmetic; floating-point addition; Floating-point arithmetic; floating-point numbers; Information systems; interval methods; optimal bounds; precise floating-point constraint solving; program analysis; radix mode; rounding mode; Software; Standards

rawabstract:
Reasoning about floating-point numbers is notoriously difficult, owing to the lack of convenient algebraic properties such as associativity. This poses a substantial challenge for program analysis and verification tools which rely on precise floating-point constraint solving. Currently, interval methods in this domain often exhibit slow convergence even on simple examples. We present a new theorem supporting efficient computation of exact bounds of the intersection of a rectangle with the preimage of an interval under floating-point addition, in any radix or rounding mode. We thus give an efficient method of deducing optimal bounds on the components of an addition, solving the convergence problem.

entry:
@InProceedings{Andrlon:2019:OBF,
  author =       "Mak Andrlon and Peter Schachte and Harald
                 S{\o}ndergaard and Peter J. Stuckey",
  title =        "Optimal Bounds for Floating-Point Addition in Constant
                 Time",
  crossref =     "Takagi:2019:ISC",
  pages =        "159--166",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00038",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Reasoning about floating-point numbers is notoriously
                 difficult, owing to the lack of convenient algebraic
                 properties such as associativity. This poses a
                 substantial challenge for program analysis and
                 verification tools which rely on precise floating-point
                 constraint solving. Currently, interval methods in this
                 domain often exhibit slow convergence even on simple
                 examples. We present a new theorem supporting efficient
                 computation of exact bounds of the intersection of a
                 rectangle with the preimage of an interval under
                 floating-point addition, in any radix or rounding mode.
                 We thus give an efficient method of deducing optimal
                 bounds on the components of an addition, solving the
                 convergence problem.",
  acknowledgement = ack-nhfb,
  keywords =     "addition; arbitrary radix; ARITH-26; Australia; bound
                 analysis; constant time; constraint handling;
                 convenient algebraic properties; Convergence; Digital
                 arithmetic; exact bounds; floating point arithmetic;
                 floating-point addition; Floating-point arithmetic;
                 floating-point numbers; Information systems; interval
                 methods; optimal bounds; precise floating-point
                 constraint solving; program analysis; radix mode;
                 rounding mode; Software; Standards",
}


bibtype: article
filename: fparith.bib
label: Anonymous:2019:CPC
author: Anonymous
title: Computational `pathology' could hamper climate and fusion simulations
journal: j-PHYS-WORLD
pages: 159--166
day: 26
month: sep
monthnumber: 9
year: 2019
CODEN: PHWOEW
ISSN: 0953-8585 (print), 2058-7058 (electronic) OR 09538585 (print), 20587058 (electronic)
bibdate: Mon Sep 30 11:21:38 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.30 11:21:38 ???
note: See cite Boghosian:2019:NPS.
URL: https://physicsworld.com/a/computational-pathology-could-hamper-climate-and-fusion-simulations/
fjournal: Physics World
acknowledgement: ack-nhfb
journalURL: http://physicsworldarchive.iop.org/
rawauthor: Anonymous
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Computational `pathology' could hamper climate and fusion simulations
entry:
@Article{Anonymous:2019:CPC,
  author =       "Anonymous",
  title =        "Computational `pathology' could hamper climate and
                 fusion simulations",
  journal =      j-PHYS-WORLD,
  day =          "26",
  month =        sep,
  year =         "2019",
  CODEN =        "PHWOEW",
  ISSN =         "0953-8585 (print), 2058-7058 (electronic)",
  bibdate =      "Mon Sep 30 11:21:38 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://physicsworld.com/a/computational-pathology-could-hamper-climate-and-fusion-simulations/",
  acknowledgement = ack-nhfb,
  fjournal =     "Physics World",
  journal-URL =  "http://physicsworldarchive.iop.org/",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:MCT
author: Anonymous
title: Multiprecision Computing Toolbox for MATLAB
pages: 159--166
day: 26
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Nov 05 15:46:16 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2019.11.05 15:46:16 ???
URL: https://www.advanpix.com/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: Multiprecision Computing Toolbox for {MATLAB}
entry:
@Misc{Anonymous:2019:MCT,
  author =       "Anonymous",
  title =        "Multiprecision Computing Toolbox for {MATLAB}",
  howpublished = "Web site",
  day =          "26",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Nov 05 15:46:16 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://www.advanpix.com/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:RMV
author: Anonymous
title: Realtime Math v1.0 Open Sourced
pages: 159--166
day: 19
month: jan
monthnumber: 1
year: 2019
bibdate: Tue Jan 22 16:00:13 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.01.22 16:00:13 ???
URL: https://www.gamedev.net/news/realtime-math-v10-open-sourced-r740/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: {Realtime Math v1.0} Open Sourced
remark:
From the Web site: ``Realtime Math ldots consists entirely of C++11 headers, it runs almost everywhere, it supports 64 bit floating point arithmetic, and it sports a very permissive MIT license.''

entry:
@Misc{Anonymous:2019:RMV,
  author =       "Anonymous",
  title =        "{Realtime Math v1.0} Open Sourced",
  howpublished = "Web site",
  day =          "19",
  month =        jan,
  year =         "2019",
  bibdate =      "Tue Jan 22 16:00:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.gamedev.net/news/realtime-math-v10-open-sourced-r740/",
  acknowledgement = ack-nhfb,
  remark =       "From the Web site: ``Realtime Math \ldots{} consists
                 entirely of C++11 headers, it runs almost everywhere,
                 it supports 64 bit floating point arithmetic, and it
                 sports a very permissive MIT license.''",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:SOL
author: Anonymous
title: SiSoftware Official Live Ranker: Top Processor Arithmetic Ranks
pages: 159--166
year: 2019
bibdate: Fri May 24 07:49:33 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.24 07:49:33 ???
note: Floating-point performance ranking of more than 94,500 CPU models.
remark: In May 2019, the top 15 entries were Intel Xeon X-3175X and AMD Ryzen Threadripper CPUs.
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawnote: Floating-point performance ranking of more than 94,500 CPU models.
rawtitle: {SiSoftware} Official Live Ranker: Top Processor Arithmetic Ranks
entry:
@Misc{Anonymous:2019:SOL,
  author =       "Anonymous",
  title =        "{SiSoftware} Official Live Ranker: Top Processor
                 Arithmetic Ranks",
  howpublished = "Web site",
  year =         "2019",
  bibdate =      "Fri May 24 07:49:33 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Floating-point performance ranking of more than 94,500
                 CPU models.",
  acknowledgement = ack-nhfb,
  remark =       "In May 2019, the top 15 entries were Intel Xeon
                 X-3175X and AMD Ryzen Threadripper CPUs.",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:UFP
author: Anonymous
pages: 136
day: 14
month: aug
monthnumber: 8
year: 2019
bibdate: Fri Aug 30 07:24:55 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.30 07:24:55 ???
acknowledgement: ack-nhfb
howpublished: Attorney Docket No. 6324-5986
rawauthor: Anonymous
title:
Universal floating-point instruction set architecture, method, and language for computing directly with decimal character sequences and binary formats in any combination

URL:
https://drive.google.com/file/d/1-gx_P5vBRppa6T3rdv8h6RNXz2Q_ILwg/view; https://drive.google.com/file/d/1fOhVAwdhiebumKkgljKfLqyOaFpUDhQL/view

abstract:
A universal floating-point Instruction Set Architecture (ISA) and associated method and language. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 ``H'' in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls ``gobs'' of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware HconvertFromDecimalCharacter conversion operators.

rawabstract:
A universal floating-point Instruction Set Architecture (ISA) and associated method and language. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 ``H'' in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls ``gobs'' of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware HconvertFromDecimalCharacter conversion operators.

rawtitle:
Universal floating-point instruction set architecture, method, and language for computing directly with decimal character sequences and binary formats in any combination

entry:
@Misc{Anonymous:2019:UFP,
  author =       "Anonymous",
  title =        "Universal floating-point instruction set architecture,
                 method, and language for computing directly with
                 decimal character sequences and binary formats in any
                 combination",
  howpublished = "Attorney Docket No. 6324-5986",
  pages =        "136",
  day =          "14",
  month =        aug,
  year =         "2019",
  bibdate =      "Fri Aug 30 07:24:55 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://drive.google.com/file/d/1-gx_P5vBRppa6T3rdv8h6RNXz2Q_ILwg/view;
                 https://drive.google.com/file/d/1fOhVAwdhiebumKkgljKfLqyOaFpUDhQL/view",
  abstract =     "A universal floating-point Instruction Set
                 Architecture (ISA) and associated method and language.
                 Using a single instruction, the universal
                 floating-point ISA has the ability, in hardware, to
                 compute directly with dual decimal character sequences
                 up to IEEE 754-2008 ``H'' in length, without first
                 having to explicitly perform a
                 conversion-to-binary-format process in software before
                 computing with these human-readable floating-point or
                 integer representations. The ISA does not employ
                 opcodes, but rather pushes and pulls ``gobs'' of data
                 without the encumbering opcode fetch, decode, and
                 execute bottleneck. Instead, the ISA employs
                 stand-alone, memory-mapped operators, complete with
                 their own pipeline that is completely decoupled from
                 the processor's primary push-pull pipeline. The ISA
                 employs special three-port, 1024-bit wide SRAMS; a
                 special dual asymmetric system stack; memory-mapped
                 stand-alone hardware operators with private result
                 buffers having simultaneously readable side-A and
                 side-B read ports; and dual hardware
                 HconvertFromDecimalCharacter conversion operators.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:YAF
author: Anonymous
title: Yet another floating point tutorial
pages: 136
year: 2019
bibdate: Fri May 17 07:24:35 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.17 07:24:35 ???
URL: https://wordsandbuttons.online/yet_another_floating_point_tutorial.html
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: Yet another floating point tutorial
entry:
@Misc{Anonymous:2019:YAF,
  author =       "Anonymous",
  title =        "Yet another floating point tutorial",
  howpublished = "Web site",
  year =         "2019",
  bibdate =      "Fri May 17 07:24:35 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://wordsandbuttons.online/yet_another_floating_point_tutorial.html",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2019:UOD
author: Mark G. Arnold and Ioannis Kouretas and Vassilis Paliouras and John R. Cowles
title: Under- and Overflow Detection in the Residue Logarithmic Number System
crossref: Takagi:2019:ISC
pages: 112--115
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00030
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Mark G. Arnold and Ioannis Kouretas and Vassilis Paliouras and John R. Cowles
rawtitle: Under- and Overflow Detection in the Residue Logarithmic Number System
abstract:
The Residue Number System (RNS) offers fast and cheap carry-free integer arithmetic but has slow and expensive overflow detection. The Logarithmic Number System (LNS) offers fast real multiplication, division and powers with floating-point-like relative precision. The Residue Logarithmic Number System (RLNS) is a combination of the two systems that offers advantages for moderate-precision real applications where a-priori analysis allows under-and overflow to be ignored. An arithmetic hardware generator is essential because of the mathematical obscurity of combining RNS and LNS. Unfortunately, real applications often underflow. We consider options to deal with under-and overflow using the RLNSTool generator as a foundation.

keywords:
ARITH-26; Arithmetic Generator; carry-free integer arithmetic; Computational modeling; Delays; Digital arithmetic; dividing circuits; expensive overflow detection; fast carry-free integer arithmetic; floating point arithmetic; floating-point-like relative precision; Generators; Hardware; Hardware design languages; LNS; moderate-precision real applications; multiplying circuits; number theory; Overflow; Residue Logarithmic Number System; residue number systems; RNS; Wires

rawabstract:
The Residue Number System (RNS) offers fast and cheap carry-free integer arithmetic but has slow and expensive overflow detection. The Logarithmic Number System (LNS) offers fast real multiplication, division and powers with floating-point-like relative precision. The Residue Logarithmic Number System (RLNS) is a combination of the two systems that offers advantages for moderate-precision real applications where a-priori analysis allows under-and overflow to be ignored. An arithmetic hardware generator is essential because of the mathematical obscurity of combining RNS and LNS. Unfortunately, real applications often underflow. We consider options to deal with under-and overflow using the RLNSTool generator as a foundation.

entry:
@InProceedings{Arnold:2019:UOD,
  author =       "Mark G. Arnold and Ioannis Kouretas and Vassilis
                 Paliouras and John R. Cowles",
  title =        "Under- and Overflow Detection in the Residue
                 Logarithmic Number System",
  crossref =     "Takagi:2019:ISC",
  pages =        "112--115",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00030",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Residue Number System (RNS) offers fast and cheap
                 carry-free integer arithmetic but has slow and
                 expensive overflow detection. The Logarithmic Number
                 System (LNS) offers fast real multiplication, division
                 and powers with floating-point-like relative precision.
                 The Residue Logarithmic Number System (RLNS) is a
                 combination of the two systems that offers advantages
                 for moderate-precision real applications where a-priori
                 analysis allows under-and overflow to be ignored. An
                 arithmetic hardware generator is essential because of
                 the mathematical obscurity of combining RNS and LNS.
                 Unfortunately, real applications often underflow. We
                 consider options to deal with under-and overflow using
                 the RLNSTool generator as a foundation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Arithmetic Generator; carry-free integer
                 arithmetic; Computational modeling; Delays; Digital
                 arithmetic; dividing circuits; expensive overflow
                 detection; fast carry-free integer arithmetic; floating
                 point arithmetic; floating-point-like relative
                 precision; Generators; Hardware; Hardware design
                 languages; LNS; moderate-precision real applications;
                 multiplying circuits; number theory; Overflow; Residue
                 Logarithmic Number System; residue number systems; RNS;
                 Wires",
}


bibtype: inproceedings
filename: fparith.bib
label: Arzelier:2019:EAE
author: Denis Arzelier and Florent Brehard and Mioara Joldes
title: Exchange Algorithm for Evaluation and Approximation Error-Optimized Polynomials
crossref: Takagi:2019:ISC
pages: 30--37
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00014
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Denis Arzelier and Florent Br{\'e}hard and Mioara Joldes
rawtitle: Exchange Algorithm for Evaluation and Approximation Error-Optimized Polynomials
abstract:
Machine implementation of mathematical functions often relies on polynomial approximations. The particularity is that rounding errors occur both when representing the polynomial coefficients on a finite number of bits, and when evaluating it in finite precision. Hence, for finding the best polynomial (for a given fixed degree, norm and interval), one has to consider both types of errors: approximation and evaluation. While efficient algorithms were already developed for taking into account the approximation error, the evaluation part is usually a posteriori handled, in an ad-hoc manner. Here, we formulate a semi-infinite linear optimization problem whose solution is the best polynomial with respect to the supremum norm of the sum of both errors. This problem is then solved with an iterative exchange algorithm, which can be seen as an extension of the well-known Remez algorithm. A discussion and comparison of the obtained results on different examples are finally presented.

keywords:
Approximation algorithms; Approximation error; approximation error; approximation error-optimized polynomials; ARITH-26; Digital arithmetic; evaluation error; exchange algorithm; function approximation; Indexes; Input variables; iterative exchange algorithm; iterative methods; learning (artificial intelligence); libm; linear programming; machine implementation; mathematical functions; mathematics computing; optimisation; Optimization; polynomial approximation; polynomial approximations; polynomial coefficients; Programming; remez algorithm; Remez algorithm; semi-infinite programming; semiinfinite linear optimization problem

rawabstract:
Machine implementation of mathematical functions often relies on polynomial approximations. The particularity is that rounding errors occur both when representing the polynomial coefficients on a finite number of bits, and when evaluating it in finite precision. Hence, for finding the best polynomial (for a given fixed degree, norm and interval), one has to consider both types of errors: approximation and evaluation. While efficient algorithms were already developed for taking into account the approximation error, the evaluation part is usually a posteriori handled, in an ad-hoc manner. Here, we formulate a semi-infinite linear optimization problem whose solution is the best polynomial with respect to the supremum norm of the sum of both errors. This problem is then solved with an iterative exchange algorithm, which can be seen as an extension of the well-known Remez algorithm. A discussion and comparison of the obtained results on different examples are finally presented.

entry:
@InProceedings{Arzelier:2019:EAE,
  author =       "Denis Arzelier and Florent Br{\'e}hard and Mioara
                 Joldes",
  title =        "Exchange Algorithm for Evaluation and Approximation
                 Error-Optimized Polynomials",
  crossref =     "Takagi:2019:ISC",
  pages =        "30--37",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00014",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Machine implementation of mathematical functions often
                 relies on polynomial approximations. The particularity
                 is that rounding errors occur both when representing
                 the polynomial coefficients on a finite number of bits,
                 and when evaluating it in finite precision. Hence, for
                 finding the best polynomial (for a given fixed degree,
                 norm and interval), one has to consider both types of
                 errors: approximation and evaluation. While efficient
                 algorithms were already developed for taking into
                 account the approximation error, the evaluation part is
                 usually a posteriori handled, in an ad-hoc manner.
                 Here, we formulate a semi-infinite linear optimization
                 problem whose solution is the best polynomial with
                 respect to the supremum norm of the sum of both errors.
                 This problem is then solved with an iterative exchange
                 algorithm, which can be seen as an extension of the
                 well-known Remez algorithm. A discussion and comparison
                 of the obtained results on different examples are
                 finally presented.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; Approximation error;
                 approximation error; approximation error-optimized
                 polynomials; ARITH-26; Digital arithmetic; evaluation
                 error; exchange algorithm; function approximation;
                 Indexes; Input variables; iterative exchange algorithm;
                 iterative methods; learning (artificial intelligence);
                 libm; linear programming; machine implementation;
                 mathematical functions; mathematics computing;
                 optimisation; Optimization; polynomial approximation;
                 polynomial approximations; polynomial coefficients;
                 Programming; remez algorithm; Remez algorithm;
                 semi-infinite programming; semiinfinite linear
                 optimization problem",
}


bibtype: misc
filename: fparith.bib
label: Bailey:2019:AM
author: David H. Bailey
title: An $ n log (n) $ algorithm for multiplication
pages: 30--37
day: 12
month: apr
monthnumber: 4
year: 2019
bibdate: Fri Apr 12 14:14:40 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.04.12 14:14:40 ???
URL: https://mathscholar.org/2019/04/an-n-log-n-algorithm-for-multiplication/
remark: Description of research in cite Harvey:2019:IMT.
acknowledgement: ack-nhfb
howpublished: Math Scholar blog
rawauthor: David H. Bailey
rawtitle: An $ n \log (n) $ algorithm for multiplication
entry:
@Misc{Bailey:2019:AM,
  author =       "David H. Bailey",
  title =        "An $ n \log (n) $ algorithm for multiplication",
  howpublished = "Math Scholar blog",
  day =          "12",
  month =        apr,
  year =         "2019",
  bibdate =      "Fri Apr 12 14:14:40 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://mathscholar.org/2019/04/an-n-log-n-algorithm-for-multiplication/",
  acknowledgement = ack-nhfb,
  remark =       "Description of research in \cite{Harvey:2019:IMT}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Barthel:2019:SAM
author: Moritz Barthel and Pascal Seidel and Jochen Rust and Steffen Paul
booktitle: 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)
title: SORN Arithmetic for MIMO Symbol Detection --- Exploration of the Type-2 Unum Format
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2019
DOI: https://doi.org/10.1109/NEWCAS44328.2019.8961226
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Moritz B{\"a}rthel and Pascal Seidel and Jochen Rust and Steffen Paul
rawbooktitle: {2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)}
rawtitle: {SORN} Arithmetic for {MIMO} Symbol Detection --- Exploration of the {Type-2} Unum Format
entry:
@InProceedings{Barthel:2019:SAM,
  author =       "Moritz B{\"a}rthel and Pascal Seidel and Jochen Rust
                 and Steffen Paul",
  booktitle =    "{2019 17th IEEE International New Circuits and Systems
                 Conference (NEWCAS)}",
  title =        "{SORN} Arithmetic for {MIMO} Symbol Detection ---
                 Exploration of the {Type-2} Unum Format",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/NEWCAS44328.2019.8961226",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Beame:2019:TVN
author: Paul Beame and Vincent Liew
title: Toward Verifying Nonlinear Integer Arithmetic
journal: j-J-ACM
volume: 66
number: 3
pages: 22:1--22:??
month: jun
monthnumber: 6
year: 2019
CODEN: JACOAH
DOI: https://doi.org/10.1145/3319396
ISSN: 0004-5411 (print), 1557-735X (electronic) OR 00045411 (print), 1557735X (electronic)
ISSNL: 0004-5411 OR 00045411
bibdate: Wed Oct 23 06:51:06 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jacm.bib
bibtimestamp: 2019.10.23 06:51:06 MDT
URL: https://dl.acm.org/ft_gateway.cfm?id=3319396
fjournal: Journal of the ACM
acknowledgement: ack-nhfb
ajournal: J. Assoc. Comput. Mach.
articleno: 22
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J401
rawauthor: Paul Beame and Vincent Liew
rawtitle: Toward Verifying Nonlinear Integer Arithmetic
abstract:
We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give $ n^O (1) $ size regular resolution proofs for arbitrary degree $2$ identities on array, diagonal, and Booth multipliers and $ n^O(log n)$ size proofs for these identities on Wallace tree multipliers.

rawabstract:
We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give $ n^{O (1)} $ size regular resolution proofs for arbitrary degree $2$ identities on array, diagonal, and Booth multipliers and $ n^{O(\log n)}$ size proofs for these identities on Wallace tree multipliers.

entry:
@Article{Beame:2019:TVN,
  author =       "Paul Beame and Vincent Liew",
  title =        "Toward Verifying Nonlinear Integer Arithmetic",
  journal =      j-J-ACM,
  volume =       "66",
  number =       "3",
  pages =        "22:1--22:??",
  month =        jun,
  year =         "2019",
  CODEN =        "JACOAH",
  DOI =          "https://doi.org/10.1145/3319396",
  ISSN =         "0004-5411 (print), 1557-735X (electronic)",
  ISSN-L =       "0004-5411",
  bibdate =      "Wed Oct 23 06:51:06 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jacm.bib",
  URL =          "https://dl.acm.org/ft_gateway.cfm?id=3319396",
  abstract =     "We eliminate a key roadblock to efficient verification
                 of nonlinear integer arithmetic using CDCL SAT solvers,
                 by showing how to construct short resolution proofs for
                 many properties of the most widely used multiplier
                 circuits. Such short proofs were conjectured not to
                 exist. More precisely, we give $ n^{O (1)} $ size
                 regular resolution proofs for arbitrary degree $2$
                 identities on array, diagonal, and Booth multipliers
                 and $ n^{O(\log n)}$ size proofs for these identities
                 on Wallace tree multipliers.",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Assoc. Comput. Mach.",
  articleno =    "22",
  fjournal =     "Journal of the ACM",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J401",
}


bibtype: article
filename: fparith.bib
label: Bellal:2019:IAA
author: R. Bellal and E. Lamini and H. Belbachir and S. Tagzout and A. Belouchrani
title: Improved Affine Arithmetic-Based Precision Analysis for Polynomial Function Evaluation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 702--712
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2882537
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Bellal and E. Lamini and H. Belbachir and S. Tagzout and A. Belouchrani
rawtitle: Improved Affine Arithmetic-Based Precision Analysis for Polynomial Function Evaluation
keywords:
affine arithmetic; affine arithmetic-based precision analysis; Compounds; degree-n polynomial Horner's rule; design phase; enhanced precision analysis; error propagating formula; fixed point arithmetic; Fixed-point arithmetic; fixed-point numbers; Hardware; hardware function evaluation; hardware implementations; hardware resources; Interpolation; iterative methods; optimisation; Optimization; polynomial approximation; polynomial function evaluation; polynomials; precision analysis; quantisation (signal); Quantization (signal); quantization error; Resource management; table lookup; tighter upper bound error; Upper bound; VLSI systems; word-length allocation; word-length optimization

entry:
@Article{Bellal:2019:IAA,
  author =       "R. Bellal and E. Lamini and H. Belbachir and S.
                 Tagzout and A. Belouchrani",
  title =        "Improved Affine Arithmetic-Based Precision Analysis
                 for Polynomial Function Evaluation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "702--712",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2882537",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "affine arithmetic; affine arithmetic-based precision
                 analysis; Compounds; degree-n polynomial Horner's rule;
                 design phase; enhanced precision analysis; error
                 propagating formula; fixed point arithmetic;
                 Fixed-point arithmetic; fixed-point numbers; Hardware;
                 hardware function evaluation; hardware implementations;
                 hardware resources; Interpolation; iterative methods;
                 optimisation; Optimization; polynomial approximation;
                 polynomial function evaluation; polynomials; precision
                 analysis; quantisation (signal); Quantization (signal);
                 quantization error; Resource management; table lookup;
                 tighter upper bound error; Upper bound; VLSI systems;
                 word-length allocation; word-length optimization",
}


bibtype: techreport
filename: fparith.bib
label: Blanchard:2019:MPB
author: Pierre Blanchard and Nicholas J. Higham and Florent Lopez and Theo Mary and Srikara Pranesh
title: Mixed Precision Block Fused Multiply-Add: Error Analysis and Application to GPU Tensor Cores
type: MIMS EPrint
number: 2019.18
institution: Manchester Institute for Mathematical Sciences, School of Mathematics, The University of Manchester
address: Manchester, UK
pages: 702--712
day: 24
month: sep
monthnumber: 9
year: 2019
ISSN: 1749-9097 OR 17499097
bibdate: Thu Dec 05 10:14:37 2019
bibtimestamp: 2019.12.05 10:14:37 ???
acknowledgement: ack-nhfb
rawauthor: Pierre Blanchard and Nicholas J. Higham and Florent Lopez and Theo Mary and Srikara Pranesh
rawtitle: Mixed Precision Block Fused Multiply-Add: Error Analysis and Application to {GPU} Tensor Cores
URL:
http://eprints.maths.manchester.ac.uk/2733/; https://en.wikipedia.org/wiki/Bfloat16_floating-point_format

abstract:
Computing units that carry out a fused multiply-add (FMA) operation with matrix arguments, referred to as tensor units by some vendors, have great potential for use in scientific computing. However, these units are inherently mixed precision and existing rounding error analyses do not support them. We consider a mixed precision block FMA that generalizes both the usual scalar FMA and existing tensor units. We describe how to exploit such a block FMA in the numerical linear algebra kernels of matrix multiplication and LU factorization and give rounding error analyses of both kernels. An important application is to GMRES-based iterative refinement with block FMAs, for which our analysis provides new insight. Our framework is applicable to the tensor core units in the NVIDIA Volta and Turing GPUs. For these we compare matrix multiplication and LU factorization with TC16 and TC32 forms of FMA, which differ in the precision used for the output of the tensor cores. Our experiments on an NVDIA V100 GPU confirm the predictions of the analysis that the TC32 variant is much more accurate than the TC16 one, while achieving almost the same performance.

keywords:
floating-point arithmetic; fused multiply-add; LU factorization; matrix multiplication; rounding error analysis, NVIDIA GPU; tensor cores

rawabstract:
Computing units that carry out a fused multiply-add (FMA) operation with matrix arguments, referred to as tensor units by some vendors, have great potential for use in scientific computing. However, these units are inherently mixed precision and existing rounding error analyses do not support them. We consider a mixed precision block FMA that generalizes both the usual scalar FMA and existing tensor units. We describe how to exploit such a block FMA in the numerical linear algebra kernels of matrix multiplication and LU factorization and give rounding error analyses of both kernels. An important application is to GMRES-based iterative refinement with block FMAs, for which our analysis provides new insight. Our framework is applicable to the tensor core units in the NVIDIA Volta and Turing GPUs. For these we compare matrix multiplication and LU factorization with TC16 and TC32 forms of FMA, which differ in the precision used for the output of the tensor cores. Our experiments on an NVDIA V100 GPU confirm the predictions of the analysis that the TC32 variant is much more accurate than the TC16 one, while achieving almost the same performance.

entry:
@TechReport{Blanchard:2019:MPB,
  author =       "Pierre Blanchard and Nicholas J. Higham and Florent
                 Lopez and Theo Mary and Srikara Pranesh",
  title =        "Mixed Precision Block Fused Multiply-Add: Error
                 Analysis and Application to {GPU} Tensor Cores",
  type =         "MIMS EPrint",
  number =       "2019.18",
  institution =  "Manchester Institute for Mathematical Sciences, School
                 of Mathematics, The University of Manchester",
  address =      "Manchester, UK",
  day =          "24",
  month =        sep,
  year =         "2019",
  ISSN =         "1749-9097",
  bibdate =      "Thu Dec 05 10:14:37 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://eprints.maths.manchester.ac.uk/2733/;
                 https://en.wikipedia.org/wiki/Bfloat16_floating-point_format",
  abstract =     "Computing units that carry out a fused multiply-add
                 (FMA) operation with matrix arguments, referred to as
                 tensor units by some vendors, have great potential for
                 use in scientific computing. However, these units are
                 inherently mixed precision and existing rounding error
                 analyses do not support them. We consider a mixed
                 precision block FMA that generalizes both the usual
                 scalar FMA and existing tensor units. We describe how
                 to exploit such a block FMA in the numerical linear
                 algebra kernels of matrix multiplication and LU
                 factorization and give rounding error analyses of both
                 kernels. An important application is to GMRES-based
                 iterative refinement with block FMAs, for which our
                 analysis provides new insight. Our framework is
                 applicable to the tensor core units in the NVIDIA Volta
                 and Turing GPUs. For these we compare matrix
                 multiplication and LU factorization with TC16 and TC32
                 forms of FMA, which differ in the precision used for
                 the output of the tensor cores. Our experiments on an
                 NVDIA V100 GPU confirm the predictions of the analysis
                 that the TC32 variant is much more accurate than the
                 TC16 one, while achieving almost the same
                 performance.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; fused multiply-add; LU
                 factorization; matrix multiplication; rounding error
                 analysis, NVIDIA GPU; tensor cores",
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:BAF
booktitle: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
title: Byte-Aware Floating-point Operations through a UNUM Computing Unit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 323--328
year: 2019
DOI: https://doi.org/10.1109/VLSI-SoC.2019.8920387
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)}
rawtitle: Byte-Aware Floating-point Operations through a {UNUM} Computing Unit
author:
Andrea Bocco and Tiago T. Jost and Albert Cohen and Florent de Dinechin and Yves Durand and Christian Fabre

rawauthor:
Andrea Bocco and Tiago T. Jost and Albert Cohen and Florent de Dinechin and Yves Durand and Christian Fabre

entry:
@InProceedings{Bocco:2019:BAF,
  author =       "Andrea Bocco and Tiago T. Jost and Albert Cohen and
                 Florent de Dinechin and Yves Durand and Christian
                 Fabre",
  booktitle =    "{2019 IFIP/IEEE 27th International Conference on Very
                 Large Scale Integration (VLSI-SoC)}",
  title =        "Byte-Aware Floating-point Operations through a {UNUM}
                 Computing Unit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "323--328",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2019.8920387",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:DPN
author: Andrea Bocco and Yves Durand and Florent de Dinechin
title: Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor
crossref: Takagi:2019:ISC
pages: 104--107
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00028
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrea Bocco and Yves Durand and Florent de Dinechin
rawtitle: Dynamic Precision Numerics Using a Variable-Precision {UNUM Type I HW} Coprocessor
abstract:
A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is integrated on FPGA and demonstrated on a representative example.

keywords:
ARITH-26; Arrays; cache storage; Computational modeling; coprocessors; Coprocessors; dynamic Precision numerics; field programmable gate arrays; floating point arithmetic; floating point arithmetic co-processor architecture; FPGA; internal accumulation register; iterative kernels; iterative methods; Kernel; Programming; reduced instruction set computing; Registers; RISC-V; Variable Precision; Variable precision, Floating-point, UNUM, Scientific computing, Instruction set design, Hardware architecture, RISC-V, Coprocessor, Multiple precision, FPGA, ASIC; variable-precision UNUM Type I HW coprocessor

rawabstract:
A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is integrated on FPGA and demonstrated on a representative example.

entry:
@InProceedings{Bocco:2019:DPN,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "Dynamic Precision Numerics Using a Variable-Precision
                 {UNUM Type I HW} Coprocessor",
  crossref =     "Takagi:2019:ISC",
  pages =        "104--107",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00028",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A very large internal accumulation register has been
                 proposed to increase the accuracy of scientific code.
                 However, there is a general class of iterative kernels
                 where a vector of high-precision data must be saved
                 from one iteration to the next. Saving the large
                 internal accumulator to memory is impractical in such
                 cases. This work proposes a Variable Precision (VP)
                 Floating Point (FP) arithmetic co-processor
                 architecture based on RISC-V, which 1/ supports legacy
                 IEEE formats for input and output variables, 2/ uses
                 variable length internal registers (up to 512 bits of
                 mantissa) for inner loop multiply-add and 3/ supports
                 loads and stores of intermediate results to cache
                 memory with a dynamically adjustable precision (up to
                 256 bits of mantissa). It exploits the UNUM type I
                 floating point format, proposing solutions to address
                 some of its pitfalls such as the variable latency of
                 the internal operation, and the variable memory
                 footprint of the intermediate variables. This work is
                 integrated on FPGA and demonstrated on a representative
                 example.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Arrays; cache storage; Computational
                 modeling; coprocessors; Coprocessors; dynamic Precision
                 numerics; field programmable gate arrays; floating
                 point arithmetic; floating point arithmetic
                 co-processor architecture; FPGA; internal accumulation
                 register; iterative kernels; iterative methods; Kernel;
                 Programming; reduced instruction set computing;
                 Registers; RISC-V; Variable Precision; Variable
                 precision, Floating-point, UNUM, Scientific computing,
                 Instruction set design, Hardware architecture, RISC-V,
                 Coprocessor, Multiple precision, FPGA, ASIC;
                 variable-precision UNUM Type I HW coprocessor",
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:SSM
author: Andrea Bocco and Yves Durand and Florent de Dinechin
title: SMURF: Scalar Multiple-precision Unum RISC-V Floating-point Accelerator for Scientific Computing
crossref: Gustafson:2019:CPC
pages: 1:1--1:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316280
bibdate: Mon Feb 10 09:31:49 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2020.02.10 09:31:49 ???
URL: https://hal.inria.fr/hal-02087098
acknowledgement: ack-nhfb
articleno: 1
rawauthor: Andrea Bocco and Yves Durand and Florent de Dinechin
abstract:
This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

keywords:
ASIC, UNUM, Floating-point, RISC-V, Coprocessor, Instruction set design, Variable precision, Scientific computing, Hardware architecture, Multiple precision, FPGA

rawabstract:
This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

rawtitle:
{SMURF}: {Scalar Multiple-precision Unum RISC-V Floating-point} Accelerator for Scientific Computing

entry:
@InProceedings{Bocco:2019:SSM,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "{SMURF}: {Scalar Multiple-precision Unum RISC-V
                 Floating-point} Accelerator for Scientific Computing",
  crossref =     "Gustafson:2019:CPC",
  pages =        "1:1--1:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316280",
  bibdate =      "Mon Feb 10 09:31:49 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://hal.inria.fr/hal-02087098",
  abstract =     "This paper proposes an innovative Floating Point (FP)
                 architecture for Variable Precision (VP) computation
                 suitable for high precision FP computing, based on a
                 refined version of the UNUM type I format. This
                 architecture supports VP FP intervals where each
                 interval endpoint can have up to 512 bits of mantissa.
                 The proposed hardware architecture is pipelined and has
                 an internal word-size of 64 bits. Computations on
                 longer mantissas are performed iteratively on the
                 existing hardware. The prototype is integrated in a
                 RISC-V environment, it is exposed to the user through
                 an instruction set extension. The paper we provide an
                 example of software usage. The system has been
                 prototyped on a FPGA (Field-Programmable Gate Array)
                 platform and also synthesized for a 28nm FDSOI process
                 technology. The respective working frequency of FPGA
                 and ASIC implementations are 50MHz and 600MHz. The
                 estimated chip area is 1.5mm 2 and the estimated power
                 consumption is 95mW. The flops performance of this
                 architecture remains within the range of a regular
                 fixed-precision IEEE FPU while enabling arbitrary
                 precision computation at reasonable cost.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  keywords =     "ASIC, UNUM, Floating-point, RISC-V, Coprocessor,
                 Instruction set design, Variable precision, Scientific
                 computing, Hardware architecture, Multiple precision,
                 FPGA",
}


bibtype: article
filename: fparith.bib
label: Boghosian:2019:NPS
author: Bruce M. Boghosian and Peter V. Coveney and Hongyan Wang
title: A New Pathology in the Simulation of Chaotic Dynamical Systems on Digital Computers
journal: j-ADV-THEORY-SIMUL
pages: 1900125
month: sep
monthnumber: 9
year: 2019
CODEN: ATSDCW
DOI: https://doi.org/10.1002/adts.201900125
ISSN: 2513-0390 OR 25130390
bibdate: Tue Sep 24 05:31:42 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:31:42 ???
URL: https://onlinelibrary.wiley.com/journal/25130390
fjournal: Advanced Theory and Simulations
acknowledgement: ack-nhfb
ajournal: Adv. Theory Simul.
journalURL: https://onlinelibrary.wiley.com/journal/25130390
rawauthor: Bruce M. Boghosian and Peter V. Coveney and Hongyan Wang
rawtitle: A New Pathology in the Simulation of Chaotic Dynamical Systems on Digital Computers
note:
See also news releases cite Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC.

abstract:
Systematic distortions are uncovered in the statistical properties of chaotic dynamical systems when represented and simulated on digital computers using standard IEEE floating-point numbers. This is done by studying a model chaotic dynamical system with a single free parameter $ beta $, known as the generalized Bernoulli map, many of whose exact properties are known. Much of the structure of the dynamical system is lost in the floating-point representation. For even integer values of the parameter, the long time behaviour is completely wrong, subsuming the known anomalous behaviour for $ beta = 2 $. For non-integer $ beta $, relative errors in observables can reach 14%. For odd integer values of $ beta $, floating-point results are more accurate, but still produce relative errors two orders of magnitude larger than those attributable to roundoff. The analysis indicates that the pathology described, which cannot be mitigated by increasing the precision of the floating point numbers, is a representative example of a deeper problem in the computation of expectation values for chaotic systems. The findings sound a warning about the uncritical application of numerical methods in studies of the statistical properties of chaotic dynamical systems, such as are routinely performed throughout computational science, including turbulence and molecular dynamics.

remark:
This study demonstrates the perils of computing with too few significant digits in the floating-point representation. However, the authors report: ``Though the root of this problem resides in the use of finite-precision floating-point arithmetic, it cannot be mitigated by increasing the precision of the floating-point representation. Our analysis strongly suggests that the pathology we describe will exhibit for mantissa and exponent fields of any finite length whatsoever, and for floating-point numbers encoded in any radix whatsoever. Indeed, there is every reason to anticipate that this anomalous behaviour is generic in dissipative chaotic systems of the kind encountered in turbulence and molecular dynamics, and that it is entirely possible that many published results of numerical simulation are substantially inaccurate for this reason.''

rawabstract:
Systematic distortions are uncovered in the statistical properties of chaotic dynamical systems when represented and simulated on digital computers using standard IEEE floating-point numbers. This is done by studying a model chaotic dynamical system with a single free parameter $ \beta $, known as the generalized Bernoulli map, many of whose exact properties are known. Much of the structure of the dynamical system is lost in the floating-point representation. For even integer values of the parameter, the long time behaviour is completely wrong, subsuming the known anomalous behaviour for $ \beta = 2 $. For non-integer $ \beta $, relative errors in observables can reach 14\%. For odd integer values of $ \beta $, floating-point results are more accurate, but still produce relative errors two orders of magnitude larger than those attributable to roundoff. The analysis indicates that the pathology described, which cannot be mitigated by increasing the precision of the floating point numbers, is a representative example of a deeper problem in the computation of expectation values for chaotic systems. The findings sound a warning about the uncritical application of numerical methods in studies of the statistical properties of chaotic dynamical systems, such as are routinely performed throughout computational science, including turbulence and molecular dynamics.

rawnote:
See also news releases \cite{Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC}.

entry:
@Article{Boghosian:2019:NPS,
  author =       "Bruce M. Boghosian and Peter V. Coveney and Hongyan
                 Wang",
  title =        "A New Pathology in the Simulation of Chaotic Dynamical
                 Systems on Digital Computers",
  journal =      j-ADV-THEORY-SIMUL,
  pages =        "1900125",
  month =        sep,
  year =         "2019",
  CODEN =        "ATSDCW",
  DOI =          "https://doi.org/10.1002/adts.201900125",
  ISSN =         "2513-0390",
  bibdate =      "Tue Sep 24 05:31:42 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See also news releases
                 \cite{Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC}.",
  URL =          "https://onlinelibrary.wiley.com/journal/25130390",
  abstract =     "Systematic distortions are uncovered in the
                 statistical properties of chaotic dynamical systems
                 when represented and simulated on digital computers
                 using standard IEEE floating-point numbers. This is
                 done by studying a model chaotic dynamical system with
                 a single free parameter $ \beta $, known as the
                 generalized Bernoulli map, many of whose exact
                 properties are known. Much of the structure of the
                 dynamical system is lost in the floating-point
                 representation. For even integer values of the
                 parameter, the long time behaviour is completely wrong,
                 subsuming the known anomalous behaviour for $ \beta = 2
                 $. For non-integer $ \beta $, relative errors in
                 observables can reach 14\%. For odd integer values of $
                 \beta $, floating-point results are more accurate, but
                 still produce relative errors two orders of magnitude
                 larger than those attributable to roundoff. The
                 analysis indicates that the pathology described, which
                 cannot be mitigated by increasing the precision of the
                 floating point numbers, is a representative example of
                 a deeper problem in the computation of expectation
                 values for chaotic systems. The findings sound a
                 warning about the uncritical application of numerical
                 methods in studies of the statistical properties of
                 chaotic dynamical systems, such as are routinely
                 performed throughout computational science, including
                 turbulence and molecular dynamics.",
  acknowledgement = ack-nhfb,
  ajournal =     "Adv. Theory Simul.",
  fjournal =     "Advanced Theory and Simulations",
  journal-URL =  "https://onlinelibrary.wiley.com/journal/25130390",
  remark =       "This study demonstrates the perils of computing with
                 too few significant digits in the floating-point
                 representation. However, the authors report: ``Though
                 the root of this problem resides in the use of
                 finite-precision floating-point arithmetic, it cannot
                 be mitigated by increasing the precision of the
                 floating-point representation. Our analysis strongly
                 suggests that the pathology we describe will exhibit
                 for mantissa and exponent fields of any finite length
                 whatsoever, and for floating-point numbers encoded in
                 any radix whatsoever. Indeed, there is every reason to
                 anticipate that this anomalous behaviour is generic in
                 dissipative chaotic systems of the kind encountered in
                 turbulence and molecular dynamics, and that it is
                 entirely possible that many published results of
                 numerical simulation are substantially inaccurate for
                 this reason.''",
}


bibtype: article
filename: fparith.bib
label: Borges:2019:IAH
author: Carlos F. Borges
title: An Improved Algorithm for tt hypot(a,b)
journal: arXiv.org
pages: 1--15
day: 14
month: jun
monthnumber: 6
year: 2019
bibdate: Fri Apr 19 05:40:55 2024
bibtimestamp: 2024.04.19 05:40:55 ???
URL: https://arxiv.org/abs/1904.09481
acknowledgement: ack-nhfb
rawauthor: Carlos F. Borges
rawtitle: An Improved Algorithm for {\tt hypot(a,b)}
abstract:
We develop a fast and accurate algorithm for evaluating $ sqrt x^2 + y^2 $ for two floating point numbers $a$ and $b$. Library functions that perform this computation are generally named tt hypot(a,b). We will compare four approaches that we will develop in this paper to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will demonstrate the performance of our algorithms by simulation.

rawabstract:
We develop a fast and accurate algorithm for evaluating $ \sqrt {x^2 + y^2} $ for two floating point numbers $a$ and $b$. Library functions that perform this computation are generally named {\tt hypot(a,b)}. We will compare four approaches that we will develop in this paper to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will demonstrate the performance of our algorithms by simulation.

entry:
@Article{Borges:2019:IAH,
  author =       "Carlos F. Borges",
  title =        "An Improved Algorithm for {\tt hypot(a,b)}",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--15",
  day =          "14",
  month =        jun,
  year =         "2019",
  bibdate =      "Fri Apr 19 05:40:55 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1904.09481",
  abstract =     "We develop a fast and accurate algorithm for
                 evaluating $ \sqrt {x^2 + y^2} $ for two floating point
                 numbers $a$ and $b$. Library functions that perform
                 this computation are generally named {\tt hypot(a,b)}.
                 We will compare four approaches that we will develop in
                 this paper to the current resident library function
                 that is delivered with Julia 1.1 and to the code that
                 has been distributed with the C math library for
                 decades. We will demonstrate the performance of our
                 algorithms by simulation.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bos:2019:ACI
author: J. W. Bos and S. J. Friedberger
title: Arithmetic Considerations for Isogeny-Based Cryptography
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 979--990
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2851238
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. W. Bos and S. J. Friedberger
rawtitle: Arithmetic Considerations for Isogeny-Based Cryptography
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

keywords:
arithmetic; arithmetic considerations; arithmetic techniques; Computer architecture; cryptographic protocols; curve models; digital arithmetic; efficient addition-subtraction chains; efficient arithmetic modulo; efficient chains; elliptic curve scalar multiplication; Elliptic curves; isogeny-based cryptography; Montgomery curves; Montgomery reduction; NIST; Optimization; post-quantum public-key arena; Protocols; Public key cryptography; quadratic extension field; scalar multiplication arithmetic; SIDH setting; special shape; supersingular isogeny Diffie-Hellman key-exchange protocol; systematic overview; twisted Edwards curves

entry:
@Article{Bos:2019:ACI,
  author =       "J. W. Bos and S. J. Friedberger",
  title =        "Arithmetic Considerations for Isogeny-Based
                 Cryptography",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "979--990",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2851238",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic; arithmetic considerations; arithmetic
                 techniques; Computer architecture; cryptographic
                 protocols; curve models; digital arithmetic; efficient
                 addition-subtraction chains; efficient arithmetic
                 modulo; efficient chains; elliptic curve scalar
                 multiplication; Elliptic curves; isogeny-based
                 cryptography; Montgomery curves; Montgomery reduction;
                 NIST; Optimization; post-quantum public-key arena;
                 Protocols; Public key cryptography; quadratic extension
                 field; scalar multiplication arithmetic; SIDH setting;
                 special shape; supersingular isogeny Diffie-Hellman
                 key-exchange protocol; systematic overview; twisted
                 Edwards curves",
}


bibtype: misc
filename: fparith.bib
label: Bright:2019:CEN
author: Peter Bright
pages: 979--990
day: 7
month: mar
monthnumber: 3
year: 2019
bibdate: Fri Mar 08 07:46:06 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.03.08 07:46:06 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Peter Bright
title:
tt calc.exe is now open source; there's surprising depth in its ancient code. The actual calculation engine is more than 20 years old

URL:
https://arstechnica.com/gadgets/2019/03/calc-exe-is-now-open-source-theres-surprising-depth-in-its-ancient-code/; https://github.com/Microsoft/calculator

abstract:
Microsoft's embrace and adoption of open source software has continued with the surprising decision to publish the code for Windows Calculator and release it on GitHub under the permissive MIT license.

rawabstract:
Microsoft's embrace and adoption of open source software has continued with the surprising decision to publish the code for Windows Calculator and release it on GitHub under the permissive MIT license.

rawtitle:
{\tt calc.exe} is now open source; there's surprising depth in its ancient code. {The} actual calculation engine is more than 20 years old

entry:
@Misc{Bright:2019:CEN,
  author =       "Peter Bright",
  title =        "{\tt calc.exe} is now open source; there's surprising
                 depth in its ancient code. {The} actual calculation
                 engine is more than 20 years old",
  howpublished = "Web site",
  day =          "7",
  month =        mar,
  year =         "2019",
  bibdate =      "Fri Mar 08 07:46:06 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arstechnica.com/gadgets/2019/03/calc-exe-is-now-open-source-theres-surprising-depth-in-its-ancient-code/;
                 https://github.com/Microsoft/calculator",
  abstract =     "Microsoft's embrace and adoption of open source
                 software has continued with the surprising decision to
                 publish the code for Windows Calculator and release it
                 on GitHub under the permissive MIT license.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Brown:2019:RCF
author: Erin Clare Brown
title: Rust and C++ on Floating-point Intensive Code
pages: 979--990
day: 19
month: oct
monthnumber: 10
year: 2019
bibdate: Fri Oct 25 06:25:15 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.25 06:25:15 ???
URL: https://upshed.com/2019/10/24/rust-and-c-on-floating-point-intensive-code/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Erin Clare Brown
rawtitle: {Rust} and {C++} on Floating-point Intensive Code
entry:
@Misc{Brown:2019:RCF,
  author =       "Erin Clare Brown",
  title =        "{Rust} and {C++} on Floating-point Intensive Code",
  howpublished = "Web site.",
  day =          "19",
  month =        oct,
  year =         "2019",
  bibdate =      "Fri Oct 25 06:25:15 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://upshed.com/2019/10/24/rust-and-c-on-floating-point-intensive-code/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bruguera:2019:GEI
author: J. D. Bruguera and F. de Dinechin
title: Guest Editors Introduction: Special Section on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 951--952
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2918447
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
keywords: Cryptography; Digital arithmetic; Mathematics; Software algorithms; Special issues and sections
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. D. Bruguera and F. de Dinechin
rawtitle: {Guest Editors} Introduction: Special Section on Computer Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

entry:
@Article{Bruguera:2019:GEI,
  author =       "J. D. Bruguera and F. de Dinechin",
  title =        "{Guest Editors} Introduction: Special Section on
                 Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "951--952",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2918447",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Cryptography; Digital arithmetic; Mathematics;
                 Software algorithms; Special issues and sections",
}


bibtype: inproceedings
filename: fparith.bib
label: Bui:2019:VMS
author: Ngoc-Tu Bui and Trong-Thuc Hoang and Duc-Hung Le and Cong-Kha Pham
booktitle: 2019 IEEE International Conference on Industrial Technology (ICIT)
title: A 0.75-V 32-MHz 181-$ mu $W SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 835--840
year: 2019
DOI: https://doi.org/10.1109/ICIT.2019.8754955
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Ngoc-Tu Bui and Trong-Thuc Hoang and Duc-Hung Le and Cong-Kha Pham
rawbooktitle: {2019 IEEE International Conference on Industrial Technology (ICIT)}
rawtitle: A 0.75-V {32-MHz 181-$ \mu $W} {SOTB-65nm} Floating-point Twiddle Factor Using Adaptive {CORDIC}
keywords:
Decision making; Frequency measurement; Registers; Semiconductor device measurement; Silicon; Table lookup

entry:
@InProceedings{Bui:2019:VMS,
  author =       "Ngoc-Tu Bui and Trong-Thuc Hoang and Duc-Hung Le and
                 Cong-Kha Pham",
  booktitle =    "{2019 IEEE International Conference on Industrial
                 Technology (ICIT)}",
  title =        "A 0.75-V {32-MHz 181-$ \mu $W} {SOTB-65nm}
                 Floating-point Twiddle Factor Using Adaptive {CORDIC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "835--840",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICIT.2019.8754955",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Decision making; Frequency measurement; Registers;
                 Semiconductor device measurement; Silicon; Table
                 lookup",
}


bibtype: inproceedings
filename: fparith.bib
label: Burgess:2019:BPN
title: Bfloat16 Processing for Neural Networks
crossref: Takagi:2019:ISC
pages: 88--91
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00022
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawtitle: {Bfloat16} Processing for Neural Networks
author:
Neil Burgess and Jelena Milanovic and Nigel Stephens and Konstantinos Monachopoulos and David Mansell

abstract:
Bfloat16 (``BF16'') is a new floating-point format tailored specifically for high-performance processing of Neural Networks and will be supported by major CPU and GPU architectures as well as Neural Network accelerators. This paper proposes a possible implementation of a BF16 multiply-accumulation operation that relaxes several IEEE Floating-Point Standard features to afford low-cost hardware implementations. Specifically, subnorms are flushed to zero; only one non-standard rounding mode (Round-Odd) is supported; NaNs are not propagated; and IEEE exception flags are not provided. The paper shows that this approach achieves the same network-level accuracy as using IEEE single-precision arithmetic (``FP32'') for less than half the datapath area cost and with greater throughput.

keywords:
ARITH-26; Artificial neural networks; BF16 multiply-accumulation operation; bfloat16 processing; Computer architecture; CPU architectures; Digital arithmetic; Error analysis; floating point arithmetic; floating-point, rounding mode, neural networks; FP32; GPU architectures; high-performance processing; IEEE exception flags; IEEE floating-point standard features; IEEE single-precision arithmetic; low-cost hardware implementations; network-level accuracy; neural nets; Neural Network accelerators; neural networks; nonstandard rounding mode; Standards; Training

rawabstract:
Bfloat16 (``BF16'') is a new floating-point format tailored specifically for high-performance processing of Neural Networks and will be supported by major CPU and GPU architectures as well as Neural Network accelerators. This paper proposes a possible implementation of a BF16 multiply-accumulation operation that relaxes several IEEE Floating-Point Standard features to afford low-cost hardware implementations. Specifically, subnorms are flushed to zero; only one non-standard rounding mode (Round-Odd) is supported; NaNs are not propagated; and IEEE exception flags are not provided. The paper shows that this approach achieves the same network-level accuracy as using IEEE single-precision arithmetic (``FP32'') for less than half the datapath area cost and with greater throughput.

rawauthor:
Neil Burgess and Jelena Milanovic and Nigel Stephens and Konstantinos Monachopoulos and David Mansell

entry:
@InProceedings{Burgess:2019:BPN,
  author =       "Neil Burgess and Jelena Milanovic and Nigel Stephens
                 and Konstantinos Monachopoulos and David Mansell",
  title =        "{Bfloat16} Processing for Neural Networks",
  crossref =     "Takagi:2019:ISC",
  pages =        "88--91",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00022",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Bfloat16 (``BF16'') is a new floating-point format
                 tailored specifically for high-performance processing
                 of Neural Networks and will be supported by major CPU
                 and GPU architectures as well as Neural Network
                 accelerators. This paper proposes a possible
                 implementation of a BF16 multiply-accumulation
                 operation that relaxes several IEEE Floating-Point
                 Standard features to afford low-cost hardware
                 implementations. Specifically, subnorms are flushed to
                 zero; only one non-standard rounding mode (Round-Odd)
                 is supported; NaNs are not propagated; and IEEE
                 exception flags are not provided. The paper shows that
                 this approach achieves the same network-level accuracy
                 as using IEEE single-precision arithmetic (``FP32'')
                 for less than half the datapath area cost and with
                 greater throughput.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Artificial neural networks; BF16
                 multiply-accumulation operation; bfloat16 processing;
                 Computer architecture; CPU architectures; Digital
                 arithmetic; Error analysis; floating point arithmetic;
                 floating-point, rounding mode, neural networks; FP32;
                 GPU architectures; high-performance processing; IEEE
                 exception flags; IEEE floating-point standard features;
                 IEEE single-precision arithmetic; low-cost hardware
                 implementations; network-level accuracy; neural nets;
                 Neural Network accelerators; neural networks;
                 nonstandard rounding mode; Standards; Training",
}


bibtype: article
filename: fparith.bib
label: Burgess:2019:HPA
author: Neil Burgess and Chris Goodyer and Christopher N. Hinds and David R. Lutz
title: High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 967--978
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2855729
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Neil Burgess and Chris Goodyer and Christopher N. Hinds and David R. Lutz
rawtitle: High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
keywords:
2-lane HPA accumulation; 3-lane reproducible FP summation; accurate floating-point summation; computational properties; Computer architecture; datatype; double double accumulation; Electronic mail; Encoding; existing FP formats; floating point arithmetic; Floating-point addition; floating-point numbers; floating-point summation; FP arithmetic; FP16 summations; FP32 summations; FP64 accumulations; FP64 operands; Hardware; high-precision anchored accumulators; high-precision anchored number; high-precision computing; HPA processing; Instruction sets; modest ranges; programmer-selectable range; Proposals; Registers; reproducibility; reproducible accumulation; reproducible floating-point summation; scalable vector extension; SVE; vector architecture; vector processing

entry:
@Article{Burgess:2019:HPA,
  author =       "Neil Burgess and Chris Goodyer and Christopher N.
                 Hinds and David R. Lutz",
  title =        "High-Precision Anchored Accumulators for Reproducible
                 Floating-Point Summation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "967--978",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2855729",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "2-lane HPA accumulation; 3-lane reproducible FP
                 summation; accurate floating-point summation;
                 computational properties; Computer architecture;
                 datatype; double double accumulation; Electronic mail;
                 Encoding; existing FP formats; floating point
                 arithmetic; Floating-point addition; floating-point
                 numbers; floating-point summation; FP arithmetic; FP16
                 summations; FP32 summations; FP64 accumulations; FP64
                 operands; Hardware; high-precision anchored
                 accumulators; high-precision anchored number;
                 high-precision computing; HPA processing; Instruction
                 sets; modest ranges; programmer-selectable range;
                 Proposals; Registers; reproducibility; reproducible
                 accumulation; reproducible floating-point summation;
                 scalable vector extension; SVE; vector architecture;
                 vector processing",
}


bibtype: article
filename: fparith.bib
label: Cappello:2019:UCL
title: Use cases of lossy compression for floating-point data in scientific data sets
journal: j-IJHPCA
volume: 33
number: 6
pages: 1201--1220
day: 1
month: nov
monthnumber: 11
year: 2019
CODEN: IHPCFL
DOI: https://doi.org/10.1177/1094342019853336
ISSN: 1094-3420 (print), 1741-2846 (electronic) OR 10943420 (print), 17412846 (electronic)
ISSNL: 1094-3420 OR 10943420
bibdate: Wed Oct 9 14:35:54 MDT 2019
bibtimestamp: 2019.10.09 14:35:54 MDT
URL: https://journals.sagepub.com/doi/full/10.1177/1094342019853336
fjournal: International Journal of High Performance Computing Applications
acknowledgement: ack-nhfb
journalURL: https://journals.sagepub.com/home/hpc
rawtitle: Use cases of lossy compression for floating-point data in scientific data sets
author:
Franck Cappello and Sheng Di and Sihuan Li and Xin Liang and Ali Murat Gok and Dingwen Tao and Chun Hong Yoon and Xin-Chuan Wu and Yuri Alexeev and Frederic T. Chong

bibsource:
http://hpc.sagepub.com/; https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ijsa.bib

rawauthor:
Franck Cappello and Sheng Di and Sihuan Li and Xin Liang and Ali Murat Gok and Dingwen Tao and Chun Hong Yoon and Xin-Chuan Wu and Yuri Alexeev and Frederic T. Chong

entry:
@Article{Cappello:2019:UCL,
  author =       "Franck Cappello and Sheng Di and Sihuan Li and Xin
                 Liang and Ali Murat Gok and Dingwen Tao and Chun Hong
                 Yoon and Xin-Chuan Wu and Yuri Alexeev and Frederic T.
                 Chong",
  title =        "Use cases of lossy compression for floating-point data
                 in scientific data sets",
  journal =      j-IJHPCA,
  volume =       "33",
  number =       "6",
  pages =        "1201--1220",
  day =          "1",
  month =        nov,
  year =         "2019",
  CODEN =        "IHPCFL",
  DOI =          "https://doi.org/10.1177/1094342019853336",
  ISSN =         "1094-3420 (print), 1741-2846 (electronic)",
  ISSN-L =       "1094-3420",
  bibdate =      "Wed Oct 9 14:35:54 MDT 2019",
  bibsource =    "http://hpc.sagepub.com/;
                 https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ijsa.bib",
  URL =          "https://journals.sagepub.com/doi/full/10.1177/1094342019853336",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of High Performance Computing
                 Applications",
  journal-URL =  "https://journals.sagepub.com/home/hpc",
}


bibtype: misc
filename: fparith.bib
label: Carlough:2019:DBF
title: Decimal and binary floating point arithmetic calculations
pages: 1201--1220
day: 17
month: sep
monthnumber: 9
year: 2019
bibdate: Thu Oct 17 11:29:24 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 11:29:24 ???
URL: https://patents.google.com/patent/US10416962B2
acknowledgement: ack-nhfb
howpublished: US Patent 10,416,962
rawtitle: Decimal and binary floating point arithmetic calculations
author:
Steven R. Carlough and Juergen Haess and Michael Klein and Klaus M. Kroener and Petra Leber and Silvia M. Mueller and Kerstin Schelm

abstract:
Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

remark:
Patent filed 2 October 2015 based on British patent GB1417582.2 of 6 October 2014, granted 17 September 2019 to IBM, expected expiration 11 January 2036 (in 17th year after grant).

rawabstract:
Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

rawauthor:
Steven R. Carlough and Juergen Haess and Michael Klein and Klaus M. Kroener and Petra Leber and Silvia M. Mueller and Kerstin Schelm

entry:
@Misc{Carlough:2019:DBF,
  author =       "Steven R. Carlough and Juergen Haess and Michael Klein
                 and Klaus M. Kroener and Petra Leber and Silvia M.
                 Mueller and Kerstin Schelm",
  title =        "Decimal and binary floating point arithmetic
                 calculations",
  howpublished = "US Patent 10,416,962",
  day =          "17",
  month =        sep,
  year =         "2019",
  bibdate =      "Thu Oct 17 11:29:24 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US10416962B2",
  abstract =     "Logic is provided for performing decimal and binary
                 floating point arithmetic calculations on first and
                 second operands. The method includes: receiving the
                 first and second operands in packed format; unpacking
                 the first and second operands; swapping the first
                 operand to a fourth operand and the second operand to a
                 third operand, if an exponent of the first operand is
                 less than an exponent of the second operand, otherwise
                 storing the first operand to the third operand and the
                 second operand to the fourth operand; aligning the
                 third operand and the fourth operands based on the
                 exponent difference of the third and fourth operand and
                 a number of leading zeroes of the third operand;
                 performing an add/subtract operation on the aligned
                 third and fourth operands with normalizing and rounding
                 between the operands; and packing the result obtained
                 from the add/subtract.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 2 October 2015 based on British patent
                 GB1417582.2 of 6 October 2014, granted 17 September
                 2019 to IBM, expected expiration 11 January 2036 (in
                 17th year after grant).",
}


bibtype: inproceedings
filename: fparith.bib
label: Carmichael:2019:DPD
editor: IEEE
booktitle: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
title: Deep Positron: a Deep Neural Network Using the Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1421--1426
year: 2019
DOI: https://doi.org/10.23919/DATE.2019.8715262
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2019 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
raweditor: {IEEE}
rawtitle: {Deep Positron}: a Deep Neural Network Using the Posit Number System
author:
Zachariah Carmichael and Hamed F. Langroudi and Char Khazanov and Jeffrey Lillie and John L. Gustafson and Dhireesha Kudithipudi

rawauthor:
Zachariah Carmichael and Hamed F. Langroudi and Char Khazanov and Jeffrey Lillie and John L. Gustafson and Dhireesha Kudithipudi

entry:
@InProceedings{Carmichael:2019:DPD,
  author =       "Zachariah Carmichael and Hamed F. Langroudi and Char
                 Khazanov and Jeffrey Lillie and John L. Gustafson and
                 Dhireesha Kudithipudi",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{Deep Positron}: a Deep Neural Network Using the Posit
                 Number System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1421--1426",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8715262",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Carmichael:2019:PET
title: Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks
crossref: Gustafson:2019:CPC
pages: 3:1--3:9
year: 2019
DOI: https://doi.org/10.1145/3316279.3316282
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
acknowledgement: ack-nhfb
articleno: 3
rawtitle: Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks
author:
Zachariah Carmichael and Hamed F. Langroudi and Char Khazanov and Jeffrey Lillie and John L. Gustafson and Dhireesha Kudithipudi

keywords:
machine learning, deep neural networks, floating point, posit numerical format, DNN accelerators, tapered precision, low-precision

entry:
@InProceedings{Carmichael:2019:PET,
  author =       "Zachariah Carmichael and Hamed F. Langroudi and Char
                 Khazanov and Jeffrey Lillie and John L. Gustafson and
                 Dhireesha Kudithipudi",
  title =        "Performance-Efficiency Trade-off of Low-Precision
                 Numerical Formats in Deep Neural Networks",
  crossref =     "Gustafson:2019:CPC",
  pages =        "3:1--3:9",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316282",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  keywords =     "machine learning, deep neural networks, floating
                 point, posit numerical format, DNN accelerators,
                 tapered precision, low-precision",
  location =     "Singapore, Singapore",
  numpages =     "9",
}


bibtype: misc
filename: fparith.bib
label: Caygill:2019:DCF
author: Rebecca Caygill
title: Digital Computers Fail to Accurately Model Chaos Because of Fundamental Numbers Limit
pages: 3:1--3:9
day: 23
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Sep 24 05:29:26 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:29:26 ???
note: See cite Boghosian:2019:NPS.
acknowledgement: ack-nhfb
howpublished: University College London news release.
rawauthor: Rebecca Caygill
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Digital Computers Fail to Accurately Model Chaos Because of Fundamental Numbers Limit
URL:
https://scitechdaily.com/digital-computers-fail-to-accurately-model-chaos-because-of-fundamental-numbers-limit/

entry:
@Misc{Caygill:2019:DCF,
  author =       "Rebecca Caygill",
  title =        "Digital Computers Fail to Accurately Model Chaos
                 Because of Fundamental Numbers Limit",
  howpublished = "University College London news release.",
  day =          "23",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Sep 24 05:29:26 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://scitechdaily.com/digital-computers-fail-to-accurately-model-chaos-because-of-fundamental-numbers-limit/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Caygill:2019:NLH
author: Rebecca Caygill
title: Numbers limit how accurately digital computers model chaos
pages: 3:1--3:9
day: 23
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Sep 24 05:29:26 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:29:26 ???
note: See cite Boghosian:2019:NPS.
URL: https://www.eurekalert.org/pub_releases/2019-09/ucl-nlh092019.php
acknowledgement: ack-nhfb
howpublished: University College London news release.
rawauthor: Rebecca Caygill
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Numbers limit how accurately digital computers model chaos
entry:
@Misc{Caygill:2019:NLH,
  author =       "Rebecca Caygill",
  title =        "Numbers limit how accurately digital computers model
                 chaos",
  howpublished = "University College London news release.",
  day =          "23",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Sep 24 05:29:26 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://www.eurekalert.org/pub_releases/2019-09/ucl-nlh092019.php",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Chen:2019:EIR
author: K. Chen and L. Chen and P. Reviriego and F. Lombardi
title: Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC)
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 784--790
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2885044
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: K. Chen and L. Chen and P. Reviriego and F. Lombardi
rawtitle: Efficient Implementations of Reduced Precision Redundancy ({RPR}) Multiply and Accumulate ({MAC})
keywords:
Adders; arithmetic circuits; circuit overhead; computational environments; critical systems; deep machine learning; digital arithmetic; Discrete cosine transforms; error correction; error correction capabilities; error correction codes; implementation overhead; learning (artificial intelligence); MAC implementations; MAC operation; Machine learning; matrix multiplication; Mean Square Error; mean square error methods; modern computing systems; multiply and accumulate; neural networks; Neural networks; object recognition; precision copies; reduced precision redundancy; redundancy; Redundancy; RPR implementations; signed integer multiplication; soft error; Soft errors; Tunneling magnetoresistance

entry:
@Article{Chen:2019:EIR,
  author =       "K. Chen and L. Chen and P. Reviriego and F. Lombardi",
  title =        "Efficient Implementations of Reduced Precision
                 Redundancy ({RPR}) Multiply and Accumulate ({MAC})",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "784--790",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2885044",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; arithmetic circuits; circuit overhead;
                 computational environments; critical systems; deep
                 machine learning; digital arithmetic; Discrete cosine
                 transforms; error correction; error correction
                 capabilities; error correction codes; implementation
                 overhead; learning (artificial intelligence); MAC
                 implementations; MAC operation; Machine learning;
                 matrix multiplication; Mean Square Error; mean square
                 error methods; modern computing systems; multiply and
                 accumulate; neural networks; Neural networks; object
                 recognition; precision copies; reduced precision
                 redundancy; redundancy; Redundancy; RPR
                 implementations; signed integer multiplication; soft
                 error; Soft errors; Tunneling magnetoresistance",
}


bibtype: article
filename: fparith.bib
label: Cheng:2019:TCI
author: Xi Cheng and Min Zhou and Xiaoyu Song and Ming Gu and Jiaguang Sun
title: Tolerating C Integer Error via Precision Elevation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 2
pages: 270--286
month: feb
monthnumber: 2
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2866388
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Feb 4 19:28:55 MST 2019
bibtimestamp: 2019.02.04 19:28:55 MST
URL: https://ieeexplore.ieee.org/document/8443077/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Xi Cheng and Min Zhou and Xiaoyu Song and Ming Gu and Jiaguang Sun
rawtitle: Tolerating {C} Integer Error via Precision Elevation
entry:
@Article{Cheng:2019:TCI,
  author =       "Xi Cheng and Min Zhou and Xiaoyu Song and Ming Gu and
                 Jiaguang Sun",
  title =        "Tolerating {C} Integer Error via Precision Elevation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "2",
  pages =        "270--286",
  month =        feb,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2866388",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Feb 4 19:28:55 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8443077/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2019:NTI
author: Marius Cornea
title: New Technologies for Improved Computing
crossref: Takagi:2019:ISC
pages: 96--96
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00024
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Marius Cornea
rawtitle: New Technologies for Improved Computing
abstract:
In recent years, we learned to live with a slow-down in the growth rates predicted so far with remarkable accuracy by Moore's law. However, this does not necessarily mean that advancements in performance and reduced power consumption are not possible anymore. There will be more innovations and improvements in processor and system architecture and microarchitecture than before, which will enable continued growth - at Intel, and in the industry. Intel has identified several areas which deserve focused efforts and investment, with the promise of providing in return growth and results we came to expect. Manufacturing processes constitute the first such area. Besides using more advanced technologies to achieve smaller features on our ICs, Intel is also introducing advanced packaging solutions, which will enable exponential scaling in computing density by extending transistor placement in a third dimension. The second area is that of processor and system architecture. Computing architectures from Intel span most of the existing compute spectrum, with scalar, vector, matrix, and spatial architectures. These map roughly to our CPUs, GPUs, accelerators, and FPGAs. Memory is at the center of the third focus area. The memory hierarchy is optimized by capacity, latency, bandwidth, cost, and other features. Persistent memory and high-bandwidth memory have been introduced relatively recently in Intel systems, and will continue to influence the way the memory system is structured. The interconnect is the next important component, in a vastly heterogeneous computing environment for almost all compute devices. Communication has to keep up with computation capacity, a true challenge when trillions of operations per second are possible in many commonly used systems. Security is the fifth focus area, where Intel has the components to improve safety in computation and data preservation in a world where threats increase in number and sophistication, as seen too often recently. Last but not least, software has a significant potential in increasing computing capabilities. Intel is aiming to offer a common set of tools that can address the needs of developers for all the devices we offer, from CPUs and GPUs, to accelerators and FPGAs. Computer arithmetic is central to several of the areas highlighted above. Advancements in this field will play an important role in present as well as future processor architectures and implementations. In conclusion, we will also look at developments in this area for future Intel processors.

keywords:
accelerator; ARITH-26; Computer architecture; computer arithmetic; computing architectures; Cornea; CPU; data preservation; data security; Digital arithmetic; digital arithmetic; Field programmable gate arrays; field programmable gate arrays; FPGA; GPU; hardware accelerators; heterogeneous computing environment; improved computing; industrial economics; integrated circuit manufacture; integrated circuit packaging; manufacturing processes; memory hierarchy; microprocessor chips; packaging solutions; Power demand; security of data; semiconductor storage; semiconductor technology; Systems architecture; Technological innovation; three-dimensional integrated circuits; transistor placement

rawabstract:
In recent years, we learned to live with a slow-down in the growth rates predicted so far with remarkable accuracy by Moore's law. However, this does not necessarily mean that advancements in performance and reduced power consumption are not possible anymore. There will be more innovations and improvements in processor and system architecture and microarchitecture than before, which will enable continued growth - at Intel, and in the industry. Intel has identified several areas which deserve focused efforts and investment, with the promise of providing in return growth and results we came to expect. Manufacturing processes constitute the first such area. Besides using more advanced technologies to achieve smaller features on our ICs, Intel is also introducing advanced packaging solutions, which will enable exponential scaling in computing density by extending transistor placement in a third dimension. The second area is that of processor and system architecture. Computing architectures from Intel span most of the existing compute spectrum, with scalar, vector, matrix, and spatial architectures. These map roughly to our CPUs, GPUs, accelerators, and FPGAs. Memory is at the center of the third focus area. The memory hierarchy is optimized by capacity, latency, bandwidth, cost, and other features. Persistent memory and high-bandwidth memory have been introduced relatively recently in Intel systems, and will continue to influence the way the memory system is structured. The interconnect is the next important component, in a vastly heterogeneous computing environment for almost all compute devices. Communication has to keep up with computation capacity, a true challenge when trillions of operations per second are possible in many commonly used systems. Security is the fifth focus area, where Intel has the components to improve safety in computation and data preservation in a world where threats increase in number and sophistication, as seen too often recently. Last but not least, software has a significant potential in increasing computing capabilities. Intel is aiming to offer a common set of tools that can address the needs of developers for all the devices we offer, from CPUs and GPUs, to accelerators and FPGAs. Computer arithmetic is central to several of the areas highlighted above. Advancements in this field will play an important role in present as well as future processor architectures and implementations. In conclusion, we will also look at developments in this area for future Intel processors.

entry:
@InProceedings{Cornea:2019:NTI,
  author =       "Marius Cornea",
  title =        "New Technologies for Improved Computing",
  crossref =     "Takagi:2019:ISC",
  pages =        "96--96",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00024",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In recent years, we learned to live with a slow-down
                 in the growth rates predicted so far with remarkable
                 accuracy by Moore's law. However, this does not
                 necessarily mean that advancements in performance and
                 reduced power consumption are not possible anymore.
                 There will be more innovations and improvements in
                 processor and system architecture and microarchitecture
                 than before, which will enable continued growth - at
                 Intel, and in the industry. Intel has identified
                 several areas which deserve focused efforts and
                 investment, with the promise of providing in return
                 growth and results we came to expect. Manufacturing
                 processes constitute the first such area. Besides using
                 more advanced technologies to achieve smaller features
                 on our ICs, Intel is also introducing advanced
                 packaging solutions, which will enable exponential
                 scaling in computing density by extending transistor
                 placement in a third dimension. The second area is that
                 of processor and system architecture. Computing
                 architectures from Intel span most of the existing
                 compute spectrum, with scalar, vector, matrix, and
                 spatial architectures. These map roughly to our CPUs,
                 GPUs, accelerators, and FPGAs. Memory is at the center
                 of the third focus area. The memory hierarchy is
                 optimized by capacity, latency, bandwidth, cost, and
                 other features. Persistent memory and high-bandwidth
                 memory have been introduced relatively recently in
                 Intel systems, and will continue to influence the way
                 the memory system is structured. The interconnect is
                 the next important component, in a vastly heterogeneous
                 computing environment for almost all compute devices.
                 Communication has to keep up with computation capacity,
                 a true challenge when trillions of operations per
                 second are possible in many commonly used systems.
                 Security is the fifth focus area, where Intel has the
                 components to improve safety in computation and data
                 preservation in a world where threats increase in
                 number and sophistication, as seen too often recently.
                 Last but not least, software has a significant
                 potential in increasing computing capabilities. Intel
                 is aiming to offer a common set of tools that can
                 address the needs of developers for all the devices we
                 offer, from CPUs and GPUs, to accelerators and FPGAs.
                 Computer arithmetic is central to several of the areas
                 highlighted above. Advancements in this field will play
                 an important role in present as well as future
                 processor architectures and implementations. In
                 conclusion, we will also look at developments in this
                 area for future Intel processors.",
  acknowledgement = ack-nhfb,
  keywords =     "accelerator; ARITH-26; Computer architecture; computer
                 arithmetic; computing architectures; Cornea; CPU; data
                 preservation; data security; Digital arithmetic;
                 digital arithmetic; Field programmable gate arrays;
                 field programmable gate arrays; FPGA; GPU; hardware
                 accelerators; heterogeneous computing environment;
                 improved computing; industrial economics; integrated
                 circuit manufacture; integrated circuit packaging;
                 manufacturing processes; memory hierarchy;
                 microprocessor chips; packaging solutions; Power
                 demand; security of data; semiconductor storage;
                 semiconductor technology; Systems architecture;
                 Technological innovation; three-dimensional integrated
                 circuits; transistor placement",
}


bibtype: article
filename: fparith.bib
label: Courtois:2019:RRR
author: J. Courtois and L. Abbas-Turki and J. Bajard
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 12
pages: 1720--1730
month: dec
monthnumber: 12
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2924630
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Nov 7 11:20:24 2019
bibtimestamp: 2019.11.07 11:20:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. Courtois and L. Abbas-Turki and J. Bajard
title:
Resilience of Randomized RNS Arithmetic with Respect to Side-Channel Leaks of Cryptographic Computation

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

keywords:
CPA; DPA; ECC; Elliptic curve cryptography; Elliptic curves; Hamming distance; Hamming weight; information leakage; Maximum likelihood estimation; maximum likelihood estimator; moduli randomization; Monte Carlo; Multiprotocol label switching; Resilience; RNS; side channel

rawtitle:
Resilience of Randomized {RNS} Arithmetic with Respect to Side-Channel Leaks of Cryptographic Computation

entry:
@Article{Courtois:2019:RRR,
  author =       "J. Courtois and L. Abbas-Turki and J. Bajard",
  title =        "Resilience of Randomized {RNS} Arithmetic with Respect
                 to Side-Channel Leaks of Cryptographic Computation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "12",
  pages =        "1720--1730",
  month =        dec,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2924630",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Nov 7 11:20:24 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "CPA; DPA; ECC; Elliptic curve cryptography; Elliptic
                 curves; Hamming distance; Hamming weight; information
                 leakage; Maximum likelihood estimation; maximum
                 likelihood estimator; moduli randomization; Monte
                 Carlo; Multiprotocol label switching; Resilience; RNS;
                 side channel",
}


bibtype: article
filename: fparith.bib
label: Covanov:2019:FIM
author: Svyatoslav Covanov and Emmanuel Thome
title: Fast integer multiplication using generalized Fermat primes
journal: j-MATH-COMPUT
volume: 88
number: 317
pages: 1449--1477
month: jan
monthnumber: 1
year: 2019
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3367
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Tue Jul 14 06:45:38 MDT 2020
bibtimestamp: 2020.07.14 06:45:38 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Svyatoslav Covanov and Emmanuel Thom{\'e}
rawtitle: Fast integer multiplication using generalized {Fermat} primes
bibsource:
http://www.ams.org/mcom/2019-88-317; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1; https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1/S0025-5718-2018-03367-1.pdf; https://www.ams.org/mathscinet/search/authors.html?authorName=Thome%2C%20Emmanuel; https://www.ams.org/mathscinet/search/authors.html?mrauthid=1105937

entry:
@Article{Covanov:2019:FIM,
  author =       "Svyatoslav Covanov and Emmanuel Thom{\'e}",
  title =        "Fast integer multiplication using generalized {Fermat}
                 primes",
  journal =      j-MATH-COMPUT,
  volume =       "88",
  number =       "317",
  pages =        "1449--1477",
  month =        jan,
  year =         "2019",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3367",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Tue Jul 14 06:45:38 MDT 2020",
  bibsource =    "http://www.ams.org/mcom/2019-88-317;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1;
                 https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1/S0025-5718-2018-03367-1.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?authorName=Thome%2C%20Emmanuel;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=1105937",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: misc
filename: fparith.bib
label: Cowlishaw:2019:AIS
author: Mike Cowlishaw and David Hough
title: ANSI / IEEE Std 754-2019
pages: 1449--1477
day: 13
month: jun
monthnumber: 6
year: 2019
bibdate: Fri Aug 30 07:30:45 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.30 07:30:45 ???
URL: http://754r.ucbtest.org/remote/background/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Mike Cowlishaw and David Hough
rawtitle: {ANSI\slash IEEE Std 754-2019}
abstract:
The IEEE 754-2008 standard expired in 2019, so a minor revision was undertaken, to determine a set of relatively non-controversial upward-compatible editorial corrections and clarifications and minor enhancements to the 2008 standard. 754-2019 was approved by IEEE Standards Board on 13 June 2019 and published in July 2019. David Hough was chair, Mike Cowlishaw was editor. The base document was the technical content of ANSI/IEEE Std 754-2008. Some new operations have been recommended in 2019. In particular, new min/max operations better match application requirements, augmented addition, subtraction, and multiplication operations support building higher precision in software and support reproducible reductions on arrays, and new operations get and set NaN payloads. These recommended operations might be required in a future edition of this standard.

rawabstract:
The IEEE 754-2008 standard expired in 2019, so a minor revision was undertaken, to determine a set of relatively non-controversial upward-compatible editorial corrections and clarifications and minor enhancements to the 2008 standard. 754-2019 was approved by IEEE Standards Board on 13 June 2019 and published in July 2019. David Hough was chair, Mike Cowlishaw was editor. The base document was the technical content of ANSI/IEEE Std 754-2008. Some new operations have been recommended in 2019. In particular, new min/max operations better match application requirements, augmented addition, subtraction, and multiplication operations support building higher precision in software and support reproducible reductions on arrays, and new operations get and set NaN payloads. These recommended operations might be required in a future edition of this standard.

entry:
@Misc{Cowlishaw:2019:AIS,
  author =       "Mike Cowlishaw and David Hough",
  title =        "{ANSI\slash IEEE Std 754-2019}",
  howpublished = "Web site",
  day =          "13",
  month =        jun,
  year =         "2019",
  bibdate =      "Fri Aug 30 07:30:45 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://754r.ucbtest.org/remote/background/",
  abstract =     "The IEEE 754-2008 standard expired in 2019, so a minor
                 revision was undertaken, to determine a set of
                 relatively non-controversial upward-compatible
                 editorial corrections and clarifications and minor
                 enhancements to the 2008 standard. 754-2019 was
                 approved by IEEE Standards Board on 13 June 2019 and
                 published in July 2019. David Hough was chair, Mike
                 Cowlishaw was editor. The base document was the
                 technical content of ANSI/IEEE Std 754-2008.

                 Some new operations have been recommended in 2019. In
                 particular, new min/max operations better match
                 application requirements, augmented addition,
                 subtraction, and multiplication operations support
                 building higher precision in software and support
                 reproducible reductions on arrays, and new operations
                 get and set NaN payloads. These recommended operations
                 might be required in a future edition of this
                 standard.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Das:2019:FSA
booktitle: SC19: International Conference for High Performance Computing, Networking, Storage and Analysis
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--11
year: 2019
DOI: https://doi.org/10.1145/3295500.3357157
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {SC19: International Conference for High Performance Computing, Networking, Storage and Analysis}
author:
Sambit Das and Phani Motamarri and Vikram Gavini and Bruno Turcksin and Ying Wai Li and Brent Leback

title:
Fast, Scalable and Accurate Finite-Element Based Ab Initio Calculations Using Mixed Precision Computing: 46 PFLOPS Simulation of a Metallic Dislocation System

keywords:
Accuracy; Codes; Computational efficiency; Density functional theory; Discrete Fourier transforms; Electrons; Finite element analysis; Finite-elements; Graphics processing units; Heterogeneous architectures; High performance computing; Light-weight alloys; Magnesium; Mixed precision; Scalability

rawauthor:
Sambit Das and Phani Motamarri and Vikram Gavini and Bruno Turcksin and Ying Wai Li and Brent Leback

rawtitle:
Fast, Scalable and Accurate Finite-Element Based Ab Initio Calculations Using Mixed Precision Computing: 46 {PFLOPS} Simulation of a Metallic Dislocation System

entry:
@InProceedings{Das:2019:FSA,
  author =       "Sambit Das and Phani Motamarri and Vikram Gavini and
                 Bruno Turcksin and Ying Wai Li and Brent Leback",
  booktitle =    "{SC19: International Conference for High Performance
                 Computing, Networking, Storage and Analysis}",
  title =        "Fast, Scalable and Accurate Finite-Element Based Ab
                 Initio Calculations Using Mixed Precision Computing: 46
                 {PFLOPS} Simulation of a Metallic Dislocation System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--11",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3295500.3357157",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Codes; Computational efficiency; Density
                 functional theory; Discrete Fourier transforms;
                 Electrons; Finite element analysis; Finite-elements;
                 Graphics processing units; Heterogeneous architectures;
                 High performance computing; Light-weight alloys;
                 Magnesium; Mixed precision; Scalability",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2019:PGB
author: Florent de Dinechin and Luc Forget and Jean-Michel Muller and Yohann Uguen
title: Posits: The Good, the Bad and the Ugly
crossref: Gustafson:2019:CPC
pages: 6:1--6:10
year: 2019
DOI: https://doi.org/10.1145/3316279.3316285
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
keywords: numerical analysis, Posits, floating-point
acknowledgement: ack-nhfb
articleno: 6
rawauthor: Florent de Dinechin and Luc Forget and Jean-Michel Muller and Yohann Uguen
rawtitle: Posits: The Good, the Bad and the Ugly
entry:
@InProceedings{deDinechin:2019:PGB,
  author =       "Florent de Dinechin and Luc Forget and Jean-Michel
                 Muller and Yohann Uguen",
  title =        "Posits: The Good, the Bad and the Ugly",
  crossref =     "Gustafson:2019:CPC",
  pages =        "6:1--6:10",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316285",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  keywords =     "numerical analysis, Posits, floating-point",
  location =     "Singapore, Singapore",
  numpages =     "10",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2019:RYF
author: Florent de Dinechin
title: Reflections on 10 Years of FloPoCo
crossref: Takagi:2019:ISC
pages: 187--189
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00042
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin
rawtitle: Reflections on 10 Years of {FloPoCo}
abstract:
The FloPoCo open-source arithmetic core generator project started modestly in 2008 with a few parametric floating point cores. It has since then evolved to become a framework for research on hardware arithmetic cores at large. This article reviews some of the choices made in this past decade, and some of the challenges ahead for the next.

keywords:
ARITH-26; arithmetic core generation; Computer architecture; Digital arithmetic; Field programmable gate arrays; floating point arithmetic; flopoco; FloPoCo open-source arithmetic core generator project; Generators; Hardware; hardware arithmetic cores; parametric floating point cores; Tools; VHDL

rawabstract:
The FloPoCo open-source arithmetic core generator project started modestly in 2008 with a few parametric floating point cores. It has since then evolved to become a framework for research on hardware arithmetic cores at large. This article reviews some of the choices made in this past decade, and some of the challenges ahead for the next.

entry:
@InProceedings{deDinechin:2019:RYF,
  author =       "Florent de Dinechin",
  title =        "Reflections on 10 Years of {FloPoCo}",
  crossref =     "Takagi:2019:ISC",
  pages =        "187--189",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00042",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The FloPoCo open-source arithmetic core generator
                 project started modestly in 2008 with a few parametric
                 floating point cores. It has since then evolved to
                 become a framework for research on hardware arithmetic
                 cores at large. This article reviews some of the
                 choices made in this past decade, and some of the
                 challenges ahead for the next.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic core generation; Computer
                 architecture; Digital arithmetic; Field programmable
                 gate arrays; floating point arithmetic; flopoco;
                 FloPoCo open-source arithmetic core generator project;
                 Generators; Hardware; hardware arithmetic cores;
                 parametric floating point cores; Tools; VHDL",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2019:TBV
author: Florent de Dinechin and Silviu-Ioan Filip and Martin Kumm and Luc Forget
title: Table-Based versus Shift-And-Add Constant Multipliers for FPGAs
crossref: Takagi:2019:ISC
pages: 151--158
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00037
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Silviu-Ioan Filip and Martin Kumm and Luc Forget
rawtitle: Table-Based versus Shift-And-Add Constant Multipliers for {FPGAs}
abstract:
The multiplication by a constant is a frequently used operation. To implement it on Field Programmable Gate Arrays (FPGAs), the state of the art offers two completely different methods: one relying on bit shifts and additions/subtractions, and another one using look-up tables and additions. So far, it was unclear which method performs best for a given constant and input/output data types. The main contribution of this work is a thorough comparison of both methods in the main application contexts of constant multiplication: filters, signal-processing transforms, and elementary functions. Most of the previous state of the art addresses multiplication by an integer constant. This work shows that, in most of these application contexts, a formulation of the problem as the multiplication by a real constant allows for more efficient architectures. Another contribution is a novel extension of the shift-and-add method to real constants. For that, an integer linear programming (ILP) formulation is proposed, which truncates each component in the shift-and-add network to a minimum necessary word size that is aligned with the approximation error of the coefficient. All methods are implemented within the open-source FloPoCo framework.

keywords:
Adders; approximation theory; ARITH-26; Complexity theory; constant multiplier, FPGA, optimization, ILP; Field programmable gate arrays; Field Programmable Gate Arrays; field programmable gate arrays; FPGAs; Hardware; integer linear programming; integer programming; linear programming; look-up tables; multiplying circuits; shift-and-add network; signal-processing transforms; Table lookup; table lookup; table-based versus shift-and-add constant multipliers; Throughput

rawabstract:
The multiplication by a constant is a frequently used operation. To implement it on Field Programmable Gate Arrays (FPGAs), the state of the art offers two completely different methods: one relying on bit shifts and additions/subtractions, and another one using look-up tables and additions. So far, it was unclear which method performs best for a given constant and input/output data types. The main contribution of this work is a thorough comparison of both methods in the main application contexts of constant multiplication: filters, signal-processing transforms, and elementary functions. Most of the previous state of the art addresses multiplication by an integer constant. This work shows that, in most of these application contexts, a formulation of the problem as the multiplication by a real constant allows for more efficient architectures. Another contribution is a novel extension of the shift-and-add method to real constants. For that, an integer linear programming (ILP) formulation is proposed, which truncates each component in the shift-and-add network to a minimum necessary word size that is aligned with the approximation error of the coefficient. All methods are implemented within the open-source FloPoCo framework.

entry:
@InProceedings{deDinechin:2019:TBV,
  author =       "Florent de Dinechin and Silviu-Ioan Filip and Martin
                 Kumm and Luc Forget",
  title =        "Table-Based versus Shift-And-Add Constant Multipliers
                 for {FPGAs}",
  crossref =     "Takagi:2019:ISC",
  pages =        "151--158",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00037",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The multiplication by a constant is a frequently used
                 operation. To implement it on Field Programmable Gate
                 Arrays (FPGAs), the state of the art offers two
                 completely different methods: one relying on bit shifts
                 and additions/subtractions, and another one using
                 look-up tables and additions. So far, it was unclear
                 which method performs best for a given constant and
                 input/output data types. The main contribution of this
                 work is a thorough comparison of both methods in the
                 main application contexts of constant multiplication:
                 filters, signal-processing transforms, and elementary
                 functions. Most of the previous state of the art
                 addresses multiplication by an integer constant. This
                 work shows that, in most of these application contexts,
                 a formulation of the problem as the multiplication by a
                 real constant allows for more efficient architectures.
                 Another contribution is a novel extension of the
                 shift-and-add method to real constants. For that, an
                 integer linear programming (ILP) formulation is
                 proposed, which truncates each component in the
                 shift-and-add network to a minimum necessary word size
                 that is aligned with the approximation error of the
                 coefficient. All methods are implemented within the
                 open-source FloPoCo framework.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; approximation theory; ARITH-26; Complexity
                 theory; constant multiplier, FPGA, optimization, ILP;
                 Field programmable gate arrays; Field Programmable Gate
                 Arrays; field programmable gate arrays; FPGAs;
                 Hardware; integer linear programming; integer
                 programming; linear programming; look-up tables;
                 multiplying circuits; shift-and-add network;
                 signal-processing transforms; Table lookup; table
                 lookup; table-based versus shift-and-add constant
                 multipliers; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Didier:2019:RAP
title: Randomization of Arithmetic Over Polynomial Modular Number System
crossref: Takagi:2019:ISC
pages: 199--206
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00048
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawtitle: Randomization of Arithmetic Over Polynomial Modular Number System
author:
Laurent-Stephane Didier and Fangan-Yssouf Dosso and Nadia El Mrabet and Jeremy Marrez and Pascal Veron

abstract:
The Polynomial Modular Number System (PMNS) is an integer number system designed to speed up arithmetic operations modulo a prime p. Such a system is defined by a tuple B = (p, n, E) where E Z[X] and E() = 0 mod p. In a PMNS, an element a of Z/pZ is represented by a polynomial A such that: A() = a mod p, deg A <; n ||A|| <; p. In [6], the authors mentioned that PMNS can be highly redundant but they didn't really take advantage of this possibility. In this paper we use, for the first time, the redundancy of PMNS to protect algorithms against Side Channel Attacks (SCA). More precisely, we focus on elliptic curve cryptography. We show how to randomize the modular multiplication in order to be safe against existing SCA and we demonstrate the resistance of our construction. We describe the generation of a PMNS while guaranteeing, for all elements of Z/pZ, the minimum number of distinct representations we want. We also show how to reach all these representations.

keywords:
ARITH-26; arithmetic operations; digital arithmetic; elliptic curve cryptography; Elliptic curve cryptography; Elliptic curves; integer number system; Lattices; Manganese; modular multiplication; PMNS; polynomial modular number system; Polynomial Modular Number System, Side Channel Countermeasure, Modular Arithmetic; polynomials; Protocols; public key cryptography; Resistance; side channel attacks; Side-channel attacks

rawabstract:
The Polynomial Modular Number System (PMNS) is an integer number system designed to speed up arithmetic operations modulo a prime p. Such a system is defined by a tuple B = (p, n, E) where E Z[X] and E() = 0 mod p. In a PMNS, an element a of Z/pZ is represented by a polynomial A such that: A() = a mod p, deg A <; n ||A|| <; p. In [6], the authors mentioned that PMNS can be highly redundant but they didn't really take advantage of this possibility. In this paper we use, for the first time, the redundancy of PMNS to protect algorithms against Side Channel Attacks (SCA). More precisely, we focus on elliptic curve cryptography. We show how to randomize the modular multiplication in order to be safe against existing SCA and we demonstrate the resistance of our construction. We describe the generation of a PMNS while guaranteeing, for all elements of Z/pZ, the minimum number of distinct representations we want. We also show how to reach all these representations.

rawauthor:
Laurent-Stephane Didier and Fangan-Yssouf Dosso and Nadia {El Mrabet} and Jeremy Marrez and Pascal V{\'e}ron

entry:
@InProceedings{Didier:2019:RAP,
  author =       "Laurent-Stephane Didier and Fangan-Yssouf Dosso and
                 Nadia {El Mrabet} and Jeremy Marrez and Pascal
                 V{\'e}ron",
  title =        "Randomization of Arithmetic Over Polynomial Modular
                 Number System",
  crossref =     "Takagi:2019:ISC",
  pages =        "199--206",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00048",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Polynomial Modular Number System (PMNS) is an
                 integer number system designed to speed up arithmetic
                 operations modulo a prime p. Such a system is defined
                 by a tuple B = (p, n, E) where E Z[X] and E() = 0 mod
                 p. In a PMNS, an element a of Z/pZ is represented by a
                 polynomial A such that: A() = a mod p, deg A <; n ||A||
                 <; p. In [6], the authors mentioned that PMNS can be
                 highly redundant but they didn't really take advantage
                 of this possibility. In this paper we use, for the
                 first time, the redundancy of PMNS to protect
                 algorithms against Side Channel Attacks (SCA). More
                 precisely, we focus on elliptic curve cryptography. We
                 show how to randomize the modular multiplication in
                 order to be safe against existing SCA and we
                 demonstrate the resistance of our construction. We
                 describe the generation of a PMNS while guaranteeing,
                 for all elements of Z/pZ, the minimum number of
                 distinct representations we want. We also show how to
                 reach all these representations.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic operations; digital arithmetic;
                 elliptic curve cryptography; Elliptic curve
                 cryptography; Elliptic curves; integer number system;
                 Lattices; Manganese; modular multiplication; PMNS;
                 polynomial modular number system; Polynomial Modular
                 Number System, Side Channel Countermeasure, Modular
                 Arithmetic; polynomials; Protocols; public key
                 cryptography; Resistance; side channel attacks;
                 Side-channel attacks",
}


bibtype: article
filename: fparith.bib
label: Diffenderfer:2019:EAZ
title: Error Analysis of ZFP Compression for Floating-Point Data
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 3
pages: A1867--A1898
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/18M1168832
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Thu Oct 10 06:58:05 MDT 2019
bibtimestamp: 2019.10.10 06:58:05 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawtitle: Error Analysis of {ZFP} Compression for Floating-Point Data
author:
James Diffenderfer and Alyson L. Fox and Jeffrey A. Hittinger and Geoffrey Sanders and Peter G. Lindstrom

bibsource:
http://epubs.siam.org/toc/sjoce3/41/3; https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

rawauthor:
James Diffenderfer and Alyson L. Fox and Jeffrey A. Hittinger and Geoffrey Sanders and Peter G. Lindstrom

entry:
@Article{Diffenderfer:2019:EAZ,
  author =       "James Diffenderfer and Alyson L. Fox and Jeffrey A.
                 Hittinger and Geoffrey Sanders and Peter G. Lindstrom",
  title =        "Error Analysis of {ZFP} Compression for Floating-Point
                 Data",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "3",
  pages =        "A1867--A1898",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/18M1168832",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Thu Oct 10 06:58:05 MDT 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/3;
                 https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  onlinedate =   "January 2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Djath:2019:HAR
author: Libey Djath and Karim Bigou and Arnaud Tisserand
title: Hierarchical Approach in RNS Base Extension for Asymmetric Cryptography
crossref: Takagi:2019:ISC
pages: 46--53
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00016
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Libey Djath and Karim Bigou and Arnaud Tisserand
rawtitle: Hierarchical Approach in {RNS} Base Extension for Asymmetric Cryptography
abstract:
Base extension is a critical operation in RNS implementations of asymmetric cryptosystems. In this paper, we propose a new way to perform base extensions using a hierarchical approach for computing the Chinese remainder theorem. For well chosen parameters, it significantly reduces the computational cost and still ensures a high level of internal parallelism. We illustrate the interest of the proposed approach on the cost of typical arithmetic primitives used in asymmetric cryptography. We also demonstrate improvements in FPGA implementations of base extensions on typical elliptic curve cryptography field sizes using high-level synthesis tools.

keywords:
ARITH-26; asymmetric cryptosystems; Cathode ray tubes; Chinese remainder theorem; Computer architecture; computer arithmetic; cryptography; Elliptic curve cryptography; elliptic curve cryptography field sizes; field programmable gate arrays; FPGA implementations; hardware implementation; high level synthesis; high-level synthesis tools; modular reduction; Parallel processing; residue number system; residue number systems; RNS base extension; RNS implementations; Signal processing algorithms; Standards

rawabstract:
Base extension is a critical operation in RNS implementations of asymmetric cryptosystems. In this paper, we propose a new way to perform base extensions using a hierarchical approach for computing the Chinese remainder theorem. For well chosen parameters, it significantly reduces the computational cost and still ensures a high level of internal parallelism. We illustrate the interest of the proposed approach on the cost of typical arithmetic primitives used in asymmetric cryptography. We also demonstrate improvements in FPGA implementations of base extensions on typical elliptic curve cryptography field sizes using high-level synthesis tools.

entry:
@InProceedings{Djath:2019:HAR,
  author =       "Libey Djath and Karim Bigou and Arnaud Tisserand",
  title =        "Hierarchical Approach in {RNS} Base Extension for
                 Asymmetric Cryptography",
  crossref =     "Takagi:2019:ISC",
  pages =        "46--53",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00016",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Base extension is a critical operation in RNS
                 implementations of asymmetric cryptosystems. In this
                 paper, we propose a new way to perform base extensions
                 using a hierarchical approach for computing the Chinese
                 remainder theorem. For well chosen parameters, it
                 significantly reduces the computational cost and still
                 ensures a high level of internal parallelism. We
                 illustrate the interest of the proposed approach on the
                 cost of typical arithmetic primitives used in
                 asymmetric cryptography. We also demonstrate
                 improvements in FPGA implementations of base extensions
                 on typical elliptic curve cryptography field sizes
                 using high-level synthesis tools.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; asymmetric cryptosystems; Cathode ray tubes;
                 Chinese remainder theorem; Computer architecture;
                 computer arithmetic; cryptography; Elliptic curve
                 cryptography; elliptic curve cryptography field sizes;
                 field programmable gate arrays; FPGA implementations;
                 hardware implementation; high level synthesis;
                 high-level synthesis tools; modular reduction; Parallel
                 processing; residue number system; residue number
                 systems; RNS base extension; RNS implementations;
                 Signal processing algorithms; Standards",
}


bibtype: misc
filename: fparith.bib
label: Dockrill:2019:CMH
author: Peter Dockrill
title: Computers Are Making Huge Mistakes Because They Can't Understand Chaos, Scientists Warn
pages: 46--53
day: 27
month: sep
monthnumber: 9
year: 2019
bibdate: Mon Sep 30 11:25:59 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.30 11:25:59 ???
note: See cite Boghosian:2019:NPS.
acknowledgement: ack-nhfb
howpublished: ScienceAlert Web site
rawauthor: Peter Dockrill
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Computers Are Making Huge Mistakes Because They Can't Understand Chaos, Scientists Warn
URL:
https://www.sciencealert.com/computers-are-making-huge-mistakes-because-they-can-t-understand-chaos-scientists-warn

entry:
@Misc{Dockrill:2019:CMH,
  author =       "Peter Dockrill",
  title =        "Computers Are Making Huge Mistakes Because They Can't
                 Understand Chaos, Scientists Warn",
  howpublished = "ScienceAlert Web site",
  day =          "27",
  month =        sep,
  year =         "2019",
  bibdate =      "Mon Sep 30 11:25:59 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://www.sciencealert.com/computers-are-making-huge-mistakes-because-they-can-t-understand-chaos-scientists-warn",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Ensor:2019:BNB
author: Andrew Ensor
title: Big Numbers for a Big Universe
crossref: Takagi:2019:ISC
pages: 99--99
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00026
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrew Ensor
rawtitle: Big Numbers for a Big Universe
abstract:
The Square Kilometre Array is the world's largest mega-Science project of the next decade aiming to build enormous radio telescope arrays across Western Australia and Southern Africa. With 160 TeraByte/sec data generated in just stage one of the 50 year project and over 260 PetaFLOPS compute requirements it presents unprecedented data movement and processing challenges in its correlators, the detection and timing of pulsars, supercomputing pipelines for generating images, and scalable middleware. This talk will outline the project and its scientific goals, some of the key data processing pipelines, and will discuss the progress made by the design teams toward overcoming its computing challenges.

keywords:
Africa; ARITH-26; Arrays; Australia; big numbers; big universe; computing challenges; design teams; Digital arithmetic; generating images; High performance computing; key data processing pipelines; mega-Science project; middleware; parallel machines; PetaFLOPS compute requirements; Pipelines; processing challenges; Radio astronomy; radio telescope arrays; radiotelescopes; scalable middleware; scientific goals; Southern Africa; Square Kilometre Array; supercomputing pipelines; time 50.0 year; unprecedented data movement; Western Australia

rawabstract:
The Square Kilometre Array is the world's largest mega-Science project of the next decade aiming to build enormous radio telescope arrays across Western Australia and Southern Africa. With 160 TeraByte/sec data generated in just stage one of the 50 year project and over 260 PetaFLOPS compute requirements it presents unprecedented data movement and processing challenges in its correlators, the detection and timing of pulsars, supercomputing pipelines for generating images, and scalable middleware. This talk will outline the project and its scientific goals, some of the key data processing pipelines, and will discuss the progress made by the design teams toward overcoming its computing challenges.

entry:
@InProceedings{Ensor:2019:BNB,
  author =       "Andrew Ensor",
  title =        "Big Numbers for a Big Universe",
  crossref =     "Takagi:2019:ISC",
  pages =        "99--99",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00026",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Square Kilometre Array is the world's largest
                 mega-Science project of the next decade aiming to build
                 enormous radio telescope arrays across Western
                 Australia and Southern Africa. With 160 TeraByte/sec
                 data generated in just stage one of the 50 year project
                 and over 260 PetaFLOPS compute requirements it presents
                 unprecedented data movement and processing challenges
                 in its correlators, the detection and timing of
                 pulsars, supercomputing pipelines for generating
                 images, and scalable middleware. This talk will outline
                 the project and its scientific goals, some of the key
                 data processing pipelines, and will discuss the
                 progress made by the design teams toward overcoming its
                 computing challenges.",
  acknowledgement = ack-nhfb,
  keywords =     "Africa; ARITH-26; Arrays; Australia; big numbers; big
                 universe; computing challenges; design teams; Digital
                 arithmetic; generating images; High performance
                 computing; key data processing pipelines; mega-Science
                 project; middleware; parallel machines; PetaFLOPS
                 compute requirements; Pipelines; processing challenges;
                 Radio astronomy; radio telescope arrays;
                 radiotelescopes; scalable middleware; scientific goals;
                 Southern Africa; Square Kilometre Array; supercomputing
                 pipelines; time 50.0 year; unprecedented data movement;
                 Western Australia",
}


bibtype: article
filename: fparith.bib
label: Fabiano:2019:ATW
author: Nicolas Fabiano and Jean-Michel Muller and Joris Picot
title: Algorithms for Triple-Word Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1573--1583
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2918451
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
URL: https://hal.archives-ouvertes.fr/hal-01869009v2
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Nicolas Fabiano and Jean-Michel Muller and Joris Picot
rawtitle: Algorithms for Triple-Word Arithmetic
abstract:
Triple-word arithmetic consists in representing high-precision numbers as the unevaluated sum of three floating-point numbers (with nonoverlapping constraints that are explicited in the paper). We introduce and analyze various algorithms for manipulating triple-word numbers: rounding a triple-word number to a floating-point number, adding, multiplying, dividing, and computing square-roots of triple-word numbers, etc. We compare our algorithms, implemented in the Campary library, with other solutions of comparable accuracy. It turns out that our new algorithms are significantly faster than what one would obtain by just using the usual floating-point expansion algorithms in the special case of expansions of length 3.

keywords:
Computer arithmetic, floating-point arithmetic, triple-word arithmetic; Floating-point arithmetic; Libraries; Lips; Memory management; Physics; Programming; Standards

rawabstract:
Triple-word arithmetic consists in representing high-precision numbers as the unevaluated sum of three floating-point numbers (with nonoverlapping constraints that are explicited in the paper). We introduce and analyze various algorithms for manipulating triple-word numbers: rounding a triple-word number to a floating-point number, adding, multiplying, dividing, and computing square-roots of triple-word numbers, etc. We compare our algorithms, implemented in the Campary library, with other solutions of comparable accuracy. It turns out that our new algorithms are significantly faster than what one would obtain by just using the usual floating-point expansion algorithms in the special case of expansions of length 3.

entry:
@Article{Fabiano:2019:ATW,
  author =       "Nicolas Fabiano and Jean-Michel Muller and Joris
                 Picot",
  title =        "Algorithms for Triple-Word Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1573--1583",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2918451",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-01869009v2",
  abstract =     "Triple-word arithmetic consists in representing
                 high-precision numbers as the unevaluated sum of three
                 floating-point numbers (with nonoverlapping constraints
                 that are explicited in the paper). We introduce and
                 analyze various algorithms for manipulating triple-word
                 numbers: rounding a triple-word number to a
                 floating-point number, adding, multiplying, dividing,
                 and computing square-roots of triple-word numbers, etc.
                 We compare our algorithms, implemented in the Campary
                 library, with other solutions of comparable accuracy.
                 It turns out that our new algorithms are significantly
                 faster than what one would obtain by just using the
                 usual floating-point expansion algorithms in the
                 special case of expansions of length 3.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Computer arithmetic, floating-point arithmetic,
                 triple-word arithmetic; Floating-point arithmetic;
                 Libraries; Lips; Memory management; Physics;
                 Programming; Standards",
}


bibtype: article
filename: fparith.bib
label: Fang:2019:GSC
author: Linlin Fang and Yizhuang Xie and Bingyi Li and He Chen
title: Generation scheme of chirp scaling phase functions based on floating-point CORDIC processor
journal: The Journal of Engineering
volume: 2019
number: 21
pages: 7436--7439
year: 2019
DOI: https://doi.org/10.1049/joe.2019.0623
bibdate: Wed Oct 29 15:08:31 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.29 15:08:31 ???
URL: https://onlinelibrary.wiley.com/doi/abs/10.1049/joe.2019.0623
acknowledgement: ack-nhfb
rawauthor: Linlin Fang and Yizhuang Xie and Bingyi Li and He Chen
rawtitle: Generation scheme of chirp scaling phase functions based on floating-point {CORDIC} processor
keywords:
synthetic aperture radar, floating point arithmetic, field programmable gate arrays, radar imaging, logic design, function generators, chirp scaling phase functions, chirp scaling phase function generation scheme, CORDIC algorithm, single precision floating-point CORDIC processor, nonlinear operations, hardware resource reduction scheme, unified CORDIC processor, division operation, Xilinx XC7VX690T FPGA platform, SAR imaging system, CS synthetic aperture radar imaging algorithm, multiplication operation, square root operation

entry:
@Article{Fang:2019:GSC,
  author =       "Linlin Fang and Yizhuang Xie and Bingyi Li and He
                 Chen",
  title =        "Generation scheme of chirp scaling phase functions
                 based on floating-point {CORDIC} processor",
  journal =      "The Journal of Engineering",
  volume =       "2019",
  number =       "21",
  pages =        "7436--7439",
  year =         "2019",
  DOI =          "https://doi.org/10.1049/joe.2019.0623",
  bibdate =      "Wed Oct 29 15:08:31 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://onlinelibrary.wiley.com/doi/abs/10.1049/joe.2019.0623",
  acknowledgement = ack-nhfb,
  eprint =       "https://onlinelibrary.wiley.com/doi/pdf/10.1049/joe.2019.0623",
  keywords =     "synthetic aperture radar, floating point arithmetic,
                 field programmable gate arrays, radar imaging, logic
                 design, function generators, chirp scaling phase
                 functions, chirp scaling phase function generation
                 scheme, CORDIC algorithm, single precision
                 floating-point CORDIC processor, nonlinear operations,
                 hardware resource reduction scheme, unified CORDIC
                 processor, division operation, Xilinx XC7VX690T FPGA
                 platform, SAR imaging system, CS synthetic aperture
                 radar imaging algorithm, multiplication operation,
                 square root operation",
}


bibtype: misc
filename: fparith.bib
label: Feldman:2019:NAC
author: Michael Feldman
title: New Approach Could Sink Floating Point Computation
pages: 7436--7439
day: 8
month: jul
monthnumber: 7
year: 2019
bibdate: Tue Jul 09 10:28:21 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.07.09 10:28:21 ???
URL: https://www.nextplatform.com/2019/07/08/new-approach-could-sink-floating-point-computation/
remark: Interview with John L. Gustafson on Posits (universal numbers).
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Michael Feldman
rawtitle: New Approach Could Sink Floating Point Computation
entry:
@Misc{Feldman:2019:NAC,
  author =       "Michael Feldman",
  title =        "New Approach Could Sink Floating Point Computation",
  howpublished = "Web site",
  day =          "8",
  month =        jul,
  year =         "2019",
  bibdate =      "Tue Jul 09 10:28:21 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.nextplatform.com/2019/07/08/new-approach-could-sink-floating-point-computation/",
  acknowledgement = ack-nhfb,
  remark =       "Interview with John L. Gustafson on Posits (universal
                 numbers).",
}


bibtype: article
filename: fparith.bib
label: Flegar:2019:FCL
title: FloatX: A C++ Library for Customized Floating-Point Arithmetic
journal: j-TOMS
volume: 45
number: 4
pages: 40:1--40:??
month: dec
monthnumber: 12
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3368086
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Dec 27 14:56:25 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2019.12.27 14:56:25 MST
URL: https://dl.acm.org/citation.cfm?id=3368086
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 40
journalURL: https://dl.acm.org/loi/toms
rawtitle: {FloatX}: A {C++} Library for Customized Floating-Point Arithmetic
author:
Goran Flegar and Florian Scheidegger and Vedran Novakovic and Giovani Mariani and Andres E. Tomas and A. Cristiano I. Malossi and Enrique S. Quintana-Orti

abstract:
We present FloatX (Float eXtended), a C ++ framework to investigate the effect of leveraging customized floating-point formats in numerical applications. FloatX formats are based on binary IEEE 754 with smaller significand and exponent bit counts specified by the user. Among other properties, FloatX facilitates an incremental transformation of the code, relies on hardware-supported floating-point types as back-end to preserve efficiency, and incurs no storage overhead. The article discusses in detail the design principles, programming interface, and datatype casting rules behind FloatX. Furthermore, it demonstrates FloatX's usage and benefits via several case studies from well-known numerical dense linear algebra libraries, such as BLAS and LAPACK; the Ginkgo library for sparse linear systems; and two neural network applications related with image processing and text recognition.

rawabstract:
We present FloatX (Float eXtended), a C ++ framework to investigate the effect of leveraging customized floating-point formats in numerical applications. FloatX formats are based on binary IEEE 754 with smaller significand and exponent bit counts specified by the user. Among other properties, FloatX facilitates an incremental transformation of the code, relies on hardware-supported floating-point types as back-end to preserve efficiency, and incurs no storage overhead. The article discusses in detail the design principles, programming interface, and datatype casting rules behind FloatX. Furthermore, it demonstrates FloatX's usage and benefits via several case studies from well-known numerical dense linear algebra libraries, such as BLAS and LAPACK; the Ginkgo library for sparse linear systems; and two neural network applications related with image processing and text recognition.

rawauthor:
Goran Flegar and Florian Scheidegger and Vedran Novakovi{\'c} and Giovani Mariani and Andr{\'e}s E. Tom{\'a}s and A. Cristiano I. Malossi and Enrique S. Quintana-Ort{\'\i}

entry:
@Article{Flegar:2019:FCL,
  author =       "Goran Flegar and Florian Scheidegger and Vedran
                 Novakovi{\'c} and Giovani Mariani and Andr{\'e}s E.
                 Tom{\'a}s and A. Cristiano I. Malossi and Enrique S.
                 Quintana-Ort{\'\i}",
  title =        "{FloatX}: A {C++} Library for Customized
                 Floating-Point Arithmetic",
  journal =      j-TOMS,
  volume =       "45",
  number =       "4",
  pages =        "40:1--40:??",
  month =        dec,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3368086",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Dec 27 14:56:25 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3368086",
  abstract =     "We present FloatX (Float eXtended), a C ++ framework
                 to investigate the effect of leveraging customized
                 floating-point formats in numerical applications.
                 FloatX formats are based on binary IEEE 754 with
                 smaller significand and exponent bit counts specified
                 by the user. Among other properties, FloatX facilitates
                 an incremental transformation of the code, relies on
                 hardware-supported floating-point types as back-end to
                 preserve efficiency, and incurs no storage overhead.
                 The article discusses in detail the design principles,
                 programming interface, and datatype casting rules
                 behind FloatX. Furthermore, it demonstrates FloatX's
                 usage and benefits via several case studies from
                 well-known numerical dense linear algebra libraries,
                 such as BLAS and LAPACK; the Ginkgo library for sparse
                 linear systems; and two neural network applications
                 related with image processing and text recognition.",
  acknowledgement = ack-nhfb,
  articleno =    "40",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: manual
filename: fparith.bib
label: Fog:2019:ITL
author: Agner Fog
organization: Technical University of Denmark
address: Lyngby, Denmark
pages: 367
day: 15
month: aug
monthnumber: 8
year: 2019
bibdate: Thu Jan 30 16:18:42 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.30 16:18:42 ???
URL: https://www.agner.org/optimize/instruction_tables.pdf
acknowledgement: ack-nhfb
rawauthor: Agner Fog
title:
4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD, and VIA CPUs

remark:
This is the fourth in a series of five manuals: 1. Optimizing software in C++: An optimization guide for Windows, Linux and Mac platforms. 2. Optimizing subroutines in assembly language: An optimization guide for x86 platforms. 3. The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers. 4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs. 5. Calling conventions for different C++ compilers and operating systems. The manuals are copyrighted from 1996 to 2019.

rawtitle:
4. {Instruction} tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for {Intel}, {AMD}, and {VIA CPUs}

entry:
@Manual{Fog:2019:ITL,
  author =       "Agner Fog",
  title =        "4. {Instruction} tables: Lists of instruction
                 latencies, throughputs and micro-operation breakdowns
                 for {Intel}, {AMD}, and {VIA CPUs}",
  organization = "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "367",
  day =          "15",
  month =        aug,
  year =         "2019",
  bibdate =      "Thu Jan 30 16:18:42 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/instruction_tables.pdf",
  acknowledgement = ack-nhfb,
  remark =       "This is the fourth in a series of five manuals: 1.
                 Optimizing software in C++: An optimization guide for
                 Windows, Linux and Mac platforms. 2. Optimizing
                 subroutines in assembly language: An optimization guide
                 for x86 platforms. 3. The microarchitecture of Intel,
                 AMD and VIA CPUs: An optimization guide for assembly
                 programmers and compiler makers. 4. Instruction tables:
                 Lists of instruction latencies, throughputs and
                 micro-operation breakdowns for Intel, AMD and VIA CPUs.
                 5. Calling conventions for different C++ compilers and
                 operating systems. The manuals are copyrighted from
                 1996 to 2019.",
}


bibtype: article
filename: fparith.bib
label: Gallin:2019:GFP
author: G. Gallin and A. Tisserand
title: Generation of Finely-Pipelined GF($P$P) Multipliers for Flexible Curve Based Cryptography on FPGAs
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1612--1622
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2920352
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Gallin and A. Tisserand
keywords:
arithmetic operator generation; Clocks; Computer architecture; Cryptography; elliptic curve cryptography; Field programmable gate arrays; Hardware; Modular arithmetic; Montgomery multiplication; Pipelines; Tools

rawtitle:
Generation of Finely-Pipelined {GF($P$P)} Multipliers for Flexible Curve Based Cryptography on {FPGAs}

entry:
@Article{Gallin:2019:GFP,
  author =       "G. Gallin and A. Tisserand",
  title =        "Generation of Finely-Pipelined {GF($P$P)} Multipliers
                 for Flexible Curve Based Cryptography on {FPGAs}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1612--1622",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2920352",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic operator generation; Clocks; Computer
                 architecture; Cryptography; elliptic curve
                 cryptography; Field programmable gate arrays; Hardware;
                 Modular arithmetic; Montgomery multiplication;
                 Pipelines; Tools",
}


bibtype: inproceedings
filename: fparith.bib
label: Gorodecky:2019:EIM
author: Danila Gorodecky and Tiziano Villa
title: Efficient Implementation of Modular Division by Input Bit Splitting
crossref: Takagi:2019:ISC
pages: 54--60
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00017
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Danila Gorodecky and Tiziano Villa
rawtitle: Efficient Implementation of Modular Division by Input Bit Splitting
abstract:
Arithmetic operations, such as addition, multiplication, division and modular division, impact on the quality of arithmetic logic units and of the whole processor, with respect to area and delay of the circuit, power consumption, testability. In this article we propose an algorithm to implement efficiently the operation of modular division (X (mod P)), where P is pre-selected. The proposed approach is based on splitting the input operands into smaller binary tuples and then minimizing in parallel the two-level form of each suboperation on the tuples of the decomposition. The experiments show gains in performance and area of our approach vs. to circuits synthesized by state-of-art EDA tools with an advantage in delay and area up to 30 times.

keywords:
ARITH-26; arithmetic logic units; Boolean functions; Complexity theory; computer arithmetic, multiplication, modular division, logic minimization; Delays; digital arithmetic; dividing circuits; EDA tools; input bit splitting; input operands; logic design; Minimization; modular division; Partitioning algorithms; Power demand; smaller binary tuples; Tools

rawabstract:
Arithmetic operations, such as addition, multiplication, division and modular division, impact on the quality of arithmetic logic units and of the whole processor, with respect to area and delay of the circuit, power consumption, testability. In this article we propose an algorithm to implement efficiently the operation of modular division (X (mod P)), where P is pre-selected. The proposed approach is based on splitting the input operands into smaller binary tuples and then minimizing in parallel the two-level form of each suboperation on the tuples of the decomposition. The experiments show gains in performance and area of our approach vs. to circuits synthesized by state-of-art EDA tools with an advantage in delay and area up to 30 times.

entry:
@InProceedings{Gorodecky:2019:EIM,
  author =       "Danila Gorodecky and Tiziano Villa",
  title =        "Efficient Implementation of Modular Division by Input
                 Bit Splitting",
  crossref =     "Takagi:2019:ISC",
  pages =        "54--60",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00017",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Arithmetic operations, such as addition,
                 multiplication, division and modular division, impact
                 on the quality of arithmetic logic units and of the
                 whole processor, with respect to area and delay of the
                 circuit, power consumption, testability. In this
                 article we propose an algorithm to implement
                 efficiently the operation of modular division (X (mod
                 P)), where P is pre-selected. The proposed approach is
                 based on splitting the input operands into smaller
                 binary tuples and then minimizing in parallel the
                 two-level form of each suboperation on the tuples of
                 the decomposition. The experiments show gains in
                 performance and area of our approach vs. to circuits
                 synthesized by state-of-art EDA tools with an advantage
                 in delay and area up to 30 times.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic logic units; Boolean functions;
                 Complexity theory; computer arithmetic, multiplication,
                 modular division, logic minimization; Delays; digital
                 arithmetic; dividing circuits; EDA tools; input bit
                 splitting; input operands; logic design; Minimization;
                 modular division; Partitioning algorithms; Power
                 demand; smaller binary tuples; Tools",
}


bibtype: article
filename: fparith.bib
label: Graillat:2019:ATF
author: Stef Graillat and Fabienne Jezequel and Romain Picot and Francois Fevotte and Bruno Lathuiliere
title: Auto-tuning for floating-point precision with Discrete Stochastic Arithmetic
journal: j-J-COMPUT-SCI
volume: 36
pages: ??--??
month: sep
monthnumber: 9
year: 2019
DOI: https://doi.org/10.1016/j.jocs.2019.07.004
ISSN: 1877-7503 (print), 1877-7511 (electronic) OR 18777503 (print), 18777511 (electronic)
ISSNL: 1877-7503 OR 18777503
MRclass: 65Y20 (65C50)
MRnumber: 4007597
bibdate: Tue Sep 19 13:55:19 MDT 2023
bibtimestamp: 2023.09.19 13:55:19 MDT
URL: https://www.sciencedirect.com/science/article/pii/S1877750318309475
fjournal: Journal of Computational Science
acknowledgement: ack-nhfb
ajournal: J. Comput. Sci.
articleno: 101017
journalURL: https://www.sciencedirect.com/journal/journal-of-computational-science
rawtitle: Auto-tuning for floating-point precision with {Discrete Stochastic Arithmetic}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputsci.bib

rawauthor:
Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain Picot and Fran{\c{c}}ois F{\'e}votte and Bruno Lathuili{\`e}re

entry:
@Article{Graillat:2019:ATF,
  author =       "Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain
                 Picot and Fran{\c{c}}ois F{\'e}votte and Bruno
                 Lathuili{\`e}re",
  title =        "Auto-tuning for floating-point precision with
                 {Discrete Stochastic Arithmetic}",
  journal =      j-J-COMPUT-SCI,
  volume =       "36",
  pages =        "??--??",
  month =        sep,
  year =         "2019",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/j.jocs.2019.07.004",
  ISSN =         "1877-7503 (print), 1877-7511 (electronic)",
  ISSN-L =       "1877-7503",
  MRclass =      "65Y20 (65C50)",
  MRnumber =     "4007597",
  bibdate =      "Tue Sep 19 13:55:19 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputsci.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S1877750318309475",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Comput. Sci.",
  articleno =    "101017",
  fjournal =     "Journal of Computational Science",
  journal-URL =  "https://www.sciencedirect.com/journal/journal-of-computational-science",
  pagecount =    "11",
}


bibtype: misc
filename: fparith.bib
label: Grossman:2019:CSC
author: David Grossman
title: Computers Suck at Creating Chaos
pages: ??--??
day: 30
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Oct 01 08:57:55 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.01 08:57:55 ???
note: See cite Boghosian:2019:NPS.
URL: https://www.popularmechanics.com/science/a29271351/computers-chaotic-systems/
acknowledgement: ack-nhfb
howpublished: Popular Mechanics Web site
rawauthor: David Grossman
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Computers Suck at Creating Chaos
entry:
@Misc{Grossman:2019:CSC,
  author =       "David Grossman",
  title =        "Computers Suck at Creating Chaos",
  howpublished = "Popular Mechanics Web site",
  day =          "30",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Oct 01 08:57:55 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://www.popularmechanics.com/science/a29271351/computers-chaotic-systems/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Gu:2019:GRM
author: Z. Gu and S. Li
title: A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1689--1696
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2917433
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Z. Gu and S. Li
rawtitle: A Generalized {RNS} {Mclaughlin} Modular Multiplication with Non-Coprime Moduli Sets
keywords:
Digital arithmetic; Elliptic curve cryptography; Indexes; McLaughlin modular multiplication; Microelectronics; Montgomery modular multiplication; Performance evaluation; Residue number systems

entry:
@Article{Gu:2019:GRM,
  author =       "Z. Gu and S. Li",
  title =        "A Generalized {RNS} {Mclaughlin} Modular
                 Multiplication with Non-Coprime Moduli Sets",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1689--1696",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2917433",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Digital arithmetic; Elliptic curve cryptography;
                 Indexes; McLaughlin modular multiplication;
                 Microelectronics; Montgomery modular multiplication;
                 Performance evaluation; Residue number systems",
}


bibtype: article
filename: fparith.bib
label: Guerreiro:2019:MDG
author: Joao Guerreiro and Aleksandar Ilic and Nuno Roma and Pedro Tomas
title: Modeling and Decoupling the GPU Power Consumption for Cross-Domain DVFS
journal: j-IEEE-TRANS-PAR-DIST-SYS
volume: 30
number: 11
pages: 2494--2506
year: 2019
CODEN: ITDSEO
DOI: https://doi.org/10.1109/TPDS.2019.2917181
ISSN: 1045-9219 (print), 1558-2183 (electronic) OR 10459219 (print), 15582183 (electronic)
ISSNL: 1045-9219 OR 10459219
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Transactions on Parallel and Distributed Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71
rawauthor: Jo{\~a}o Guerreiro and Aleksandar Ilic and Nuno Roma and Pedro Tom{\'a}s
rawtitle: Modeling and Decoupling the {GPU} Power Consumption for Cross-Domain {DVFS}
keywords:
Benchmark testing; Computational modeling; DVFS; Frequency-domain analysis; GPGPU; Graphics processing units; Memory management; Power demand; power modeling; Predictive models; scaling-factors

entry:
@Article{Guerreiro:2019:MDG,
  author =       "Jo{\~a}o Guerreiro and Aleksandar Ilic and Nuno Roma
                 and Pedro Tom{\'a}s",
  title =        "Modeling and Decoupling the {GPU} Power Consumption
                 for Cross-Domain {DVFS}",
  journal =      j-IEEE-TRANS-PAR-DIST-SYS,
  volume =       "30",
  number =       "11",
  pages =        "2494--2506",
  year =         "2019",
  CODEN =        "ITDSEO",
  DOI =          "https://doi.org/10.1109/TPDS.2019.2917181",
  ISSN =         "1045-9219 (print), 1558-2183 (electronic)",
  ISSN-L =       "1045-9219",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Parallel and Distributed
                 Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71",
  keywords =     "Benchmark testing; Computational modeling; DVFS;
                 Frequency-domain analysis; GPGPU; Graphics processing
                 units; Memory management; Power demand; power modeling;
                 Predictive models; scaling-factors",
}


bibtype: article
filename: fparith.bib
label: Han:2019:FFE
author: Dong Han and Shengyuan Zhou and Tian Zhi and Yibo Wang and Shaoli Liu
title: Float-Fix: An Efficient and Hardware-Friendly Data Type for Deep Neural Network
journal: j-INT-J-PARALLEL-PROG
volume: 47
number: 3
pages: 345--359
month: jun
monthnumber: 6
year: 2019
CODEN: IJPPE5
DOI: https://doi.org/10.1007/s10766-018-00626-7
ISSN: 0885-7458 (print), 1573-7640 (electronic) OR 08857458 (print), 15737640 (electronic)
ISSNL: 0885-7458 OR 08857458
bibdate: Fri Oct 11 08:37:52 MDT 2019
bibtimestamp: 2019.10.11 08:37:52 MDT
fjournal: International Journal of Parallel Programming
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10766
rawauthor: Dong Han and Shengyuan Zhou and Tian Zhi and Yibo Wang and Shaoli Liu
rawtitle: {Float-Fix}: An Efficient and Hardware-Friendly Data Type for Deep Neural Network
bibsource:
http://link.springer.com/journal/10766/47/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/intjparallelprogram.bib

entry:
@Article{Han:2019:FFE,
  author =       "Dong Han and Shengyuan Zhou and Tian Zhi and Yibo Wang
                 and Shaoli Liu",
  title =        "{Float-Fix}: An Efficient and Hardware-Friendly Data
                 Type for Deep Neural Network",
  journal =      j-INT-J-PARALLEL-PROG,
  volume =       "47",
  number =       "3",
  pages =        "345--359",
  month =        jun,
  year =         "2019",
  CODEN =        "IJPPE5",
  DOI =          "https://doi.org/10.1007/s10766-018-00626-7",
  ISSN =         "0885-7458 (print), 1573-7640 (electronic)",
  ISSN-L =       "0885-7458",
  bibdate =      "Fri Oct 11 08:37:52 MDT 2019",
  bibsource =    "http://link.springer.com/journal/10766/47/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/intjparallelprogram.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Parallel Programming",
  journal-URL =  "http://link.springer.com/journal/10766",
}


bibtype: article
filename: fparith.bib
label: Hanuman:2019:IMP
author: C. R. S. Hanuman and J. Kamala and A. R. Aruna
journal: j-J-SUPERCOMPUTING
volume: 75
number: 9
pages: 6038--6054
month: sep
monthnumber: 9
year: 2019
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-019-02902-w
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Oct 10 15:31:22 MDT 2019
bibtimestamp: 2019.10.10 15:31:22 MDT
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: C. R. S. Hanuman and J. Kamala and A. R. Aruna
title:
Implementation of multi-precision floating point divider for high speed signal processing applications

bibsource:
http://link.springer.com/journal/11227/75/9; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper.bib

rawtitle:
Implementation of multi-precision floating point divider for high speed signal processing applications

entry:
@Article{Hanuman:2019:IMP,
  author =       "C. R. S. Hanuman and J. Kamala and A. R. Aruna",
  title =        "Implementation of multi-precision floating point
                 divider for high speed signal processing applications",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "75",
  number =       "9",
  pages =        "6038--6054",
  month =        sep,
  year =         "2019",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-019-02902-w",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Oct 10 15:31:22 MDT 2019",
  bibsource =    "http://link.springer.com/journal/11227/75/9;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: inproceedings
filename: fparith.bib
label: Hao:2019:VID
author: Liu Hao and Wang Ming-Jiang and Chen Mo-Ran and Liu Ming
booktitle: 2019 IEEE 4th International Conference on Signal and Image Processing (ICSIP)
title: A VLSI Implementation of Double Precision Floating-Point Logarithmic Function
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 345--349
year: 2019
DOI: https://doi.org/10.1109/SIPROCESS.2019.8868367
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Liu Hao and Wang Ming-Jiang and Chen Mo-Ran and Liu Ming
rawbooktitle: {2019 IEEE 4th International Conference on Signal and Image Processing (ICSIP)}
rawtitle: A {VLSI} Implementation of Double Precision Floating-Point Logarithmic Function
keywords:
Clocks; Convergence; CORDIC algorithm; Delays; double precision; floating-point number; Hardware; logarithmic function; Parallel processing; Prediction algorithms; Very large scale integration; VLSI

entry:
@InProceedings{Hao:2019:VID,
  author =       "Liu Hao and Wang Ming-Jiang and Chen Mo-Ran and Liu
                 Ming",
  booktitle =    "{2019 IEEE 4th International Conference on Signal and
                 Image Processing (ICSIP)}",
  title =        "A {VLSI} Implementation of Double Precision
                 Floating-Point Logarithmic Function",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "345--349",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SIPROCESS.2019.8868367",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Clocks; Convergence; CORDIC algorithm; Delays; double
                 precision; floating-point number; Hardware; logarithmic
                 function; Parallel processing; Prediction algorithms;
                 Very large scale integration; VLSI",
}


bibtype: article
filename: fparith.bib
label: Harase:2019:CMT
author: Shin Harase
title: Conversion of Mersenne Twister to double-precision floating-point numbers
journal: j-MATH-COMPUT-SIMUL
volume: 161
pages: 76--83
month: jul
monthnumber: 7
year: 2019
CODEN: MCSIDR
DOI: https://doi.org/10.1016/j.matcom.2018.08.006
ISSN: 0378-4754 (print), 1872-7166 (electronic) OR 03784754 (print), 18727166 (electronic)
ISSNL: 0378-4754 OR 03784754
bibdate: Sat Aug 16 06:05:54 MDT 2025
bibtimestamp: 2025.08.16 06:05:54 MDT
URL: https://www.sciencedirect.com/science/article/pii/S0378475418302040
fjournal: Mathematics and Computers in Simulation
acknowledgement: ack-nhfb
ajournal: Math. Comput. Simul.
journalURL: https://www.sciencedirect.com/science/journal/03784754
rawauthor: Shin Harase
rawtitle: Conversion of {Mersenne Twister} to double-precision floating-point numbers
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomputsimul2010.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib

entry:
@Article{Harase:2019:CMT,
  author =       "Shin Harase",
  title =        "Conversion of {Mersenne Twister} to double-precision
                 floating-point numbers",
  journal =      j-MATH-COMPUT-SIMUL,
  volume =       "161",
  pages =        "76--83",
  month =        jul,
  year =         "2019",
  CODEN =        "MCSIDR",
  DOI =          "https://doi.org/10.1016/j.matcom.2018.08.006",
  ISSN =         "0378-4754 (print), 1872-7166 (electronic)",
  ISSN-L =       "0378-4754",
  bibdate =      "Sat Aug 16 06:05:54 MDT 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomputsimul2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S0378475418302040",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput. Simul.",
  fjournal =     "Mathematics and Computers in Simulation",
  journal-URL =  "https://www.sciencedirect.com/science/journal/03784754",
}


bibtype: misc
filename: fparith.bib
label: Harthcock:2019:BUF
author: Jerry D. Harthcock
title: 64-bit-Universal-Floating-Point-ISA-Compute-Engine
pages: 76--83
day: 8
month: oct
monthnumber: 10
year: 2019
bibdate: Wed Oct 09 05:34:48 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.09 05:34:48 ???
URL: https://github.com/jerry-D/64-bit-Universal-Floating-Point-ISA-Compute-Engine
acknowledgement: ack-nhfb
howpublished: Github Web site.
rawauthor: Jerry D. Harthcock
rawtitle: {64-bit-Universal-Floating-Point-ISA-Compute-Engine}
abstract:
New 64-bit Universal Floating-Point ISA Compute Engine computes directly with human-readable decimal character sequences, binary64, 32, 16 or bfloat16 formatted numbers in any combination.

rawabstract:
New 64-bit Universal Floating-Point ISA Compute Engine computes directly with human-readable decimal character sequences, binary64, 32, 16 or bfloat16 formatted numbers in any combination.

entry:
@Misc{Harthcock:2019:BUF,
  author =       "Jerry D. Harthcock",
  title =        "{64-bit-Universal-Floating-Point-ISA-Compute-Engine}",
  howpublished = "Github Web site.",
  day =          "8",
  month =        oct,
  year =         "2019",
  bibdate =      "Wed Oct 09 05:34:48 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/jerry-D/64-bit-Universal-Floating-Point-ISA-Compute-Engine",
  abstract =     "New 64-bit Universal Floating-Point ISA Compute Engine
                 computes directly with human-readable decimal character
                 sequences, binary64, 32, 16 or bfloat16 formatted
                 numbers in any combination.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Harvey:2019:FIM
author: David Harvey and Joris van der Hoeven
title: Faster integer multiplication using plain vanilla FFT primes
journal: j-MATH-COMPUT
volume: 88
number: 315
pages: 501--514
month: jul
monthnumber: 7
year: 2019
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3328
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Tue Jul 14 06:45:34 MDT 2020
bibtimestamp: 2020.07.14 06:45:34 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: David Harvey and Joris van der Hoeven
rawtitle: Faster integer multiplication using plain vanilla {FFT} primes
bibsource:
http://www.ams.org/mcom/2019-88-315; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2; https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2/S0025-5718-2018-03328-2.pdf; https://www.ams.org/mathscinet/search/authors.html?mrauthid=621578; https://www.ams.org/mathscinet/search/authors.html?mrauthid=734771

entry:
@Article{Harvey:2019:FIM,
  author =       "David Harvey and Joris van der Hoeven",
  title =        "Faster integer multiplication using plain vanilla
                 {FFT} primes",
  journal =      j-MATH-COMPUT,
  volume =       "88",
  number =       "315",
  pages =        "501--514",
  month =        jul,
  year =         "2019",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3328",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Tue Jul 14 06:45:34 MDT 2020",
  bibsource =    "http://www.ams.org/mcom/2019-88-315;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2;
                 https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2/S0025-5718-2018-03328-2.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=621578;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=734771",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: techreport
filename: fparith.bib
label: Harvey:2019:IMT
author: David Harvey and Joris Van Der Hoeven
title: Integer multiplication in time $ O(n log n) $
type: Report
number: hal-02070778
address: Sydney, NSW 2052, Australia and 91128 Palaiseau, France
pages: 501--514
day: 18
month: mar
monthnumber: 3
year: 2019
bibdate: Fri Apr 12 14:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.04.12 14:09:18 ???
URL: https://hal.archives-ouvertes.fr/hal-02070778/document
acknowledgement: ack-nhfb
rawauthor: David Harvey and Joris {Van Der Hoeven}
rawtitle: Integer multiplication in time {$ O(n \log n) $}
institution:
School of Mathematics and Statistics, University of New South Wales, and CNRS, Laboratoire d'informatique, Ecole polytechnique

abstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n log n)$ bit operations.

rawabstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n \log n)$ bit operations.

entry:
@TechReport{Harvey:2019:IMT,
  author =       "David Harvey and Joris {Van Der Hoeven}",
  title =        "Integer multiplication in time {$ O(n \log n) $}",
  type =         "Report",
  number =       "hal-02070778",
  institution =  "School of Mathematics and Statistics, University of
                 New South Wales, and CNRS, Laboratoire d'informatique,
                 {\'E}cole polytechnique",
  address =      "Sydney, NSW 2052, Australia and 91128 Palaiseau,
                 France",
  day =          "18",
  month =        mar,
  year =         "2019",
  bibdate =      "Fri Apr 12 14:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-02070778/document",
  abstract =     "We present an algorithm that computes the product of
                 two $n$-bit integers in $ O(n \log n)$ bit
                 operations.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hayes:2019:DCB
author: Ari B. Hayes and Fei Hua and Jin Huang and Yanhao Chen and Eddy Z. Zhang
editor: Mahmut Taylan Kandemir and Alexandra Jimborean and Tipp Moseley
title: Decoding CUDA Binary
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 229--241
year: 2019
DOI: https://doi.org/10.1109/cgo.2019.8661186
ISBN: 1-72811-436-5, 1-72811-437-3 OR 1728114365, 1728114373
ISBN13: 978-1-72811-436-1, 978-1-72811-437-8 OR 9781728114361, 9781728114378
LCCN: QA76.76.G46 I57 2019
bibdate: Mon Sep 11 06:57:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 06:57:08 ???
note: IEEE Catalog Number CFP19CGO-ART.
URL: https://ieeexplore.ieee.org/document/8661186
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1109/CGO46174.2019
bookpages: xv + 287
rawauthor: Ari B. Hayes and Fei Hua and Jin Huang and Yanhao Chen and Eddy Z. Zhang
raweditor: Mahmut Taylan Kandemir and Alexandra Jimborean and Tipp Moseley
rawnote: IEEE Catalog Number CFP19CGO-ART.
rawtitle: Decoding {CUDA} Binary
booktitle:
CGO'19: Proceedings of the 2019 IEEE / ACM International Symposium on Code Generation and Optimization, 16--20 February 2019, Washington, DC, USA

abstract:
NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.

rawabstract:
NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.

rawbooktitle:
{CGO'19: Proceedings of the 2019 IEEE\slash ACM International Symposium on Code Generation and Optimization, 16--20 February 2019, Washington, DC, USA}

entry:
@InProceedings{Hayes:2019:DCB,
  author =       "Ari B. Hayes and Fei Hua and Jin Huang and Yanhao Chen
                 and Eddy Z. Zhang",
  editor =       "Mahmut Taylan Kandemir and Alexandra Jimborean and
                 Tipp Moseley",
  booktitle =    "{CGO'19: Proceedings of the 2019 IEEE\slash ACM
                 International Symposium on Code Generation and
                 Optimization, 16--20 February 2019, Washington, DC,
                 USA}",
  title =        "Decoding {CUDA} Binary",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xv + 287",
  pages =        "229--241",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/cgo.2019.8661186",
  ISBN =         "1-72811-436-5, 1-72811-437-3",
  ISBN-13 =      "978-1-72811-436-1, 978-1-72811-437-8",
  LCCN =         "QA76.76.G46 I57 2019",
  bibdate =      "Mon Sep 11 06:57:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IEEE Catalog Number CFP19CGO-ART.",
  URL =          "https://ieeexplore.ieee.org/document/8661186",
  abstract =     "NVIDIA's software does not offer translation of
                 assembly code to binary for their GPUs, since the
                 specifications are closed-source. This work fills that
                 gap. We develop a systematic method of decoding the
                 Instruction Set Architectures (ISAs) of NVIDIA's GPUs,
                 and generating assemblers for different generations of
                 GPUs. Our framework enables cross-architecture binary
                 analysis and transformation. Making the ISA accessible
                 in this manner opens up a world of opportunities for
                 developers and researchers, enabling numerous
                 optimizations and explorations that are unachievable at
                 the source-code level. Our infrastructure has already
                 benefited and been adopted in important applications
                 including performance tuning, binary instrumentation,
                 resource allocation, and memory protection.",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1109/CGO46174.2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Henry:2019:LBA
author: Greg Henry and Ping Tak Peter Tang and Alexander Heinecke
title: Leveraging the bfloat16 Artificial Intelligence Datatype For Higher-Precision Computations
crossref: Takagi:2019:ISC
pages: 69--76
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00019
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Greg Henry and Ping Tak Peter Tang and Alexander Heinecke
rawtitle: Leveraging the bfloat16 Artificial Intelligence Datatype For Higher-Precision Computations
abstract:
In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks due to their extreme computational intensity. Compared to classical IEEE-754 32 bit (FP32) and 64 bit (FP64) arithmetic, these reduced precision arithmetic can naturally be sped up disproportional to their shortened width. The common strategy of all major hardware vendors is to aggressively further enhance their performance disproportionately. One particular FMA operation that multiplies two BF16 numbers while accumulating in FP32 has been found useful in deep learning, where BF16 is the 16-bit floating point datatype with IEEE FP32 numerical range but 8 significant bits of precision. In this paper, we examine the use this FMA unit to implement higher-precision matrix routines in terms of potential performance gain and implications on accuracy. We demonstrate how a decomposition into multiple smaller datatypes can be used to assemble a high-precision result, leveraging the higher precision accumulation of the FMA unit. We first demonstrate that computations of vector inner products and by natural extension, matrix-matrix products can be achieved by decomposing FP32 numbers in several BF16 numbers followed by appropriate computations that can accommodate the dynamic range and preserve accuracy compared to standard FP32 computations, while projecting up to 5.2x speed-up. Furthermore, we examine solution of linear equations formulated in the residual form that allows for iterative refinement. We demonstrate that the solution obtained to be comparable to those offered by FP64 under a large range of linear system condition numbers.

keywords:
ARITH-26; artificial intelligence datatype; bfloat16, float16, mixed precision, combined datatypes; Deep learning; deep learning; deep neural networks; floating point arithmetic; floating point datatype; FMA unit; FP32 computations; fused-multiply-add units; Hardware; higher-precision matrix routines; IEEE-754 32 bit arithmetic; IEEE-754 FP32 arithmetic; IEEE-754 FP64 arithmetic; iterative methods; learning (artificial intelligence); matrix algebra; Matrix decomposition; matrix-matrix products; neural nets; Neural networks; Standards; Task analysis; Training

rawabstract:
In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks due to their extreme computational intensity. Compared to classical IEEE-754 32 bit (FP32) and 64 bit (FP64) arithmetic, these reduced precision arithmetic can naturally be sped up disproportional to their shortened width. The common strategy of all major hardware vendors is to aggressively further enhance their performance disproportionately. One particular FMA operation that multiplies two BF16 numbers while accumulating in FP32 has been found useful in deep learning, where BF16 is the 16-bit floating point datatype with IEEE FP32 numerical range but 8 significant bits of precision. In this paper, we examine the use this FMA unit to implement higher-precision matrix routines in terms of potential performance gain and implications on accuracy. We demonstrate how a decomposition into multiple smaller datatypes can be used to assemble a high-precision result, leveraging the higher precision accumulation of the FMA unit. We first demonstrate that computations of vector inner products and by natural extension, matrix-matrix products can be achieved by decomposing FP32 numbers in several BF16 numbers followed by appropriate computations that can accommodate the dynamic range and preserve accuracy compared to standard FP32 computations, while projecting up to 5.2x speed-up. Furthermore, we examine solution of linear equations formulated in the residual form that allows for iterative refinement. We demonstrate that the solution obtained to be comparable to those offered by FP64 under a large range of linear system condition numbers.

entry:
@InProceedings{Henry:2019:LBA,
  author =       "Greg Henry and Ping Tak Peter Tang and Alexander
                 Heinecke",
  title =        "Leveraging the bfloat16 Artificial Intelligence
                 Datatype For Higher-Precision Computations",
  crossref =     "Takagi:2019:ISC",
  pages =        "69--76",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00019",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In recent years fused-multiply-add (FMA) units with
                 lower-precision multiplications and higher-precision
                 accumulation have proven useful in machine
                 learning/artificial intelligence applications, most
                 notably in training deep neural networks due to their
                 extreme computational intensity. Compared to classical
                 IEEE-754 32 bit (FP32) and 64 bit (FP64) arithmetic,
                 these reduced precision arithmetic can naturally be
                 sped up disproportional to their shortened width. The
                 common strategy of all major hardware vendors is to
                 aggressively further enhance their performance
                 disproportionately. One particular FMA operation that
                 multiplies two BF16 numbers while accumulating in FP32
                 has been found useful in deep learning, where BF16 is
                 the 16-bit floating point datatype with IEEE FP32
                 numerical range but 8 significant bits of precision. In
                 this paper, we examine the use this FMA unit to
                 implement higher-precision matrix routines in terms of
                 potential performance gain and implications on
                 accuracy. We demonstrate how a decomposition into
                 multiple smaller datatypes can be used to assemble a
                 high-precision result, leveraging the higher precision
                 accumulation of the FMA unit. We first demonstrate that
                 computations of vector inner products and by natural
                 extension, matrix-matrix products can be achieved by
                 decomposing FP32 numbers in several BF16 numbers
                 followed by appropriate computations that can
                 accommodate the dynamic range and preserve accuracy
                 compared to standard FP32 computations, while
                 projecting up to 5.2x speed-up. Furthermore, we examine
                 solution of linear equations formulated in the residual
                 form that allows for iterative refinement. We
                 demonstrate that the solution obtained to be comparable
                 to those offered by FP64 under a large range of linear
                 system condition numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; artificial intelligence datatype; bfloat16,
                 float16, mixed precision, combined datatypes; Deep
                 learning; deep learning; deep neural networks; floating
                 point arithmetic; floating point datatype; FMA unit;
                 FP32 computations; fused-multiply-add units; Hardware;
                 higher-precision matrix routines; IEEE-754 32 bit
                 arithmetic; IEEE-754 FP32 arithmetic; IEEE-754 FP64
                 arithmetic; iterative methods; learning (artificial
                 intelligence); matrix algebra; Matrix decomposition;
                 matrix-matrix products; neural nets; Neural networks;
                 Standards; Task analysis; Training",
}


bibtype: article
filename: fparith.bib
label: Hiasat:2019:DRI
author: Ahmad Hiasat and Leonel Sousa
journal: j-COMP-J
volume: 62
number: 2
pages: 292--300
day: 1
month: feb
monthnumber: 2
year: 2019
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxy119
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Mon Feb 11 10:50:41 MST 2019
bibtimestamp: 2019.02.11 10:50:41 MST
URL: http://academic.oup.com/comjnl/article/62/2/292/5224762
fjournal: Computer Journal
keywords: Residue Number System (RNS)
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Ahmad Hiasat and Leonel Sousa
title:
On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets $ 2^n + k $, $ 2^n - 1 $, $ 2^n + 1 - 1 $

bibsource:
https://www.math.utah.edu/pub/tex/bib/compj2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
On the Design of {RNS} Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets $ 2^{n + k} $, $ 2^n - 1 $, $ 2^{n + 1} - 1 $

entry:
@Article{Hiasat:2019:DRI,
  author =       "Ahmad Hiasat and Leonel Sousa",
  title =        "On the Design of {RNS} Inter-Modulo Processing Units
                 for the Arithmetic-Friendly Moduli Sets $ 2^{n + k} $,
                 $ 2^n - 1 $, $ 2^{n + 1} - 1 $",
  journal =      j-COMP-J,
  volume =       "62",
  number =       "2",
  pages =        "292--300",
  day =          "1",
  month =        feb,
  year =         "2019",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxy119",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Mon Feb 11 10:50:41 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compj2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://academic.oup.com/comjnl/article/62/2/292/5224762",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "Residue Number System (RNS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Hickmann:2019:EAM
author: Brian Hickmann and Dennis Bradford
title: Experimental Analysis of Matrix Multiplication Functional Units
crossref: Takagi:2019:ISC
pages: 116--119
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00031
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Brian Hickmann and Dennis Bradford
rawtitle: Experimental Analysis of Matrix Multiplication Functional Units
abstract:
The rapid growth of AI has led to the introduction of several new hardware designs to accelerate the matrix multiplication operation at the heart of AI applications. Examples include NVIDIA's Tensor Core*, Google's TPU*, and Intel's Neural Compute Stick*. However, the IEEE 754 standard gives significant implementation-specific flexibility in the definition of the matrix multiplication operation and the precision and compatibility of these new accelerators is not well documented. This paper describes a method exploiting the rounding modes and other features of the IEEE 754 standard in order to gain deeper insight into the design and functionality of matrix multiplication units. We apply this method to the NVIDIA V100 GPU Tensor Core* units and report our findings on the design properties and micro-architecture.

keywords:
AI applications; ARITH-26; Deep learning; Google TPU; Graphics processing units; Hardware; hardware designs; IEEE 754 standard; IEEE standards; implementation-specific flexibility; Intel Neural Compute Stick; learning (artificial intelligence); Machine learning, deep learning, tensor, half precision, single precision, Volta, matrix multiplication; mathematics computing; matrix multiplication; matrix multiplication functional units; matrix multiplication units; Microarchitecture; neural nets; NVIDIA Tensor Core; NVIDIA V100 GPU Tensor Core units; Standards; Testing

rawabstract:
The rapid growth of AI has led to the introduction of several new hardware designs to accelerate the matrix multiplication operation at the heart of AI applications. Examples include NVIDIA's Tensor Core*, Google's TPU*, and Intel's Neural Compute Stick*. However, the IEEE 754 standard gives significant implementation-specific flexibility in the definition of the matrix multiplication operation and the precision and compatibility of these new accelerators is not well documented. This paper describes a method exploiting the rounding modes and other features of the IEEE 754 standard in order to gain deeper insight into the design and functionality of matrix multiplication units. We apply this method to the NVIDIA V100 GPU Tensor Core* units and report our findings on the design properties and micro-architecture.

entry:
@InProceedings{Hickmann:2019:EAM,
  author =       "Brian Hickmann and Dennis Bradford",
  title =        "Experimental Analysis of Matrix Multiplication
                 Functional Units",
  crossref =     "Takagi:2019:ISC",
  pages =        "116--119",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00031",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The rapid growth of AI has led to the introduction of
                 several new hardware designs to accelerate the matrix
                 multiplication operation at the heart of AI
                 applications. Examples include NVIDIA's Tensor Core*,
                 Google's TPU*, and Intel's Neural Compute Stick*.
                 However, the IEEE 754 standard gives significant
                 implementation-specific flexibility in the definition
                 of the matrix multiplication operation and the
                 precision and compatibility of these new accelerators
                 is not well documented. This paper describes a method
                 exploiting the rounding modes and other features of the
                 IEEE 754 standard in order to gain deeper insight into
                 the design and functionality of matrix multiplication
                 units. We apply this method to the NVIDIA V100 GPU
                 Tensor Core* units and report our findings on the
                 design properties and micro-architecture.",
  acknowledgement = ack-nhfb,
  keywords =     "AI applications; ARITH-26; Deep learning; Google TPU;
                 Graphics processing units; Hardware; hardware designs;
                 IEEE 754 standard; IEEE standards;
                 implementation-specific flexibility; Intel Neural
                 Compute Stick; learning (artificial intelligence);
                 Machine learning, deep learning, tensor, half
                 precision, single precision, Volta, matrix
                 multiplication; mathematics computing; matrix
                 multiplication; matrix multiplication functional units;
                 matrix multiplication units; Microarchitecture; neural
                 nets; NVIDIA Tensor Core; NVIDIA V100 GPU Tensor Core
                 units; Standards; Testing",
}


bibtype: article
filename: fparith.bib
label: Higham:2019:NAP
author: Nicholas J. Higham and Theo Mary
title: A New Approach to Probabilistic Rounding Error Analysis
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 5
pages: A2815--A2835
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/18M1226312
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Tue Nov 5 05:24:19 MST 2019
bibtimestamp: 2019.11.05 05:24:19 MST
fjournal: SIAM Journal on Scientific Computing
keywords: floating-point arithmetic; MATLAB; numerical linear algebra; rounding error analysis
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawauthor: Nicholas J. Higham and Theo Mary
rawtitle: A New Approach to Probabilistic Rounding Error Analysis
bibsource:
http://epubs.siam.org/toc/sjoce3/41/5; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{Higham:2019:NAP,
  author =       "Nicholas J. Higham and Theo Mary",
  title =        "A New Approach to Probabilistic Rounding Error
                 Analysis",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "5",
  pages =        "A2815--A2835",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/18M1226312",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Tue Nov 5 05:24:19 MST 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/5;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "floating-point arithmetic; MATLAB; numerical linear
                 algebra; rounding error analysis",
  onlinedate =   "January 2019",
}


bibtype: article
filename: fparith.bib
label: Higham:2019:SLP
author: Nicholas J. Higham and Srikara Pranesh
title: Simulating Low Precision Floating-Point Arithmetic
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 5
pages: C585--C602
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/19M1251308
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Tue Nov 5 05:24:19 MST 2019
bibtimestamp: 2019.11.05 05:24:19 MST
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawauthor: Nicholas J. Higham and Srikara Pranesh
rawtitle: Simulating Low Precision Floating-Point Arithmetic
bibsource:
http://epubs.siam.org/toc/sjoce3/41/5; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

keywords:
bfloat16; bit flips; directed rounding; floating-point arithmetic; fp16; half precision; IEEE arithmetic; low precision; MATLAB; mixed precision; round to nearest; rounding error analysis; simulation; stochastic rounding; subnormal numbers

entry:
@Article{Higham:2019:SLP,
  author =       "Nicholas J. Higham and Srikara Pranesh",
  title =        "Simulating Low Precision Floating-Point Arithmetic",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "5",
  pages =        "C585--C602",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/19M1251308",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Tue Nov 5 05:24:19 MST 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/5;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "bfloat16; bit flips; directed rounding; floating-point
                 arithmetic; fp16; half precision; IEEE arithmetic; low
                 precision; MATLAB; mixed precision; round to nearest;
                 rounding error analysis; simulation; stochastic
                 rounding; subnormal numbers",
  onlinedate =   "January 2019",
}


bibtype: article
filename: fparith.bib
label: Higham:2019:SMH
author: Nicholas J. Higham and Srikara Pranesh and Mawussi Zounon
title: Squeezing a Matrix into Half Precision, with an Application to Solving Linear Systems
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 4
pages: A2536--A2551
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/18M1229511
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Thu Oct 10 06:58:08 MDT 2019
bibtimestamp: 2019.10.10 06:58:08 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawauthor: Nicholas J. Higham and Srikara Pranesh and Mawussi Zounon
rawtitle: Squeezing a Matrix into Half Precision, with an Application to Solving Linear Systems
bibsource:
http://epubs.siam.org/toc/sjoce3/41/4; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

keywords:
diagonal scaling; fp16; GMRES; half precision arithmetic; iterative refinement; linear system; MATLAB; mixed precision; overflow; preconditioning; subnormal numbers; underflow

entry:
@Article{Higham:2019:SMH,
  author =       "Nicholas J. Higham and Srikara Pranesh and Mawussi
                 Zounon",
  title =        "Squeezing a Matrix into Half Precision, with an
                 Application to Solving Linear Systems",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "4",
  pages =        "A2536--A2551",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/18M1229511",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Thu Oct 10 06:58:08 MDT 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/4;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "diagonal scaling; fp16; GMRES; half precision
                 arithmetic; iterative refinement; linear system;
                 MATLAB; mixed precision; overflow; preconditioning;
                 subnormal numbers; underflow",
  onlinedate =   "January 2019",
}


bibtype: article
filename: fparith.bib
label: Hoang:2019:LPF
author: Trong-Thuc Hoang and Xuan-Thuan Nguyen and Duc-Hung Le and Cong-Kha Pham
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 66
number: 10
pages: 1723--1727
year: 2019
DOI: https://doi.org/10.1109/TCSII.2019.2928138
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Trong-Thuc Hoang and Xuan-Thuan Nguyen and Duc-Hung Le and Cong-Kha Pham
title:
Low-Power Floating-Point Adaptive-CORDIC-based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias

keywords:
Back-gate bias; Circuits and systems; CORDIC; Delays; Energy consumption; floating-point; Frequency measurement; low-power; Memory management; SOTB; Table lookup; twiddle factor

rawtitle:
Low-Power Floating-Point Adaptive-{CORDIC}-based {FFT} Twiddle Factor on 65-nm {Silicon-on-Thin-BOX} ({SOTB}) With Back-Gate Bias

entry:
@Article{Hoang:2019:LPF,
  author =       "Trong-Thuc Hoang and Xuan-Thuan Nguyen and Duc-Hung Le
                 and Cong-Kha Pham",
  title =        "Low-Power Floating-Point Adaptive-{CORDIC}-based {FFT}
                 Twiddle Factor on 65-nm {Silicon-on-Thin-BOX} ({SOTB})
                 With Back-Gate Bias",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "66",
  number =       "10",
  pages =        "1723--1727",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/TCSII.2019.2928138",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "Back-gate bias; Circuits and systems; CORDIC; Delays;
                 Energy consumption; floating-point; Frequency
                 measurement; low-power; Memory management; SOTB; Table
                 lookup; twiddle factor",
}


bibtype: article
filename: fparith.bib
label: Horyachyy:2019:SEF
author: Oleh Horyachyy and Leonid Moroz and Viktor Otenko
title: Simple Effective Fast Inverse Square Root Algorithm with Two Magic Constants
journal: International Journal of Computing
volume: 18
number: 4
pages: 461--470
month: dec
monthnumber: 12
year: 2019
ISSN: 1727-6209 (print), 2312-5381 (electronic) OR 17276209 (print), 23125381 (electronic)
ISSNL: 1727-6209 OR 17276209
bibdate: Thu Feb 11 11:01:47 2021
bibtimestamp: 2021.02.11 11:01:47 ???
acknowledgement: ack-nhfb
rawauthor: Oleh Horyachyy and Leonid Moroz and Viktor Otenko
rawtitle: Simple Effective Fast Inverse Square Root Algorithm with Two Magic Constants
URL:
https://www.computingonline.net/computing/article/view/1616; https://www.researchgate.net/publication/349173096_SIMPLE_EFFECTIVE_FAST_INVERSE_SQUARE_ROOT_ALGORITHM_WITH_TWO_MAGIC_CONSTANTS

keywords:
FISR algorithm; floating-point arithmetic; FMA function; Householder.; IEEE 754 standard; initial approximation; inverse square root; magic constant; maximum relative error; Newton-Raphson

entry:
@Article{Horyachyy:2019:SEF,
  author =       "Oleh Horyachyy and Leonid Moroz and Viktor Otenko",
  title =        "Simple Effective Fast Inverse Square Root Algorithm
                 with Two Magic Constants",
  journal =      "International Journal of Computing",
  volume =       "18",
  number =       "4",
  pages =        "461--470",
  month =        dec,
  year =         "2019",
  ISSN =         "1727-6209 (print), 2312-5381 (electronic)",
  ISSN-L =       "1727-6209",
  bibdate =      "Thu Feb 11 11:01:47 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.computingonline.net/computing/article/view/1616;
                 https://www.researchgate.net/publication/349173096_SIMPLE_EFFECTIVE_FAST_INVERSE_SQUARE_ROOT_ALGORITHM_WITH_TWO_MAGIC_CONSTANTS",
  acknowledgement = ack-nhfb,
  keywords =     "FISR algorithm; floating-point arithmetic; FMA
                 function; Householder.; IEEE 754 standard; initial
                 approximation; inverse square root; magic constant;
                 maximum relative error; Newton-Raphson",
}


bibtype: inproceedings
filename: fparith.bib
label: Hou:2019:LLF
author: Nanxin Hou and Mingjiang Wang and Xiafeng Zou and Ming Liu
booktitle: 2019 IEEE 4th International Conference on Signal and Image Processing (ICSIP)
title: A Low Latency Floating Point CORDIC Algorithm for Sin / Cosine Function
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 751--755
year: 2019
DOI: https://doi.org/10.1109/SIPROCESS.2019.8868623
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Nanxin Hou and Mingjiang Wang and Xiafeng Zou and Ming Liu
rawbooktitle: {2019 IEEE 4th International Conference on Signal and Image Processing (ICSIP)}
rawtitle: A Low Latency Floating Point {CORDIC} Algorithm for Sin\slash Cosine Function
keywords:
Circuits and systems; Conferences; CORDIC; Digital arithmetic; Digital signal processing; double-precision; floating-point; IEEE transactions; Image processing; low latency; Manganese; sin/cosine

entry:
@InProceedings{Hou:2019:LLF,
  author =       "Nanxin Hou and Mingjiang Wang and Xiafeng Zou and Ming
                 Liu",
  booktitle =    "{2019 IEEE 4th International Conference on Signal and
                 Image Processing (ICSIP)}",
  title =        "A Low Latency Floating Point {CORDIC} Algorithm for
                 Sin\slash Cosine Function",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "751--755",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SIPROCESS.2019.8868623",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Circuits and systems; Conferences; CORDIC; Digital
                 arithmetic; Digital signal processing;
                 double-precision; floating-point; IEEE transactions;
                 Image processing; low latency; Manganese; sin/cosine",
}


bibtype: article
filename: fparith.bib
label: Hough:2019:ISO
author: David G. Hough
title: The IEEE Standard 754: One for the History Books
journal: j-COMPUTER
volume: 52
number: 12
pages: 109--112
month: dec
monthnumber: 12
year: 2019
CODEN: CPTRB4
DOI: https://doi.org/10.1109/MC.2019.2926614
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Fri Nov 29 06:16:06 2019
bibtimestamp: 2019.11.29 06:16:06 ???
fjournal: Computer
keywords: Floating-point arithmetic; Hardware; History; IEEE Standards; Microprocessors; Software
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: David G. Hough
rawtitle: The {IEEE Standard 754}: One for the History Books
bibsource:
https://www.math.utah.edu/pub/tex/bib/computer2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/ieee-computer.pdf; https://www.computer.org/csdl/magazine/co/2019/12/08909942/1f8KFWxbTCU

entry:
@Article{Hough:2019:ISO,
  author =       "David G. Hough",
  title =        "The {IEEE Standard 754}: One for the History Books",
  journal =      j-COMPUTER,
  volume =       "52",
  number =       "12",
  pages =        "109--112",
  month =        dec,
  year =         "2019",
  CODEN =        "CPTRB4",
  DOI =          "https://doi.org/10.1109/MC.2019.2926614",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Fri Nov 29 06:16:06 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computer2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/ieee-computer.pdf;
                 https://www.computer.org/csdl/magazine/co/2019/12/08909942/1f8KFWxbTCU",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Floating-point arithmetic; Hardware; History; IEEE
                 Standards; Microprocessors; Software",
}


bibtype: article
filename: fparith.bib
label: Hrycak:2019:AEC
author: Tomasz Hrycak and Sebastian Schmutzhard
title: Accurate evaluation of Chebyshev polynomials in floating-point arithmetic
journal: j-BIT-NUM-MATH
volume: 59
number: 2
pages: 403--416
month: jun
monthnumber: 6
year: 2019
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-018-0738-5
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Fri Sep 6 09:16:11 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.06 09:16:11 MDT
URL: http://link.springer.com/article/10.1007/s10543-018-0738-5
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Tomasz Hrycak and Sebastian Schmutzhard
rawtitle: Accurate evaluation of {Chebyshev} polynomials in floating-point arithmetic
entry:
@Article{Hrycak:2019:AEC,
  author =       "Tomasz Hrycak and Sebastian Schmutzhard",
  title =        "Accurate evaluation of {Chebyshev} polynomials in
                 floating-point arithmetic",
  journal =      j-BIT-NUM-MATH,
  volume =       "59",
  number =       "2",
  pages =        "403--416",
  month =        jun,
  year =         "2019",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-018-0738-5",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Fri Sep 6 09:16:11 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.com/article/10.1007/s10543-018-0738-5",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: book
filename: fparith.bib
label: IEEE-754:2019:ISF
author: IEEE-754
title: IEEE 754-2019, Standard for Floating-Point Arithmetic
publisher: pub-IEEE-STD
address: pub-IEEE-STD:adr
pages: 82
day: 13
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/IEEESTD.2019.876622
ISBN: 1-5044-5925-3 (print), 1-5044-5924-5 (e-PDF) OR 1504459253 (print), 1504459245 (ePDF)
ISBN13: 978-1-5044-5925-9 (print), 978-1-5044-5924-2 (e-PDF) OR 9781504459259 (print), 9781504459242 (ePDF)
bibdate: Tue Nov 05 08:49:56 2019
bibtimestamp: 2019.11.05 08:49:56 ???
acknowledgement: ack-nhfb
rawauthor: {IEEE-754}
rawtitle: {IEEE 754-2019, Standard for Floating-Point Arithmetic}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeestd.bib

abstract:
This standard specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming environments. This standard specifies exception conditions and their default handling. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware. For operations specified in the normative part of this standard, numerical results and exceptions are uniquely determined by the values of the input data, sequence of operations, and destination formats, all under user control.

entry:
@Book{IEEE-754:2019:ISF,
  author =       "{IEEE-754}",
  title =        "{IEEE 754-2019, Standard for Floating-Point
                 Arithmetic}",
  publisher =    pub-IEEE-STD,
  address =      pub-IEEE-STD:adr,
  pages =        "82",
  day =          "13",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/IEEESTD.2019.876622",
  ISBN =         "1-5044-5925-3 (print), 1-5044-5924-5 (e-PDF)",
  ISBN-13 =      "978-1-5044-5925-9 (print), 978-1-5044-5924-2 (e-PDF)",
  bibdate =      "Tue Nov 05 08:49:56 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeestd.bib",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: IEEE:2019:PDA
author: IEEE
pages: 82
month: apr
monthnumber: 4
year: 2019
bibdate: Thu Jun 20 15:39:16 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.06.20 15:39:16 ???
URL: https://ieeexplore.ieee.org/document/8739150
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: {IEEE}
title:
P754 / D2.50, Apr 2019 --- IEEE Approved Draft Standard for Floating-Point Arithmetic: Revision of IEEE Std 754-2008

rawtitle:
{P754\slash D2.50, Apr 2019 --- IEEE Approved Draft Standard for Floating-Point Arithmetic: Revision of IEEE Std 754-2008}

entry:
@Misc{IEEE:2019:PDA,
  author =       "{IEEE}",
  title =        "{P754\slash D2.50, Apr 2019 --- IEEE Approved Draft
                 Standard for Floating-Point Arithmetic: Revision of
                 IEEE Std 754-2008}",
  howpublished = "Web site",
  month =        apr,
  year =         "2019",
  bibdate =      "Thu Jun 20 15:39:16 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/8739150",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Issa:2019:FIF
author: Hanady Hussein Issa and Saleh Mohamed Eisa Ahmed
title: FPGA Implementation of Floating Point Based Cuckoo Search Algorithm
journal: j-IEEE-ACCESS
volume: 7
pages: 134434--134447
year: 2019
DOI: https://doi.org/10.1109/ACCESS.2019.2942205
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Hanady Hussein Issa and Saleh Mohamed Eisa Ahmed
rawtitle: {FPGA} Implementation of Floating Point Based Cuckoo Search Algorithm
keywords:
Birds; Cuckoo search algorithm (CSA); field programmable gate array (FPGA); Field programmable gate arrays; finite state machine (FSM); Hardware; IEEE floating point format; Optimization; Search problems; Signal processing algorithms; Wireless sensor networks

entry:
@Article{Issa:2019:FIF,
  author =       "Hanady Hussein Issa and Saleh Mohamed Eisa Ahmed",
  title =        "{FPGA} Implementation of Floating Point Based Cuckoo
                 Search Algorithm",
  journal =      j-IEEE-ACCESS,
  volume =       "7",
  pages =        "134434--134447",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ACCESS.2019.2942205",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Birds; Cuckoo search algorithm (CSA); field
                 programmable gate array (FPGA); Field programmable gate
                 arrays; finite state machine (FSM); Hardware; IEEE
                 floating point format; Optimization; Search problems;
                 Signal processing algorithms; Wireless sensor
                 networks",
}


bibtype: inproceedings
filename: fparith.bib
label: Jaberipur:2019:MPP
author: Ghassem Jaberipur and Sahar Moradi Cherati
title: Modulo-$ (2 n + 3) $ Parallel Prefix Addition via Diminished-3 Representation of Residues
crossref: Takagi:2019:ISC
pages: 135--142
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00035
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Ghassem Jaberipur and Sahar {Moradi Cherati}
rawtitle: Modulo-$ (2 n + 3) $ Parallel Prefix Addition via Diminished-3 Representation of Residues
abstract:
Diminished-1 (D1) representation of modulo-(2n + 1) residues in [1, 2n] uses the n-bit codes [0, 2n - 1] and maintains a zero-indicator bit. Such D1 encoding has led to efficient parallel prefix modulo-(2n + 1) adders that perform as fast as the companion modulo-(2n - 1) and -2n adders with (3 + 2 log n) delay, where denotes the delay of a simple 2-input gate. Also similar, but slower (i.e., with one more delay) and slightly more complex, parallel prefix architectures have been offered for modulo-(2n - 3) adders. On the other hand, reverse conversion schemes for 4and 5-moduli sets that include conjugate moduli pairs 2n pm 1 and 2n pm 3 are already available, while we have not encountered any efficient modulo(2n + 3) adder. Therefore, in this paper, we offer the diminished-3 (D3) representation of modulo-(2n + 3) residues that maps the residue interval [3, 2n + 2] to [0, 2n - 1] and maintains a 2-bit 0,1, 2-indicator. The corresponding parallel prefix adder, which performs as fast as the fastest previous modulo-(2n - 3) adder is designed, where a 3-way compound architecture is devised as the bulk of modular addition that yields sum, sum+1, and sum+2. The proposed architecture is fully synthesized via Synopsis Design Compiler and tested for correctness, and its figures of merit compared with modulo(2n - 3) and -(2n + 1) adders.

keywords:
3-way compound architecture; adders; Adders; ARITH-26; complex prefix architectures; Compounds; Computer architecture; Computer science; D1 representation; D3 representation; Delays; Digital arithmetic; Diminished-1 representation; diminished-3 representation; Encoding; logic design; Modulo-(2n+3) parallel prefix addition; modulo-(2n-3) adders; parallel prefix adder; Residue Number System, Parallel Prefix Adder, Diminished-1, Diminished 3, 3-way compound adder; residue number systems; simple 2-input gate; Synopsis Design Compiler; zero-indicator bit

rawabstract:
Diminished-1 (D1) representation of modulo-(2n + 1) residues in [1, 2n] uses the n-bit codes [0, 2n - 1] and maintains a zero-indicator bit. Such D1 encoding has led to efficient parallel prefix modulo-(2n + 1) adders that perform as fast as the companion modulo-(2n - 1) and -2n adders with (3 + 2 log n) delay, where denotes the delay of a simple 2-input gate. Also similar, but slower (i.e., with one more delay) and slightly more complex, parallel prefix architectures have been offered for modulo-(2n - 3) adders. On the other hand, reverse conversion schemes for 4and 5-moduli sets that include conjugate moduli pairs 2n \pm 1 and 2n \pm 3 are already available, while we have not encountered any efficient modulo(2n + 3) adder. Therefore, in this paper, we offer the diminished-3 (D3) representation of modulo-(2n + 3) residues that maps the residue interval [3, 2n + 2] to [0, 2n - 1] and maintains a 2-bit {0,1, 2}-indicator. The corresponding parallel prefix adder, which performs as fast as the fastest previous modulo-(2n - 3) adder is designed, where a 3-way compound architecture is devised as the bulk of modular addition that yields sum, sum+1, and sum+2. The proposed architecture is fully synthesized via Synopsis Design Compiler and tested for correctness, and its figures of merit compared with modulo(2n - 3) and -(2n + 1) adders.

entry:
@InProceedings{Jaberipur:2019:MPP,
  author =       "Ghassem Jaberipur and Sahar {Moradi Cherati}",
  title =        "Modulo-$ (2 n + 3) $ Parallel Prefix Addition via
                 Diminished-3 Representation of Residues",
  crossref =     "Takagi:2019:ISC",
  pages =        "135--142",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00035",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Diminished-1 (D1) representation of modulo-(2n + 1)
                 residues in [1, 2n] uses the n-bit codes [0, 2n - 1]
                 and maintains a zero-indicator bit. Such D1 encoding
                 has led to efficient parallel prefix modulo-(2n + 1)
                 adders that perform as fast as the companion modulo-(2n
                 - 1) and -2n adders with (3 + 2 log n) delay, where
                 denotes the delay of a simple 2-input gate. Also
                 similar, but slower (i.e., with one more delay) and
                 slightly more complex, parallel prefix architectures
                 have been offered for modulo-(2n - 3) adders. On the
                 other hand, reverse conversion schemes for 4and
                 5-moduli sets that include conjugate moduli pairs 2n
                 \pm 1 and 2n \pm 3 are already available, while we have
                 not encountered any efficient modulo(2n + 3) adder.
                 Therefore, in this paper, we offer the diminished-3
                 (D3) representation of modulo-(2n + 3) residues that
                 maps the residue interval [3, 2n + 2] to [0, 2n - 1]
                 and maintains a 2-bit {0,1, 2}-indicator. The
                 corresponding parallel prefix adder, which performs as
                 fast as the fastest previous modulo-(2n - 3) adder is
                 designed, where a 3-way compound architecture is
                 devised as the bulk of modular addition that yields
                 sum, sum+1, and sum+2. The proposed architecture is
                 fully synthesized via Synopsis Design Compiler and
                 tested for correctness, and its figures of merit
                 compared with modulo(2n - 3) and -(2n + 1) adders.",
  acknowledgement = ack-nhfb,
  keywords =     "3-way compound architecture; adders; Adders; ARITH-26;
                 complex prefix architectures; Compounds; Computer
                 architecture; Computer science; D1 representation; D3
                 representation; Delays; Digital arithmetic;
                 Diminished-1 representation; diminished-3
                 representation; Encoding; logic design; Modulo-(2n+3)
                 parallel prefix addition; modulo-(2n-3) adders;
                 parallel prefix adder; Residue Number System, Parallel
                 Prefix Adder, Diminished-1, Diminished 3, 3-way
                 compound adder; residue number systems; simple 2-input
                 gate; Synopsis Design Compiler; zero-indicator bit",
}


bibtype: article
filename: fparith.bib
label: Jaiswal:2019:PHP
author: Manish Kumar Jaiswal and Hayden K.-H. So
title: PACoGen: a Hardware Posit Arithmetic Core Generator
journal: j-IEEE-ACCESS
volume: 7
pages: 74586--74601
year: 2019
DOI: https://doi.org/10.1109/access.2019.2920936
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Thu Dec 14 18:07:06 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 18:07:06 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Manish Kumar Jaiswal and Hayden K.-H. So
rawtitle: {PACoGen}: a Hardware Posit Arithmetic Core Generator
keywords:
Adder; Adders; ASIC; digital arithmetic; division; Dynamic range; Field programmable gate arrays; floating point arithmetic; FPGA; Generators; Hardware; Hardware design languages; multiplier; posit arithmetic; Standards; subtractor; universal number system

entry:
@Article{Jaiswal:2019:PHP,
  author =       "Manish Kumar Jaiswal and Hayden K.-H. So",
  title =        "{PACoGen}: a Hardware Posit Arithmetic Core
                 Generator",
  journal =      j-IEEE-ACCESS,
  volume =       "7",
  pages =        "74586--74601",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/access.2019.2920936",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Thu Dec 14 18:07:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Adder; Adders; ASIC; digital arithmetic; division;
                 Dynamic range; Field programmable gate arrays; floating
                 point arithmetic; FPGA; Generators; Hardware; Hardware
                 design languages; multiplier; posit arithmetic;
                 Standards; subtractor; universal number system",
}


bibtype: article
filename: fparith.bib
label: Jia:2019:DNT
author: Zhe Jia and Marco Maggioni and Jeffrey Smith and Daniele Paolo Scarpazza
title: Dissecting the NVidia Turing T4 GPU via Microbenchmarking
journal: arXiv.org
pages: 65
day: 18
month: mar
monthnumber: 3
year: 2019
DOI: https://doi.org/10.48550/ARXIV.1903.07486
bibdate: Mon Sep 11 07:00:16 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:00:16 ???
URL: https://arxiv.org/abs/1903.07486
acknowledgement: ack-nhfb
rawauthor: Zhe Jia and Marco Maggioni and Jeffrey Smith and Daniele Paolo Scarpazza
rawtitle: Dissecting the {NVidia Turing T4 GPU} via Microbenchmarking
abstract:
In 2019, the rapid rate at which GPU manufacturers refresh their designs, coupled with their reluctance to disclose microarchitectural details, is still a hurdle for those software designers who want to extract the highest possible performance. Last year, these very reasons motivated us to dissect the Volta GPU architecture using microbenchmarks.par The introduction in August 2018 of Turing, NVidia's latest architecture, pressed us to update our study. In this report, we examine Turing and compare it quantitatively against previous NVidia GPU generations. Specifically, we study the T4 GPU: a low-power board aiming at inference applications. We describe its improvements against its inference-oriented predecessor: the P4 GPU based on the Pascal architecture. Both T4 and P4 GPUs achieve significantly higher frequency-per-Watt figures than their full-size counterparts.par We study the performance of the T4's TensorCores, finding a much higher throughput on low-precision operands than on the P4 GPU. We reveal that Turing introduces new instructions that express matrix math more succinctly. We map Turing's instruction space, finding the same encoding as Volta, and additional instructions. We reveal that the Turing TU104 chip has the same memory hierarchy depth as the Volta GV100; cache levels sizes on the TU104 are frequently twice as large as those found on the Pascal GP104. We benchmark each constituent of the T4 memory hierarchy and find substantial overall performance improvements over its P4 predecessor. We studied how clock throttling affects compute-intensive workloads that hit power or thermal limits.par Many of our findings are novel, published here for the first time. All of them can guide high-performance software developers get closer to the GPU's peak performance.

rawabstract:
In 2019, the rapid rate at which GPU manufacturers refresh their designs, coupled with their reluctance to disclose microarchitectural details, is still a hurdle for those software designers who want to extract the highest possible performance. Last year, these very reasons motivated us to dissect the Volta GPU architecture using microbenchmarks.\par The introduction in August 2018 of Turing, NVidia's latest architecture, pressed us to update our study. In this report, we examine Turing and compare it quantitatively against previous NVidia GPU generations. Specifically, we study the T4 GPU: a low-power board aiming at inference applications. We describe its improvements against its inference-oriented predecessor: the P4 GPU based on the Pascal architecture. Both T4 and P4 GPUs achieve significantly higher frequency-per-Watt figures than their full-size counterparts.\par We study the performance of the T4's TensorCores, finding a much higher throughput on low-precision operands than on the P4 GPU. We reveal that Turing introduces new instructions that express matrix math more succinctly. We map Turing's instruction space, finding the same encoding as Volta, and additional instructions. We reveal that the Turing TU104 chip has the same memory hierarchy depth as the Volta GV100; cache levels sizes on the TU104 are frequently twice as large as those found on the Pascal GP104. We benchmark each constituent of the T4 memory hierarchy and find substantial overall performance improvements over its P4 predecessor. We studied how clock throttling affects compute-intensive workloads that hit power or thermal limits.\par Many of our findings are novel, published here for the first time. All of them can guide high-performance software developers get closer to the GPU's peak performance.

entry:
@Article{Jia:2019:DNT,
  author =       "Zhe Jia and Marco Maggioni and Jeffrey Smith and
                 Daniele Paolo Scarpazza",
  title =        "Dissecting the {NVidia Turing T4 GPU} via
                 Microbenchmarking",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "65",
  day =          "18",
  month =        mar,
  year =         "2019",
  DOI =          "https://doi.org/10.48550/ARXIV.1903.07486",
  bibdate =      "Mon Sep 11 07:00:16 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1903.07486",
  abstract =     "In 2019, the rapid rate at which GPU manufacturers
                 refresh their designs, coupled with their reluctance to
                 disclose microarchitectural details, is still a hurdle
                 for those software designers who want to extract the
                 highest possible performance. Last year, these very
                 reasons motivated us to dissect the Volta GPU
                 architecture using microbenchmarks.\par

                 The introduction in August 2018 of Turing, NVidia's
                 latest architecture, pressed us to update our study. In
                 this report, we examine Turing and compare it
                 quantitatively against previous NVidia GPU generations.
                 Specifically, we study the T4 GPU: a low-power board
                 aiming at inference applications. We describe its
                 improvements against its inference-oriented
                 predecessor: the P4 GPU based on the Pascal
                 architecture. Both T4 and P4 GPUs achieve significantly
                 higher frequency-per-Watt figures than their full-size
                 counterparts.\par

                 We study the performance of the T4's TensorCores,
                 finding a much higher throughput on low-precision
                 operands than on the P4 GPU. We reveal that Turing
                 introduces new instructions that express matrix math
                 more succinctly. We map Turing's instruction space,
                 finding the same encoding as Volta, and additional
                 instructions. We reveal that the Turing TU104 chip has
                 the same memory hierarchy depth as the Volta GV100;
                 cache levels sizes on the TU104 are frequently twice as
                 large as those found on the Pascal GP104. We benchmark
                 each constituent of the T4 memory hierarchy and find
                 substantial overall performance improvements over its
                 P4 predecessor. We studied how clock throttling affects
                 compute-intensive workloads that hit power or thermal
                 limits.\par

                 Many of our findings are novel, published here for the
                 first time. All of them can guide high-performance
                 software developers get closer to the GPU's peak
                 performance.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Jiang:2019:LPU
author: H. Jiang and L. Liu and F. Lombardi and J. Han
title: Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1635--1646
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2916817
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Jiang and L. Liu and F. Lombardi and J. Han
rawtitle: Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation
keywords:
Adaptive approximation; Circuit synthesis; Delays; divider; Error correction; Hardware; image processing; Image reconstruction; low-power; overflow; Power dissipation; SQR circuit

entry:
@Article{Jiang:2019:LPU,
  author =       "H. Jiang and L. Liu and F. Lombardi and J. Han",
  title =        "Low-Power Unsigned Divider and Square Root Circuit
                 Designs Using Adaptive Approximation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1635--1646",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2916817",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adaptive approximation; Circuit synthesis; Delays;
                 divider; Error correction; Hardware; image processing;
                 Image reconstruction; low-power; overflow; Power
                 dissipation; SQR circuit",
}


bibtype: inproceedings
filename: fparith.bib
label: Johansson:2019:FAP
author: Fredrik Johansson
title: Faster Arbitrary-Precision Dot Product and Matrix Multiplication
crossref: Takagi:2019:ISC
pages: 15--22
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00012
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Fredrik Johansson
rawtitle: Faster Arbitrary-Precision Dot Product and Matrix Multiplication
abstract:
We present algorithms for real and complex dot product and matrix multiplication in arbitrary-precision floating-point and ball arithmetic. A low-overhead dot product is implemented on the level of GMP limb arrays; it is about twice as fast as previous code in MPFR and Arb at precision up to several hundred bits. Up to 128 bits, it is 3-4 times as fast, costing 20-30 cycles per term for floating-point evaluation and 40-50 cycles per term for balls. We handle large matrix multiplications even more efficiently via blocks of scaled integer matrices. The new methods are implemented in Arb and significantly speed up polynomial operations and linear algebra.

keywords:
arbitrary-precision arithmetic, ball arithmetic, dot product, matrix multiplication; arbitrary-precision dot product; arbitrary-precision floating-point; ARITH-26; ball arithmetic; complex dot product; Costing; Digital arithmetic; floating point arithmetic; floating-point evaluation; GMP limb arrays; Indexes; Libraries; Linear algebra; linear algebra; low-overhead dot product; mathematics computing; matrix multiplication; polynomial operations; polynomials; real dot product; scaled integer matrices; Software; Upper bound; word length 128.0 bit

rawabstract:
We present algorithms for real and complex dot product and matrix multiplication in arbitrary-precision floating-point and ball arithmetic. A low-overhead dot product is implemented on the level of GMP limb arrays; it is about twice as fast as previous code in MPFR and Arb at precision up to several hundred bits. Up to 128 bits, it is 3-4 times as fast, costing 20-30 cycles per term for floating-point evaluation and 40-50 cycles per term for balls. We handle large matrix multiplications even more efficiently via blocks of scaled integer matrices. The new methods are implemented in Arb and significantly speed up polynomial operations and linear algebra.

entry:
@InProceedings{Johansson:2019:FAP,
  author =       "Fredrik Johansson",
  title =        "Faster Arbitrary-Precision Dot Product and Matrix
                 Multiplication",
  crossref =     "Takagi:2019:ISC",
  pages =        "15--22",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00012",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present algorithms for real and complex dot product
                 and matrix multiplication in arbitrary-precision
                 floating-point and ball arithmetic. A low-overhead dot
                 product is implemented on the level of GMP limb arrays;
                 it is about twice as fast as previous code in MPFR and
                 Arb at precision up to several hundred bits. Up to 128
                 bits, it is 3-4 times as fast, costing 20-30 cycles per
                 term for floating-point evaluation and 40-50 cycles per
                 term for balls. We handle large matrix multiplications
                 even more efficiently via blocks of scaled integer
                 matrices. The new methods are implemented in Arb and
                 significantly speed up polynomial operations and linear
                 algebra.",
  acknowledgement = ack-nhfb,
  keywords =     "arbitrary-precision arithmetic, ball arithmetic, dot
                 product, matrix multiplication; arbitrary-precision dot
                 product; arbitrary-precision floating-point; ARITH-26;
                 ball arithmetic; complex dot product; Costing; Digital
                 arithmetic; floating point arithmetic; floating-point
                 evaluation; GMP limb arrays; Indexes; Libraries; Linear
                 algebra; linear algebra; low-overhead dot product;
                 mathematics computing; matrix multiplication;
                 polynomial operations; polynomials; real dot product;
                 scaled integer matrices; Software; Upper bound; word
                 length 128.0 bit",
}


bibtype: inproceedings
filename: fparith.bib
label: Jugade:2019:MEE
author: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
editor: IEEE
booktitle: 2019 Sixth Indian Control Conference (ICC)
title: A Memory-Efficient Explicit Model Predictive Control using Posits
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 188--193
year: 2019
DOI: https://doi.org/10.1109/ICC47138.2019.9123179
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
rawbooktitle: {2019 Sixth Indian Control Conference (ICC)}
raweditor: {IEEE}
rawtitle: A Memory-Efficient Explicit Model Predictive Control using Posits
entry:
@InProceedings{Jugade:2019:MEE,
  author =       "Chaitanya Jugade and Deepak Ingole and Dayaram
                 Sonawane and Michal Kvasnica and John Gustafson",
  editor =       "{IEEE}",
  booktitle =    "{2019 Sixth Indian Control Conference (ICC)}",
  title =        "A Memory-Efficient Explicit Model Predictive Control
                 using Posits",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "188--193",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICC47138.2019.9123179",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kalamkar:2019:SBD
title: A Study of BFLOAT16 for Deep Learning Training
journal: arXiv.org
pages: 1--10
day: 29
month: may
monthnumber: 5
year: 2019
bibdate: Fri Aug 30 17:25:53 2019
bibsource: DBLP archive; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.30 17:25:53 ???
URL: http://arxiv.org/abs/1905.12322
acknowledgement: ack-nhfb
rawtitle: A Study of {BFLOAT16} for Deep Learning Training
author:
Dhiraj D. Kalamkar and Dheevatsa Mudigere and Naveen Mellempudi and Dipankar Das and Kunal Banerjee and Sasikanth Avancha and Dharma Teja Vooturi and Nataraj Jammalamadaka and Jianyu Huang and Hector Yuen and Jiyan Yang and Jongsoo Park and Alexander Heinecke and Evangelos Georganas and Sudarshan Srinivasan and Abhisek Kundu and Misha Smelyanskiy and Bharat Kaul and Pradeep Dubey

abstract:
This paper presents the first comprehensive empirical study demonstrating the efficacy of the Brain Floating Point (BFLOAT16) half-precision format for Deep Learning training across image classification, speech recognition, language modeling, generative networks and industrial recommendation systems. BFLOAT16 is attractive for Deep Learning training for two reasons: the range of values it can represent is the same as that of IEEE 754 floating-point format (FP32) and conversion to/from FP32 is simple. Maintaining the same range as FP32 is important to ensure that no hyper-parameter tuning is required for convergence; e.g., IEEE 754 compliant half-precision floating point (FP16) requires hyper-parameter tuning. In this paper, we discuss the flow of tensors and various key operations in mixed precision training, and delve into details of operations, such as the rounding modes for converting FP32 tensors to BFLOAT16. We have implemented a method to emulate BFLOAT16 operations in Tensorflow, Caffe2, IntelCaffe, and Neon for our experiments. Our results show that deep learning training using BFLOAT16 tensors achieves the same state-of-the-art (SOTA) results across domains as FP32 tensors in the same number of iterations and with no changes to hyper-parameters.

rawabstract:
This paper presents the first comprehensive empirical study demonstrating the efficacy of the Brain Floating Point (BFLOAT16) half-precision format for Deep Learning training across image classification, speech recognition, language modeling, generative networks and industrial recommendation systems. BFLOAT16 is attractive for Deep Learning training for two reasons: the range of values it can represent is the same as that of IEEE 754 floating-point format (FP32) and conversion to/from FP32 is simple. Maintaining the same range as FP32 is important to ensure that no hyper-parameter tuning is required for convergence; e.g., IEEE 754 compliant half-precision floating point (FP16) requires hyper-parameter tuning. In this paper, we discuss the flow of tensors and various key operations in mixed precision training, and delve into details of operations, such as the rounding modes for converting FP32 tensors to BFLOAT16. We have implemented a method to emulate BFLOAT16 operations in Tensorflow, Caffe2, IntelCaffe, and Neon for our experiments. Our results show that deep learning training using BFLOAT16 tensors achieves the same state-of-the-art (SOTA) results across domains as FP32 tensors in the same number of iterations and with no changes to hyper-parameters.

rawauthor:
Dhiraj D. Kalamkar and Dheevatsa Mudigere and Naveen Mellempudi and Dipankar Das and Kunal Banerjee and Sasikanth Avancha and Dharma Teja Vooturi and Nataraj Jammalamadaka and Jianyu Huang and Hector Yuen and Jiyan Yang and Jongsoo Park and Alexander Heinecke and Evangelos Georganas and Sudarshan Srinivasan and Abhisek Kundu and Misha Smelyanskiy and Bharat Kaul and Pradeep Dubey

entry:
@Article{Kalamkar:2019:SBD,
  author =       "Dhiraj D. Kalamkar and Dheevatsa Mudigere and Naveen
                 Mellempudi and Dipankar Das and Kunal Banerjee and
                 Sasikanth Avancha and Dharma Teja Vooturi and Nataraj
                 Jammalamadaka and Jianyu Huang and Hector Yuen and
                 Jiyan Yang and Jongsoo Park and Alexander Heinecke and
                 Evangelos Georganas and Sudarshan Srinivasan and
                 Abhisek Kundu and Misha Smelyanskiy and Bharat Kaul and
                 Pradeep Dubey",
  title =        "A Study of {BFLOAT16} for Deep Learning Training",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--10",
  day =          "29",
  month =        may,
  year =         "2019",
  bibdate =      "Fri Aug 30 17:25:53 2019",
  bibsource =    "DBLP archive;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1905.12322",
  abstract =     "This paper presents the first comprehensive empirical
                 study demonstrating the efficacy of the Brain Floating
                 Point (BFLOAT16) half-precision format for Deep
                 Learning training across image classification, speech
                 recognition, language modeling, generative networks and
                 industrial recommendation systems. BFLOAT16 is
                 attractive for Deep Learning training for two reasons:
                 the range of values it can represent is the same as
                 that of IEEE 754 floating-point format (FP32) and
                 conversion to/from FP32 is simple. Maintaining the same
                 range as FP32 is important to ensure that no
                 hyper-parameter tuning is required for convergence;
                 e.g., IEEE 754 compliant half-precision floating point
                 (FP16) requires hyper-parameter tuning. In this paper,
                 we discuss the flow of tensors and various key
                 operations in mixed precision training, and delve into
                 details of operations, such as the rounding modes for
                 converting FP32 tensors to BFLOAT16. We have
                 implemented a method to emulate BFLOAT16 operations in
                 Tensorflow, Caffe2, IntelCaffe, and Neon for our
                 experiments. Our results show that deep learning
                 training using BFLOAT16 tensors achieves the same
                 state-of-the-art (SOTA) results across domains as FP32
                 tensors in the same number of iterations and with no
                 changes to hyper-parameters.",
  acknowledgement = ack-nhfb,
  biburl =       "https://dblp.org/rec/bib/journals/corr/abs-1905-12322",
  eprint =       "1905.12322",
  timestamp =    "Wed Jan 3 07:58:16 2024",
}


bibtype: inproceedings
filename: fparith.bib
label: Katajainen:2019:HMP
author: Jyrki Katajainen
editor: I. Kotsireas and P. Pardalos and K. Parsopoulos and D. Souravlias and A. Tsokas
booktitle: Analysis of Experimental Algorithms. SEA 2019
title: Hacker's Multiple-Precision Integer-Division Program in Close Scrutiny
publisher: pub-SV
address: pub-SV:adr
pages: 376--391
year: 2019
DOI: https://doi.org/10.1007/978-3-030-34029-2_25
bibdate: Thu Jan 28 19:43:12 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.01.28 19:43:12 ???
series: ser-LNCS
URL: http://www.cphstl.dk/Paper/Division/division.pdf
acknowledgement: ack-nhfb
rawauthor: Jyrki Katajainen
rawbooktitle: Analysis of Experimental Algorithms. {SEA 2019}
raweditor: I. Kotsireas and P. Pardalos and K. Parsopoulos and D. Souravlias and A. Tsokas
rawtitle: Hacker's Multiple-Precision Integer-Division Program in Close Scrutiny
ORCID: Katajainen, Jyrki/0000-0002-7714-5588
abstract:
Before the era of ubiquitous computers, the long-division method was presented in primary schools as a paper-and-pencil technique to do whole-number division. In the book booktitle Hacker's Delight by Warren [2nd edition, 2013], an implementation of this algorithm was given using the C programming language. In this paper we will report our experiences when converting this program to a generic program-library routine.par The highlights of the paper are as follows: (1) We describe the long-division algorithm this is done for educational purposes. (2) We outline its implementation the goal is to show how to use modern C++ to achieve flexibility, portability, and efficiency. (3) We analyse its computational complexity by paying attention to how the digit width affects the running time. (4) We compare the practical performance of the library routine against Warren's original. It is pleasure to announce that the library routine is faster. (5) We release the developed routine as part of a software package that provides fixed-width integers of arbitrary length, e.g. a number of type Open image in new window has 2019 bits and it supports the same operations with the same semantics as a number of type tt unsigned int

keywords:
Algorithm; Description; Experimentation; Implementation; Long division; Meticulous analysis; Multiple-precision arithmetic; Software library

rawabstract:
Before the era of ubiquitous computers, the long-division method was presented in primary schools as a paper-and-pencil technique to do whole-number division. In the book \booktitle{Hacker's Delight} by Warren [2nd edition, 2013], an implementation of this algorithm was given using the C programming language. In this paper we will report our experiences when converting this program to a generic program-library routine.\par The highlights of the paper are as follows: (1) We describe the long-division algorithm this is done for educational purposes. (2) We outline its implementation the goal is to show how to use modern C++ to achieve flexibility, portability, and efficiency. (3) We analyse its computational complexity by paying attention to how the digit width affects the running time. (4) We compare the practical performance of the library routine against Warren's original. It is pleasure to announce that the library routine is faster. (5) We release the developed routine as part of a software package that provides fixed-width integers of arbitrary length, e.g. a number of type Open image in new window has 2019 bits and it supports the same operations with the same semantics as a number of type {\tt unsigned int}

entry:
@InProceedings{Katajainen:2019:HMP,
  author =       "Jyrki Katajainen",
  editor =       "I. Kotsireas and P. Pardalos and K. Parsopoulos and D.
                 Souravlias and A. Tsokas",
  booktitle =    "Analysis of Experimental Algorithms. {SEA 2019}",
  title =        "Hacker's Multiple-Precision Integer-Division Program
                 in Close Scrutiny",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "376--391",
  year =         "2019",
  DOI =          "https://doi.org/10.1007/978-3-030-34029-2_25",
  bibdate =      "Thu Jan 28 19:43:12 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  URL =          "http://www.cphstl.dk/Paper/Division/division.pdf",
  abstract =     "Before the era of ubiquitous computers, the
                 long-division method was presented in primary schools
                 as a paper-and-pencil technique to do whole-number
                 division. In the book \booktitle{Hacker's Delight} by
                 Warren [2nd edition, 2013], an implementation of this
                 algorithm was given using the C programming language.
                 In this paper we will report our experiences when
                 converting this program to a generic program-library
                 routine.\par

                 The highlights of the paper are as follows: (1) We
                 describe the long-division algorithm this is done for
                 educational purposes. (2) We outline its implementation
                 the goal is to show how to use modern C++ to achieve
                 flexibility, portability, and efficiency. (3) We
                 analyse its computational complexity by paying
                 attention to how the digit width affects the running
                 time. (4) We compare the practical performance of the
                 library routine against Warren's original. It is
                 pleasure to announce that the library routine is
                 faster. (5) We release the developed routine as part of
                 a software package that provides fixed-width integers
                 of arbitrary length, e.g. a number of type Open image
                 in new window has 2019 bits and it supports the same
                 operations with the same semantics as a number of type
                 {\tt unsigned int}",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm; Description; Experimentation;
                 Implementation; Long division; Meticulous analysis;
                 Multiple-precision arithmetic; Software library",
  ORCID-numbers = "Katajainen, Jyrki/0000-0002-7714-5588",
}


