# bibtab

bibtype: article
filename: fparith.bib
label: Bapst:2008:SIO
author: Frederic Bapst and Francois Kilchoer
title: Signalling Integer Overflows in Java: a tool for checking overflows in Java code
journal: j-DDJ
volume: 33
number: 9
pages: 54--58
month: sep
monthnumber: 9
year: 2008
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Aug 12 18:02:50 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.12 18:02:50 ???
URL: http://home.hefr.ch/bapst/cojac
fjournal: Dr. Dobb's Journal of Software Tools
keywords: integer overflow detection; Java
acknowledgement: ack-nhfb
rawauthor: Frederic Bapst and Fran{\c{c}}ois Kilchoer
rawtitle: Signalling Integer Overflows in {Java}: a tool for checking overflows in {Java} code
remark:
The COJAC (Checking Overflows in JAva Code) tool instruments a compiled tt .class file, replacing integer instructions subject to overflow with calls to routines that report any overflow.

entry:
@Article{Bapst:2008:SIO,
  author =       "Frederic Bapst and Fran{\c{c}}ois Kilchoer",
  title =        "Signalling Integer Overflows in {Java}: a tool for
                 checking overflows in {Java} code",
  journal =      j-DDJ,
  volume =       "33",
  number =       "9",
  pages =        "54--58",
  month =        sep,
  year =         "2008",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Aug 12 18:02:50 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home.hefr.ch/bapst/cojac",
  acknowledgement = ack-nhfb,
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "integer overflow detection; Java",
  remark =       "The COJAC (Checking Overflows in JAva Code) tool
                 instruments a compiled {\tt .class} file, replacing
                 integer instructions subject to overflow with calls to
                 routines that report any overflow.",
}


bibtype: article
filename: fparith.bib
label: Beuchat:2008:AGM
author: Jean-Luc Beuchat and Jean-Michel Muller
title: Automatic Generation of Modular Multipliers for FPGA Applications
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 12
pages: 1600--1613
month: dec
monthnumber: 12
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.102
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:44 MDT 2011
bibtimestamp: 2011.07.04 12:17:44 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4564441
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jean-Luc Beuchat and Jean-Michel Muller
rawtitle: Automatic Generation of Modular Multipliers for {FPGA} Applications
entry:
@Article{Beuchat:2008:AGM,
  author =       "Jean-Luc Beuchat and Jean-Michel Muller",
  title =        "Automatic Generation of Modular Multipliers for {FPGA}
                 Applications",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "12",
  pages =        "1600--1613",
  month =        dec,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.102",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4564441",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Boldo:2008:EFC
author: Sylvie Boldo and Guillaume Melquiond
title: Emulation of a FMA and Correctly Rounded Sums: Proved Algorithms Using Rounding to Odd
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 4
pages: 462--471
month: apr
monthnumber: 4
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70819
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:40 MDT 2011
bibtimestamp: 2011.07.04 12:17:40 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sylvie Boldo and Guillaume Melquiond
rawtitle: Emulation of a {FMA} and Correctly Rounded Sums: Proved Algorithms Using Rounding to Odd
URL:
https://ens-lyon.hal.science/inria-00080427/file/odd-rounding.pdf; https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358278

abstract:
Rounding to odd is a nonstandard rounding on floating-point numbers. By using it for some intermediate values instead of rounding to nearest, correctly rounded results can be obtained at the end of computations. We present an algorithm for emulating the fused multiply-and-add operator. We also present an iterative algorithm for computing the correctly rounded sum of a set of floating-point numbers under mild assumptions. A variation on both previous algorithms is the correctly rounded sum of any three floating-point numbers. This leads to efficient implementations, even when this rounding is not available. In order to guarantee the correctness of these properties and algorithms, we formally proved them by using the Coq proof checker.

rawabstract:
Rounding to odd is a nonstandard rounding on floating-point numbers. By using it for some intermediate values instead of rounding to nearest, correctly rounded results can be obtained at the end of computations. We present an algorithm for emulating the fused multiply-and-add operator. We also present an iterative algorithm for computing the correctly rounded sum of a set of floating-point numbers under mild assumptions. A variation on both previous algorithms is the correctly rounded sum of any three floating-point numbers. This leads to efficient implementations, even when this rounding is not available. In order to guarantee the correctness of these properties and algorithms, we formally proved them by using the Coq proof checker.

entry:
@Article{Boldo:2008:EFC,
  author =       "Sylvie Boldo and Guillaume Melquiond",
  title =        "Emulation of a {FMA} and Correctly Rounded Sums:
                 Proved Algorithms Using Rounding to Odd",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "4",
  pages =        "462--471",
  month =        apr,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70819",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ens-lyon.hal.science/inria-00080427/file/odd-rounding.pdf;
                 https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358278",
  abstract =     "Rounding to odd is a nonstandard rounding on
                 floating-point numbers. By using it for some
                 intermediate values instead of rounding to nearest,
                 correctly rounded results can be obtained at the end of
                 computations. We present an algorithm for emulating the
                 fused multiply-and-add operator. We also present an
                 iterative algorithm for computing the correctly rounded
                 sum of a set of floating-point numbers under mild
                 assumptions. A variation on both previous algorithms is
                 the correctly rounded sum of any three floating-point
                 numbers. This leads to efficient implementations, even
                 when this rounding is not available. In order to
                 guarantee the correctness of these properties and
                 algorithms, we formally proved them by using the Coq
                 proof checker.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keyword =      "double rounding; round-to-odd (RO(x))",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2008:CRM
author: Nicolas Brisebarre and Jean-Michel Muller
title: Correctly Rounded Multiplication by Arbitrary Precision Constants
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 2
pages: 165--174
month: feb
monthnumber: 2
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70813
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:40 MDT 2011
bibtimestamp: 2011.07.04 12:17:40 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358257
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Nicolas Brisebarre and Jean-Michel Muller
rawtitle: Correctly Rounded Multiplication by Arbitrary Precision Constants
entry:
@Article{Brisebarre:2008:CRM,
  author =       "Nicolas Brisebarre and Jean-Michel Muller",
  title =        "Correctly Rounded Multiplication by Arbitrary
                 Precision Constants",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "2",
  pages =        "165--174",
  month =        feb,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70813",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358257",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2008:EME
title: An Efficient Method for Evaluating Polynomial and Rational Function Approximations
crossref: IEEE:2008:ICA
pages: 233--238
year: 2008
DOI: https://doi.org/10.1109/ASAP.2008.4580185
bibdate: Mon Feb 10 07:28:25 2020
bibtimestamp: 2020.02.10 07:28:25 ???
acknowledgement: ack-nhfb
rawtitle: An Efficient Method for Evaluating Polynomial and Rational Function Approximations
author:
Nicolas Brisebarre and Sylvain Chevillard and Milos D. Ercegovac and Jean-Michel Muller and Serge Torres

rawauthor:
Nicolas Brisebarre and Sylvain Chevillard and Milo{\v{s}} D. Ercegovac and Jean-Michel Muller and Serge Torres

entry:
@InProceedings{Brisebarre:2008:EME,
  author =       "Nicolas Brisebarre and Sylvain Chevillard and
                 Milo{\v{s}} D. Ercegovac and Jean-Michel Muller and
                 Serge Torres",
  title =        "An Efficient Method for Evaluating Polynomial and
                 Rational Function Approximations",
  crossref =     "IEEE:2008:ICA",
  pages =        "233--238",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ASAP.2008.4580185",
  bibdate =      "Mon Feb 10 07:28:25 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2008:IFP
author: Nicolas Brisebarre and Florent de Dinechin and Jean-Michel Muller
title: Integer and floating-point constant multipliers for FPGAs
crossref: IEEE:2008:ICA
pages: 239--244
year: 2008
DOI: https://doi.org/10.1109/ASAP.2008.4580184
bibdate: Mon Feb 10 08:12:58 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 08:12:58 ???
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Florent de Dinechin and Jean-Michel Muller
rawtitle: Integer and floating-point constant multipliers for {FPGAs}
entry:
@InProceedings{Brisebarre:2008:IFP,
  author =       "Nicolas Brisebarre and Florent de Dinechin and
                 Jean-Michel Muller",
  title =        "Integer and floating-point constant multipliers for
                 {FPGAs}",
  crossref =     "IEEE:2008:ICA",
  pages =        "239--244",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ASAP.2008.4580184",
  bibdate =      "Mon Feb 10 08:12:58 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Buttari:2008:UMP
author: Alfredo Buttari and Jack Dongarra and Jakub Kurzak and Piotr Luszczek and Stanimir Tomov
journal: j-TOMS
volume: 34
number: 4
pages: 17:1--17:22
month: jul
monthnumber: 7
year: 2008
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1377596.1377597
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Jul 16 11:30:01 MDT 2008
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.16 11:30:01 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: floating point; iterative refinement; linear systems; precision
acknowledgement: ack-nhfb
articleno: 17
journalURL: https://dl.acm.org/loi/toms
rawauthor: Alfredo Buttari and Jack Dongarra and Jakub Kurzak and Piotr Luszczek and Stanimir Tomov
title:
Using Mixed Precision for Sparse Matrix Computations to Enhance the Performance while Achieving 64-bit Accuracy

abstract:
By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution. These ideas can be applied to sparse multifrontal and supernodal direct techniques and sparse iterative techniques such as Krylov subspace methods. The approach presented here can apply not only to conventional processors but also to exotic technologies such as Field Programmable Gate Arrays (FPGA), Graphical Processing Units (GPU), and the Cell BE processor.

rawabstract:
By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution. These ideas can be applied to sparse multifrontal and supernodal direct techniques and sparse iterative techniques such as Krylov subspace methods. The approach presented here can apply not only to conventional processors but also to exotic technologies such as Field Programmable Gate Arrays (FPGA), Graphical Processing Units (GPU), and the Cell BE processor.

rawtitle:
Using Mixed Precision for Sparse Matrix Computations to Enhance the Performance while Achieving 64-bit Accuracy

entry:
@Article{Buttari:2008:UMP,
  author =       "Alfredo Buttari and Jack Dongarra and Jakub Kurzak and
                 Piotr Luszczek and Stanimir Tomov",
  title =        "Using Mixed Precision for Sparse Matrix Computations
                 to Enhance the Performance while Achieving 64-bit
                 Accuracy",
  journal =      j-TOMS,
  volume =       "34",
  number =       "4",
  pages =        "17:1--17:22",
  month =        jul,
  year =         "2008",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1377596.1377597",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Jul 16 11:30:01 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "By using a combination of 32-bit and 64-bit floating
                 point arithmetic, the performance of many sparse linear
                 algebra algorithms can be significantly enhanced while
                 maintaining the 64-bit accuracy of the resulting
                 solution. These ideas can be applied to sparse
                 multifrontal and supernodal direct techniques and
                 sparse iterative techniques such as Krylov subspace
                 methods. The approach presented here can apply not only
                 to conventional processors but also to exotic
                 technologies such as Field Programmable Gate Arrays
                 (FPGA), Graphical Processing Units (GPU), and the Cell
                 BE processor.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "floating point; iterative refinement; linear systems;
                 precision",
}


bibtype: article
filename: fparith.bib
label: Carnicer:2008:REP
author: J. M. Carnicer and T. N. T. Goodman and J. M. Pena
title: Roundoff errors for polynomial evaluation by a family of formulae
journal: j-COMPUTING
volume: 82
number: 2--3
pages: 199--215
month: jul
monthnumber: 7
year: 2008
CODEN: CMPTA2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Sun Oct 31 11:09:47 MDT 2010
bibtimestamp: 2010.10.31 11:09:47 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=82&issue=2&spage=199
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: J. M. Carnicer and T. N. T. Goodman and J. M. Pe{\~n}a
rawtitle: Roundoff errors for polynomial evaluation by a family of formulae
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=82&issue=2; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Carnicer:2008:REP,
  author =       "J. M. Carnicer and T. N. T. Goodman and J. M.
                 Pe{\~n}a",
  title =        "Roundoff errors for polynomial evaluation by a family
                 of formulae",
  journal =      j-COMPUTING,
  volume =       "82",
  number =       "2--3",
  pages =        "199--215",
  month =        jul,
  year =         "2008",
  CODEN =        "CMPTA2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Sun Oct 31 11:09:47 MDT 2010",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=82&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=82&issue=2&spage=199",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
}


bibtype: article
filename: fparith.bib
label: Castaldo:2008:RFP
author: Anthony M. Castaldo and R. Clint Whaley and Anthony T. Chronopoulos
title: Reducing Floating Point Error in Dot Product Using the Superblock Family of Algorithms
journal: j-SIAM-J-SCI-COMP
volume: 31
number: 2
pages: 1156--1174
year: 2008
CODEN: SJOCE3
DOI: https://doi.org/10.1137/070679946
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:44:14 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:44:14 MDT
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; floating-point dot product
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Anthony M. Castaldo and R. Clint Whaley and Anthony T. Chronopoulos
rawtitle: Reducing Floating Point Error in Dot Product Using the Superblock Family of Algorithms
abstract:
This paper discusses both the theoretical and statistical errors obtained by various well-known dot products, from the canonical to pairwise algorithms, and introduces a new and more general framework that we have named superblock which subsumes them and permits a practitioner to make trade-offs between computational performance, memory usage, and error behavior. We show that algorithms with lower error bounds tend to behave noticeably better in practice. Unlike many such error-reducing algorithms, superblock requires no additional floating point operations and should be implementable with little to no performance loss, making it suitable for use as a performance-critical building block of a linear algebra kernel.

rawabstract:
This paper discusses both the theoretical and statistical errors obtained by various well-known dot products, from the canonical to pairwise algorithms, and introduces a new and more general framework that we have named superblock which subsumes them and permits a practitioner to make trade-offs between computational performance, memory usage, and error behavior. We show that algorithms with lower error bounds tend to behave noticeably better in practice. Unlike many such error-reducing algorithms, superblock requires no additional floating point operations and should be implementable with little to no performance loss, making it suitable for use as a performance-critical building block of a linear algebra kernel.

entry:
@Article{Castaldo:2008:RFP,
  author =       "Anthony M. Castaldo and R. Clint Whaley and Anthony T.
                 Chronopoulos",
  title =        "Reducing Floating Point Error in Dot Product Using the
                 Superblock Family of Algorithms",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "31",
  number =       "2",
  pages =        "1156--1174",
  month =        "????",
  year =         "2008",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/070679946",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:44:14 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper discusses both the theoretical and
                 statistical errors obtained by various well-known dot
                 products, from the canonical to pairwise algorithms,
                 and introduces a new and more general framework that we
                 have named superblock which subsumes them and permits a
                 practitioner to make trade-offs between computational
                 performance, memory usage, and error behavior. We show
                 that algorithms with lower error bounds tend to behave
                 noticeably better in practice. Unlike many such
                 error-reducing algorithms, superblock requires no
                 additional floating point operations and should be
                 implementable with little to no performance loss,
                 making it suitable for use as a performance-critical
                 building block of a linear algebra kernel.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; floating-point dot
                 product",
}


bibtype: inproceedings
filename: fparith.bib
label: Castellanos:2008:CTD
author: Ivan D. Castellanos and James E. Stine
title: Compressor trees for decimal partial product reduction
crossref: ACM:2008:GPA
pages: 107--110
year: 2008
DOI: https://doi.org/10.1145/1366110.1366137
bibdate: Thu Aug 07 17:39:02 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 17:39:02 ???
acknowledgement: ack-nhfb
rawauthor: Ivan D. Castellanos and James E. Stine
rawtitle: Compressor trees for decimal partial product reduction
abstract:
Decimal multiplication has grown in interest due to the recent announcement of new IEEE 754R standards and the availability of high-speed decimal computation hardware. Prior research enabled partial products to be coded more efficiently for their use in radix 10 architectures. This paper clarifies previous techniques for partial product reduction using carry-save adders and presents a new 4:2 compressor structure. This new structure improves performance at the expense of more gates, however, regularity is introduced into the circuit to promote implementations in Very Large Scale Integration (VLSI) Designs. Results are presented and compared for several designs using a TSMC SCN6M $ 0.18 mu $ m feature size.

rawabstract:
Decimal multiplication has grown in interest due to the recent announcement of new IEEE 754R standards and the availability of high-speed decimal computation hardware. Prior research enabled partial products to be coded more efficiently for their use in radix 10 architectures. This paper clarifies previous techniques for partial product reduction using carry-save adders and presents a new 4:2 compressor structure. This new structure improves performance at the expense of more gates, however, regularity is introduced into the circuit to promote implementations in Very Large Scale Integration (VLSI) Designs. Results are presented and compared for several designs using a TSMC SCN6M $ 0.18 \mu $ m feature size.

entry:
@InProceedings{Castellanos:2008:CTD,
  author =       "Ivan D. Castellanos and James E. Stine",
  title =        "Compressor trees for decimal partial product
                 reduction",
  crossref =     "ACM:2008:GPA",
  pages =        "107--110",
  year =         "2008",
  DOI =          "https://doi.org/10.1145/1366110.1366137",
  bibdate =      "Thu Aug 07 17:39:02 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Decimal multiplication has grown in interest due to
                 the recent announcement of new IEEE 754R standards and
                 the availability of high-speed decimal computation
                 hardware. Prior research enabled partial products to be
                 coded more efficiently for their use in radix 10
                 architectures. This paper clarifies previous techniques
                 for partial product reduction using carry-save adders
                 and presents a new 4:2 compressor structure. This new
                 structure improves performance at the expense of more
                 gates, however, regularity is introduced into the
                 circuit to promote implementations in Very Large Scale
                 Integration (VLSI) Designs. Results are presented and
                 compared for several designs using a TSMC SCN6M $ 0.18
                 \mu $ m feature size.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Cavagnino:2008:EAI
author: D. Cavagnino and A. E. Werbrouck
title: Efficient Algorithms for Integer Division by Constants Using Multiplication
journal: j-COMP-J
volume: 51
number: 4
pages: 470--480
month: jul
monthnumber: 7
year: 2008
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxm082
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Apr 28 14:33:34 MDT 2010
bibtimestamp: 2010.04.28 14:33:34 MDT
fjournal: The Computer Journal
keywords: division by multiplication; efficiency; integer constants; integer division; multiplicative inverse
remark: See cite Cavagnino:2011:AAD.
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: D. Cavagnino and A. E. Werbrouck
rawtitle: Efficient Algorithms for Integer Division by Constants Using Multiplication
bibsource:
http://comjnl.oxfordjournals.org/content/vol51/issue4/index.dtl; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/cgi/content/abstract/51/4/470; http://comjnl.oxfordjournals.org/cgi/content/full/51/4/470; http://comjnl.oxfordjournals.org/cgi/reprint/51/4/470

abstract:
We present a complete analysis of the integer division of a single unsigned dividend word by a single unsigned divisor word based on double-word multiplication of the dividend by an inverse of the divisor. The well-known advantage of this method yields run-time efficiency, if the inverse of the divisor can be calculated at compile time, since multiplication is much faster than division in arithmetic units. Our analysis leads to the discovery of a limit to the straightforward application of this method in the form of a critical dividend, which fortunately associates with a minority of the possible divisors (20%) and defines only a small upper part of the available dividend space. We present two algorithms for ascertaining whether a critical dividend exists and, if so, its value along with a circumvention of this limit. For completeness, we include an algorithm for integer division of a unsigned double-word dividend by an unsigned single-word divisor in which the quotient is not limited to a single word and the remainder is an intrinsic part of the result.

rawabstract:
We present a complete analysis of the integer division of a single unsigned dividend word by a single unsigned divisor word based on double-word multiplication of the dividend by an inverse of the divisor. The well-known advantage of this method yields run-time efficiency, if the inverse of the divisor can be calculated at compile time, since multiplication is much faster than division in arithmetic units. Our analysis leads to the discovery of a limit to the straightforward application of this method in the form of a critical dividend, which fortunately associates with a minority of the possible divisors (20\%) and defines only a small upper part of the available dividend space. We present two algorithms for ascertaining whether a critical dividend exists and, if so, its value along with a circumvention of this limit. For completeness, we include an algorithm for integer division of a unsigned double-word dividend by an unsigned single-word divisor in which the quotient is not limited to a single word and the remainder is an intrinsic part of the result.

entry:
@Article{Cavagnino:2008:EAI,
  author =       "D. Cavagnino and A. E. Werbrouck",
  title =        "Efficient Algorithms for Integer Division by Constants
                 Using Multiplication",
  journal =      j-COMP-J,
  volume =       "51",
  number =       "4",
  pages =        "470--480",
  month =        jul,
  year =         "2008",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxm082",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Apr 28 14:33:34 MDT 2010",
  bibsource =    "http://comjnl.oxfordjournals.org/content/vol51/issue4/index.dtl;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/cgi/content/abstract/51/4/470;
                 http://comjnl.oxfordjournals.org/cgi/content/full/51/4/470;
                 http://comjnl.oxfordjournals.org/cgi/reprint/51/4/470",
  abstract =     "We present a complete analysis of the integer division
                 of a single unsigned dividend word by a single unsigned
                 divisor word based on double-word multiplication of the
                 dividend by an inverse of the divisor. The well-known
                 advantage of this method yields run-time efficiency, if
                 the inverse of the divisor can be calculated at compile
                 time, since multiplication is much faster than division
                 in arithmetic units. Our analysis leads to the
                 discovery of a limit to the straightforward application
                 of this method in the form of a critical dividend,
                 which fortunately associates with a minority of the
                 possible divisors (20\%) and defines only a small upper
                 part of the available dividend space. We present two
                 algorithms for ascertaining whether a critical dividend
                 exists and, if so, its value along with a circumvention
                 of this limit. For completeness, we include an
                 algorithm for integer division of a unsigned
                 double-word dividend by an unsigned single-word divisor
                 in which the quotient is not limited to a single word
                 and the remainder is an intrinsic part of the result.",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "division by multiplication; efficiency; integer
                 constants; integer division; multiplicative inverse",
  remark =       "See \cite{Cavagnino:2011:AAD}.",
}


bibtype: article
filename: fparith.bib
label: Colon-Bonet:2008:MEF
author: Glenn Colon-Bonet and Paul Winterrowd, Jr.
title: Multiplier Evolution: a Family of Multiplier VLSI Implementations
journal: j-COMP-J
volume: 51
number: 5
pages: 585--594
month: sep
monthnumber: 9
year: 2008
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxm123
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Apr 28 14:33:34 MDT 2010
bibtimestamp: 2010.04.28 14:33:34 MDT
fjournal: The Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Glenn Col{\'o}n-Bonet and Paul {Winterrowd, Jr.}
rawtitle: Multiplier Evolution: a Family of Multiplier {VLSI} Implementations
bibsource:
http://comjnl.oxfordjournals.org/content/vol51/issue5/index.dtl; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/cgi/content/abstract/51/5/585; http://comjnl.oxfordjournals.org/cgi/content/full/51/5/585; http://comjnl.oxfordjournals.org/cgi/reprint/51/5/585

entry:
@Article{Colon-Bonet:2008:MEF,
  author =       "Glenn Col{\'o}n-Bonet and Paul {Winterrowd, Jr.}",
  title =        "Multiplier Evolution: a Family of Multiplier {VLSI}
                 Implementations",
  journal =      j-COMP-J,
  volume =       "51",
  number =       "5",
  pages =        "585--594",
  month =        sep,
  year =         "2008",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxm123",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Apr 28 14:33:34 MDT 2010",
  bibsource =    "http://comjnl.oxfordjournals.org/content/vol51/issue5/index.dtl;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/cgi/content/abstract/51/5/585;
                 http://comjnl.oxfordjournals.org/cgi/content/full/51/5/585;
                 http://comjnl.oxfordjournals.org/cgi/reprint/51/5/585",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: article
filename: fparith.bib
label: Cordeiro:2008:MSI
author: Gauss M. Cordeiro and Borko D. Stosic
title: Maple script for improving test statistics
journal: j-J-STAT-COMPUT-SIMUL
volume: 78
number: 11
pages: 1045--1053
year: 2008
CODEN: JSCSAJ
DOI: https://doi.org/10.1080/00949650701490969
ISSNL: 0094-9655 OR 00949655
bibdate: Tue Apr 22 09:12:46 MDT 2014
bibtimestamp: 2014.04.22 09:12:46 MDT
fjournal: Journal of Statistical Computation and Simulation
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/gscs20
rawauthor: Gauss M. Cordeiro and Borko D. Stosi{\'c}
rawtitle: {Maple} script for improving test statistics
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jstatcomputsimul.bib; https://www.math.utah.edu/pub/tex/bib/maple-extract.bib

entry:
@Article{Cordeiro:2008:MSI,
  author =       "Gauss M. Cordeiro and Borko D. Stosi{\'c}",
  title =        "{Maple} script for improving test statistics",
  journal =      j-J-STAT-COMPUT-SIMUL,
  volume =       "78",
  number =       "11",
  pages =        "1045--1053",
  year =         "2008",
  CODEN =        "JSCSAJ",
  DOI =          "https://doi.org/10.1080/00949650701490969",
  ISSN =         "0094-9655 (print), 1026-7778 (electronic), 1563-5163",
  ISSN-L =       "0094-9655",
  bibdate =      "Tue Apr 22 09:12:46 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jstatcomputsimul.bib;
                 https://www.math.utah.edu/pub/tex/bib/maple-extract.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Statistical Computation and Simulation",
  journal-URL =  "http://www.tandfonline.com/loi/gscs20",
}


bibtype: inproceedings
filename: fparith.bib
label: De:2008:FIM
author: Anindya De and Piyush P. Kurur and Chandan Saha and Ramprasad Saptharishi
title: Fast integer multiplication using modular arithmetic
crossref: ACM:2008:SPA
pages: 499--506
year: 2008
DOI: https://doi.org/10.1145/1374376.1374447
bibdate: Fri Jun 20 18:31:53 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 18:31:53 MDT
keywords: computational algebra; integer multiplication; modular arithmetic
acknowledgement: ack-nhfb
rawauthor: Anindya De and Piyush P. Kurur and Chandan Saha and Ramprasad Saptharishi
rawtitle: Fast integer multiplication using modular arithmetic
abstract:
We give an $ O(N log N 2^O(log *N)) $ algorithm for multiplying two $N$-bit integers that improves the $ O(N log N log log N) $ algorithm by Schonhage--Strassen. Both these algorithms use modular arithmetic. Recently, Furer gave an $ O(N log N 2^O(log *N)) $ algorithm which however uses arithmetic over complex numbers as opposed to modular arithmetic. In this paper, we use multivariate polynomial multiplication along with ideas from Furer's algorithm to achieve this improvement in the modular setting. Our algorithm can also be viewed as a $p$-adic version of Furer's algorithm. Thus, we show that the two seemingly different approaches to integer multiplication, modular and complex arithmetic, are similar.

rawabstract:
We give an $ O(N \log N 2^{O(\log *N)}) $ algorithm for multiplying two $N$-bit integers that improves the $ O(N \log N \log \log N) $ algorithm by Sch{\"o}nhage--Strassen. Both these algorithms use modular arithmetic. Recently, F{\"u}rer gave an $ O(N \log N 2^{O(\log *N)}) $ algorithm which however uses arithmetic over complex numbers as opposed to modular arithmetic. In this paper, we use multivariate polynomial multiplication along with ideas from F{\"u}rer's algorithm to achieve this improvement in the modular setting. Our algorithm can also be viewed as a $p$-adic version of F{\"u}rer's algorithm. Thus, we show that the two seemingly different approaches to integer multiplication, modular and complex arithmetic, are similar.

entry:
@InProceedings{De:2008:FIM,
  author =       "Anindya De and Piyush P. Kurur and Chandan Saha and
                 Ramprasad Saptharishi",
  title =        "Fast integer multiplication using modular arithmetic",
  crossref =     "ACM:2008:SPA",
  pages =        "499--506",
  year =         "2008",
  DOI =          "https://doi.org/10.1145/1374376.1374447",
  bibdate =      "Fri Jun 20 18:31:53 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We give an $ O(N \log N 2^{O(\log *N)}) $ algorithm
                 for multiplying two $N$-bit integers that improves the
                 $ O(N \log N \log \log N) $ algorithm by
                 Sch{\"o}nhage--Strassen. Both these algorithms use
                 modular arithmetic. Recently, F{\"u}rer gave an $ O(N
                 \log N 2^{O(\log *N)}) $ algorithm which however uses
                 arithmetic over complex numbers as opposed to modular
                 arithmetic. In this paper, we use multivariate
                 polynomial multiplication along with ideas from
                 F{\"u}rer's algorithm to achieve this improvement in
                 the modular setting. Our algorithm can also be viewed
                 as a $p$-adic version of F{\"u}rer's algorithm. Thus,
                 we show that the two seemingly different approaches to
                 integer multiplication, modular and complex arithmetic,
                 are similar.",
  acknowledgement = ack-nhfb,
  keywords =     "computational algebra; integer multiplication; modular
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: DeDinechin:2008:CFP
author: Florent De Dinechin and Christoph Quirin Lauter and Guillaume Melquiond
title: Certifying floating-point implementations using Gappa
journal: arXiv.org
pages: ??--??
day: 3
month: jan
monthnumber: 1
year: 2008
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0801.0523
subject: Numerical Analysis (cs.NA); Mathematical Software (cs.MS)
acknowledgement: ack-nhfb
rawauthor: Florent {De Dinechin} and Christoph Quirin Lauter and Guillaume Melquiond
rawtitle: Certifying floating-point implementations using {Gappa}
abstract:
High confidence in floating-point programs requires proving numerical properties of final and intermediate values. One may need to guarantee that a value stays within some range, or that the error relative to some ideal value is well bounded. Such work may require several lines of proof for each line of code, and will usually be broken by the smallest change to the code (e.g. for maintenance or optimization purpose). Certifying these programs by hand is therefore very tedious and error-prone. This article discusses the use of the Gappa proof assistant in this context. Gappa has two main advantages over previous approaches: Its input format is very close to the actual C code to validate, and it automates error evaluation and propagation using interval arithmetic. Besides, it can be used to incrementally prove complex mathematical properties pertaining to the C code. Yet it does not require any specific knowledge about automatic theorem proving, and thus is accessible to a wide community. Moreover, Gappa may generate a formal proof of the results that can be checked independently by a lower-level proof assistant like Coq, hence providing an even higher confidence in the certification of the numerical code. The article demonstrates the use of this tool on a real-size example, an elementary function with correctly rounded output.

rawabstract:
High confidence in floating-point programs requires proving numerical properties of final and intermediate values. One may need to guarantee that a value stays within some range, or that the error relative to some ideal value is well bounded. Such work may require several lines of proof for each line of code, and will usually be broken by the smallest change to the code (e.g. for maintenance or optimization purpose). Certifying these programs by hand is therefore very tedious and error-prone. This article discusses the use of the Gappa proof assistant in this context. Gappa has two main advantages over previous approaches: Its input format is very close to the actual C code to validate, and it automates error evaluation and propagation using interval arithmetic. Besides, it can be used to incrementally prove complex mathematical properties pertaining to the C code. Yet it does not require any specific knowledge about automatic theorem proving, and thus is accessible to a wide community. Moreover, Gappa may generate a formal proof of the results that can be checked independently by a lower-level proof assistant like Coq, hence providing an even higher confidence in the certification of the numerical code. The article demonstrates the use of this tool on a real-size example, an elementary function with correctly rounded output.

entry:
@Article{DeDinechin:2008:CFP,
  author =       "Florent {De Dinechin} and Christoph Quirin Lauter and
                 Guillaume Melquiond",
  title =        "Certifying floating-point implementations using
                 {Gappa}",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "3",
  month =        jan,
  year =         "2008",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0801.0523",
  abstract =     "High confidence in floating-point programs requires
                 proving numerical properties of final and intermediate
                 values. One may need to guarantee that a value stays
                 within some range, or that the error relative to some
                 ideal value is well bounded. Such work may require
                 several lines of proof for each line of code, and will
                 usually be broken by the smallest change to the code
                 (e.g. for maintenance or optimization purpose).
                 Certifying these programs by hand is therefore very
                 tedious and error-prone. This article discusses the use
                 of the Gappa proof assistant in this context. Gappa has
                 two main advantages over previous approaches: Its input
                 format is very close to the actual C code to validate,
                 and it automates error evaluation and propagation using
                 interval arithmetic. Besides, it can be used to
                 incrementally prove complex mathematical properties
                 pertaining to the C code. Yet it does not require any
                 specific knowledge about automatic theorem proving, and
                 thus is accessible to a wide community. Moreover, Gappa
                 may generate a formal proof of the results that can be
                 checked independently by a lower-level proof assistant
                 like Coq, hence providing an even higher confidence in
                 the certification of the numerical code. The article
                 demonstrates the use of this tool on a real-size
                 example, an elementary function with correctly rounded
                 output.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA); Mathematical Software
                 (cs.MS)",
}


bibtype: article
filename: fparith.bib
label: DeDinechin:2008:OPF
author: Florent De Dinechin and Christoph Quirin Lauter
title: Optimizing polynomials for floating-point implementation
journal: arXiv.org
pages: 1--12
day: 4
month: mar
monthnumber: 3
year: 2008
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0803.0439
subject: Numerical Analysis (cs.NA); Mathematical Software (cs.MS)
acknowledgement: ack-nhfb
rawauthor: Florent {De Dinechin} and Christoph Quirin Lauter
rawtitle: Optimizing polynomials for floating-point implementation
abstract:
The floating-point implementation of a function on an interval often reduces to polynomial approximation, the polynomial being typically provided by Remez algorithm. However, the floating-point evaluation of a Remez polynomial sometimes leads to catastrophic cancellations. This happens when some of the polynomial coefficients are very small in magnitude with respects to others. In this case, it is better to force these coefficients to zero, which also reduces the operation count. This technique, classically used for odd or even functions, may be generalized to a much larger class of functions. An algorithm is presented that forces to zero the smaller coefficients of the initial polynomial thanks to a modified Remez algorithm targeting an incomplete monomial basis. One advantage of this technique is that it is purely numerical, the function being used as a numerical black box. This algorithm is implemented within a larger polynomial implementation tool that is demonstrated on a range of examples, resulting in polynomials with less coefficients than those obtained the usual way.

rawabstract:
The floating-point implementation of a function on an interval often reduces to polynomial approximation, the polynomial being typically provided by Remez algorithm. However, the floating-point evaluation of a Remez polynomial sometimes leads to catastrophic cancellations. This happens when some of the polynomial coefficients are very small in magnitude with respects to others. In this case, it is better to force these coefficients to zero, which also reduces the operation count. This technique, classically used for odd or even functions, may be generalized to a much larger class of functions. An algorithm is presented that forces to zero the smaller coefficients of the initial polynomial thanks to a modified Remez algorithm targeting an incomplete monomial basis. One advantage of this technique is that it is purely numerical, the function being used as a numerical black box. This algorithm is implemented within a larger polynomial implementation tool that is demonstrated on a range of examples, resulting in polynomials with less coefficients than those obtained the usual way.

entry:
@Article{DeDinechin:2008:OPF,
  author =       "Florent {De Dinechin} and Christoph Quirin Lauter",
  title =        "Optimizing polynomials for floating-point
                 implementation",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--12",
  day =          "4",
  month =        mar,
  year =         "2008",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0803.0439",
  abstract =     "The floating-point implementation of a function on an
                 interval often reduces to polynomial approximation, the
                 polynomial being typically provided by Remez algorithm.
                 However, the floating-point evaluation of a Remez
                 polynomial sometimes leads to catastrophic
                 cancellations. This happens when some of the polynomial
                 coefficients are very small in magnitude with respects
                 to others. In this case, it is better to force these
                 coefficients to zero, which also reduces the operation
                 count. This technique, classically used for odd or even
                 functions, may be generalized to a much larger class of
                 functions. An algorithm is presented that forces to
                 zero the smaller coefficients of the initial polynomial
                 thanks to a modified Remez algorithm targeting an
                 incomplete monomial basis. One advantage of this
                 technique is that it is purely numerical, the function
                 being used as a numerical black box. This algorithm is
                 implemented within a larger polynomial implementation
                 tool that is demonstrated on a range of examples,
                 resulting in polynomials with less coefficients than
                 those obtained the usual way.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA); Mathematical Software
                 (cs.MS)",
}


bibtype: article
filename: fparith.bib
label: Dimitrov:2008:PSP
author: V. S. Dimitrov and K. U. Jarvinen and M. J. Jacobson and W. Chan and Zhun Huang
title: Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 11
pages: 1469--1481
month: nov
monthnumber: 11
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.65
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:44 MDT 2011
bibtimestamp: 2011.07.04 12:17:44 MDT
note: See comments cite Lee:2012:CPS.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4487060
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: V. S. Dimitrov and K. U. Jarvinen and M. J. Jacobson and W. Chan and Zhun Huang
rawnote: See comments \cite{Lee:2012:CPS}.
rawtitle: Provably Sublinear Point Multiplication on {Koblitz} Curves and Its Hardware Implementation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

entry:
@Article{Dimitrov:2008:PSP,
  author =       "V. S. Dimitrov and K. U. Jarvinen and M. J. Jacobson
                 and W. Chan and Zhun Huang",
  title =        "Provably Sublinear Point Multiplication on {Koblitz}
                 Curves and Its Hardware Implementation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "11",
  pages =        "1469--1481",
  month =        nov,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.65",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  note =         "See comments \cite{Lee:2012:CPS}.",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4487060",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Dvir:2008:HRT
author: Zeev Dvir and Amir Shpilka and Amir Yehudayoff
title: Hardness-randomness tradeoffs for bounded depth arithmetic circuits
crossref: ACM:2008:SPA
pages: 741--748
year: 2008
DOI: https://doi.org/10.1145/1374376.1374482
bibdate: Fri Jun 20 18:31:53 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 18:31:53 MDT
acknowledgement: ack-nhfb
rawauthor: Zeev Dvir and Amir Shpilka and Amir Yehudayoff
rawtitle: Hardness-randomness tradeoffs for bounded depth arithmetic circuits
abstract:
In this paper we show that lower bounds for bounded depth arithmetic circuits imply derandomization of polynomial identity testing for bounded depth arithmetic circuits. More formally, if there exists an explicit polynomial $ f(x_1, ldots , x_m) $ that cannot be computed by a depth $d$ arithmetic circuit of small size then there exists an efficient deterministic algorithm to test whether a given depth $ d - 8 $ circuit is identically zero or not (assuming the individual degrees of the tested circuit are not too high). In particular, if we are guaranteed that the circuit computes a multilinear polynomial then we can perform the identity test efficiently. To the best of our knowledge this is the first hardness-randomness tradeoff for bounded depth arithmetic circuits. The above results are obtained using the arithmetic Nisan-Wigderson generator of Impagliazzo and Kabanets together with a new theorem on bounded depth circuits, which is the main technical contribution of our work. This theorem deals with polynomial equations of the form $ P(x_1, ldots , x_n, y) equiv 0 $ and shows that if $P$ has a circuit of depth $d$ and size $s$ and if the polynomial $ f(x_1, ldots , x_n) $ satisfies $ P(x_1, ldots , x_n, f(x_1, ldots , x_n)) equiv 0 $ then $f$ has a circuit of depth $ d + 3 $ and size $ O(s times r + m^r) $, where $m$ is the degree of $f$ and $r$ is the highest degree of the variable $y$ appearing in $P$. In the other direction we observe that the methods of Impagliazzo and Kabanets imply that if we can derandomize polynomial identity testing for bounded depth circuits then NEXP does not have bounded depth arithmetic circuits. That is, either NEXP $ not subset $ P/poly or the Permanent is not computable by polynomial size bounded depth arithmetic circuits.

keywords:
arithmetic circuits; bounded depth circuits; hardness-randomness tradeoffs; identity testing; lower bounds

rawabstract:
In this paper we show that lower bounds for bounded depth arithmetic circuits imply derandomization of polynomial identity testing for bounded depth arithmetic circuits. More formally, if there exists an explicit polynomial $ f(x_1, \ldots {}, x_m) $ that cannot be computed by a depth $d$ arithmetic circuit of small size then there exists an efficient deterministic algorithm to test whether a given depth $ d - 8 $ circuit is identically zero or not (assuming the individual degrees of the tested circuit are not too high). In particular, if we are guaranteed that the circuit computes a multilinear polynomial then we can perform the identity test efficiently. To the best of our knowledge this is the first hardness-randomness tradeoff for bounded depth arithmetic circuits. The above results are obtained using the arithmetic Nisan-Wigderson generator of Impagliazzo and Kabanets together with a new theorem on bounded depth circuits, which is the main technical contribution of our work. This theorem deals with polynomial equations of the form $ P(x_1, \ldots {}, x_n, y) \equiv 0 $ and shows that if $P$ has a circuit of depth $d$ and size $s$ and if the polynomial $ f(x_1, \ldots {}, x_n) $ satisfies $ P(x_1, \ldots {}, x_n, f(x_1, \ldots {}, x_n)) \equiv 0 $ then $f$ has a circuit of depth $ d + 3 $ and size $ O(s \times r + m^r) $, where $m$ is the degree of $f$ and $r$ is the highest degree of the variable $y$ appearing in $P$. In the other direction we observe that the methods of Impagliazzo and Kabanets imply that if we can derandomize polynomial identity testing for bounded depth circuits then NEXP does not have bounded depth arithmetic circuits. That is, either NEXP $ \not \subset $ P/poly or the Permanent is not computable by polynomial size bounded depth arithmetic circuits.

entry:
@InProceedings{Dvir:2008:HRT,
  author =       "Zeev Dvir and Amir Shpilka and Amir Yehudayoff",
  title =        "Hardness-randomness tradeoffs for bounded depth
                 arithmetic circuits",
  crossref =     "ACM:2008:SPA",
  pages =        "741--748",
  year =         "2008",
  DOI =          "https://doi.org/10.1145/1374376.1374482",
  bibdate =      "Fri Jun 20 18:31:53 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we show that lower bounds for bounded
                 depth arithmetic circuits imply derandomization of
                 polynomial identity testing for bounded depth
                 arithmetic circuits. More formally, if there exists an
                 explicit polynomial $ f(x_1, \ldots {}, x_m) $ that
                 cannot be computed by a depth $d$ arithmetic circuit of
                 small size then there exists an efficient deterministic
                 algorithm to test whether a given depth $ d - 8 $
                 circuit is identically zero or not (assuming the
                 individual degrees of the tested circuit are not too
                 high). In particular, if we are guaranteed that the
                 circuit computes a multilinear polynomial then we can
                 perform the identity test efficiently. To the best of
                 our knowledge this is the first hardness-randomness
                 tradeoff for bounded depth arithmetic circuits. The
                 above results are obtained using the arithmetic
                 Nisan-Wigderson generator of Impagliazzo and Kabanets
                 together with a new theorem on bounded depth circuits,
                 which is the main technical contribution of our work.
                 This theorem deals with polynomial equations of the
                 form $ P(x_1, \ldots {}, x_n, y) \equiv 0 $ and shows
                 that if $P$ has a circuit of depth $d$ and size $s$ and
                 if the polynomial $ f(x_1, \ldots {}, x_n) $ satisfies
                 $ P(x_1, \ldots {}, x_n, f(x_1, \ldots {}, x_n)) \equiv
                 0 $ then $f$ has a circuit of depth $ d + 3 $ and size
                 $ O(s \times r + m^r) $, where $m$ is the degree of $f$
                 and $r$ is the highest degree of the variable $y$
                 appearing in $P$. In the other direction we observe
                 that the methods of Impagliazzo and Kabanets imply that
                 if we can derandomize polynomial identity testing for
                 bounded depth circuits then NEXP does not have bounded
                 depth arithmetic circuits. That is, either NEXP $ \not
                 \subset $ P/poly or the Permanent is not computable by
                 polynomial size bounded depth arithmetic circuits.",
  acknowledgement = ack-nhfb,
  keywords =     "arithmetic circuits; bounded depth circuits;
                 hardness-randomness tradeoffs; identity testing; lower
                 bounds",
}


bibtype: article
filename: fparith.bib
label: Edmonson:2008:ISS
author: W. W. Edmonson and M. H. van Emden
title: Interval Semantics for Standard Floating-Point Arithmetic
journal: arXiv.org
pages: 1--10
day: 23
month: oct
monthnumber: 10
year: 2008
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0810.4196
subject: Numerical Analysis (cs.NA); Hardware Architecture (cs.AR)
acknowledgement: ack-nhfb
rawauthor: W. W. Edmonson and M. H. van Emden
rawtitle: Interval Semantics for Standard Floating-Point Arithmetic
abstract:
If the non-zero finite floating-point numbers are interpreted as point intervals, then the effect of rounding can be interpreted as computing one of the bounds of the result according to interval arithmetic. We give an interval interpretation for the signed zeros and infinities, so that the undefined operations 0*inf, inf - inf, inf/inf, and 0/0 become defined. In this way no operation remains that gives rise to an error condition. Mathematically questionable features of the floating-point standard become well-defined sets of reals. Interval semantics provides a basis for the verification of numerical algorithms. We derive the results of the newly defined operations and consider the implications for hardware implementation.

rawabstract:
If the non-zero finite floating-point numbers are interpreted as point intervals, then the effect of rounding can be interpreted as computing one of the bounds of the result according to interval arithmetic. We give an interval interpretation for the signed zeros and infinities, so that the undefined operations 0*inf, inf - inf, inf/inf, and 0/0 become defined. In this way no operation remains that gives rise to an error condition. Mathematically questionable features of the floating-point standard become well-defined sets of reals. Interval semantics provides a basis for the verification of numerical algorithms. We derive the results of the newly defined operations and consider the implications for hardware implementation.

entry:
@Article{Edmonson:2008:ISS,
  author =       "W. W. Edmonson and M. H. van Emden",
  title =        "Interval Semantics for Standard Floating-Point
                 Arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--10",
  day =          "23",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0810.4196",
  abstract =     "If the non-zero finite floating-point numbers are
                 interpreted as point intervals, then the effect of
                 rounding can be interpreted as computing one of the
                 bounds of the result according to interval arithmetic.
                 We give an interval interpretation for the signed zeros
                 and infinities, so that the undefined operations 0*inf,
                 inf - inf, inf/inf, and 0/0 become defined. In this way
                 no operation remains that gives rise to an error
                 condition. Mathematically questionable features of the
                 floating-point standard become well-defined sets of
                 reals. Interval semantics provides a basis for the
                 verification of numerical algorithms. We derive the
                 results of the newly defined operations and consider
                 the implications for hardware implementation.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA); Hardware Architecture
                 (cs.AR)",
}


bibtype: phdthesis
filename: fparith.bib
label: Erle:2008:AHD
author: Mark A. Erle
title: Algorithms and Hardware Designs for Decimal Multiplication
type: Ph.D. Thesis
school: Department of Computer Engineering, Lehigh University
address: Bethlehem, PA, USA
pages: xviii + 221
day: 21
month: nov
monthnumber: 11
year: 2008
bibdate: Tue Mar 01 19:53:02 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.01 19:53:02 ???
URL: http://speleotrove.com/decimal/erle2008-decimal-multipliers-dissertation-duplex.pdf
acknowledgement: ack-nhfb
rawauthor: Mark A. Erle
rawtitle: Algorithms and Hardware Designs for Decimal Multiplication
entry:
@PhdThesis{Erle:2008:AHD,
  author =       "Mark A. Erle",
  title =        "Algorithms and Hardware Designs for Decimal
                 Multiplication",
  type =         "{Ph.D.} Thesis",
  school =       "Department of Computer Engineering, Lehigh
                 University",
  address =      "Bethlehem, PA, USA",
  pages =        "xviii + 221",
  day =          "21",
  month =        nov,
  year =         "2008",
  bibdate =      "Tue Mar 01 19:53:02 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://speleotrove.com/decimal/erle2008-decimal-multipliers-dissertation-duplex.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Gonzalez-Navarro:2008:BID
author: S. Gonzalez-Navarro and C. Tsen and M. Schulte
title: Binary Integer Decimal-based Multiplier for Decimal Floating-Point Arithmetic
crossref: Matthews:2008:CRF
pages: 353--357
year: 2008
DOI: https://doi.org/10.1109/ACSSC.2007.4487228
bibdate: Sat Dec 04 10:25:08 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 10:25:08 ???
acknowledgement: ack-nhfb
rawauthor: S. Gonzalez-Navarro and C. Tsen and M. Schulte
rawtitle: Binary Integer Decimal-based Multiplier for Decimal Floating-Point Arithmetic
abstract:
Demand for decimal floating-point (DFP) arithmetic is increasing because global business, e-commerce, financial applications, and the standards and laws that govern them require it. The IEEE P754 draft standard for floating-point arithmetic specifies formats and operations for DFP numbers. In this paper, we present an IEEE P754-compliant multiplier that operates on values that use the binary encoding of DFP numbers, commonly referred to as the binary integer decimal (BID) encoding. Our BID-based DFP multiplier uses high-speed binary hardware, has variable latency, and is optimized for the common case that the product does not need to be rounded. Our multiplier also uses a novel technique that estimates the number of product digits that needed to be rounded in parallel with the significant multiplication. In this design, a single multiplier is used to multiply the significants and round the product. We believe this the first hardware design of a DFP multiplier for BID-encoded numbers.

rawabstract:
Demand for decimal floating-point (DFP) arithmetic is increasing because global business, e-commerce, financial applications, and the standards and laws that govern them require it. The IEEE P754 draft standard for floating-point arithmetic specifies formats and operations for DFP numbers. In this paper, we present an IEEE P754-compliant multiplier that operates on values that use the binary encoding of DFP numbers, commonly referred to as the binary integer decimal (BID) encoding. Our BID-based DFP multiplier uses high-speed binary hardware, has variable latency, and is optimized for the common case that the product does not need to be rounded. Our multiplier also uses a novel technique that estimates the number of product digits that needed to be rounded in parallel with the significant multiplication. In this design, a single multiplier is used to multiply the significants and round the product. We believe this the first hardware design of a DFP multiplier for BID-encoded numbers.

entry:
@InProceedings{Gonzalez-Navarro:2008:BID,
  author =       "S. Gonzalez-Navarro and C. Tsen and M. Schulte",
  title =        "Binary Integer Decimal-based Multiplier for Decimal
                 Floating-Point Arithmetic",
  crossref =     "Matthews:2008:CRF",
  pages =        "353--357",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ACSSC.2007.4487228",
  bibdate =      "Sat Dec 04 10:25:08 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Demand for decimal floating-point (DFP) arithmetic is
                 increasing because global business, e-commerce,
                 financial applications, and the standards and laws that
                 govern them require it. The IEEE P754 draft standard
                 for floating-point arithmetic specifies formats and
                 operations for DFP numbers. In this paper, we present
                 an IEEE P754-compliant multiplier that operates on
                 values that use the binary encoding of DFP numbers,
                 commonly referred to as the binary integer decimal
                 (BID) encoding. Our BID-based DFP multiplier uses
                 high-speed binary hardware, has variable latency, and
                 is optimized for the common case that the product does
                 not need to be rounded. Our multiplier also uses a
                 novel technique that estimates the number of product
                 digits that needed to be rounded in parallel with the
                 significant multiplication. In this design, a single
                 multiplier is used to multiply the significants and
                 round the product. We believe this the first hardware
                 design of a DFP multiplier for BID-encoded numbers.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Graillat:2008:ASZ
author: Stef Graillat
title: Accurate simple zeros of polynomials in floating point arithmetic
journal: j-COMPUT-MATH-APPL
volume: 56
number: 4
pages: 1114--1120
month: aug
monthnumber: 8
year: 2008
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:50:16 MST 2017
bibtimestamp: 2017.03.01 21:50:16 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122108001120
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Stef Graillat
rawtitle: Accurate simple zeros of polynomials in floating point arithmetic
entry:
@Article{Graillat:2008:ASZ,
  author =       "Stef Graillat",
  title =        "Accurate simple zeros of polynomials in floating point
                 arithmetic",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "56",
  number =       "4",
  pages =        "1114--1120",
  month =        aug,
  year =         "2008",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:50:16 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122108001120",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: book
filename: fparith.bib
label: Hardy:2008:ITN
title: An introduction to the theory of numbers
publisher: pub-OXFORD
address: pub-OXFORD:adr
edition: Sixth
pages: xxi + 621
year: 2008
LCCN: QA241 .H28 2008
bibdate: Thu Nov 18 09:18:59 MST 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; library.ox.ac.uk:210/ADVANCE
bibtimestamp: 2010.11.18 09:18:59 MST
series: Oxford mathematics
remark: Previous (fifth) edition 1979.
subject: Number theory
acknowledgement: ack-nhfb
authordates: G. H. Hardy (1877--1947)
rawtitle: An introduction to the theory of numbers
author:
G. H. (Godfrey Harold) Hardy and Edward Maitland Wright and D. R. Heath-Brown and Joseph H. Silverman

ISBN:
0-19-921985-0 (hardcover), 0-19-921986-9 (paperback) OR 0199219850 (hardcover), 0199219869 (paperback)

ISBN13:
978-0-19-921985-8 (hardcover), 978-0-19-921986-5 (paperback) OR 9780199219858 (hardcover), 9780199219865 (paperback)

rawauthor:
G. H. (Godfrey Harold) Hardy and Edward Maitland Wright and D. R. Heath-Brown and Joseph H. Silverman

entry:
@Book{Hardy:2008:ITN,
  author =       "G. H. (Godfrey Harold) Hardy and Edward Maitland
                 Wright and D. R. Heath-Brown and Joseph H. Silverman",
  title =        "An introduction to the theory of numbers",
  publisher =    pub-OXFORD,
  address =      pub-OXFORD:adr,
  edition =      "Sixth",
  pages =        "xxi + 621",
  year =         "2008",
  ISBN =         "0-19-921985-0 (hardcover), 0-19-921986-9 (paperback)",
  ISBN-13 =      "978-0-19-921985-8 (hardcover), 978-0-19-921986-5
                 (paperback)",
  LCCN =         "QA241 .H28 2008",
  bibdate =      "Thu Nov 18 09:18:59 MST 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 library.ox.ac.uk:210/ADVANCE",
  series =       "Oxford mathematics",
  acknowledgement = ack-nhfb,
  author-dates = "G. H. Hardy (1877--1947)",
  remark =       "Previous (fifth) edition 1979.",
  subject =      "Number theory",
}


bibtype: article
filename: fparith.bib
label: Homma:2008:SAD
author: N. Homma and T. Aoki and T. Higuchi
title: A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 12
pages: 1633--1646
month: dec
monthnumber: 12
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.106
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:44 MDT 2011
bibtimestamp: 2011.07.04 12:17:44 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4569835
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: N. Homma and T. Aoki and T. Higuchi
rawtitle: A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams
entry:
@Article{Homma:2008:SAD,
  author =       "N. Homma and T. Aoki and T. Higuchi",
  title =        "A Systematic Approach for Designing Redundant
                 Arithmetic Adders Based on Counter Tree Diagrams",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "12",
  pages =        "1633--1646",
  month =        dec,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.106",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4569835",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Hsiao:2008:EDF
author: Shen-Fu Hsiao and Hsin-Mau Lee and Yen-Chun Cheng and Ming-Yu Tsai
booktitle: APCCAS 2008 --- 2008 IEEE Asia Pacific Conference on Circuits and Systems
title: Efficient designs of floating-point CORDIC rotation and vectoring operations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1422--1425
year: 2008
DOI: https://doi.org/10.1109/APCCAS.2008.4746297
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Shen-Fu Hsiao and Hsin-Mau Lee and Yen-Chun Cheng and Ming-Yu Tsai
rawbooktitle: {APCCAS 2008 --- 2008 IEEE Asia Pacific Conference on Circuits and Systems}
rawtitle: Efficient designs of floating-point {CORDIC} rotation and vectoring operations
keywords:
Computer architecture; Computer science; Costs; Delay; Design engineering; Fixed-point arithmetic; Floating-point arithmetic; Graphics; High performance computing; Process design

entry:
@InProceedings{Hsiao:2008:EDF,
  author =       "Shen-Fu Hsiao and Hsin-Mau Lee and Yen-Chun Cheng and
                 Ming-Yu Tsai",
  booktitle =    "{APCCAS 2008 --- 2008 IEEE Asia Pacific Conference on
                 Circuits and Systems}",
  title =        "Efficient designs of floating-point {CORDIC} rotation
                 and vectoring operations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1422--1425",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/APCCAS.2008.4746297",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture; Computer science; Costs; Delay;
                 Design engineering; Fixed-point arithmetic;
                 Floating-point arithmetic; Graphics; High performance
                 computing; Process design",
}


bibtype: article
filename: fparith.bib
label: Jager:2008:DAD
author: Hendrik Jager and Pierre Liardet
volume: 91
number: 2
pages: 181--197
day: 20
month: jun
monthnumber: 6
year: 2008
DOI: https://doi.org/10.1016/S1385-7258(88)80026-X
ISSN: 1385-7258 (print), 1878-5972 (electronic) OR 13857258 (print), 18785972 (electronic)
bibdate: Tue Nov 22 11:28:19 MST 2011
bibtimestamp: 2011.11.22 11:28:19 MST
URL: http://www.sciencedirect.com/science/article/pii/S138572588880026X
fjournal: Indagationes Mathematicae (Proceedings)
keywords: Benford's Law
language: French
acknowledgement: ack-nhfb
rawauthor: Hendrik Jager and Pierre Liardet
title:
Distributions arithmetiques des denominateurs de convergents de fractions continues. (French) [Arithmetic distributions of the denominators of continued fractions]

journal:
Proceedings of the Koninklijke Nederlandse Akademie van Wetenschappen, Series A, Indagationes mathematicae

bibsource:
http://www.sciencedirect.com/; https://www.math.utah.edu/pub/tex/bib/benfords-law.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Distributions arithm{\'e}tiques des d{\'e}nominateurs de convergents de fractions continues. ({French}) [Arithmetic distributions of the denominators of continued fractions]

entry:
@Article{Jager:2008:DAD,
  author =       "Hendrik Jager and Pierre Liardet",
  title =        "Distributions arithm{\'e}tiques des d{\'e}nominateurs
                 de convergents de fractions continues. ({French})
                 [Arithmetic distributions of the denominators of
                 continued fractions]",
  journal =      "Proceedings of the Koninklijke Nederlandse Akademie
                 van Wetenschappen, Series A, Indagationes
                 mathematicae",
  volume =       "91",
  number =       "2",
  pages =        "181--197",
  day =          "20",
  month =        jun,
  year =         "2008",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/S1385-7258(88)80026-X",
  ISSN =         "1385-7258 (print), 1878-5972 (electronic)",
  bibdate =      "Tue Nov 22 11:28:19 MST 2011",
  bibsource =    "http://www.sciencedirect.com/;
                 https://www.math.utah.edu/pub/tex/bib/benfords-law.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S138572588880026X",
  acknowledgement = ack-nhfb,
  fjournal =     "Indagationes Mathematicae (Proceedings)",
  keywords =     "Benford's Law",
  language =     "French",
  xxjournal =    "Indagationes Mathematicae (Proceedings)",
}


bibtype: article
filename: fparith.bib
label: Jezequel:2008:CLE
author: Fabienne Jezequel and Jean-Marie Chesneaux
title: CADNA: a library for estimating round-off error propagation
journal: j-COMP-PHYS-COMM
volume: 178
number: 12
pages: 933--955
day: 15
month: jun
monthnumber: 6
year: 2008
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2008.02.003
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Mon Feb 13 23:42:31 MST 2012
bibtimestamp: 2012.02.13 23:42:31 MST
URL: http://www.sciencedirect.com/science/article/pii/S0010465508000775
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Fabienne J{\'e}z{\'e}quel and Jean-Marie Chesneaux
rawtitle: {CADNA}: a library for estimating round-off error propagation
bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Jezequel:2008:CLE,
  author =       "Fabienne J{\'e}z{\'e}quel and Jean-Marie Chesneaux",
  title =        "{CADNA}: a library for estimating round-off error
                 propagation",
  journal =      j-COMP-PHYS-COMM,
  volume =       "178",
  number =       "12",
  pages =        "933--955",
  day =          "15",
  month =        jun,
  year =         "2008",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2008.02.003",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Mon Feb 13 23:42:31 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465508000775",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: article
filename: fparith.bib
label: Jimeno:2008:BBA
author: Antonio Jimeno and Higinio Mora and Jose L. Sanchez and Francisco Pujol
title: A BCD-based architecture for fast coordinate rotation
journal: j-J-SYST-ARCH
volume: 54
number: 8
pages: 829--840
month: aug
monthnumber: 8
year: 2008
CODEN: JSARFB
DOI: https://doi.org/10.1016/j.sysarc.2008.02.001
ISSN: 1383-7621 (print), 1873-6165 (electronic) OR 13837621 (print), 18736165 (electronic)
ISSNL: 1383-7621 OR 13837621
bibdate: Thu Aug 07 18:04:43 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:04:43 ???
fjournal: Journal of Systems Architecture: the EUROMICRO Journal
keywords: binary coded decimals; computer performance; CORDIC; decimal arithmetic; digital arithmetic
acknowledgement: ack-nhfb
rawauthor: Antonio Jimeno and Higinio Mora and Jose L. Sanchez and Francisco Pujol
rawtitle: A {BCD}-based architecture for fast coordinate rotation
abstract:
Although radix 10 based arithmetic has been gaining renewed importance over the last few years, decimal systems are not efficient enough and techniques are still under development. In this paper, an improvement of the CORDIC (coordinate rotation digital computer) method for decimal representation is proposed and applied to produce fast rotations. The algorithm uses BCD operands as inputs, combining the advantages of both decimal and binary systems. The result is a reduction of 50% in the number of iterations if compared with the original Decimal CORDIC method. Finally, we present a hardware architecture useful to produce BCD coordinates rotations accurately and fast, and different experiments demonstrating the advantages of the new method are shown. A reduction of 75% in a single stage delay is obtained, whereas the circuit area just increases in about 5%.

rawabstract:
Although radix 10 based arithmetic has been gaining renewed importance over the last few years, decimal systems are not efficient enough and techniques are still under development. In this paper, an improvement of the CORDIC (coordinate rotation digital computer) method for decimal representation is proposed and applied to produce fast rotations. The algorithm uses BCD operands as inputs, combining the advantages of both decimal and binary systems. The result is a reduction of 50\% in the number of iterations if compared with the original Decimal CORDIC method. Finally, we present a hardware architecture useful to produce BCD coordinates rotations accurately and fast, and different experiments demonstrating the advantages of the new method are shown. A reduction of 75\% in a single stage delay is obtained, whereas the circuit area just increases in about 5\%.

entry:
@Article{Jimeno:2008:BBA,
  author =       "Antonio Jimeno and Higinio Mora and Jose L. Sanchez
                 and Francisco Pujol",
  title =        "A {BCD}-based architecture for fast coordinate
                 rotation",
  journal =      j-J-SYST-ARCH,
  volume =       "54",
  number =       "8",
  pages =        "829--840",
  month =        aug,
  year =         "2008",
  CODEN =        "JSARFB",
  DOI =          "https://doi.org/10.1016/j.sysarc.2008.02.001",
  ISSN =         "1383-7621 (print), 1873-6165 (electronic)",
  ISSN-L =       "1383-7621",
  bibdate =      "Thu Aug 07 18:04:43 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Although radix 10 based arithmetic has been gaining
                 renewed importance over the last few years, decimal
                 systems are not efficient enough and techniques are
                 still under development. In this paper, an improvement
                 of the CORDIC (coordinate rotation digital computer)
                 method for decimal representation is proposed and
                 applied to produce fast rotations. The algorithm uses
                 BCD operands as inputs, combining the advantages of
                 both decimal and binary systems. The result is a
                 reduction of 50\% in the number of iterations if
                 compared with the original Decimal CORDIC method.
                 Finally, we present a hardware architecture useful to
                 produce BCD coordinates rotations accurately and fast,
                 and different experiments demonstrating the advantages
                 of the new method are shown. A reduction of 75\% in a
                 single stage delay is obtained, whereas the circuit
                 area just increases in about 5\%.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Systems Architecture: the EUROMICRO
                 Journal",
  keywords =     "binary coded decimals; computer performance; CORDIC;
                 decimal arithmetic; digital arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Kahan:2008:BFU
author: William Kahan
title: Back to the Future of Undebuggable Floating-Point Computation in Science and Engineering
pages: 829--840
day: 30
month: mar
monthnumber: 3
year: 2008
bibdate: Mon Mar 31 16:50:19 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.03.31 16:50:19 ???
URL: http://math.berkeley.edu/bascd08; http://www.eecs.berkeley.edu/~wkahan/BASCD08K.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: William Kahan
rawtitle: Back to the Future of Undebuggable Floating-Point Computation in Science and Engineering
note:
The Bay Area Scientific Computing Day, BASCD08, honoring Profs. Kahan and Parlett, 29--30 March, 2008.

abstract:
When I began to program an electronic computer in 1953, von Neumann was still disparaging floating-point computation, which was generally deemed impervious to error-analysis. Occasional anomalous results were expected. Often they were attributed wrongly to ``Ill-Condition''. Putting one's data through several numerical methods some of whose results might agree was a prudent policy. Those days are back. Their challenges will be illustrated by a program like some used by structural engineers for forty years. To cope, we need debugging aids like those in Section 14 of my web page's tt Mindless.pdf. Help can come only from the designers of hardware, compilers and software development systems after they are persuaded that the demand for such aids is commercially significant.

rawabstract:
When I began to program an electronic computer in 1953, von Neumann was still disparaging floating-point computation, which was generally deemed impervious to error-analysis. Occasional anomalous results were expected. Often they were attributed wrongly to ``Ill-Condition''. Putting one's data through several numerical methods some of whose results might agree was a prudent policy. Those days are back. Their challenges will be illustrated by a program like some used by structural engineers for forty years. To cope, we need debugging aids like those in Section 14 of my web page's {\tt Mindless.pdf}. Help can come only from the designers of hardware, compilers and software development systems after they are persuaded that the demand for such aids is commercially significant.

rawnote:
The Bay Area Scientific Computing Day, BASCD08, honoring Profs. Kahan and Parlett, 29--30 March, 2008.

entry:
@Misc{Kahan:2008:BFU,
  author =       "William Kahan",
  title =        "Back to the Future of Undebuggable Floating-Point
                 Computation in Science and Engineering",
  howpublished = "Web document",
  day =          "30",
  month =        mar,
  year =         "2008",
  bibdate =      "Mon Mar 31 16:50:19 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "The Bay Area Scientific Computing Day, BASCD08,
                 honoring Profs. Kahan and Parlett, 29--30 March,
                 2008.",
  URL =          "http://math.berkeley.edu/bascd08;
                 http://www.eecs.berkeley.edu/~wkahan/BASCD08K.pdf",
  abstract =     "When I began to program an electronic computer in
                 1953, von Neumann was still disparaging floating-point
                 computation, which was generally deemed impervious to
                 error-analysis. Occasional anomalous results were
                 expected. Often they were attributed wrongly to
                 ``Ill-Condition''. Putting one's data through several
                 numerical methods some of whose results might agree was
                 a prudent policy. Those days are back. Their challenges
                 will be illustrated by a program like some used by
                 structural engineers for forty years. To cope, we need
                 debugging aids like those in Section 14 of my web
                 page's {\tt Mindless.pdf}. Help can come only from the
                 designers of hardware, compilers and software
                 development systems after they are persuaded that the
                 demand for such aids is commercially significant.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kaihara:2008:BMM
author: M. E. Kaihara and N. Takagi
title: Bipartite Modular Multiplication Method
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 2
pages: 157--164
month: feb
monthnumber: 2
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70793
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:40 MDT 2011
bibtimestamp: 2011.07.04 12:17:40 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358245
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. E. Kaihara and N. Takagi
rawtitle: Bipartite Modular Multiplication Method
entry:
@Article{Kaihara:2008:BMM,
  author =       "M. E. Kaihara and N. Takagi",
  title =        "Bipartite Modular Multiplication Method",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "2",
  pages =        "157--164",
  month =        feb,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70793",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358245",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Khalid:2008:NRE
author: M. S. Khalid and M. R. Amin and M. M. Hossain and M. Anwer
editor: IEEE
title: Numerical round-off error in cellular phone services billing system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2008
DOI: https://doi.org/10.1109/ICCITECHN.2007.4579417
ISBN: 1-4244-1550-0, 1-4244-1551-9 OR 1424415500, 1424415519
ISBN13: 978-1-4244-1550-2, 978-1-4244-1551-9 OR 9781424415502, 9781424415519
LCCN: QA75.5 .I574 2007
bibdate: Wed Jul 06 19:14:16 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.07.06 19:14:16 ???
acknowledgement: ack-nhfb
bookpages: 534 + 7
rawauthor: M. S. Khalid and M. R. Amin and M. M. Hossain and M. Anwer
raweditor: {IEEE}
rawtitle: Numerical round-off error in cellular phone services billing system
booktitle:
Proceedings of 10th International Conference on Computer and Information Technology (ICCIT 2007), 27-29, December 2007, United International University, Dhanmondi, Dhaka-1209, Bangladesh

abstract:
Cellular phone services billing for per minute tariff plan and 1-second pulse involve floating point division and multiplication operation to calculate per call bill. Monthly customer billing involves addition operations on per call bills, which are floating point numbers. Round-off errors occur due to floating point numberspsila computer representation limitations and for storing limited significant figures during billing. The study analyzed post-paid itemized bills of a cellular phone service operator in Bangladesh and identified that accumulated round-off error for active post-paid subscribers is significantly high for subscriber group of large number. The research recommends a per second tariff plan to completely eliminate round-off error which also reduces floating point number operations.

rawabstract:
Cellular phone services billing for per minute tariff plan and 1-second pulse involve floating point division and multiplication operation to calculate per call bill. Monthly customer billing involves addition operations on per call bills, which are floating point numbers. Round-off errors occur due to floating point numberspsila computer representation limitations and for storing limited significant figures during billing. The study analyzed post-paid itemized bills of a cellular phone service operator in Bangladesh and identified that accumulated round-off error for active post-paid subscribers is significantly high for subscriber group of large number. The research recommends a per second tariff plan to completely eliminate round-off error which also reduces floating point number operations.

rawbooktitle:
{Proceedings of 10th International Conference on Computer and Information Technology (ICCIT 2007), 27-29, December 2007, United International University, Dhanmondi, Dhaka-1209, Bangladesh}

entry:
@InProceedings{Khalid:2008:NRE,
  author =       "M. S. Khalid and M. R. Amin and M. M. Hossain and M.
                 Anwer",
  editor =       "{IEEE}",
  booktitle =    "{Proceedings of 10th International Conference on
                 Computer and Information Technology (ICCIT 2007),
                 27-29, December 2007, United International University,
                 Dhanmondi, Dhaka-1209, Bangladesh}",
  title =        "Numerical round-off error in cellular phone services
                 billing system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "534 + 7",
  pages =        "1--5",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ICCITECHN.2007.4579417",
  ISBN =         "1-4244-1550-0, 1-4244-1551-9",
  ISBN-13 =      "978-1-4244-1550-2, 978-1-4244-1551-9",
  LCCN =         "QA75.5 .I574 2007",
  bibdate =      "Wed Jul 06 19:14:16 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Cellular phone services billing for per minute tariff
                 plan and 1-second pulse involve floating point division
                 and multiplication operation to calculate per call
                 bill. Monthly customer billing involves addition
                 operations on per call bills, which are floating point
                 numbers. Round-off errors occur due to floating point
                 numberspsila computer representation limitations and
                 for storing limited significant figures during billing.
                 The study analyzed post-paid itemized bills of a
                 cellular phone service operator in Bangladesh and
                 identified that accumulated round-off error for active
                 post-paid subscribers is significantly high for
                 subscriber group of large number. The research
                 recommends a per second tariff plan to completely
                 eliminate round-off error which also reduces floating
                 point number operations.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kong:2008:RMI
author: I. Kong and E. E. Swartzlander, Jr.
editor: Michael B. Matthews
title: A Rounding Method with Improved Error Tolerance for Division by Convergence
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1814--1818
year: 2008
DOI: https://doi.org/10.1109/ACSSC.2008.5074740
ISBN: 1-4244-2941-2 OR 1424429412
ISBN13: 978-1-4244-2941-7 OR 9781424429417
ISSN: 1058-6393 OR 10586393
ISSNL: 1058-6393 OR 10586393
LCCN: TK7801 .A83 2008
bibdate: Sun Dec 10 14:05:54 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 14:05:54 ???
acknowledgement: ack-nhfb
rawauthor: I. Kong and E. E. {Swartzlander, Jr.}
raweditor: Michael B. Matthews
rawtitle: A Rounding Method with Improved Error Tolerance for Division by Convergence
booktitle:
42nd Asilomar Conference on Signals, Systems and Computers: October 26--29, 2008, Pacific Grove, California

abstract:
A new rounding method for division by convergence is presented. It allows twice the error tolerance of current methods, so it allows the multiplier of a 3-iteration Goldschmidt divider to be implemented using only 3 extra bits. The new rounding method applies special truncation methods at the final iteration step, and it requires a minor modification in rounding constants of the multiplier. It has been verified using a SystemC model of the Goldschmidt divider supporting variable precision. The verification consists of two parts: the maximum error of approximate quotients and the rounding result correctness. The maximum error of approximate quotients is checked by analysis and via simulation. The final rounding results are checked with both random double precision floating-point significands and exhaustive 17-bit precision test vectors

rawabstract:
A new rounding method for division by convergence is presented. It allows twice the error tolerance of current methods, so it allows the multiplier of a 3-iteration Goldschmidt divider to be implemented using only 3 extra bits. The new rounding method applies special truncation methods at the final iteration step, and it requires a minor modification in rounding constants of the multiplier. It has been verified using a SystemC model of the Goldschmidt divider supporting variable precision. The verification consists of two parts: the maximum error of approximate quotients and the rounding result correctness. The maximum error of approximate quotients is checked by analysis and via simulation. The final rounding results are checked with both random double precision floating-point significands and exhaustive 17-bit precision test vectors

rawbooktitle:
42nd Asilomar Conference on Signals, Systems and Computers: {October 26--29, 2008, Pacific Grove, California}

entry:
@InProceedings{Kong:2008:RMI,
  author =       "I. Kong and E. E. {Swartzlander, Jr.}",
  editor =       "Michael B. Matthews",
  booktitle =    "42nd Asilomar Conference on Signals, Systems and
                 Computers: {October 26--29, 2008, Pacific Grove,
                 California}",
  title =        "A Rounding Method with Improved Error Tolerance for
                 Division by Convergence",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1814--1818",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ACSSC.2008.5074740",
  ISBN =         "1-4244-2941-2",
  ISBN-13 =      "978-1-4244-2941-7",
  ISSN =         "1058-6393",
  ISSN-L =       "1058-6393",
  LCCN =         "TK7801 .A83 2008",
  bibdate =      "Sun Dec 10 14:05:54 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A new rounding method for division by convergence is
                 presented. It allows twice the error tolerance of
                 current methods, so it allows the multiplier of a
                 3-iteration Goldschmidt divider to be implemented using
                 only 3 extra bits. The new rounding method applies
                 special truncation methods at the final iteration step,
                 and it requires a minor modification in rounding
                 constants of the multiplier. It has been verified using
                 a SystemC model of the Goldschmidt divider supporting
                 variable precision. The verification consists of two
                 parts: the maximum error of approximate quotients and
                 the rounding result correctness. The maximum error of
                 approximate quotients is checked by analysis and via
                 simulation. The final rounding results are checked with
                 both random double precision floating-point
                 significands and exhaustive 17-bit precision test
                 vectors",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Kulisch:2008:CAV
author: Ulrich Kulisch
title: Computer Arithmetic and Validity --- Theory, Implementation, and Applications
publisher: pub-GRUYTER
address: pub-GRUYTER:adr
pages: 410 (est.)
year: 2008
ISBN: 3-11-020318-9 (hardcover) OR 3110203189 (hardcover)
ISBN13: 978-3-11-020318-9 (hardcover) OR 9783110203189 (hardcover)
ISSN: 0179-0986 OR 01790986
bibdate: Wed Jun 11 14:53:52 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.11 14:53:52 ???
series: De Gruyter Studies in Mathematics
acknowledgement: ack-nhfb
rawauthor: Ulrich Kulisch
rawtitle: Computer Arithmetic and Validity --- Theory, Implementation, and Applications
abstract:
A New Approach to Scientific Computation is a collection of papers delivered at a symposium held at the IBM Thomas J. Watson Research Center on August 3, 1982. The symposium provided a forum for reviewing various aspects of an approach to scientific computation based on a systematic theory of computer arithmetic. Computer demonstration packages for standard problems of numerical mathematics are considered. Comprised of 12 chapters, this volume begins by summarizing an extensive research activity in scientific computation as well as the experience gained through various implementations ldots 

rawabstract:
A New Approach to Scientific Computation is a collection of papers delivered at a symposium held at the IBM Thomas J. Watson Research Center on August 3, 1982. The symposium provided a forum for reviewing various aspects of an approach to scientific computation based on a systematic theory of computer arithmetic. Computer demonstration packages for standard problems of numerical mathematics are considered. Comprised of 12 chapters, this volume begins by summarizing an extensive research activity in scientific computation as well as the experience gained through various implementations \ldots{}

entry:
@Book{Kulisch:2008:CAV,
  author =       "Ulrich Kulisch",
  title =        "Computer Arithmetic and Validity --- Theory,
                 Implementation, and Applications",
  publisher =    pub-GRUYTER,
  address =      pub-GRUYTER:adr,
  pages =        "410 (est.)",
  year =         "2008",
  ISBN =         "3-11-020318-9 (hardcover)",
  ISBN-13 =      "978-3-11-020318-9 (hardcover)",
  ISSN =         "0179-0986",
  LCCN =         "????",
  bibdate =      "Wed Jun 11 14:53:52 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$108.00",
  series =       "De Gruyter Studies in Mathematics",
  abstract =     "A New Approach to Scientific Computation is a
                 collection of papers delivered at a symposium held at
                 the IBM Thomas J. Watson Research Center on August 3,
                 1982. The symposium provided a forum for reviewing
                 various aspects of an approach to scientific
                 computation based on a systematic theory of computer
                 arithmetic. Computer demonstration packages for
                 standard problems of numerical mathematics are
                 considered. Comprised of 12 chapters, this volume
                 begins by summarizing an extensive research activity in
                 scientific computation as well as the experience gained
                 through various implementations \ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: phdthesis
filename: fparith.bib
label: Lauter:2008:ACF
author: Christoph Quirin Lauter
type: Ph.D. dissertation
school: Ecole Normale Superieure de Lyon
address: Lyon, France
pages: xiii + 197 + 3
month: oct
monthnumber: 10
year: 2008
bibdate: Fri Dec 08 10:03:47 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 10:03:47 ???
URL: https://www.christoph-lauter.org/these.pdf
acknowledgement: ack-nhfb
advisor: Florent de Dinechin and Jean-Michel Muller
rawauthor: Christoph Quirin Lauter
title:
Arrondi correct de fonctions mathematiques --- Fonctions univariees et bivariees, certification et automatisation. (French) [Correct rounding of mathematical functions --- univariate and bivariate functions, certification and automation]

rawtitle:
Arrondi correct de fonctions math{\'e}matiques --- Fonctions univari{\'e}es et bivari{\'e}es, certification et automatisation. ({French}) [{Correct} rounding of mathematical functions --- univariate and bivariate functions, certification and automation]

entry:
@PhdThesis{Lauter:2008:ACF,
  author =       "Christoph Quirin Lauter",
  title =        "Arrondi correct de fonctions math{\'e}matiques ---
                 Fonctions univari{\'e}es et bivari{\'e}es,
                 certification et automatisation. ({French}) [{Correct}
                 rounding of mathematical functions --- univariate and
                 bivariate functions, certification and automation]",
  type =         "{Ph.D.} dissertation",
  school =       "{\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "Lyon, France",
  pages =        "xiii + 197 + 3",
  month =        oct,
  year =         "2008",
  bibdate =      "Fri Dec 08 10:03:47 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.christoph-lauter.org/these.pdf",
  acknowledgement = ack-nhfb,
  advisor =      "Florent de Dinechin and Jean-Michel Muller",
}


bibtype: article
filename: fparith.bib
label: Lefevre:2008:WCE
author: Vincent Lefevre and Damien Stehle and Paul Zimmermann
title: Worst Cases for the Exponential Function in the IEEE 754r decimal64 Format
journal: j-LECT-NOTES-COMP-SCI
volume: 5045
pages: 114--126
year: 2008
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-540-85521-7_7
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Thu Oct 1 11:29:36 MDT 2015
bibtimestamp: 2015.10.01 11:29:36 MDT
URL: http://link.springer.com/content/pdf/10.1007/978-3-540-85521-7_7.pdf
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-540-85521-7
bookURL: http://www.springerlink.com/content/978-3-540-85521-7
journalURL: http://link.springer.com/bookseries/558
rawauthor: Vincent Lef{\`e}vre and Damien Stehl{\'e} and Paul Zimmermann
rawtitle: Worst Cases for the Exponential Function in the {IEEE 754r decimal64} Format
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2008a.bib

remark:
From the abstract: ``the worst case for $ |x| geq 3 times 10^-11 $ is exp(9.407822313572878e-2) = 1.09864568206633850000000000000000278.''

entry:
@Article{Lefevre:2008:WCE,
  author =       "Vincent Lef{\`e}vre and Damien Stehl{\'e} and Paul
                 Zimmermann",
  title =        "Worst Cases for the Exponential Function in the {IEEE
                 754r decimal64} Format",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "5045",
  pages =        "114--126",
  year =         "2008",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-540-85521-7_7",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Thu Oct 1 11:29:36 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2008a.bib",
  URL =          "http://link.springer.com/content/pdf/10.1007/978-3-540-85521-7_7.pdf",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-540-85521-7",
  book-URL =     "http://www.springerlink.com/content/978-3-540-85521-7",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  remark =       "From the abstract: ``the worst case for $ |x| \geq 3
                 \times 10^{-11} $ is exp(9.407822313572878e-2) =
                 1.09864568206633850000000000000000278.''",
}


bibtype: article
filename: fparith.bib
label: Li:2008:MLB
author: Xin Li and Marc Moreno Maza and Raqeeb Rasheed and Eric Schost
title: The tt modpn library: bringing fast polynomial arithmetic into MAPLE
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 42
number: 3
pages: 172--174
month: sep
monthnumber: 9
year: 2008
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Fri Feb 13 18:17:36 MST 2009
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.02.13 18:17:36 MST
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: Xin Li and Marc Moreno Maza and Raqeeb Rasheed and {\'E}ric Schost
rawtitle: The {\tt modpn} library: bringing fast polynomial arithmetic into {MAPLE}
entry:
@Article{Li:2008:MLB,
  author =       "Xin Li and Marc Moreno Maza and Raqeeb Rasheed and
                 {\'E}ric Schost",
  title =        "The {\tt modpn} library: bringing fast polynomial
                 arithmetic into {MAPLE}",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "42",
  number =       "3",
  pages =        "172--174",
  month =        sep,
  year =         "2008",
  CODEN =        "????",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Fri Feb 13 18:17:36 MST 2009",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Liu:2008:FIM
author: J. Liu and B. Weaver and Y. Zakharov
title: FPGA implementation of multiplication-free complex division
journal: j-ELECT-LETTERS
volume: 44
number: 2
pages: 5--96
day: 17
month: jan
monthnumber: 1
year: 2008
CODEN: ELLEAK
DOI: https://doi.org/10.1049/el:20082567
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Fri Dec 03 14:53:57 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.03 14:53:57 ???
fjournal: Electronics Letters
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: J. Liu and B. Weaver and Y. Zakharov
rawtitle: {FPGA} implementation of multiplication-free complex division
abstract:
The FPGA implementation of a new complex division algorithm is described. It is based on the dichotomous co-ordinate descent method and requires only bit-shift and addition operations. Consequently, the footprint of the new complex division core is remarkably small.

rawabstract:
The FPGA implementation of a new complex division algorithm is described. It is based on the dichotomous co-ordinate descent method and requires only bit-shift and addition operations. Consequently, the footprint of the new complex division core is remarkably small.

entry:
@Article{Liu:2008:FIM,
  author =       "J. Liu and B. Weaver and Y. Zakharov",
  title =        "{FPGA} implementation of multiplication-free complex
                 division",
  journal =      j-ELECT-LETTERS,
  volume =       "44",
  number =       "2",
  pages =        "5--96",
  day =          "17",
  month =        jan,
  year =         "2008",
  CODEN =        "ELLEAK",
  DOI =          "https://doi.org/10.1049/el:20082567",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Fri Dec 03 14:53:57 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The FPGA implementation of a new complex division
                 algorithm is described. It is based on the dichotomous
                 co-ordinate descent method and requires only bit-shift
                 and addition operations. Consequently, the footprint of
                 the new complex division core is remarkably small.",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
  keyword =      "FPGA; bit-shift; dichotomous coordinate descent
                 method; multiplication-free complex division; field
                 programmable gate arrays; signal processing",
}


bibtype: misc
filename: fparith.bib
label: Melquiond:2008:DRA
author: Guillaume Melquiond and Sylvain Pion
title: Directed Rounding Arithmetic Operations
pages: 5--96
day: 05
month: dec
monthnumber: 12
year: 2008
bibdate: Mon Dec 08 14:57:52 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.08 14:57:52 ???
note: ISO WG21 Document N2811=08-0321, posted to the stds-1788 mailing list on 8-Dec-2008.
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: Guillaume Melquiond and Sylvain Pion
rawnote: ISO WG21 Document N2811=08-0321, posted to the stds-1788 mailing list on 8-Dec-2008.
rawtitle: Directed Rounding Arithmetic Operations
entry:
@Misc{Melquiond:2008:DRA,
  author =       "Guillaume Melquiond and Sylvain Pion",
  title =        "Directed Rounding Arithmetic Operations",
  howpublished = "Web document",
  day =          "05",
  month =        dec,
  year =         "2008",
  bibdate =      "Mon Dec 08 14:57:52 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "ISO WG21 Document N2811=08-0321, posted to the
                 stds-1788 mailing list on 8-Dec-2008.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Monniaux:2008:PVF
author: David Monniaux
title: The pitfalls of verifying floating-point computations
journal: j-TOPLAS
volume: 30
number: 3
pages: 12:1--12:41
month: may
monthnumber: 5
year: 2008
CODEN: ATPSDT
DOI: https://doi.org/10.1145/1353445.1353446
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Wed Jun 11 19:14:53 MDT 2008
bibtimestamp: 2008.06.11 19:14:53 MDT
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
articleno: 12
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawauthor: David Monniaux
rawtitle: The pitfalls of verifying floating-point computations
bibsource:
http://www.acm.org/pubs/contents/journals/toplas/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Current critical systems often use a lot of floating-point computations, and thus the testing or static analysis of programs containing floating-point operators has become a priority. However, correctly defining the semantics of common implementations of floating-point is tricky, because semantics may change according to many factors beyond source-code level, such as choices made by compilers. We here give concrete examples of problems that can appear and solutions for implementing in analysis software.

rawabstract:
Current critical systems often use a lot of floating-point computations, and thus the testing or static analysis of programs containing floating-point operators has become a priority. However, correctly defining the semantics of common implementations of floating-point is tricky, because semantics may change according to many factors beyond source-code level, such as choices made by compilers. We here give concrete examples of problems that can appear and solutions for implementing in analysis software.

entry:
@Article{Monniaux:2008:PVF,
  author =       "David Monniaux",
  title =        "The pitfalls of verifying floating-point
                 computations",
  journal =      j-TOPLAS,
  volume =       "30",
  number =       "3",
  pages =        "12:1--12:41",
  month =        may,
  year =         "2008",
  CODEN =        "ATPSDT",
  DOI =          "https://doi.org/10.1145/1353445.1353446",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Wed Jun 11 19:14:53 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toplas/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Current critical systems often use a lot of
                 floating-point computations, and thus the testing or
                 static analysis of programs containing floating-point
                 operators has become a priority. However, correctly
                 defining the semantics of common implementations of
                 floating-point is tricky, because semantics may change
                 according to many factors beyond source-code level,
                 such as choices made by compilers. We here give
                 concrete examples of problems that can appear and
                 solutions for implementing in analysis software.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
}


bibtype: article
filename: fparith.bib
label: Moore:2008:IMB
author: Samuel K. Moore
title: Intel Makes A Big Jump In Computer Math
journal: j-IEEE-SPECTRUM
volume: 45
number: 2
pages: 14--15
month: feb
monthnumber: 2
year: 2008
CODEN: IEESAM
DOI: https://doi.org/10.1109/SPEC.2008.4445770
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Sat Jan 18 12:29:46 2020
bibtimestamp: 2020.01.18 12:29:46 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: Samuel K. Moore
rawtitle: {Intel} Makes A Big Jump In Computer Math
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum2000.bib

keywords:
45-nanometer processors; Clocks; Computer architecture; computer math; Convergence; Crops; Digital arithmetic; financial computing; Frequency conversion; Intel; Intel Pentium; Loans and mortgages; microprocessor chips; Microprocessors; Penryn; Penryn chip; Programming profession; scientific computing; Scientific computing; size 45 nm; SRT Radix-4 (Sweeney, Robertson, Tocher) division

entry:
@Article{Moore:2008:IMB,
  author =       "Samuel K. Moore",
  title =        "{Intel} Makes A Big Jump In Computer Math",
  journal =      j-IEEE-SPECTRUM,
  volume =       "45",
  number =       "2",
  pages =        "14--15",
  month =        feb,
  year =         "2008",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/SPEC.2008.4445770",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Sat Jan 18 12:29:46 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum2000.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "45-nanometer processors; Clocks; Computer
                 architecture; computer math; Convergence; Crops;
                 Digital arithmetic; financial computing; Frequency
                 conversion; Intel; Intel Pentium; Loans and mortgages;
                 microprocessor chips; Microprocessors; Penryn; Penryn
                 chip; Programming profession; scientific computing;
                 Scientific computing; size 45 nm; SRT Radix-4 (Sweeney,
                 Robertson, Tocher) division",
}


bibtype: article
filename: fparith.bib
label: Morris:2008:PLC
author: Gerald R. Morris and Viktor K. Prasanna
journal: j-J-PAR-DIST-COMP
volume: 68
number: 7
pages: 913--921
month: jul
monthnumber: 7
year: 2008
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Fri Jul 11 20:32:36 MDT 2008
bibtimestamp: 2008.07.11 20:32:36 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Gerald R. Morris and Viktor K. Prasanna
title:
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer

bibsource:
http://www.sciencedirect.com/science/journal/07437315; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer

entry:
@Article{Morris:2008:PLC,
  author =       "Gerald R. Morris and Viktor K. Prasanna",
  title =        "A pipelined-loop-compatible architecture and algorithm
                 to reduce variable-length sets of floating-point data
                 on a reconfigurable computer",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "68",
  number =       "7",
  pages =        "913--921",
  month =        jul,
  year =         "2008",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Fri Jul 11 20:32:36 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/07437315;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: article
filename: fparith.bib
label: Nakamori:2008:SRA
author: S. Nakamori
journal: j-APPL-MATH-COMP
volume: 203
number: 1
pages: 186--193
day: 1
month: sep
monthnumber: 9
year: 2008
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Fri Sep 3 10:53:23 MDT 2010
bibtimestamp: 2010.09.03 10:53:23 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: S. Nakamori
title:
Square-root algorithms of RLS Wiener filter and fixed-point smoother in linear discrete stochastic systems

rawtitle:
Square-root algorithms of {RLS Wiener} filter and fixed-point smoother in linear discrete stochastic systems

entry:
@Article{Nakamori:2008:SRA,
  author =       "S. Nakamori",
  title =        "Square-root algorithms of {RLS Wiener} filter and
                 fixed-point smoother in linear discrete stochastic
                 systems",
  journal =      j-APPL-MATH-COMP,
  volume =       "203",
  number =       "1",
  pages =        "186--193",
  day =          "1",
  month =        sep,
  year =         "2008",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Fri Sep 3 10:53:23 MDT 2010",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: article
filename: fparith.bib
label: Namin:2008:NFF
author: A. H. Namin and Huapeng Wu and M. Ahmadi
title: A New Finite-Field Multiplier Using Redundant Representation
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 5
pages: 716--720
month: may
monthnumber: 5
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70834
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:41 MDT 2011
bibtimestamp: 2011.07.04 12:17:41 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4378354
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. H. Namin and Huapeng Wu and M. Ahmadi
rawtitle: A New Finite-Field Multiplier Using Redundant Representation
entry:
@Article{Namin:2008:NFF,
  author =       "A. H. Namin and Huapeng Wu and M. Ahmadi",
  title =        "A New Finite-Field Multiplier Using Redundant
                 Representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "5",
  pages =        "716--720",
  month =        may,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70834",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4378354",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: book
filename: fparith.bib
label: P754:2008:ISF
author: IEEE Task P754
title: IEEE 754-2008, Standard for Floating-Point Arithmetic
publisher: pub-IEEE-STD
address: pub-IEEE-STD:adr
pages: 58
day: 29
month: aug
monthnumber: 8
year: 2008
DOI: https://doi.org/10.1109/IEEESTD.2008.4610935
ISBN: 0-7381-5753-8 (paper), 0-7381-5752-X (electronic) OR 0738157538 (paper), 073815752X (electronic)
bibdate: Thu Sep 25 09:50:30 2008
bibtimestamp: 2008.09.25 09:50:30 ???
acknowledgement: ack-nhfb
rawauthor: {IEEE Task P754}
rawtitle: {IEEE 754-2008, Standard for Floating-Point Arithmetic}
ISBN13:
978-0-7381-5753-5 (paper), 978-0-7381-5752-8 (electronic) OR 9780738157535 (paper), 9780738157528 (electronic)

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeestd.bib

URL:
http://en.wikipedia.org/wiki/IEEE_754-2008; http://ieeexplore.ieee.org/servlet/opac?punumber=4610933

abstract:
This standard specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming environments. This standard specifies exception conditions and their default handling. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware. For operations specified in the normative part of this standard, numerical results and exceptions are uniquely determined by the values of the input data, sequence of operations, and destination formats, all under user control.

rawabstract:
This standard specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming environments. This standard specifies exception conditions and their default handling. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware. For operations specified in the normative part of this standard, numerical results and exceptions are uniquely determined by the values of the input data, sequence of operations, and destination formats, all under user control.

entry:
@Book{P754:2008:ISF,
  author =       "{IEEE Task P754}",
  title =        "{IEEE 754-2008, Standard for Floating-Point
                 Arithmetic}",
  publisher =    pub-IEEE-STD,
  address =      pub-IEEE-STD:adr,
  pages =        "58",
  day =          "29",
  month =        aug,
  year =         "2008",
  DOI =          "https://doi.org/10.1109/IEEESTD.2008.4610935",
  ISBN =         "0-7381-5753-8 (paper), 0-7381-5752-X (electronic)",
  ISBN-13 =      "978-0-7381-5753-5 (paper), 978-0-7381-5752-8
                 (electronic)",
  LCCN =         "????",
  bibdate =      "Thu Sep 25 09:50:30 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeestd.bib",
  URL =          "http://en.wikipedia.org/wiki/IEEE_754-2008;
                 http://ieeexplore.ieee.org/servlet/opac?punumber=4610933",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Pan:2008:SAL
author: V. Y. Pan and D. Grady and B. Murphy and G. Qian and R. E. Rosholt and A. D. Ruslanov
title: Schur aggregation for linear systems and determinants
journal: j-THEOR-COMP-SCI
volume: 409
number: 2
pages: 255--268
day: 17
month: dec
monthnumber: 12
year: 2008
CODEN: TCSCDI
DOI: https://doi.org/10.1016/j.tcs.2008.09.005
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Mon Mar 28 21:21:44 MDT 2011
bibtimestamp: 2011.03.28 21:21:44 MDT
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975/
rawauthor: V. Y. Pan and D. Grady and B. Murphy and G. Qian and R. E. Rosholt and A. D. Ruslanov
rawtitle: {Schur} aggregation for linear systems and determinants
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tcs2005.bib

keywords:
accurate floating-point summation; Additive preconditioning; Determinants; Iterative refinement; Linear systems of equations; Sherman Morrison Woodbury formula

entry:
@Article{Pan:2008:SAL,
  author =       "V. Y. Pan and D. Grady and B. Murphy and G. Qian and
                 R. E. Rosholt and A. D. Ruslanov",
  title =        "{Schur} aggregation for linear systems and
                 determinants",
  journal =      j-THEOR-COMP-SCI,
  volume =       "409",
  number =       "2",
  pages =        "255--268",
  day =          "17",
  month =        dec,
  year =         "2008",
  CODEN =        "TCSCDI",
  DOI =          "https://doi.org/10.1016/j.tcs.2008.09.005",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Mon Mar 28 21:21:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tcs2005.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975/",
  keywords =     "accurate floating-point summation; Additive
                 preconditioning; Determinants; Iterative refinement;
                 Linear systems of equations; Sherman Morrison Woodbury
                 formula",
}


bibtype: incollection
filename: fparith.bib
label: Patterson:2008:AC
author: David A. Patterson and John L. Hennessy
title: Arithmetic for Computers
crossref: Patterson:2008:COD
chapter: 3
pages: 222--297
year: 2008
bibdate: Thu Dec 04 18:36:00 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.04 18:36:00 ???
keywords: floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: David A. Patterson and John L. Hennessy
rawtitle: Arithmetic for Computers
entry:
@InCollection{Patterson:2008:AC,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Arithmetic for Computers",
  crossref =     "Patterson:2008:COD",
  chapter =      "3",
  pages =        "222--297",
  year =         "2008",
  bibdate =      "Thu Dec 04 18:36:00 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic",
}


bibtype: incollection
filename: fparith.bib
label: Patterson:2008:GCG
author: David A. Patterson and John L. Hennessy
title: Graphics and Computing GPUs
crossref: Patterson:2008:COD
chapter: A
pages: A-1--A-77
year: 2008
bibdate: Thu Dec 04 18:36:00 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.04 18:36:00 ???
keywords: floating-point arithmetic; GPU
acknowledgement: ack-nhfb
rawauthor: David A. Patterson and John L. Hennessy
rawtitle: Graphics and Computing {GPUs}
entry:
@InCollection{Patterson:2008:GCG,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Graphics and Computing {GPUs}",
  crossref =     "Patterson:2008:COD",
  chapter =      "A",
  pages =        "A-1--A-77",
  year =         "2008",
  bibdate =      "Thu Dec 04 18:36:00 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; GPU",
}


bibtype: article
filename: fparith.bib
label: Pineiro:2008:RDD
author: J.-A. Pineiro and J. D. Bruguera and F. Lamberti and P. Montuschi
title: A Radix-2 Digit-by-Digit Architecture for Cube Root
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 4
pages: 562--566
month: apr
monthnumber: 4
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70848
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:41 MDT 2011
bibtimestamp: 2011.07.04 12:17:41 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4407683
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J.-A. Pineiro and J. D. Bruguera and F. Lamberti and P. Montuschi
rawtitle: A Radix-2 Digit-by-Digit Architecture for Cube Root
abstract:
A radix-2 digit-recurrence algorithm and architecture for the computation of the cube root are presented in this paper. The original recurrence based on the concept of completing the cube is modified to allow an efficient implementation of the algorithm and the cycle time and area cost of the resulting architecture are estimated as 7.5 times the delay of a full adder and around 9,000 nand2 cells, respectively, for double-precision computations.

rawabstract:
A radix-2 digit-recurrence algorithm and architecture for the computation of the cube root are presented in this paper. The original recurrence based on the concept of completing the cube is modified to allow an efficient implementation of the algorithm and the cycle time and area cost of the resulting architecture are estimated as 7.5 times the delay of a full adder and around 9,000 nand2 cells, respectively, for double-precision computations.

entry:
@Article{Pineiro:2008:RDD,
  author =       "J.-A. Pineiro and J. D. Bruguera and F. Lamberti and
                 P. Montuschi",
  title =        "A Radix-2 Digit-by-Digit Architecture for Cube Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "4",
  pages =        "562--566",
  month =        apr,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70848",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4407683",
  abstract =     "A radix-2 digit-recurrence algorithm and architecture
                 for the computation of the cube root are presented in
                 this paper. The original recurrence based on the
                 concept of completing the cube is modified to allow an
                 efficient implementation of the algorithm and the cycle
                 time and area cost of the resulting architecture are
                 estimated as 7.5 times the delay of a full adder and
                 around 9,000 nand2 cells, respectively, for
                 double-precision computations.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Piso:2008:FOS
author: D. Piso and J. D. Bruguera
editor: Michael B. Matthews
title: Forcing em one-sided results in Goldschmidt algorithm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1830--1833
month: oct
monthnumber: 10
year: 2008
DOI: https://doi.org/10.1109/acssc.2008.5074743
ISBN: 1-4244-2941-2 OR 1424429412
ISBN13: 978-1-4244-2941-7 OR 9781424429417
ISSN: 1058-6393 OR 10586393
ISSNL: 1058-6393 OR 10586393
LCCN: TK7801 .A83 2008
bibdate: Mon Dec 11 08:10:00 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 08:10:00 ???
acknowledgement: ack-nhfb
rawauthor: D. Piso and J. D. Bruguera
raweditor: Michael B. Matthews
rawtitle: Forcing {\em one-sided\/} results in {Goldschmidt} algorithm
booktitle:
42nd Asilomar Conference on Signals, Systems and Computers: October 26--29, 2008, Pacific Grove, California

abstract:
This paper presents a method to obtain one-sided error results from Goldschmidt (GLD) algorithm. In some applications is useful to obtain a one-sided error result. This is done introducing error bias in the intermediate iterations. An error analysis permits to obtain expressions to estimate the loss of precision and to compensate it. In this way, the one-sided error results are obtained without significant additional hardware requirement.

rawabstract:
This paper presents a method to obtain one-sided error results from Goldschmidt (GLD) algorithm. In some applications is useful to obtain a one-sided error result. This is done introducing error bias in the intermediate iterations. An error analysis permits to obtain expressions to estimate the loss of precision and to compensate it. In this way, the one-sided error results are obtained without significant additional hardware requirement.

rawbooktitle:
42nd Asilomar Conference on Signals, Systems and Computers: {October 26--29, 2008, Pacific Grove, California}

entry:
@InProceedings{Piso:2008:FOS,
  author =       "D. Piso and J. D. Bruguera",
  editor =       "Michael B. Matthews",
  booktitle =    "42nd Asilomar Conference on Signals, Systems and
                 Computers: {October 26--29, 2008, Pacific Grove,
                 California}",
  title =        "Forcing {\em one-sided\/} results in {Goldschmidt}
                 algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1830--1833",
  month =        oct,
  year =         "2008",
  DOI =          "https://doi.org/10.1109/acssc.2008.5074743",
  ISBN =         "1-4244-2941-2",
  ISBN-13 =      "978-1-4244-2941-7",
  ISSN =         "1058-6393",
  ISSN-L =       "1058-6393",
  LCCN =         "TK7801 .A83 2008",
  bibdate =      "Mon Dec 11 08:10:00 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a method to obtain one-sided error
                 results from Goldschmidt (GLD) algorithm. In some
                 applications is useful to obtain a one-sided error
                 result. This is done introducing error bias in the
                 intermediate iterations. An error analysis permits to
                 obtain expressions to estimate the loss of precision
                 and to compensate it. In this way, the one-sided error
                 results are obtained without significant additional
                 hardware requirement.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Piso:2008:NRA
author: D. Piso and J. D. Bruguera
editor: Luca Fanucci
title: A New Rounding Algorithm for Variable Latency Division and Square Root Implementations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 760--767
year: 2008
DOI: https://doi.org/10.1109/DSD.2008.28.
ISBN: 0-7695-3277-2 OR 0769532772
ISBN13: 978-0-7695-3277-6 OR 9780769532776
bibdate: Sun Dec 10 13:55:38 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 13:55:38 ???
acknowledgement: ack-nhfb
rawauthor: D. Piso and J. D. Bruguera
raweditor: Luca Fanucci
rawtitle: A New Rounding Algorithm for Variable Latency Division and Square Root Implementations
booktitle:
Proceedings: 11th Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools (DSD 2008), Parma, Italy, September 3--5, 2008

abstract:
The aim of this work is to present a method for rounding quadratically converging algorithms that improves their performance. This method is able to reduce significantly the number of cases where the remainder calculation is necessary. It is based on previous methods and incorporates additional bits of the result approximation to be checked. This work includes the result of exhaustive simulations that permit us to measure exactly how many calculations are avoided. Using these simulations, it is concluded that the presented method is able to reduce by half the number of remainder calculations. Using adequate result approximations the remainder calculation is necessary in only 5% of the total cases

rawabstract:
The aim of this work is to present a method for rounding quadratically converging algorithms that improves their performance. This method is able to reduce significantly the number of cases where the remainder calculation is necessary. It is based on previous methods and incorporates additional bits of the result approximation to be checked. This work includes the result of exhaustive simulations that permit us to measure exactly how many calculations are avoided. Using these simulations, it is concluded that the presented method is able to reduce by half the number of remainder calculations. Using adequate result approximations the remainder calculation is necessary in only 5\% of the total cases

rawbooktitle:
Proceedings: {11th Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools (DSD 2008), Parma, Italy, September 3--5, 2008}

entry:
@InProceedings{Piso:2008:NRA,
  author =       "D. Piso and J. D. Bruguera",
  editor =       "Luca Fanucci",
  booktitle =    "Proceedings: {11th Euromicro Symposium on Digital
                 Systems Design: Architectures, Methods and Tools (DSD
                 2008), Parma, Italy, September 3--5, 2008}",
  title =        "A New Rounding Algorithm for Variable Latency Division
                 and Square Root Implementations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "760--767",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/DSD.2008.28.",
  ISBN =         "0-7695-3277-2",
  ISBN-13 =      "978-0-7695-3277-6",
  bibdate =      "Sun Dec 10 13:55:38 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The aim of this work is to present a method for
                 rounding quadratically converging algorithms that
                 improves their performance. This method is able to
                 reduce significantly the number of cases where the
                 remainder calculation is necessary. It is based on
                 previous methods and incorporates additional bits of
                 the result approximation to be checked. This work
                 includes the result of exhaustive simulations that
                 permit us to measure exactly how many calculations are
                 avoided. Using these simulations, it is concluded that
                 the presented method is able to reduce by half the
                 number of remainder calculations. Using adequate result
                 approximations the remainder calculation is necessary
                 in only 5\% of the total cases",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Quinnell:2008:BFP
author: E. Quinnell and E. E. Swartzlander and C. Lemonds
title: Bridge Floating-Point Fused Multiply-Add Design
journal: j-IEEE-TRANS-VLSI-SYST
volume: 16
number: 12
pages: 1727--1731
year: 2008
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2008.2001944
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Feb 19 18:54:07 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.19 18:54:07 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: E. Quinnell and E. E. Swartzlander and C. Lemonds
rawtitle: Bridge Floating-Point Fused Multiply-Add Design
entry:
@Article{Quinnell:2008:BFP,
  author =       "E. Quinnell and E. E. Swartzlander and C. Lemonds",
  title =        "Bridge Floating-Point Fused Multiply-Add Design",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "16",
  number =       "12",
  pages =        "1727--1731",
  year =         "2008",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2008.2001944",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Feb 19 18:54:07 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: inproceedings
filename: fparith.bib
label: Quinnell:2008:FPF
author: E. Quinnell and E. E. Swartzlander and C. Lemonds
title: Floating-Point Fused Multiply-Add Architectures
crossref: Matthews:2008:CRF
pages: 331--337
year: 2008
DOI: https://doi.org/10.1109/ACSSC.2007.4487224
bibdate: Sat Feb 19 18:56:18 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.19 18:56:18 ???
acknowledgement: ack-nhfb
rawauthor: E. Quinnell and E. E. Swartzlander and C. Lemonds
rawtitle: Floating-Point Fused Multiply-Add Architectures
abstract:
Two new floating-point fused multiply-add architectures for the single instruction execution of $ (A times B) + C $ are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as a collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the Advanced Micro Devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.

rawabstract:
Two new floating-point fused multiply-add architectures for the single instruction execution of $ (A \times B) + C $ are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as a collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the Advanced Micro Devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.

entry:
@InProceedings{Quinnell:2008:FPF,
  author =       "E. Quinnell and E. E. Swartzlander and C. Lemonds",
  title =        "Floating-Point Fused Multiply-Add Architectures",
  crossref =     "Matthews:2008:CRF",
  pages =        "331--337",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ACSSC.2007.4487224",
  bibdate =      "Sat Feb 19 18:56:18 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Two new floating-point fused multiply-add
                 architectures for the single instruction execution of $
                 (A \times B) + C $ are presented. The three-path
                 architecture uses parallel hardware paths similar to
                 those in dual-path floating-point adders. The new
                 bridge architecture re-uses common floating-point
                 components to add a fused multiply-add instruction.
                 Each new architecture as well as a collection of
                 floating-point arithmetic units and a classic fused
                 multiplier-adder have been designed using the Advanced
                 Micro Devices 65 nanometer silicon on insulator CMOS
                 technology to fairly compare the new architectures.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Rahaman:2008:CTB
author: H. Rahaman and J. Mathew and D. K. Pradhan and A. M. Jabir
title: C-testable bit parallel multipliers over $ rm GF(2^m) $
journal: j-TODAES
volume: 13
number: 1
pages: 5:1--5:??
month: jan
monthnumber: 1
year: 2008
CODEN: ATASFO
DOI: https://doi.org/10.1145/1297666.1297671
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Thu Jun 12 18:10:00 MDT 2008
bibtimestamp: 2008.06.12 18:10:00 MDT
fjournal: ACM Transactions on Design Automation of Electronic Systems (TODAES)
acknowledgement: ack-nhfb
articleno: 5
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J776
rawauthor: H. Rahaman and J. Mathew and D. K. Pradhan and A. M. Jabir
rawtitle: {C}-testable bit parallel multipliers over {$ {\rm GF}(2^m) $}
bibsource:
http://www.acm.org/pubs/contents/journals/todaes/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsysreg tools using UMC 0. 18 micron CMOS technology library.

keywords:
built-in self-test; C-testable; cryptography; digital signal processing; error control code; fault; floating-point testing; Galois field; multiplier; polynomials; stuck-at fault; testing; TPG; VLSI design

rawabstract:
We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m) for 100\% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6\% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys{\reg} tools using UMC 0. 18 micron CMOS technology library.

entry:
@Article{Rahaman:2008:CTB,
  author =       "H. Rahaman and J. Mathew and D. K. Pradhan and A. M.
                 Jabir",
  title =        "{C}-testable bit parallel multipliers over {$ {\rm
                 GF}(2^m) $}",
  journal =      j-TODAES,
  volume =       "13",
  number =       "1",
  pages =        "5:1--5:??",
  month =        jan,
  year =         "2008",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/1297666.1297671",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Thu Jun 12 18:10:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/todaes/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a C-testable design of polynomial basis
                 (PB) bit-parallel (BP) multipliers over GF(2 m) for
                 100\% coverage of stuck-at faults. Our design method
                 also includes the method for test vector generation,
                 which is simple and efficient. C-testability is
                 achieved with three control inputs and approximately
                 6\% additional hardware. Only 8 constant vectors are
                 required irrespective of the sizes of the fields and
                 primitive polynomial. We also present a Built-In
                 Self-Test (BIST) architecture for generating the test
                 vectors efficiently, which eliminates the need for the
                 extra control inputs. Since these circuits have
                 critical applications as parts of cryptography (e.g.,
                 Elliptic Curve Crypto (ECC) systems) hardware, the BIST
                 architecture may provide with added level of security,
                 as the tests would be done internally and without the
                 requirement of probing by external testing equipment.
                 Finally we present experimental results comprising the
                 area, delay and power of the testable multipliers of
                 various sizes with the help of the Synopsys{\reg} tools
                 using UMC 0. 18 micron CMOS technology library.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems (TODAES)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J776",
  keywords =     "built-in self-test; C-testable; cryptography; digital
                 signal processing; error control code; fault;
                 floating-point testing; Galois field; multiplier;
                 polynomials; stuck-at fault; testing; TPG; VLSI
                 design",
}


bibtype: article
filename: fparith.bib
label: Rahaman:2008:DRT
author: H. Rahaman and J. Mathew and D. K. Pradhan and A. M. Jabir
title: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over $ mathrm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 9
pages: 1289--1294
month: sep
monthnumber: 9
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.63
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:43 MDT 2011
bibtimestamp: 2011.07.04 12:17:43 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4487058
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Rahaman and J. Mathew and D. K. Pradhan and A. M. Jabir
rawtitle: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over {$ \mathrm {GF}(2^m) $}
entry:
@Article{Rahaman:2008:DRT,
  author =       "H. Rahaman and J. Mathew and D. K. Pradhan and A. M.
                 Jabir",
  title =        "Derivation of Reduced Test Vectors for Bit-Parallel
                 Multipliers over {$ \mathrm {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "9",
  pages =        "1289--1294",
  month =        sep,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.63",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:43 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4487058",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ravikumar:2008:BND
author: Bala Ravikumar
title: The Benford--Newcomb Distribution and Unambiguous Context-Free Languages
journal: j-INT-J-FOUND-COMP-SCI
volume: 19
number: 3
pages: 717--727
month: jun
monthnumber: 6
year: 2008
CODEN: IFCSEN
DOI: https://doi.org/10.1142/S0129054108005905
ISSN: 0129-0541 (print), 1793-6373 (electronic) OR 01290541 (print), 17936373 (electronic)
ISSNL: 0129-0541 OR 01290541
bibdate: Tue Aug 31 07:37:14 MDT 2010
bibtimestamp: 2010.08.31 07:37:14 MDT
fjournal: International Journal of Foundations of Computer Science (IJFCS)
acknowledgement: ack-nhfb
journalURL: http://www.worldscientific.com/loi/ijfcs
rawauthor: Bala Ravikumar
rawtitle: The {Benford--Newcomb} Distribution and Unambiguous Context-Free Languages
bibsource:
http://ejournals.wspc.com.sg/ijfcs/mkt/archive.shtml; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Ravikumar:2008:BND,
  author =       "Bala Ravikumar",
  title =        "The {Benford--Newcomb} Distribution and Unambiguous
                 Context-Free Languages",
  journal =      j-INT-J-FOUND-COMP-SCI,
  volume =       "19",
  number =       "3",
  pages =        "717--727",
  month =        jun,
  year =         "2008",
  CODEN =        "IFCSEN",
  DOI =          "https://doi.org/10.1142/S0129054108005905",
  ISSN =         "0129-0541 (print), 1793-6373 (electronic)",
  ISSN-L =       "0129-0541",
  bibdate =      "Tue Aug 31 07:37:14 MDT 2010",
  bibsource =    "http://ejournals.wspc.com.sg/ijfcs/mkt/archive.shtml;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Foundations of Computer
                 Science (IJFCS)",
  journal-URL =  "http://www.worldscientific.com/loi/ijfcs",
}


bibtype: inproceedings
filename: fparith.bib
label: Raz:2008:EFL
author: Ran Raz
title: Elusive functions and lower bounds for arithmetic circuits
crossref: ACM:2008:SPA
pages: 711--720
year: 2008
DOI: https://doi.org/10.1145/1374376.1374479
bibdate: Fri Jun 20 18:31:53 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 18:31:53 MDT
keywords: arithmetic circuits; bounded depth circuits; circuit complexity; lower bounds
acknowledgement: ack-nhfb
rawauthor: Ran Raz
rawtitle: Elusive functions and lower bounds for arithmetic circuits
abstract:
A basic fact in linear algebra is that the image of the curve $ f(x) = (x^1, x^2, x^3, ldots , x^m) $, say over $C$, is not contained in any $ m - 1 $ dimensional affine subspace of $ C^m $. In other words, the image of $f$ is not contained in the image of any polynomial-mapping $ Gamma : C^m - 1 rightarrow C^m $ of degree 1 (that is, an affine mapping). Can one give an explicit example for a polynomial curve $ f : C rightarrow C^m $, such that, the image of $f$ is not contained in the image of any polynomial-mapping $ Gamma : C^m - 1 rightarrow C^m $ of degree 2? In this paper, we show that problems of this type are closely related to proving lower bounds for the size of general arithmetic circuits. For example, any explicit $f$ as above (with the right notion of explicitness) implies super-polynomial lower bounds for computing the permanent over $C$. More generally, we say that a polynomial-mapping $ f : F^n rightarrow F^m $ is $ (s, r) $-elusive, if for every polynomial-mapping $ Gamma : F^s rightarrow F^m $ of degree $r$, $ I m(f) not subset I m(Gamma ) $. We show that for many settings of the parameters $ n, m, s, r $, explicit constructions of elusive polynomial-mappings imply strong (up to exponential) lower bounds for general arithmetic circuits. Finally, for every $r$, of degree $ O(r) $, that is $ (s, r) $-elusive for $ s = n^1 + Omega (1 / r) $. We use this to construct for any $r$, an explicit example for an $n$-variate polynomial of total-degree $ O(r) $, with coefficients in $ 0, 1, $ such that, any depth $r$ arithmetic circuit for this polynomial (over any field) is of size $ geq n^1 + Omega (1 / r) $. In particular, for any constant $r$, this gives a constant degree polynomial, such that, any depth $r$ arithmetic circuit for this polynomial is of size $ geq n^1 + Omega (1) $. Previously, only lower bounds of the type $ Omega (n lambda _r (n)) $, where $ lambda _r (n) $ are extremely slowly growing functions (e.g., $ lambda _5 (n) = log n $, and $ lambda _7 (n) = log * log * n $), were known for constant-depth arithmetic circuits for polynomials of constant degree.

rawabstract:
A basic fact in linear algebra is that the image of the curve $ f(x) = (x^1, x^2, x^3, \ldots {}, x^m) $, say over $C$, is not contained in any $ m - 1 $ dimensional affine subspace of $ C^m $. In other words, the image of $f$ is not contained in the image of any polynomial-mapping $ \Gamma : C^{m - 1} \rightarrow C^m $ of degree 1 (that is, an affine mapping). Can one give an explicit example for a polynomial curve $ f : C \rightarrow C^m $, such that, the image of $f$ is not contained in the image of any polynomial-mapping $ \Gamma : C^{m - 1} \rightarrow C^m $ of degree 2? In this paper, we show that problems of this type are closely related to proving lower bounds for the size of general arithmetic circuits. For example, any explicit $f$ as above (with the right notion of explicitness) implies super-polynomial lower bounds for computing the permanent over $C$. More generally, we say that a polynomial-mapping $ f : F^n \rightarrow F^m $ is $ (s, r) $-elusive, if for every polynomial-mapping $ \Gamma : F^s \rightarrow F^m $ of degree $r$, $ I m(f) \not \subset I m(\Gamma) $. We show that for many settings of the parameters $ n, m, s, r $, explicit constructions of elusive polynomial-mappings imply strong (up to exponential) lower bounds for general arithmetic circuits. Finally, for every $r$, of degree $ O(r) $, that is $ (s, r) $-elusive for $ s = n^{1 + \Omega (1 / r)} $. We use this to construct for any $r$, an explicit example for an $n$-variate polynomial of total-degree $ O(r) $, with coefficients in $ \{ 0, 1, \} $ such that, any depth $r$ arithmetic circuit for this polynomial (over any field) is of size $ \geq n^{1 + \Omega (1 / r)} $. In particular, for any constant $r$, this gives a constant degree polynomial, such that, any depth $r$ arithmetic circuit for this polynomial is of size $ \geq n^{1 + \Omega (1)} $. Previously, only lower bounds of the type $ \Omega (n \lambda_r (n)) $, where $ \lambda_r (n) $ are extremely slowly growing functions (e.g., $ \lambda_5 (n) = \log n $, and $ \lambda_7 (n) = \log * \log * n $), were known for constant-depth arithmetic circuits for polynomials of constant degree.

entry:
@InProceedings{Raz:2008:EFL,
  author =       "Ran Raz",
  title =        "Elusive functions and lower bounds for arithmetic
                 circuits",
  crossref =     "ACM:2008:SPA",
  pages =        "711--720",
  year =         "2008",
  DOI =          "https://doi.org/10.1145/1374376.1374479",
  bibdate =      "Fri Jun 20 18:31:53 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A basic fact in linear algebra is that the image of
                 the curve $ f(x) = (x^1, x^2, x^3, \ldots {}, x^m) $,
                 say over $C$, is not contained in any $ m - 1 $
                 dimensional affine subspace of $ C^m $. In other words,
                 the image of $f$ is not contained in the image of any
                 polynomial-mapping $ \Gamma : C^{m - 1} \rightarrow C^m
                 $ of degree 1 (that is, an affine mapping). Can one
                 give an explicit example for a polynomial curve $ f : C
                 \rightarrow C^m $, such that, the image of $f$ is not
                 contained in the image of any polynomial-mapping $
                 \Gamma : C^{m - 1} \rightarrow C^m $ of degree 2? In
                 this paper, we show that problems of this type are
                 closely related to proving lower bounds for the size of
                 general arithmetic circuits. For example, any explicit
                 $f$ as above (with the right notion of explicitness)
                 implies super-polynomial lower bounds for computing the
                 permanent over $C$. More generally, we say that a
                 polynomial-mapping $ f : F^n \rightarrow F^m $ is $ (s,
                 r) $-elusive, if for every polynomial-mapping $ \Gamma
                 : F^s \rightarrow F^m $ of degree $r$, $ I m(f) \not
                 \subset I m(\Gamma) $. We show that for many settings
                 of the parameters $ n, m, s, r $, explicit
                 constructions of elusive polynomial-mappings imply
                 strong (up to exponential) lower bounds for general
                 arithmetic circuits. Finally, for every $r$, of degree
                 $ O(r) $, that is $ (s, r) $-elusive for $ s = n^{1 +
                 \Omega (1 / r)} $. We use this to construct for any
                 $r$, an explicit example for an $n$-variate polynomial
                 of total-degree $ O(r) $, with coefficients in $ \{ 0,
                 1, \} $ such that, any depth $r$ arithmetic circuit for
                 this polynomial (over any field) is of size $ \geq n^{1
                 + \Omega (1 / r)} $. In particular, for any constant
                 $r$, this gives a constant degree polynomial, such
                 that, any depth $r$ arithmetic circuit for this
                 polynomial is of size $ \geq n^{1 + \Omega (1)} $.
                 Previously, only lower bounds of the type $ \Omega (n
                 \lambda_r (n)) $, where $ \lambda_r (n) $ are extremely
                 slowly growing functions (e.g., $ \lambda_5 (n) = \log
                 n $, and $ \lambda_7 (n) = \log * \log * n $), were
                 known for constant-depth arithmetic circuits for
                 polynomials of constant degree.",
  acknowledgement = ack-nhfb,
  keywords =     "arithmetic circuits; bounded depth circuits; circuit
                 complexity; lower bounds",
}


bibtype: article
filename: fparith.bib
label: Raz:2008:LBS
author: Ran Raz and Amir Shpilka and Amir Yehudayoff
title: A Lower Bound for the Size of Syntactically Multilinear Arithmetic Circuits
journal: j-SIAM-J-COMPUT
volume: 38
number: 4
pages: 1624--1647
year: 2008
CODEN: SMJCAT
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Tue May 18 08:22:01 MDT 2010
bibtimestamp: 2010.05.18 08:22:01 MDT
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Ran Raz and Amir Shpilka and Amir Yehudayoff
rawtitle: A Lower Bound for the Size of Syntactically Multilinear Arithmetic Circuits
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/38/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Raz:2008:LBS,
  author =       "Ran Raz and Amir Shpilka and Amir Yehudayoff",
  title =        "A Lower Bound for the Size of Syntactically
                 Multilinear Arithmetic Circuits",
  journal =      j-SIAM-J-COMPUT,
  volume =       "38",
  number =       "4",
  pages =        "1624--1647",
  month =        "????",
  year =         "2008",
  CODEN =        "SMJCAT",
  DOI =          "",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  bibdate =      "Tue May 18 08:22:01 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/38/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
}


bibtype: article
filename: fparith.bib
label: Rodriguez-Henriquez:2008:LCB
author: F. Rodriguez-Henriquez and G. Morales-Luna and J. Lopez
title: Low-Complexity Bit-Parallel Square Root Computation over $ mathrm GF(2^m) $ for All Trinomials
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 4
pages: 472--480
month: apr
monthnumber: 4
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70822
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:40 MDT 2011
bibtimestamp: 2011.07.04 12:17:40 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358282
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: F. Rodriguez-Henriquez and G. Morales-Luna and J. Lopez
rawtitle: Low-Complexity Bit-Parallel Square Root Computation over {$ \mathrm {GF}(2^m) $} for All Trinomials
entry:
@Article{Rodriguez-Henriquez:2008:LCB,
  author =       "F. Rodriguez-Henriquez and G. Morales-Luna and J.
                 Lopez",
  title =        "Low-Complexity Bit-Parallel Square Root Computation
                 over {$ \mathrm {GF}(2^m) $} for All Trinomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "4",
  pages =        "472--480",
  month =        apr,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70822",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358282",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ruiz:2008:EIR
author: Gustavo A. Ruiz and Mercedes Granda
title: Efficient implementation of 3X for radix-8 encoding
journal: j-MICROELECT-J
volume: 39
number: 1
pages: 152--159
month: jan
monthnumber: 1
year: 2008
CODEN: MICEB9
DOI: https://doi.org/10.1016/j.mejo.2007.10.006
ISSN: 0026-2692 (print), 1879-2391 (electronic) OR 00262692 (print), 18792391 (electronic)
ISSNL: 0026-2692 OR 00262692
bibdate: Wed Dec 13 09:54:52 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.13 09:54:52 ???
fjournal: Microelectronics Journal
keywords: Booth-3 encoding; computation of $3 x$; Goldschmidt division algorithm
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00262692
rawauthor: Gustavo A. Ruiz and Mercedes Granda
rawtitle: Efficient implementation of {3X} for radix-8 encoding
entry:
@Article{Ruiz:2008:EIR,
  author =       "Gustavo A. Ruiz and Mercedes Granda",
  title =        "Efficient implementation of {3X} for radix-8
                 encoding",
  journal =      j-MICROELECT-J,
  volume =       "39",
  number =       "1",
  pages =        "152--159",
  month =        jan,
  year =         "2008",
  CODEN =        "MICEB9",
  DOI =          "https://doi.org/10.1016/j.mejo.2007.10.006",
  ISSN =         "0026-2692 (print), 1879-2391 (electronic)",
  ISSN-L =       "0026-2692",
  bibdate =      "Wed Dec 13 09:54:52 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Microelectronics Journal",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00262692",
  keywords =     "Booth-3 encoding; computation of $3 x$; Goldschmidt
                 division algorithm",
}


bibtype: article
filename: fparith.bib
label: Rump:2008:AFPa
author: Siegfried M. Rump and Takeshi Ogita and Shin'ichi Oishi
title: Accurate Floating-Point Summation. Part I: Faithful Rounding
journal: j-SIAM-J-SCI-COMP
volume: 31
number: 1
pages: 189--224
year: 2008
CODEN: SJOCE3
DOI: https://doi.org/10.1137/050645671
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:44:12 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/1; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:44:12 MDT
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; distillation
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Siegfried M. Rump and Takeshi Ogita and Shin'ichi Oishi
rawtitle: Accurate Floating-Point Summation. {Part I}: Faithful Rounding
abstract:
Given a vector of floating-point numbers with exact sum $s$, we present an algorithm for calculating a faithful rounding of $s$, i.e., the result is one of the immediate floating-point neighbors of $s$. If the sum $s$ is a floating-point number, we prove that this is the result of our algorithm. The algorithm adapts to the condition number of the sum, i.e., it is fast for mildly conditioned sums with slowly increasing computing time proportional to the logarithm of the condition number. All statements are also true in the presence of underflow. The algorithm does not depend on the exponent range. Our algorithm is fast in terms of measured computing time because it allows good instruction-level parallelism, it neither requires special operations such as access to mantissa or exponent, it contains no branch in the inner loop, nor does it require some extra precision: The only operations used are standard floating-point addition, subtraction, and multiplication in one working precision, for example, double precision. Certain constants used in the algorithm are proved to be optimal.

rawabstract:
Given a vector of floating-point numbers with exact sum $s$, we present an algorithm for calculating a faithful rounding of $s$, i.e., the result is one of the immediate floating-point neighbors of $s$. If the sum $s$ is a floating-point number, we prove that this is the result of our algorithm. The algorithm adapts to the condition number of the sum, i.e., it is fast for mildly conditioned sums with slowly increasing computing time proportional to the logarithm of the condition number. All statements are also true in the presence of underflow. The algorithm does not depend on the exponent range. Our algorithm is fast in terms of measured computing time because it allows good instruction-level parallelism, it neither requires special operations such as access to mantissa or exponent, it contains no branch in the inner loop, nor does it require some extra precision: The only operations used are standard floating-point addition, subtraction, and multiplication in one working precision, for example, double precision. Certain constants used in the algorithm are proved to be optimal.

entry:
@Article{Rump:2008:AFPa,
  author =       "Siegfried M. Rump and Takeshi Ogita and Shin'ichi
                 Oishi",
  title =        "Accurate Floating-Point Summation. {Part I}: Faithful
                 Rounding",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "31",
  number =       "1",
  pages =        "189--224",
  month =        "????",
  year =         "2008",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/050645671",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:44:12 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Given a vector of floating-point numbers with exact
                 sum $s$, we present an algorithm for calculating a
                 faithful rounding of $s$, i.e., the result is one of
                 the immediate floating-point neighbors of $s$. If the
                 sum $s$ is a floating-point number, we prove that this
                 is the result of our algorithm. The algorithm adapts to
                 the condition number of the sum, i.e., it is fast for
                 mildly conditioned sums with slowly increasing
                 computing time proportional to the logarithm of the
                 condition number. All statements are also true in the
                 presence of underflow. The algorithm does not depend on
                 the exponent range. Our algorithm is fast in terms of
                 measured computing time because it allows good
                 instruction-level parallelism, it neither requires
                 special operations such as access to mantissa or
                 exponent, it contains no branch in the inner loop, nor
                 does it require some extra precision: The only
                 operations used are standard floating-point addition,
                 subtraction, and multiplication in one working
                 precision, for example, double precision. Certain
                 constants used in the algorithm are proved to be
                 optimal.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; distillation",
}


bibtype: article
filename: fparith.bib
label: Rump:2008:AFPb
author: Siegfried M. Rump and Takeshi Ogita and Shin'ichi Oishi
title: Accurate Floating-Point Summation. Part II: Sign, $K$-Fold Faithful and Rounding to Nearest
journal: j-SIAM-J-SCI-COMP
volume: 31
number: 2
pages: 1269--1302
year: 2008
CODEN: SJOCE3
DOI: https://doi.org/10.1137/07068816X
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:44:14 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:44:14 MDT
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation; distillation
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Siegfried M. Rump and Takeshi Ogita and Shin'ichi Oishi
rawtitle: Accurate Floating-Point Summation. {Part II}: Sign, {$K$}-Fold Faithful and Rounding to Nearest
abstract:
In Part II of this paper we first refine the analysis of error-free vector transformations presented in Part I. Based on that we present an algorithm for calculating the rounded-to-nearest result of $ s := sum p_i $ for a given vector of floating-point numbers $ p_i $, as well as algorithms for directed rounding. A special algorithm for computing the sign of $s$ is given, also working for huge dimensions. Assume a floating-point working precision with relative rounding error unit eps. We define and investigate a $K$-fold faithful rounding of a real number $r$. Basically the result is stored in a vector $ mathtt Res_nu $ of $K$ nonoverlapping floating-point numbers such that $ sum mathtt Res_nu $ approximates $r$ with relative accuracy $ mathtt eps^K $, and replacing $ mathtt Res_K $ by its floating-point neighbors in $ sum mathtt Res_nu $ forms a lower and upper bound for $r$. For a given vector of floating-point numbers with exact sum $s$, we present an algorithm for calculating a $K$-fold faithful rounding of $s$ using solely the working precision. Furthermore, an algorithm for calculating a faithfully rounded result of the sum of a vector of huge dimension is presented. Our algorithms are fast in terms of measured computing time because they allow good instruction-level parallelism, they neither require special operations such as access to mantissa or exponent, they contain no branch in the inner loop, nor do they require some extra precision. The only operations used are standard floating-point addition, subtraction, and multiplication in one working precision, for example, double precision. Certain constants used in the algorithms are proved to be optimal.

rawabstract:
In Part II of this paper we first refine the analysis of error-free vector transformations presented in Part I. Based on that we present an algorithm for calculating the rounded-to-nearest result of $ s := \sum p_i $ for a given vector of floating-point numbers $ p_i $, as well as algorithms for directed rounding. A special algorithm for computing the sign of $s$ is given, also working for huge dimensions. Assume a floating-point working precision with relative rounding error unit eps. We define and investigate a $K$-fold faithful rounding of a real number $r$. Basically the result is stored in a vector $ \mathtt {Res}_{\nu } $ of $K$ nonoverlapping floating-point numbers such that $ \sum \mathtt {Res}_{\nu } $ approximates $r$ with relative accuracy $ \mathtt {eps}^K $, and replacing $ \mathtt {Res}_K $ by its floating-point neighbors in $ \sum \mathtt {Res}_{\nu } $ forms a lower and upper bound for $r$. For a given vector of floating-point numbers with exact sum $s$, we present an algorithm for calculating a $K$-fold faithful rounding of $s$ using solely the working precision. Furthermore, an algorithm for calculating a faithfully rounded result of the sum of a vector of huge dimension is presented. Our algorithms are fast in terms of measured computing time because they allow good instruction-level parallelism, they neither require special operations such as access to mantissa or exponent, they contain no branch in the inner loop, nor do they require some extra precision. The only operations used are standard floating-point addition, subtraction, and multiplication in one working precision, for example, double precision. Certain constants used in the algorithms are proved to be optimal.

entry:
@Article{Rump:2008:AFPb,
  author =       "Siegfried M. Rump and Takeshi Ogita and Shin'ichi
                 Oishi",
  title =        "Accurate Floating-Point Summation. {Part II}: Sign,
                 {$K$}-Fold Faithful and Rounding to Nearest",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "31",
  number =       "2",
  pages =        "1269--1302",
  month =        "????",
  year =         "2008",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/07068816X",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:44:14 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In Part II of this paper we first refine the analysis
                 of error-free vector transformations presented in Part
                 I. Based on that we present an algorithm for
                 calculating the rounded-to-nearest result of $ s :=
                 \sum p_i $ for a given vector of floating-point numbers
                 $ p_i $, as well as algorithms for directed rounding. A
                 special algorithm for computing the sign of $s$ is
                 given, also working for huge dimensions. Assume a
                 floating-point working precision with relative rounding
                 error unit eps. We define and investigate a $K$-fold
                 faithful rounding of a real number $r$. Basically the
                 result is stored in a vector $ \mathtt {Res}_{\nu } $
                 of $K$ nonoverlapping floating-point numbers such that
                 $ \sum \mathtt {Res}_{\nu } $ approximates $r$ with
                 relative accuracy $ \mathtt {eps}^K $, and replacing $
                 \mathtt {Res}_K $ by its floating-point neighbors in $
                 \sum \mathtt {Res}_{\nu } $ forms a lower and upper
                 bound for $r$. For a given vector of floating-point
                 numbers with exact sum $s$, we present an algorithm for
                 calculating a $K$-fold faithful rounding of $s$ using
                 solely the working precision. Furthermore, an algorithm
                 for calculating a faithfully rounded result of the sum
                 of a vector of huge dimension is presented. Our
                 algorithms are fast in terms of measured computing time
                 because they allow good instruction-level parallelism,
                 they neither require special operations such as access
                 to mantissa or exponent, they contain no branch in the
                 inner loop, nor do they require some extra precision.
                 The only operations used are standard floating-point
                 addition, subtraction, and multiplication in one
                 working precision, for example, double precision.
                 Certain constants used in the algorithms are proved to
                 be optimal.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation; distillation",
}


bibtype: techreport
filename: fparith.bib
label: Rump:2008:UFA
author: Siegfried M. Rump
title: Ultimately Fast Accurate Summation
type: Technical Report
institution: Institute for Reliable Computing, Technische Universitat Hamburg
address: Hamburg, Germany
pages: 28
day: 19
month: oct
monthnumber: 10
year: 2008
MRclass: 15-04, 65G99, 65-04
bibdate: Sat Oct 25 15:15:14 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.10.25 15:15:14 ???
URL: http://www.ti3.tu-harburg.de/paper/rump/Ru08b.pdf
remark: Submitted for publication.
acknowledgement: ack-nhfb
rawauthor: Siegfried M. Rump
rawtitle: Ultimately Fast Accurate Summation
abstract:
We present two new algorithms FastAccSum and FastPrecSum, one to compute a faithful rounding of the sum of floating-point numbers, and the other for a result ``as if'' computed in $K$-fold precision. Faithful rounding means the result is one of the immediate floating-point neighbors of the exact result, or the exact sum if it is a floating-point number. The algorithms are based on our previous algorithms AccSum and PrecSum and improve them by up to 25%. The first algorithm adapts to the condition number of the sum, i.e., the computing time is proportional to the logarithm of the condition number. The second algorithm does not need extra memory, and the computing time depends only on the dimension and $K$. Both algorithms are the fastest known in terms of flops. They allow good instruction-level parallelism so that they are also fast in terms of measured computing time. The algorithms require only standard floating-point addition, subtraction and multiplication in one working precision, for example double precision.

keywords:
accurate floating-point summation; distillation; error analysis; error-free transformation; faithful rounding; high accuracy; K-fold precision; maximally accurate summation; XBLAS

rawabstract:
We present two new algorithms FastAccSum and FastPrecSum, one to compute a faithful rounding of the sum of floating-point numbers, and the other for a result ``as if'' computed in $K$-fold precision. Faithful rounding means the result is one of the immediate floating-point neighbors of the exact result, or the exact sum if it is a floating-point number. The algorithms are based on our previous algorithms AccSum and PrecSum and improve them by up to 25\%. The first algorithm adapts to the condition number of the sum, i.e., the computing time is proportional to the logarithm of the condition number. The second algorithm does not need extra memory, and the computing time depends only on the dimension and $K$. Both algorithms are the fastest known in terms of flops. They allow good instruction-level parallelism so that they are also fast in terms of measured computing time. The algorithms require only standard floating-point addition, subtraction and multiplication in one working precision, for example double precision.

entry:
@TechReport{Rump:2008:UFA,
  author =       "Siegfried M. Rump",
  title =        "Ultimately Fast Accurate Summation",
  type =         "Technical Report",
  institution =  "Institute for Reliable Computing, Technische
                 Universit{\"a}t Hamburg",
  address =      "Hamburg, Germany",
  pages =        "28",
  day =          "19",
  month =        oct,
  year =         "2008",
  MRclass =      "15-04, 65G99, 65-04",
  bibdate =      "Sat Oct 25 15:15:14 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ti3.tu-harburg.de/paper/rump/Ru08b.pdf",
  abstract =     "We present two new algorithms FastAccSum and
                 FastPrecSum, one to compute a faithful rounding of the
                 sum of floating-point numbers, and the other for a
                 result ``as if'' computed in $K$-fold precision.
                 Faithful rounding means the result is one of the
                 immediate floating-point neighbors of the exact result,
                 or the exact sum if it is a floating-point number. The
                 algorithms are based on our previous algorithms AccSum
                 and PrecSum and improve them by up to 25\%. The first
                 algorithm adapts to the condition number of the sum,
                 i.e., the computing time is proportional to the
                 logarithm of the condition number. The second algorithm
                 does not need extra memory, and the computing time
                 depends only on the dimension and $K$. Both algorithms
                 are the fastest known in terms of flops. They allow
                 good instruction-level parallelism so that they are
                 also fast in terms of measured computing time. The
                 algorithms require only standard floating-point
                 addition, subtraction and multiplication in one working
                 precision, for example double precision.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; distillation; error
                 analysis; error-free transformation; faithful rounding;
                 high accuracy; K-fold precision; maximally accurate
                 summation; XBLAS",
  remark =       "Submitted for publication.",
}


bibtype: article
filename: fparith.bib
label: Russell:2008:BOR
author: Craig Russell
title: Bridging the Object-Relational Divide
journal: j-QUEUE
volume: 6
number: 3
pages: 18--28
month: may
monthnumber: 5
year: 2008
CODEN: AQCUAE
DOI: https://doi.org/10.1145/1394127.1394139
ISSN: 1542-7730 (print), 1542-7749 (electronic) OR 15427730 (print), 15427749 (electronic)
ISSNL: 1542-7730 OR 15427730
bibdate: Tue Aug 5 19:04:31 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.05 19:04:31 MDT
fjournal: ACM Queue: Tomorrow's Computing Today
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J882
rawauthor: Craig Russell
rawtitle: Bridging the Object-Relational Divide
abstract:
ORM technologies can simplify data access, but be aware of the challenges that come with introducing this new layer of abstraction.

rawabstract:
ORM technologies can simplify data access, but be aware of the challenges that come with introducing this new layer of abstraction.

entry:
@Article{Russell:2008:BOR,
  author =       "Craig Russell",
  title =        "Bridging the Object-Relational Divide",
  journal =      j-QUEUE,
  volume =       "6",
  number =       "3",
  pages =        "18--28",
  month =        may # "\slash " # jun,
  year =         "2008",
  CODEN =        "AQCUAE",
  DOI =          "https://doi.org/10.1145/1394127.1394139",
  ISSN =         "1542-7730 (print), 1542-7749 (electronic)",
  ISSN-L =       "1542-7730",
  bibdate =      "Tue Aug 5 19:04:31 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "ORM technologies can simplify data access, but be
                 aware of the challenges that come with introducing this
                 new layer of abstraction.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Queue: Tomorrow's Computing Today",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J882",
}


bibtype: article
filename: fparith.bib
label: Schreppers:2008:ACC
author: Walter Schreppers and Annie Cuyt
title: Algorithm 871: a C / C++ precompiler for autogeneration of multiprecision programs
journal: j-TOMS
volume: 34
number: 1
pages: 5:1--5:20
month: jan
monthnumber: 1
year: 2008
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1322436.1322441
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Mar 12 17:39:58 MDT 2008
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.03.12 17:39:58 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 5
journalURL: https://dl.acm.org/loi/toms
rawauthor: Walter Schreppers and Annie Cuyt
rawtitle: {Algorithm 871}: a {C\slash C++} precompiler for autogeneration of multiprecision programs
abstract:
In the past decade a number of libraries for multiprecision floating-point arithmetic have been developed. We describe an easy to use, generic C/C++ transcription program or precompiler for the conversion of C or C++ source code into new code that uses a C++ multiprecision library of choice. The precompiler can convert any type in the input source code to another type in the output source code. The input source can be either C or C++, while the output code generated by the precompiler and using the new types, is C++. The type conversion is based on a simple XML configuration file which is provided by either the developer of the multiprecision library or by the user of the precompiler. The precompiler can also convert to data types with additional features, which are not supported in the types of the source code. Applicability of the precompiler is shown with the successful conversion of large subsets of the GNU Scientific Library and Numerical Recipes.

rawabstract:
In the past decade a number of libraries for multiprecision floating-point arithmetic have been developed. We describe an easy to use, generic C/C++ transcription program or precompiler for the conversion of C or C++ source code into new code that uses a C++ multiprecision library of choice. The precompiler can convert any type in the input source code to another type in the output source code. The input source can be either C or C++, while the output code generated by the precompiler and using the new types, is C++. The type conversion is based on a simple XML configuration file which is provided by either the developer of the multiprecision library or by the user of the precompiler. The precompiler can also convert to data types with additional features, which are not supported in the types of the source code. Applicability of the precompiler is shown with the successful conversion of large subsets of the GNU Scientific Library and Numerical Recipes.

entry:
@Article{Schreppers:2008:ACC,
  author =       "Walter Schreppers and Annie Cuyt",
  title =        "{Algorithm 871}: a {C\slash C++} precompiler for
                 autogeneration of multiprecision programs",
  journal =      j-TOMS,
  volume =       "34",
  number =       "1",
  pages =        "5:1--5:20",
  month =        jan,
  year =         "2008",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1322436.1322441",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Mar 12 17:39:58 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the past decade a number of libraries for
                 multiprecision floating-point arithmetic have been
                 developed. We describe an easy to use, generic C/C++
                 transcription program or precompiler for the conversion
                 of C or C++ source code into new code that uses a C++
                 multiprecision library of choice. The precompiler can
                 convert any type in the input source code to another
                 type in the output source code. The input source can be
                 either C or C++, while the output code generated by the
                 precompiler and using the new types, is C++. The type
                 conversion is based on a simple XML configuration file
                 which is provided by either the developer of the
                 multiprecision library or by the user of the
                 precompiler. The precompiler can also convert to data
                 types with additional features, which are not supported
                 in the types of the source code. Applicability of the
                 precompiler is shown with the successful conversion of
                 large subsets of the GNU Scientific Library and
                 Numerical Recipes.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: misc
filename: fparith.bib
label: Steele:2008:FPA
author: Guy L. Steele Jr.
title: Floating point adder with embedded status information
pages: 5:1--5:20
day: 29
month: apr
monthnumber: 4
year: 2008
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7366749/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7366749
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point adder with embedded status information
abstract:
A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data with the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the sum of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

rawabstract:
A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data with the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the sum of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

entry:
@Misc{Steele:2008:FPA,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point adder with embedded status
                 information",
  howpublished = "US Patent 7366749",
  day =          "29",
  month =        apr,
  year =         "2008",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7366749/fulltext.html",
  abstract =     "A system for providing a floating point sum includes
                 an analyzer circuit configured to determine a first
                 status of a first floating point operand and a second
                 status of a second floating point operand based upon
                 data within the first floating point operand and data
                 with the second floating point operand respectively. In
                 addition, the system includes a results circuit coupled
                 to the analyzer circuit. The results circuit is
                 configured to assert a resulting floating point operand
                 containing the sum of the first floating point operand
                 and the second floating point operand and a resulting
                 status embedded within the resulting floating point
                 operand.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2008:FPD
author: Guy L. Steele Jr.
title: Floating point divider with embedded status information
pages: 5:1--5:20
day: 22
month: apr
monthnumber: 4
year: 2008
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7363337/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7363337
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point divider with embedded status information
abstract:
A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the result of the division of the first floating point operand by the second floating point operand. Additionally, the results circuit provides resulting status embedded within the resulting floating point operand.

rawabstract:
A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the result of the division of the first floating point operand by the second floating point operand. Additionally, the results circuit provides resulting status embedded within the resulting floating point operand.

entry:
@Misc{Steele:2008:FPD,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point divider with embedded status
                 information",
  howpublished = "US Patent 7363337",
  day =          "22",
  month =        apr,
  year =         "2008",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7363337/fulltext.html",
  abstract =     "A system for providing floating point division
                 includes an analyzer circuit configured to determine a
                 first status of a first floating point operand and a
                 second status of a second floating point operand based
                 upon data within the first floating point operand and
                 data within the second floating point operand
                 respectively. In addition, the system includes a
                 results circuit coupled to the analyzer circuit. The
                 results circuit is configured to assert a resulting
                 floating point operand containing the result of the
                 division of the first floating point operand by the
                 second floating point operand. Additionally, the
                 results circuit provides resulting status embedded
                 within the resulting floating point operand.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2008:FPSa
author: Guy L. Steele Jr.
title: Floating point status information accumulation circuit
pages: 5:1--5:20
day: 28
month: oct
monthnumber: 10
year: 2008
bibdate: Tue Dec 23 15:05:52 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:05:52 ???
URL: http://www.patentstorm.us/patents/7444367/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7444367
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point status information accumulation circuit
abstract:
A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating point operands and provides an indication of one or more predetermined formats in which the plurality of floating point operands are represented. The result assembler receives the indication from the analysis circuit and assembles an accumulated result that represents a value and combines the encoded status flag information from at least two of the plurality of floating point operands.

rawabstract:
A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating point operands and provides an indication of one or more predetermined formats in which the plurality of floating point operands are represented. The result assembler receives the indication from the analysis circuit and assembles an accumulated result that represents a value and combines the encoded status flag information from at least two of the plurality of floating point operands.

entry:
@Misc{Steele:2008:FPSa,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point status information accumulation
                 circuit",
  howpublished = "US Patent 7444367",
  day =          "28",
  month =        oct,
  year =         "2008",
  bibdate =      "Tue Dec 23 15:05:52 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7444367/fulltext.html",
  abstract =     "A floating point flag combining or accumulating
                 circuit includes an analysis circuit that receives a
                 plurality of floating point operands, each having
                 encoded status flag information, and a result
                 assembler. The analysis circuit analyzes the plurality
                 of floating point operands and provides an indication
                 of one or more predetermined formats in which the
                 plurality of floating point operands are represented.
                 The result assembler receives the indication from the
                 analysis circuit and assembles an accumulated result
                 that represents a value and combines the encoded status
                 flag information from at least two of the plurality of
                 floating point operands.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2008:FPSb
author: Guy L. Steele Jr.
title: Floating point square root provider with embedded status information
pages: 5:1--5:20
day: 30
month: sep
monthnumber: 9
year: 2008
bibdate: Tue Dec 23 15:06:43 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:43 ???
URL: http://www.patentstorm.us/patents/7430576/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7430576
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point square root provider with embedded status information
abstract:
A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

rawabstract:
A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

entry:
@Misc{Steele:2008:FPSb,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point square root provider with embedded
                 status information",
  howpublished = "US Patent 7430576",
  day =          "30",
  month =        sep,
  year =         "2008",
  bibdate =      "Tue Dec 23 15:06:43 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7430576/fulltext.html",
  abstract =     "A system for providing a floating point square root
                 comprises an analyzer circuit configured to determine a
                 first status of a first floating point operand based
                 upon data within the first floating point operand. In
                 addition, the system comprises a results circuit
                 coupled to the analyzer circuit. The results circuit is
                 configured to assert a resulting floating point operand
                 containing the square root of the first floating point
                 operand and a resulting status embedded within the
                 resulting floating point operand.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2008:FPSc
author: Guy L. Steele Jr.
title: Floating point system that represents status flag information within a floating point operand
pages: 5:1--5:20
day: 01
month: jul
monthnumber: 7
year: 2008
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7395297/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7395297
rawauthor: Guy L. {Steele Jr.}
rawtitle: Floating point system that represents status flag information within a floating point operand
abstract:
A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure includes a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register. The second portion of the data structure may also have at least one bit indicative of the status condition, such as an invalid operation status, an overflow status, an underflow status, a division by zero status, an infinity status, and an inexact status.

rawabstract:
A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure includes a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register. The second portion of the data structure may also have at least one bit indicative of the status condition, such as an invalid operation status, an overflow status, an underflow status, a division by zero status, an infinity status, and an inexact status.

entry:
@Misc{Steele:2008:FPSc,
  author =       "Guy L. {Steele Jr.}",
  title =        "Floating point system that represents status flag
                 information within a floating point operand",
  howpublished = "US Patent 7395297",
  day =          "01",
  month =        jul,
  year =         "2008",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7395297/fulltext.html",
  abstract =     "A floating point unit generates results in which
                 status information generated for an operation is
                 encoded within the resulting operand, instead of
                 requiring a separate floating point status register for
                 the status information. In one embodiment, a floating
                 point operand data structure includes a first portion
                 having floating point operand data and a second portion
                 having embedded status information associated with at
                 least one status condition of the operand data. The
                 status condition may be determined from only the
                 embedded status information. The status condition may
                 also be associated with at least one floating point
                 operation that generated the operand data structure.
                 The outcome of a conditional floating point instruction
                 may be based on the embedded status information without
                 regard to contents of the floating point status
                 register. The second portion of the data structure may
                 also have at least one bit indicative of the status
                 condition, such as an invalid operation status, an
                 overflow status, an underflow status, a division by
                 zero status, an infinity status, and an inexact
                 status.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sun:2008:HPM
author: Junqing Sun and G. D. Peterson and O. O. Storaasli
title: High-Performance Mixed-Precision Linear Solver for FPGAs
journal: j-IEEE-TRANS-COMPUT
volume: 57
number: 12
pages: 1614--1623
month: dec
monthnumber: 12
year: 2008
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.89
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 12:17:44 MDT 2011
bibtimestamp: 2011.07.04 12:17:44 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4531732
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Junqing Sun and G. D. Peterson and O. O. Storaasli
rawtitle: High-Performance Mixed-Precision Linear Solver for {FPGAs}
entry:
@Article{Sun:2008:HPM,
  author =       "Junqing Sun and G. D. Peterson and O. O. Storaasli",
  title =        "High-Performance Mixed-Precision Linear Solver for
                 {FPGAs}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "57",
  number =       "12",
  pages =        "1614--1623",
  month =        dec,
  year =         "2008",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.89",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 12:17:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4531732",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Terauds:2008:CFP
author: Maris Terauds and Gatis Valters and Uldis Derums and Nauris Vasilevskis and Peteris Misans
booktitle: 2008 NORCHIP
title: Comparison of Fixed-Point Arithmetic Errors for the FPGA-based CRAIMOT Basis Function Generators
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 108--113
year: 2008
DOI: https://doi.org/10.1109/NORCHP.2008.4738293
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Maris Terauds and Gatis Valters and Uldis Derums and Nauris Vasilevskis and Peteris Misans
rawbooktitle: {2008 NORCHIP}
keywords:
Algorithm design and analysis; CORDIC algorithm; Discrete cosine transforms; Error analysis; Field programmable gate arrays; Fixed-point arithmetic; Fixed-point errors; FPGA; Generation of basis functions; Interpolation; Quantization; Signal generators; Signal synthesis; Speech synthesis

rawtitle:
Comparison of Fixed-Point Arithmetic Errors for the {FPGA}-based {CRAIMOT} Basis Function Generators

entry:
@InProceedings{Terauds:2008:CFP,
  author =       "Maris Terauds and Gatis Valters and Uldis Derums and
                 Nauris Vasilevskis and Peteris Misans",
  booktitle =    "{2008 NORCHIP}",
  title =        "Comparison of Fixed-Point Arithmetic Errors for the
                 {FPGA}-based {CRAIMOT} Basis Function Generators",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "108--113",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/NORCHP.2008.4738293",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; CORDIC algorithm;
                 Discrete cosine transforms; Error analysis; Field
                 programmable gate arrays; Fixed-point arithmetic;
                 Fixed-point errors; FPGA; Generation of basis
                 functions; Interpolation; Quantization; Signal
                 generators; Signal synthesis; Speech synthesis",
}


bibtype: article
filename: fparith.bib
label: Thill:2008:EMP
author: M. Thill
title: Erratum: a more precise rounding algorithm for rational numbers
journal: j-COMPUTING
volume: 82
number: 4
pages: 261--262
month: sep
monthnumber: 9
year: 2008
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-008-0013-8
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Sun Oct 31 11:09:49 MDT 2010
bibtimestamp: 2010.10.31 11:09:49 MDT
note: See cite Thill:2008:MPR.
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=82&issue=4&spage=261
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: M. Thill
rawnote: See \cite{Thill:2008:MPR}.
rawtitle: Erratum: a more precise rounding algorithm for rational numbers
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=82&issue=4; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Thill:2008:EMP,
  author =       "M. Thill",
  title =        "Erratum: a more precise rounding algorithm for
                 rational numbers",
  journal =      j-COMPUTING,
  volume =       "82",
  number =       "4",
  pages =        "261--262",
  month =        sep,
  year =         "2008",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-008-0013-8",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Sun Oct 31 11:09:49 MDT 2010",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=82&issue=4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Thill:2008:MPR}.",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=82&issue=4&spage=261",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
}


bibtype: article
filename: fparith.bib
label: Thill:2008:MPR
author: M. Thill
title: A more precise rounding algorithm for rational numbers
journal: j-COMPUTING
volume: 82
number: 2--3
pages: 189--198
month: jul
monthnumber: 7
year: 2008
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-008-0006-7
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Sun Oct 31 11:09:47 MDT 2010
bibtimestamp: 2010.10.31 11:09:47 MDT
note: See erratum cite Thill:2008:EMP.
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=82&issue=2&spage=189
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: M. Thill
rawnote: See erratum \cite{Thill:2008:EMP}.
rawtitle: A more precise rounding algorithm for rational numbers
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=82&issue=2; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We adjoin a more precise companion to the classical mediant rounding algorithm for rational numbers.

rawabstract:
We adjoin a more precise companion to the classical mediant rounding algorithm for rational numbers.

entry:
@Article{Thill:2008:MPR,
  author =       "M. Thill",
  title =        "A more precise rounding algorithm for rational
                 numbers",
  journal =      j-COMPUTING,
  volume =       "82",
  number =       "2--3",
  pages =        "189--198",
  month =        jul,
  year =         "2008",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-008-0006-7",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Sun Oct 31 11:09:47 MDT 2010",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=82&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See erratum \cite{Thill:2008:EMP}.",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=82&issue=2&spage=189",
  abstract =     "We adjoin a more precise companion to the classical
                 mediant rounding algorithm for rational numbers.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
}


bibtype: article
filename: fparith.bib
label: Tsigaridas:2008:CRR
author: Elias P. Tsigaridas and Ioannis Z. Emiris
title: On the complexity of real root isolation using continued fractions
journal: j-THEOR-COMP-SCI
volume: 392
number: 1--3
pages: 158--173
day: 28
month: feb
monthnumber: 2
year: 2008
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Mon Mar 28 21:49:12 MDT 2011
bibtimestamp: 2011.03.28 21:49:12 MDT
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Elias P. Tsigaridas and Ioannis Z. Emiris
rawtitle: On the complexity of real root isolation using continued fractions
entry:
@Article{Tsigaridas:2008:CRR,
  author =       "Elias P. Tsigaridas and Ioannis Z. Emiris",
  title =        "On the complexity of real root isolation using
                 continued fractions",
  journal =      j-THEOR-COMP-SCI,
  volume =       "392",
  number =       "1--3",
  pages =        "158--173",
  day =          "28",
  month =        feb,
  year =         "2008",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Mon Mar 28 21:49:12 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/03043975;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: VanMeter:2008:ADM
author: Rodney Van Meter and W. J. Munro and Kae Nemoto and Kohei M. Itoh
title: Arithmetic on a distributed-memory quantum multicomputer
journal: j-JETC
volume: 3
number: 4
pages: 2:1--2:??
month: jan
monthnumber: 1
year: 2008
DOI: https://doi.org/10.1145/1324177.1324179
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Fri Jun 20 11:04:00 MDT 2008
bibsource: http://www.acm.org/pubs/contents/journals/jetc/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 11:04:00 MDT
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
keywords: quantum computer architecture; Quantum computing
acknowledgement: ack-nhfb
articleno: 2
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J967
rawauthor: Rodney {Van Meter} and W. J. Munro and Kae Nemoto and Kohei M. Itoh
rawtitle: Arithmetic on a distributed-memory quantum multicomputer
abstract:
We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and the network topology. The tradeoff of choosing between gates executed remotely, through ``teleported gates'' on entangled pairs of qubits (telegate), versus exchanging the relevant qubits via quantum teleportation, then executing the algorithm using local gates (teledata), is examined. We show that the teledata approach performs better, and that carry-ripple adders perform well when the teleportation block is decomposed so that the key quantum operations can be parallelized. A node size of only a few logical qubits performs adequately provided that the nodes have two transceiver qubits. A linear network topology performs acceptably for a broad range of system sizes and performance parameters. We therefore recommend pursuing small, high-I/O bandwidth nodes and a simple network. Such a machine will run Shor's algorithm for factoring large numbers efficiently.

rawabstract:
We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and the network topology. The tradeoff of choosing between gates executed remotely, through ``teleported gates'' on entangled pairs of qubits (telegate), versus exchanging the relevant qubits via quantum teleportation, then executing the algorithm using local gates (teledata), is examined. We show that the teledata approach performs better, and that carry-ripple adders perform well when the teleportation block is decomposed so that the key quantum operations can be parallelized. A node size of only a few logical qubits performs adequately provided that the nodes have two transceiver qubits. A linear network topology performs acceptably for a broad range of system sizes and performance parameters. We therefore recommend pursuing small, high-I/O bandwidth nodes and a simple network. Such a machine will run Shor's algorithm for factoring large numbers efficiently.

entry:
@Article{VanMeter:2008:ADM,
  author =       "Rodney {Van Meter} and W. J. Munro and Kae Nemoto and
                 Kohei M. Itoh",
  title =        "Arithmetic on a distributed-memory quantum
                 multicomputer",
  journal =      j-JETC,
  volume =       "3",
  number =       "4",
  pages =        "2:1--2:??",
  month =        jan,
  year =         "2008",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1324177.1324179",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We evaluate the performance of quantum arithmetic
                 algorithms run on a distributed quantum computer (a
                 quantum multicomputer). We vary the node capacity and
                 I/O capabilities, and the network topology. The
                 tradeoff of choosing between gates executed remotely,
                 through ``teleported gates'' on entangled pairs of
                 qubits (telegate), versus exchanging the relevant
                 qubits via quantum teleportation, then executing the
                 algorithm using local gates (teledata), is examined. We
                 show that the teledata approach performs better, and
                 that carry-ripple adders perform well when the
                 teleportation block is decomposed so that the key
                 quantum operations can be parallelized. A node size of
                 only a few logical qubits performs adequately provided
                 that the nodes have two transceiver qubits. A linear
                 network topology performs acceptably for a broad range
                 of system sizes and performance parameters. We
                 therefore recommend pursuing small, high-I/O bandwidth
                 nodes and a simple network. Such a machine will run
                 Shor's algorithm for factoring large numbers
                 efficiently.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "quantum computer architecture; Quantum computing",
}


bibtype: article
filename: fparith.bib
label: Webb:2008:IZN
author: Charles F. Webb
title: IBM z10: The Next-Generation Mainframe Microprocessor
journal: j-IEEE-MICRO
volume: 28
number: 2
pages: 19--29
month: mar
monthnumber: 3
year: 2008
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2008.26
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Wed Jul 2 21:58:04 MDT 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.02 21:58:04 MDT
fjournal: IEEE Micro
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: Charles F. Webb
rawtitle: {IBM z10}: The Next-Generation Mainframe Microprocessor
abstract:
The IBM system z10 includes four microprocessor cores --- each with a private 3-Mbyte cache --- and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.

rawabstract:
The IBM system z10 includes four microprocessor cores --- each with a private 3-Mbyte cache --- and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.

entry:
@Article{Webb:2008:IZN,
  author =       "Charles F. Webb",
  title =        "{IBM z10}: The Next-Generation Mainframe
                 Microprocessor",
  journal =      j-IEEE-MICRO,
  volume =       "28",
  number =       "2",
  pages =        "19--29",
  month =        mar # "\slash " # apr,
  year =         "2008",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2008.26",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Jul 2 21:58:04 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IBM system z10 includes four microprocessor cores
                 --- each with a private 3-Mbyte cache --- and
                 integrated accelerators for decimal floating-point
                 computation, cryptography, and data compression. A
                 separate SMP hub chip provides a shared third-level
                 cache and interconnect fabric for multiprocessor
                 scaling. This article focuses on the high-frequency
                 design techniques used to achieve a 4.4-GHz system, and
                 on the pipeline design that optimizes z10's CPU
                 performance.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: techreport
filename: fparith.bib
label: Wirth:2008:ND
author: Niklaus Wirth
title: A Note on Division
type: Note
institution: inst-ETH
address: inst-ETH:adr
pages: 4
day: 20
month: aug
monthnumber: 8
year: 2008
bibdate: Tue Jan 09 07:42:36 2024
bibtimestamp: 2024.01.09 07:42:36 ???
URL: https://people.inf.ethz.ch/wirth/Miscellaneous/Division.pdf
acknowledgement: ack-nhfb
authordates: Niklaus Wirth (15 February 1934--1 January 2024)
rawauthor: Niklaus Wirth
rawtitle: A Note on Division
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/w/wirth-niklaus.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@TechReport{Wirth:2008:ND,
  author =       "Niklaus Wirth",
  title =        "A Note on Division",
  type =         "Note",
  institution =  inst-ETH,
  address =      inst-ETH:adr,
  pages =        "4",
  day =          "20",
  month =        aug,
  year =         "2008",
  bibdate =      "Tue Jan 09 07:42:36 2024",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/w/wirth-niklaus.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://people.inf.ethz.ch/wirth/Miscellaneous/Division.pdf",
  acknowledgement = ack-nhfb,
  author-dates = "Niklaus Wirth (15 February 1934--1 January 2024)",
}


bibtype: article
filename: fparith.bib
label: Yamanaka:2008:PAA
author: Naoya Yamanaka and Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
title: A parallel algorithm for accurate dot product
journal: j-PARALLEL-COMPUTING
volume: 34
number: 6--8
pages: 392--410
month: jul
monthnumber: 7
year: 2008
CODEN: PACOEJ
DOI: https://doi.org/10.1016/j.parco.2008.02.002
ISSN: 0167-8191 (print), 1872-7336 (electronic) OR 01678191 (print), 18727336 (electronic)
ISSNL: 0167-8191 OR 01678191
bibdate: Thu Sep 2 17:51:09 MDT 2010
bibtimestamp: 2010.09.02 17:51:09 MDT
fjournal: Parallel Computing
remark: See cite Ogita:2005:ASD for the cited paper.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01678191
rawauthor: Naoya Yamanaka and Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
rawtitle: A parallel algorithm for accurate dot product
bibsource:
http://www.sciencedirect.com/science/journal/01678191; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Parallel algorithms for accurate summation and dot product are proposed. They are parallelized versions of fast and accurate algorithms of calculating sum and dot product using error-free transformations which are recently proposed by Ogita et al. [T. Ogita, S. M. Rump, S. Oishi, Accurate sum and dot product, SIAM J. Sci. Comput. 26(6) (2005) 1955--1988]. They have shown their algorithms are fast in terms of measured computing time. However, due to the strong data dependence in the process of their algorithms, it is difficult to parallelize them. Similarly to their algorithms, the proposed parallel algorithms in this paper are designed to achieve the results as if computed in K-fold working precision with keeping the fastness of their algorithms. Numerical results are presented showing the performance of the proposed parallel algorithm of calculating dot product.

keywords:
accurate dot product; accurate summation; DotK; higher precision; parallel algorithm; PDotK; PSumK; SumK

rawabstract:
Parallel algorithms for accurate summation and dot product are proposed. They are parallelized versions of fast and accurate algorithms of calculating sum and dot product using error-free transformations which are recently proposed by Ogita et al. [T. Ogita, S. M. Rump, S. Oishi, Accurate sum and dot product, SIAM J. Sci. Comput. 26(6) (2005) 1955--1988]. They have shown their algorithms are fast in terms of measured computing time. However, due to the strong data dependence in the process of their algorithms, it is difficult to parallelize them. Similarly to their algorithms, the proposed parallel algorithms in this paper are designed to achieve the results as if computed in K-fold working precision with keeping the fastness of their algorithms. Numerical results are presented showing the performance of the proposed parallel algorithm of calculating dot product.

entry:
@Article{Yamanaka:2008:PAA,
  author =       "Naoya Yamanaka and Takeshi Ogita and Siegfried M. Rump
                 and Shin'ichi Oishi",
  title =        "A parallel algorithm for accurate dot product",
  journal =      j-PARALLEL-COMPUTING,
  volume =       "34",
  number =       "6--8",
  pages =        "392--410",
  month =        jul,
  year =         "2008",
  CODEN =        "PACOEJ",
  DOI =          "https://doi.org/10.1016/j.parco.2008.02.002",
  ISSN =         "0167-8191 (print), 1872-7336 (electronic)",
  ISSN-L =       "0167-8191",
  bibdate =      "Thu Sep 2 17:51:09 MDT 2010",
  bibsource =    "http://www.sciencedirect.com/science/journal/01678191;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Parallel algorithms for accurate summation and dot
                 product are proposed. They are parallelized versions of
                 fast and accurate algorithms of calculating sum and dot
                 product using error-free transformations which are
                 recently proposed by Ogita et al. [T. Ogita, S. M.
                 Rump, S. Oishi, Accurate sum and dot product, SIAM J.
                 Sci. Comput. 26(6) (2005) 1955--1988]. They have shown
                 their algorithms are fast in terms of measured
                 computing time. However, due to the strong data
                 dependence in the process of their algorithms, it is
                 difficult to parallelize them. Similarly to their
                 algorithms, the proposed parallel algorithms in this
                 paper are designed to achieve the results as if
                 computed in K-fold working precision with keeping the
                 fastness of their algorithms. Numerical results are
                 presented showing the performance of the proposed
                 parallel algorithm of calculating dot product.",
  acknowledgement = ack-nhfb,
  fjournal =     "Parallel Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01678191",
  keywords =     "accurate dot product; accurate summation; DotK; higher
                 precision; parallel algorithm; PDotK; PSumK; SumK",
  remark =       "See \cite{Ogita:2005:ASD} for the cited paper.",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhou:2008:DCF
author: Jie Zhou and Yazhuo Dong and Yong Dou and Yuanwu Lei
booktitle: 2008 International Conference on Embedded Software and Systems
title: Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 616--620
year: 2008
DOI: https://doi.org/10.1109/ICESS.2008.95
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Jie Zhou and Yazhuo Dong and Yong Dou and Yuanwu Lei
rawbooktitle: {2008 International Conference on Embedded Software and Systems}
rawtitle: Dynamic Configurable Floating-Point {FFT} Pipelines and Hybrid-Mode {CORDIC} on {FPGA}
keywords:
Azimuth; Clocks; CORDIC; Dynamic configurable pipeline; FFT; Field programmable gate arrays; Floating-point; FPGA; Lead; Pipelines; Process control; Table lookup

entry:
@InProceedings{Zhou:2008:DCF,
  author =       "Jie Zhou and Yazhuo Dong and Yong Dou and Yuanwu Lei",
  booktitle =    "{2008 International Conference on Embedded Software
                 and Systems}",
  title =        "Dynamic Configurable Floating-Point {FFT} Pipelines
                 and Hybrid-Mode {CORDIC} on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "616--620",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/ICESS.2008.95",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Azimuth; Clocks; CORDIC; Dynamic configurable
                 pipeline; FFT; Field programmable gate arrays;
                 Floating-point; FPGA; Lead; Pipelines; Process control;
                 Table lookup",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhou:2008:DPH
author: Jie Zhou and Yong Dou and Yuanwu Lei and Jinbo Xu and Yazhuo Dong
booktitle: 2008 10th IEEE International Conference on High Performance Computing and Communications
title: Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 182--189
year: 2008
DOI: https://doi.org/10.1109/HPCC.2008.14
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Jie Zhou and Yong Dou and Yuanwu Lei and Jinbo Xu and Yazhuo Dong
rawbooktitle: {2008 10th IEEE International Conference on High Performance Computing and Communications}
rawtitle: Double Precision Hybrid-Mode Floating-Point {FPGA} {CORDIC} Co-processor
keywords:
Algorithm design and analysis; Convergence; CORDIC; double precision; Equations; Field programmable gate arrays; floating-point; FPGA; Hardware; hybrid-mode; Mathematical model; Pipelines

entry:
@InProceedings{Zhou:2008:DPH,
  author =       "Jie Zhou and Yong Dou and Yuanwu Lei and Jinbo Xu and
                 Yazhuo Dong",
  booktitle =    "{2008 10th IEEE International Conference on High
                 Performance Computing and Communications}",
  title =        "Double Precision Hybrid-Mode Floating-Point {FPGA}
                 {CORDIC} Co-processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "182--189",
  year =         "2008",
  DOI =          "https://doi.org/10.1109/HPCC.2008.14",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; Convergence; CORDIC;
                 double precision; Equations; Field programmable gate
                 arrays; floating-point; FPGA; Hardware; hybrid-mode;
                 Mathematical model; Pipelines",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhou:2008:HMF
author: Jie Zhou and Yong Dou and Yuanwu Lei and Yazhuo Dong
title: Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
crossref: Woods:2008:RCA
pages: 256--261
year: 2008
DOI: https://doi.org/10.1007/978-3-540-78610-8_25
bibdate: Tue Oct 28 07:04:09 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.28 07:04:09 ???
acknowledgement: ack-nhfb
rawauthor: Jie Zhou and Yong Dou and Yuanwu Lei and Yazhuo Dong
rawtitle: Hybrid-Mode Floating-Point {FPGA} {CORDIC} Co-processor
entry:
@InProceedings{Zhou:2008:HMF,
  author =       "Jie Zhou and Yong Dou and Yuanwu Lei and Yazhuo Dong",
  title =        "Hybrid-Mode Floating-Point {FPGA} {CORDIC}
                 Co-processor",
  crossref =     "Woods:2008:RCA",
  pages =        "256--261",
  year =         "2008",
  DOI =          "https://doi.org/10.1007/978-3-540-78610-8_25",
  bibdate =      "Tue Oct 28 07:04:09 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Adikari:2009:HBT
author: Jithra Adikari and Vassil Dimitrov and Laurent Imbert
title: Hybrid Binary-Ternary Joint Form and Its Application in Elliptic Curve Cryptography
crossref: Bruguera:2009:PIS
pages: 76--83
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Jithra Adikari and Vassil Dimitrov and Laurent Imbert
rawtitle: Hybrid Binary-Ternary Joint Form and Its Application in Elliptic Curve Cryptography
abstract:
Multi-exponentiation is a common and time consuming operation in public-key cryptography. Its elliptic curve counterpart, called multi-scalar multiplication is extensively used for digital signature verification. Several algorithms have been proposed to speed-up those critical computations. They are based on simultaneously recoding a set of integers in order to minimize the number of general multiplications or point additions. When signed-digit recoding techniques can be used, as in the world of elliptic curves, Joint Sparse Form (JSF) and interleaving w-NAF are the most efficient algorithms. In this paper, a novel recoding algorithm for a pair of integers is proposed, based on a decomposition that mixes powers of 2 and powers of 3. The so-called Hybrid Binary-Ternary Joint Form require fewer digits and is sparser than the JSF and the interleaving w-NAF. Its advantages are illustrated for elliptic curve double-scalar multiplication; the operation counts show a gain of up to 19%.

rawabstract:
Multi-exponentiation is a common and time consuming operation in public-key cryptography. Its elliptic curve counterpart, called multi-scalar multiplication is extensively used for digital signature verification. Several algorithms have been proposed to speed-up those critical computations. They are based on simultaneously recoding a set of integers in order to minimize the number of general multiplications or point additions. When signed-digit recoding techniques can be used, as in the world of elliptic curves, Joint Sparse Form (JSF) and interleaving w-NAF are the most efficient algorithms. In this paper, a novel recoding algorithm for a pair of integers is proposed, based on a decomposition that mixes powers of 2 and powers of 3. The so-called Hybrid Binary-Ternary Joint Form require fewer digits and is sparser than the JSF and the interleaving w-NAF. Its advantages are illustrated for elliptic curve double-scalar multiplication; the operation counts show a gain of up to 19\%.

entry:
@InProceedings{Adikari:2009:HBT,
  author =       "Jithra Adikari and Vassil Dimitrov and Laurent
                 Imbert",
  title =        "Hybrid Binary-Ternary Joint Form and Its Application
                 in Elliptic Curve Cryptography",
  crossref =     "Bruguera:2009:PIS",
  pages =        "76--83",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Multi-exponentiation is a common and time consuming
                 operation in public-key cryptography. Its elliptic
                 curve counterpart, called multi-scalar multiplication
                 is extensively used for digital signature verification.
                 Several algorithms have been proposed to speed-up those
                 critical computations. They are based on simultaneously
                 recoding a set of integers in order to minimize the
                 number of general multiplications or point additions.
                 When signed-digit recoding techniques can be used, as
                 in the world of elliptic curves, Joint Sparse Form
                 (JSF) and interleaving w-NAF are the most efficient
                 algorithms. In this paper, a novel recoding algorithm
                 for a pair of integers is proposed, based on a
                 decomposition that mixes powers of 2 and powers of 3.
                 The so-called Hybrid Binary-Ternary Joint Form require
                 fewer digits and is sparser than the JSF and the
                 interleaving w-NAF. Its advantages are illustrated for
                 elliptic curve double-scalar multiplication; the
                 operation counts show a gain of up to 19\%.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: inproceedings
filename: fparith.bib
label: Amaricai:2009:DFP
author: A. Amaricai and M. Vladutiu and O. Boncalo
title: Design of floating point units for interval arithmetic
crossref: IEEE:2009:PDR
pages: 76--83
year: 2009
DOI: https://doi.org/10.1109/RME.2009.5201307
bibdate: Thu Mar 24 21:37:47 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.24 21:37:47 ???
acknowledgement: ack-nhfb
rawauthor: A. Amaricai and M. Vladutiu and O. Boncalo
rawtitle: Design of floating point units for interval arithmetic
abstract:
In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.

rawabstract:
In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.

entry:
@InProceedings{Amaricai:2009:DFP,
  author =       "A. Amaricai and M. Vladutiu and O. Boncalo",
  title =        "Design of floating point units for interval
                 arithmetic",
  crossref =     "IEEE:2009:PDR",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/RME.2009.5201307",
  bibdate =      "Thu Mar 24 21:37:47 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, hardware units for interval addition,
                 multiplication and divide-add fused are presented.
                 Regarding interval addition, a new architecture of
                 double path adder, is presented. This architecture
                 exploits the parallel structure of double path adder.
                 Regarding multiplication, the proposed architecture is
                 based on a dual result multiplier (floating point
                 multiplication unit with two differently rounded
                 results for the same pair of operands) and two floating
                 point comparators. The goal of the divide-add fused
                 unit is to increase the performance of the interval
                 Newton's method. Algorithm and architecture for this
                 operation, inspired by the ones used for multiply-add
                 fused, are proposed.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anderson:2009:PAD
crossref: IEEE:2009:IICb
pages: 465--471
year: 2009
DOI: https://doi.org/10.1109/ICCD.2009.5413114
bibdate: Thu Feb 17 08:05:14 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:05:14 ???
acknowledgement: ack-nhfb
author:
Michael J. Anderson and Charles Tsen and Liang-Kai Wang and Katherine Compton and Michael J. Schulte

title:
Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions

abstract:
The IEEE Standards Committee recently approved the IEEE 754-2008 Standard for Floating-point Arithmetic, which includes specifications for decimal floating-point (DFP) arithmetic. A growing number of DFP solutions have emerged, and developers now have many DFP design choices including arbitrary or fixed precision, binary or decimal significand encodings, 64-bit or 128-bit DFP operands, and software or hardware implementations.par There is a need for accurate analysis of these solutions on representative DFP benchmarks. In this paper, we expand previous DFP benchmark and performance analysis research. We employ a DFP benchmark suite that currently supports several DFP solutions and is easily extendable. We also present performance analysis that (1) provides execution profiles for various DFP encodings and types, (2) gives the average number cycles for common DFP operations and the total number of each DFP operation in each benchmark, and (3) highlights the tradeoffs between using 64-bit and 128-bit DFP operands for both binary and decimal significand encodings. This analysis can help guide the design of future DFP hardware and software solutions.

keywords:
binary significand encodings; decimal floating-point arithmetic; decimal floating-point libraries; decimal significand encodings; DFP encodings; DFP hardware solutions; DFP operands; DFP software solutions; IEEE 754-2008 standard; IEEE Standards Committee; performance analysis

rawabstract:
The IEEE Standards Committee recently approved the IEEE 754-2008 Standard for Floating-point Arithmetic, which includes specifications for decimal floating-point (DFP) arithmetic. A growing number of DFP solutions have emerged, and developers now have many DFP design choices including arbitrary or fixed precision, binary or decimal significand encodings, 64-bit or 128-bit DFP operands, and software or hardware implementations.\par There is a need for accurate analysis of these solutions on representative DFP benchmarks. In this paper, we expand previous DFP benchmark and performance analysis research. We employ a DFP benchmark suite that currently supports several DFP solutions and is easily extendable. We also present performance analysis that (1) provides execution profiles for various DFP encodings and types, (2) gives the average number cycles for common DFP operations and the total number of each DFP operation in each benchmark, and (3) highlights the tradeoffs between using 64-bit and 128-bit DFP operands for both binary and decimal significand encodings. This analysis can help guide the design of future DFP hardware and software solutions.

rawauthor:
Michael J. Anderson and Charles Tsen and Liang-Kai Wang and Katherine Compton and Michael J. Schulte

rawtitle:
Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions

entry:
@InProceedings{Anderson:2009:PAD,
  author =       "Michael J. Anderson and Charles Tsen and Liang-Kai
                 Wang and Katherine Compton and Michael J. Schulte",
  title =        "Performance analysis of decimal floating-point
                 libraries and its impact on decimal hardware and
                 software solutions",
  crossref =     "IEEE:2009:IICb",
  pages =        "465--471",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ICCD.2009.5413114",
  bibdate =      "Thu Feb 17 08:05:14 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IEEE Standards Committee recently approved the
                 IEEE 754-2008 Standard for Floating-point Arithmetic,
                 which includes specifications for decimal
                 floating-point (DFP) arithmetic. A growing number of
                 DFP solutions have emerged, and developers now have
                 many DFP design choices including arbitrary or fixed
                 precision, binary or decimal significand encodings,
                 64-bit or 128-bit DFP operands, and software or
                 hardware implementations.\par

                 There is a need for accurate analysis of these
                 solutions on representative DFP benchmarks. In this
                 paper, we expand previous DFP benchmark and performance
                 analysis research. We employ a DFP benchmark suite that
                 currently supports several DFP solutions and is easily
                 extendable. We also present performance analysis that
                 (1) provides execution profiles for various DFP
                 encodings and types, (2) gives the average number
                 cycles for common DFP operations and the total number
                 of each DFP operation in each benchmark, and (3)
                 highlights the tradeoffs between using 64-bit and
                 128-bit DFP operands for both binary and decimal
                 significand encodings. This analysis can help guide the
                 design of future DFP hardware and software solutions.",
  acknowledgement = ack-nhfb,
  keywords =     "binary significand encodings; decimal floating-point
                 arithmetic; decimal floating-point libraries; decimal
                 significand encodings; DFP encodings; DFP hardware
                 solutions; DFP operands; DFP software solutions; IEEE
                 754-2008 standard; IEEE Standards Committee;
                 performance analysis",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2009:AI
author: Anonymous
title: Author Index
crossref: Bruguera:2009:PIS
pages: 235--235
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Author Index
entry:
@InProceedings{Anonymous:2009:AI,
  author =       "Anonymous",
  title =        "Author Index",
  crossref =     "Bruguera:2009:PIS",
  pages =        "235--235",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Anonymous:2009:CPC
author: Anonymous
title: Call-for-Papers on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 5
pages: 719--719
month: may
monthnumber: 5
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.47
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:41 MDT 2011
bibtimestamp: 2011.07.04 11:37:41 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Anonymous
rawtitle: Call-for-Papers on Computer Arithmetic
entry:
@Article{Anonymous:2009:CPC,
  author =       "Anonymous",
  title =        "Call-for-Papers on Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "5",
  pages =        "719--719",
  month =        may,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.47",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2009:DPR
author: Mark G. Arnold and Sylvain Collange
title: A Dual-Purpose Real / Complex Logarithmic Number System ALU
crossref: Bruguera:2009:PIS
pages: 15--24
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19; complex arithmetic; FPGA; hardware function evaluation; logarithmic number system
acknowledgement: ack-nhfb
rawauthor: Mark G. Arnold and Sylvain Collange
rawtitle: A Dual-Purpose Real\slash Complex Logarithmic Number System {ALU}
abstract:
The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higher-order and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented effectively on FPGAs for a wide variety of medium-precision special-purpose applications. The Complex LNS (CLNS) is a generalization of LNS which represents complex values in log-polar form. CLNS is a more compact representation than traditional rectangular methods, reducing the cost of busses and memory in intensive complex-number applications like the FFT; however, prior CLNS implementations were either slow CORDIC-based or expensive 2D-table-based approaches. This paper attempts to leverage the recent advances made in real-valued LNS units for the more specialized context of CLNS. This paper proposes a novel approach to reduce the cost of CLNS addition by re-using a conventional real-valued LNS ALU with specialized CLNS hardware that is smaller than the real-valued LNS ALU to which it is attached. The resulting ALU is much less expensive than prior fast CLNS units at the cost of some extra delay. The extra hardware added to the ALU is for trigonometric-related functions, and may be useful in LNS applications other than CLNS. The novel algorithm proposed here is implemented using the FloPoCo library (which incorporates recent HOTBM advances in function-unit generation), and FPGA synthesis results are reported.

rawabstract:
The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higher-order and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented effectively on FPGAs for a wide variety of medium-precision special-purpose applications. The Complex LNS (CLNS) is a generalization of LNS which represents complex values in log-polar form. CLNS is a more compact representation than traditional rectangular methods, reducing the cost of busses and memory in intensive complex-number applications like the FFT; however, prior CLNS implementations were either slow CORDIC-based or expensive 2D-table-based approaches. This paper attempts to leverage the recent advances made in real-valued LNS units for the more specialized context of CLNS. This paper proposes a novel approach to reduce the cost of CLNS addition by re-using a conventional real-valued LNS ALU with specialized CLNS hardware that is smaller than the real-valued LNS ALU to which it is attached. The resulting ALU is much less expensive than prior fast CLNS units at the cost of some extra delay. The extra hardware added to the ALU is for trigonometric-related functions, and may be useful in LNS applications other than CLNS. The novel algorithm proposed here is implemented using the FloPoCo library (which incorporates recent HOTBM advances in function-unit generation), and FPGA synthesis results are reported.

entry:
@InProceedings{Arnold:2009:DPR,
  author =       "Mark G. Arnold and Sylvain Collange",
  title =        "A Dual-Purpose Real\slash Complex Logarithmic Number
                 System {ALU}",
  crossref =     "Bruguera:2009:PIS",
  pages =        "15--24",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The real Logarithmic Number System (LNS) allows fast
                 and inexpensive multiplication and division but more
                 expensive addition and subtraction as precision
                 increases. Recent advances in higher-order and
                 multipartite table methods, together with
                 cotransformation, allow real LNS ALUs to be implemented
                 effectively on FPGAs for a wide variety of
                 medium-precision special-purpose applications. The
                 Complex LNS (CLNS) is a generalization of LNS which
                 represents complex values in log-polar form. CLNS is a
                 more compact representation than traditional
                 rectangular methods, reducing the cost of busses and
                 memory in intensive complex-number applications like
                 the FFT; however, prior CLNS implementations were
                 either slow CORDIC-based or expensive 2D-table-based
                 approaches. This paper attempts to leverage the recent
                 advances made in real-valued LNS units for the more
                 specialized context of CLNS. This paper proposes a
                 novel approach to reduce the cost of CLNS addition by
                 re-using a conventional real-valued LNS ALU with
                 specialized CLNS hardware that is smaller than the
                 real-valued LNS ALU to which it is attached. The
                 resulting ALU is much less expensive than prior fast
                 CLNS units at the cost of some extra delay. The extra
                 hardware added to the ALU is for trigonometric-related
                 functions, and may be useful in LNS applications other
                 than CLNS. The novel algorithm proposed here is
                 implemented using the FloPoCo library (which
                 incorporates recent HOTBM advances in function-unit
                 generation), and FPGA synthesis results are reported.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; complex arithmetic; FPGA; hardware function
                 evaluation; logarithmic number system",
}


bibtype: article
filename: fparith.bib
label: Baboulin:2009:ASC
title: Accelerating scientific computations with mixed precision algorithms
journal: j-COMP-PHYS-COMM
volume: 180
number: 12
pages: 2526--2533
month: dec
monthnumber: 12
year: 2009
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2008.11.005
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Mon Feb 13 23:42:47 MST 2012
bibtimestamp: 2012.02.13 23:42:47 MST
URL: http://www.sciencedirect.com/science/article/pii/S0010465508003846
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawtitle: Accelerating scientific computations with mixed precision algorithms
author:
Marc Baboulin and Alfredo Buttari and Jack Dongarra and Jakub Kurzak and Julie Langou and Julien Langou and Piotr Luszczek and Stanimire Tomov

rawauthor:
Marc Baboulin and Alfredo Buttari and Jack Dongarra and Jakub Kurzak and Julie Langou and Julien Langou and Piotr Luszczek and Stanimire Tomov

entry:
@Article{Baboulin:2009:ASC,
  author =       "Marc Baboulin and Alfredo Buttari and Jack Dongarra
                 and Jakub Kurzak and Julie Langou and Julien Langou and
                 Piotr Luszczek and Stanimire Tomov",
  title =        "Accelerating scientific computations with mixed
                 precision algorithms",
  journal =      j-COMP-PHYS-COMM,
  volume =       "180",
  number =       "12",
  pages =        "2526--2533",
  month =        dec,
  year =         "2009",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2008.11.005",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Mon Feb 13 23:42:47 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465508003846",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2009:SRB
author: J. C. Bajard and M. Kaihara and T. Plantard
title: Selected RNS Bases for Modular Multiplication
crossref: Bruguera:2009:PIS
pages: 25--31
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: J. C. Bajard and M. Kaihara and T. Plantard
rawtitle: Selected {RNS} Bases for Modular Multiplication
abstract:
The selection of the elements of the bases in an RNS modular multiplication method is crucial and has a great impact in the overall performance. This work proposes specific sets of optimal RNS moduli with elements of Hamming weight three whose inverses used in the MRS reconstruction have very small Hamming weight. This property is exploited in RNS bases conversions, to completely remove and replace the products by few additions/subtractions and shifts, reducing the time complexity of modular multiplication. These bases are specially crafted to computation with operands of sizes 256 or more and are suitable for cryptographic applications such as the ECC protocols.

rawabstract:
The selection of the elements of the bases in an RNS modular multiplication method is crucial and has a great impact in the overall performance. This work proposes specific sets of optimal RNS moduli with elements of Hamming weight three whose inverses used in the MRS reconstruction have very small Hamming weight. This property is exploited in RNS bases conversions, to completely remove and replace the products by few additions/subtractions and shifts, reducing the time complexity of modular multiplication. These bases are specially crafted to computation with operands of sizes 256 or more and are suitable for cryptographic applications such as the ECC protocols.

entry:
@InProceedings{Bajard:2009:SRB,
  author =       "J. C. Bajard and M. Kaihara and T. Plantard",
  title =        "Selected {RNS} Bases for Modular Multiplication",
  crossref =     "Bruguera:2009:PIS",
  pages =        "25--31",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The selection of the elements of the bases in an RNS
                 modular multiplication method is crucial and has a
                 great impact in the overall performance. This work
                 proposes specific sets of optimal RNS moduli with
                 elements of Hamming weight three whose inverses used in
                 the MRS reconstruction have very small Hamming weight.
                 This property is exploited in RNS bases conversions, to
                 completely remove and replace the products by few
                 additions/subtractions and shifts, reducing the time
                 complexity of modular multiplication. These bases are
                 specially crafted to computation with operands of sizes
                 256 or more and are suitable for cryptographic
                 applications such as the ECC protocols.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Barsi:2009:ECP
author: Ferruccio Barsi and Maria Cristina Pinotti
title: Error control by product codes in arithmetic units
journal: j-INT-J-PAR-EMER-DIST-SYS
volume: 24
number: 5
pages: 407--419
year: 2009
ISSN: 1744-5760 (print), 1744-5779 (electronic) OR 17445760 (print), 17445779 (electronic)
ISSNL: 1744-5760 OR 17445760
bibdate: Thu Sep 2 08:12:37 MDT 2010
bibtimestamp: 2010.09.02 08:12:37 MDT
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/gpaa20
rawauthor: Ferruccio Barsi and Maria Cristina Pinotti
rawtitle: Error control by product codes in arithmetic units
bibsource:
http://www.informaworld.com/smpp/title~content=t713729127~link=cover; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Barsi:2009:ECP,
  author =       "Ferruccio Barsi and Maria Cristina Pinotti",
  title =        "Error control by product codes in arithmetic units",
  journal =      j-INT-J-PAR-EMER-DIST-SYS,
  volume =       "24",
  number =       "5",
  pages =        "407--419",
  year =         "2009",
  CODEN =        "????",
  ISSN =         "1744-5760 (print), 1744-5779 (electronic)",
  ISSN-L =       "1744-5760",
  bibdate =      "Thu Sep 2 08:12:37 MDT 2010",
  bibsource =    "http://www.informaworld.com/smpp/title~content=t713729127~link=cover;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  journal-URL =  "http://www.tandfonline.com/loi/gpaa20",
}


bibtype: article
filename: fparith.bib
label: Bayat-Sarmadi:2009:CED
author: S. Bayat-Sarmadi and M. A. Hasan
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 11
pages: 1553--1567
month: nov
monthnumber: 11
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.62
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:44 MDT 2011
bibtimestamp: 2011.07.04 11:37:44 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4815219
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Bayat-Sarmadi and M. A. Hasan
title:
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures

rawtitle:
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures

entry:
@Article{Bayat-Sarmadi:2009:CED,
  author =       "S. Bayat-Sarmadi and M. A. Hasan",
  title =        "Concurrent Error Detection in Finite-Field Arithmetic
                 Operations Using Pipelined and Systolic Architectures",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "11",
  pages =        "1553--1567",
  month =        nov,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.62",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:44 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4815219",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Beebe:2009:NML
author: Nelson H. F. Beebe
title: A new math library
journal: j-IJQC
volume: 109
number: 13
pages: 3008--3025
day: 5
month: nov
monthnumber: 11
year: 2009
CODEN: IJQCB2
DOI: https://doi.org/10.1002/qua.22266
ISSN: 0020-7608 (print), 1097-461X (electronic) OR 00207608 (print), 1097461X (electronic)
ISSNL: 0020-7608 OR 00207608
bibdate: Tue Sep 08 18:56:33 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.09.08 18:56:33 ???
fjournal: International Journal of Quantum Chemistry
remark: Submitted 28 January 2009; accepted 17 March 2009.
acknowledgement: ack-nhfb
journalURL: http://www.interscience.wiley.com/jpages/0020-7608/
rawauthor: Nelson H. F. Beebe
rawtitle: A new math library
abstract:
The design and development of a new mathematical function library is described. The library extends programming support to decimal, as well as binary, arithmetic, and aims to influence the future evolution of floating-point support in programming languages, libraries, and hardware. It encourages and facilitates research in new computer-arithmetic designs, and the analysis and comparison of historical ones.

keywords:
binary arithmetic; computer arithmetic; decimal arithmetic; elementary functions; floating-point arithmetic; hexadecimal arithmetic; input/output conversions; integer arithmetic; interpreted languages; mathematical software library; number bases; octuple-precision arithmetic; pair-precision arithmetic; programming languages; scripting languages; special functions; wobbling precision

rawabstract:
The design and development of a new mathematical function library is described. The library extends programming support to decimal, as well as binary, arithmetic, and aims to influence the future evolution of floating-point support in programming languages, libraries, and hardware. It encourages and facilitates research in new computer-arithmetic designs, and the analysis and comparison of historical ones.

entry:
@Article{Beebe:2009:NML,
  author =       "Nelson H. F. Beebe",
  title =        "A new math library",
  journal =      j-IJQC,
  volume =       "109",
  number =       "13",
  pages =        "3008--3025",
  day =          "5",
  month =        nov,
  year =         "2009",
  CODEN =        "IJQCB2",
  DOI =          "https://doi.org/10.1002/qua.22266",
  ISSN =         "0020-7608 (print), 1097-461X (electronic)",
  ISSN-L =       "0020-7608",
  bibdate =      "Tue Sep 08 18:56:33 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The design and development of a new mathematical
                 function library is described. The library extends
                 programming support to decimal, as well as binary,
                 arithmetic, and aims to influence the future evolution
                 of floating-point support in programming languages,
                 libraries, and hardware. It encourages and facilitates
                 research in new computer-arithmetic designs, and the
                 analysis and comparison of historical ones.",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Quantum Chemistry",
  journal-URL =  "http://www.interscience.wiley.com/jpages/0020-7608/",
  keywords =     "binary arithmetic; computer arithmetic; decimal
                 arithmetic; elementary functions; floating-point
                 arithmetic; hexadecimal arithmetic; input/output
                 conversions; integer arithmetic; interpreted languages;
                 mathematical software library; number bases;
                 octuple-precision arithmetic; pair-precision
                 arithmetic; programming languages; scripting languages;
                 special functions; wobbling precision",
  pagecount =    "15",
  remark =       "Submitted 28 January 2009; accepted 17 March 2009.",
}


bibtype: article
filename: fparith.bib
label: Blomquist:2009:MSC
author: Frithjof Blomquist and Werner Hofschuster and Walter Kramer
title: A Modified Staggered Correction Arithmetic with Enhanced Accuracy and Very Wide Exponent Range
journal: j-LECT-NOTES-COMP-SCI
volume: 5492
pages: 41--67
year: 2009
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-01591-5_4
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Apr 10 08:32:19 2012
bibtimestamp: 2012.04.10 08:32:19 ???
URL: http://www.springerlink.com/content/k038294004403504/
fjournal: Lecture Notes in Computer Science
remark: Conference on Numerical Validation in Current Hardware Architectures
acknowledgement: ack-nhfb
authordates: 1952--2014 (WK)
journalURL: http://link.springer.com/bookseries/558
rawauthor: Frithjof Blomquist and Werner Hofschuster and Walter Kr{\"a}mer
rawtitle: A Modified Staggered Correction Arithmetic with Enhanced Accuracy and Very Wide Exponent Range
keywords:
C-XSC; complex interval functions; interval computation; multiple precision; reliable numerical computations; staggered correction; wide exponent range

entry:
@Article{Blomquist:2009:MSC,
  author =       "Frithjof Blomquist and Werner Hofschuster and Walter
                 Kr{\"a}mer",
  title =        "A Modified Staggered Correction Arithmetic with
                 Enhanced Accuracy and Very Wide Exponent Range",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "5492",
  pages =        "41--67",
  year =         "2009",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-01591-5_4",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Apr 10 08:32:19 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/content/k038294004403504/",
  acknowledgement = ack-nhfb,
  author-dates = "1952--2014 (WK)",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "C-XSC; complex interval functions; interval
                 computation; multiple precision; reliable numerical
                 computations; staggered correction; wide exponent
                 range",
  remark =       "Conference on Numerical Validation in Current Hardware
                 Architectures",
  remark-2 =     "Includes algorithms for division, $\exp(x)$, $(1 +
                 x)^n$, $\log(x)$, $\log(1 + x)$, and $\sqrt{x}$.
                 Staggered arithmetic represents numbers with tuples
                 $(e, x_1, x_2, \ldots{}, x_n)$ where $e$ is either
                 integer or a floating-point whole number, the $x_k$ are
                 floating-point, and a number has the value $2^e \sum_{k
                 = 1}^n x_k$. For interval arithmetic, the last element
                 is a pair of lower and upper bounds.",
}


bibtype: article
filename: fparith.bib
label: Boldo:2009:CCG
author: Sylvie Boldo and Jean-Christophe Filliatre and Guillaume Melquiond
title: Combining Coq and Gappa for Certifying Floating-Point Programs
journal: j-LECT-NOTES-COMP-SCI
pages: 59--74
year: 2009
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-02614-0_10
ISBN: 3-642-02614-1 OR 3642026141
ISBN13: 978-3-642-02614-0 OR 9783642026140
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Sat Jun 8 08:31:22 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.08 08:31:22 ???
fjournal: Lecture Notes in Computer Science
keywords: Intelligent Computer Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sylvie Boldo and Jean-Christophe Filli{\^a}tre and Guillaume Melquiond
rawtitle: Combining {Coq} and {Gappa} for Certifying Floating-Point Programs
entry:
@Article{Boldo:2009:CCG,
  author =       "Sylvie Boldo and Jean-Christophe Filli{\^a}tre and
                 Guillaume Melquiond",
  title =        "Combining {Coq} and {Gappa} for Certifying
                 Floating-Point Programs",
  journal =      j-LECT-NOTES-COMP-SCI,
  pages =        "59--74",
  year =         "2009",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-02614-0_10",
  ISBN =         "3-642-02614-1",
  ISBN-13 =      "978-3-642-02614-0",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Sat Jun 8 08:31:22 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "Intelligent Computer Mathematics",
}


bibtype: article
filename: fparith.bib
label: Boldo:2009:FRC
author: Sylvie Boldo
title: Floats and Ropes: a Case Study for Formal Numerical Program Verification
journal: j-LECT-NOTES-COMP-SCI
volume: 5556
pages: 91--102
year: 2009
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-02930-1_8
ISBN: 3-642-02930-2 OR 3642029302
ISBN13: 978-3-642-02930-1 OR 9783642029301
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Sat Jun 8 08:25:53 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.08 08:25:53 ???
fjournal: Lecture Notes in Computer Science
keywords: Automata, Languages and Programming. ICALP 2009
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sylvie Boldo
rawtitle: Floats and Ropes: a Case Study for Formal Numerical Program Verification
entry:
@Article{Boldo:2009:FRC,
  author =       "Sylvie Boldo",
  title =        "Floats and Ropes: a Case Study for Formal Numerical
                 Program Verification",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "5556",
  pages =        "91--102",
  year =         "2009",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-02930-1_8",
  ISBN =         "3-642-02930-2",
  ISBN-13 =      "978-3-642-02930-1",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Sat Jun 8 08:25:53 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "Automata, Languages and Programming. ICALP 2009",
}


bibtype: article
filename: fparith.bib
label: Boldo:2009:FVA
author: S. Boldo and Marc Daumas and Ren-Cang Li
title: Formally Verified Argument Reduction with a Fused Multiply-Add
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 8
pages: 1139--1145
month: aug
monthnumber: 8
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.216
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:43 MDT 2011
bibtimestamp: 2011.07.04 11:37:43 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711042
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Boldo and Marc Daumas and Ren-Cang Li
rawtitle: Formally Verified Argument Reduction with a Fused Multiply-Add
abstract:
The Cody and Waite argument reduction technique works perfectly for reasonably large arguments, but as the input grows, there are no bits left to approximate the constant with enough accuracy. Under mild assumptions, we show that the result computed with a fused multiply-add provides a fully accurate result for many possible values of the input with a constant almost accurate to the full working precision. We also present an algorithm for a fully accurate second reduction step to reach full double accuracy (all the significand bits of two numbers are accurate) even in the worst cases of argument reduction. Our work recalls the common algorithms and presents proofs of correctness. All the proofs are formally verified using the Coq automatic proof checker.

rawabstract:
The Cody and Waite argument reduction technique works perfectly for reasonably large arguments, but as the input grows, there are no bits left to approximate the constant with enough accuracy. Under mild assumptions, we show that the result computed with a fused multiply-add provides a fully accurate result for many possible values of the input with a constant almost accurate to the full working precision. We also present an algorithm for a fully accurate second reduction step to reach full double accuracy (all the significand bits of two numbers are accurate) even in the worst cases of argument reduction. Our work recalls the common algorithms and presents proofs of correctness. All the proofs are formally verified using the Coq automatic proof checker.

entry:
@Article{Boldo:2009:FVA,
  author =       "S. Boldo and Marc Daumas and Ren-Cang Li",
  title =        "Formally Verified Argument Reduction with a Fused
                 Multiply-Add",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "8",
  pages =        "1139--1145",
  month =        aug,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.216",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:43 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711042",
  abstract =     "The Cody and Waite argument reduction technique works
                 perfectly for reasonably large arguments, but as the
                 input grows, there are no bits left to approximate the
                 constant with enough accuracy. Under mild assumptions,
                 we show that the result computed with a fused
                 multiply-add provides a fully accurate result for many
                 possible values of the input with a constant almost
                 accurate to the full working precision. We also present
                 an algorithm for a fully accurate second reduction step
                 to reach full double accuracy (all the significand bits
                 of two numbers are accurate) even in the worst cases of
                 argument reduction. Our work recalls the common
                 algorithms and presents proofs of correctness. All the
                 proofs are formally verified using the Coq automatic
                 proof checker.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Boldo:2009:KAC
author: S. Boldo
title: Kahan's Algorithm for a Correct Discriminant Computation at Last Formally Proven
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 220--225
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.200
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 12 08:51:00 MDT 2009
bibtimestamp: 2009.06.12 08:51:00 MDT
note: See cite Kahan:2004:CFP for the original algorithm.
fjournal: IEEE Transactions on Computers
keywords: Coq; correct rounding; discriminant; floating point; formal proof; Why platform
remark: Extended version of ARITH-18 article cite Boldo:2007:FVF.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Boldo
rawnote: See \cite{Kahan:2004:CFP} for the original algorithm.
rawtitle: {Kahan}'s Algorithm for a Correct Discriminant Computation at Last Formally Proven
abstract:
This article tackles Kahan's algorithm to compute accurately the discriminant. This is a known difficult problem, and this algorithm leads to an error bounded by 2 ulps of the floating-point result. The proofs involved are long and tricky and even trickier than expected as the test involved may give a result different from the result of the same test without rounding. We give here the total demonstration of the validity of this algorithm, and we provide sufficient conditions to guarantee that neither overflow nor underflow will jeopardize the result. The IEEE-754 double-precision program is annotated using the Why platform and the proof obligations are done using the Coq automatic proof checker.

rawabstract:
This article tackles Kahan's algorithm to compute accurately the discriminant. This is a known difficult problem, and this algorithm leads to an error bounded by 2 ulps of the floating-point result. The proofs involved are long and tricky and even trickier than expected as the test involved may give a result different from the result of the same test without rounding. We give here the total demonstration of the validity of this algorithm, and we provide sufficient conditions to guarantee that neither overflow nor underflow will jeopardize the result. The IEEE-754 double-precision program is annotated using the Why platform and the proof obligations are done using the Coq automatic proof checker.

entry:
@Article{Boldo:2009:KAC,
  author =       "S. Boldo",
  title =        "{Kahan}'s Algorithm for a Correct Discriminant
                 Computation at Last Formally Proven",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "220--225",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.200",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 12 08:51:00 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  note =         "See \cite{Kahan:2004:CFP} for the original
                 algorithm.",
  abstract =     "This article tackles Kahan's algorithm to compute
                 accurately the discriminant. This is a known difficult
                 problem, and this algorithm leads to an error bounded
                 by 2 ulps of the floating-point result. The proofs
                 involved are long and tricky and even trickier than
                 expected as the test involved may give a result
                 different from the result of the same test without
                 rounding. We give here the total demonstration of the
                 validity of this algorithm, and we provide sufficient
                 conditions to guarantee that neither overflow nor
                 underflow will jeopardize the result. The IEEE-754
                 double-precision program is annotated using the Why
                 platform and the proof obligations are done using the
                 Coq automatic proof checker.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Coq; correct rounding; discriminant; floating point;
                 formal proof; Why platform",
  remark =       "Extended version of ARITH-18 article
                 \cite{Boldo:2007:FVF}.",
}


bibtype: article
filename: fparith.bib
label: Bryant:2009:ABD
title: An abstraction-based decision procedure for bit-vector arithmetic
journal: j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER
volume: 11
number: 2
pages: 95--104
month: apr
monthnumber: 4
year: 2009
ISSN: 1433-2779 (print), 1433-2787 (electronic) OR 14332779 (print), 14332787 (electronic)
ISSNL: 1433-2779 OR 14332779
bibdate: Sat Sep 11 07:13:37 MDT 2010
bibtimestamp: 2010.09.11 07:13:37 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=1433-2779&volume=11&issue=2&spage=95
fjournal: International Journal on Software Tools for Technology Transfer: STTT
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10009
rawtitle: An abstraction-based decision procedure for bit-vector arithmetic
author:
Randal E. Bryant and Daniel Kroening and Joel Ouaknine and Sanjit A. Seshia and Ofer Strichman and Bryan Brady

bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1433-2779&volume=11&issue=2; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawauthor:
Randal E. Bryant and Daniel Kroening and Jo{\"e}l Ouaknine and Sanjit A. Seshia and Ofer Strichman and Bryan Brady

entry:
@Article{Bryant:2009:ABD,
  author =       "Randal E. Bryant and Daniel Kroening and Jo{\"e}l
                 Ouaknine and Sanjit A. Seshia and Ofer Strichman and
                 Bryan Brady",
  title =        "An abstraction-based decision procedure for bit-vector
                 arithmetic",
  journal =      j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER,
  volume =       "11",
  number =       "2",
  pages =        "95--104",
  month =        apr,
  year =         "2009",
  CODEN =        "????",
  ISSN =         "1433-2779 (print), 1433-2787 (electronic)",
  ISSN-L =       "1433-2779",
  bibdate =      "Sat Sep 11 07:13:37 MDT 2010",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1433-2779&volume=11&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=1433-2779&volume=11&issue=2&spage=95",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal on Software Tools for Technology
                 Transfer: STTT",
  journal-URL =  "http://link.springer.com/journal/10009",
}


bibtype: article
filename: fparith.bib
label: Bullynck:2009:MAB
author: Maarten Bullynck
journal: j-HIST-MATH
volume: 36
number: 1
pages: 48--72
month: feb
monthnumber: 2
year: 2009
CODEN: HIMADS
ISSN: 0315-0860 (print), 1090-249X (electronic) OR 03150860 (print), 1090249X (electronic)
ISSNL: 0315-0860 OR 03150860
bibdate: Wed Jun 26 06:21:00 MDT 2013
bibtimestamp: 2013.06.26 06:21:00 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0315086008000670
fjournal: Historia Mathematica
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03150860/
rawauthor: Maarten Bullynck
title:
Modular arithmetic before C. F. Gauss: Systematizations and discussions on remainder problems in 18th-Century Germany

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/histmath.bib

rawtitle:
Modular arithmetic before {C. F. Gauss}: Systematizations and discussions on remainder problems in {18th-Century Germany}

entry:
@Article{Bullynck:2009:MAB,
  author =       "Maarten Bullynck",
  title =        "Modular arithmetic before {C. F. Gauss}:
                 Systematizations and discussions on remainder problems
                 in {18th-Century Germany}",
  journal =      j-HIST-MATH,
  volume =       "36",
  number =       "1",
  pages =        "48--72",
  month =        feb,
  year =         "2009",
  CODEN =        "HIMADS",
  ISSN =         "0315-0860 (print), 1090-249X (electronic)",
  ISSN-L =       "0315-0860",
  bibdate =      "Wed Jun 26 06:21:00 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/histmath.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0315086008000670",
  acknowledgement = ack-nhfb,
  fjournal =     "Historia Mathematica",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03150860/",
}


bibtype: article
filename: fparith.bib
label: Burtscher:2009:FHS
author: M. Burtscher and P. Ratanaworabhan
title: FPC: a High-Speed Compressor for Double-Precision Floating-Point Data
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 1
pages: 18--31
month: jan
monthnumber: 1
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.131
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4589203
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Burtscher and P. Ratanaworabhan
rawtitle: {FPC}: a High-Speed Compressor for Double-Precision Floating-Point Data
abstract:
Many scientific programs exchange large quantities of double-precision data between processing nodes and with mass storage devices. Data compression can reduce the number of bytes that need to be transferred and stored. However, data compression is only likely to be employed in high-end computing environments if it does not impede the throughput. This paper describes and evaluates FPC, a fast lossless compression algorithm for linear streams of 64-bit floating-point data. FPC works well on hard-to-compress scientific data sets and meets the throughput demands of high-performance systems. A comparison with five lossless compression schemes, BZIP2, DFCM, FSD, GZIP, and PLMI, on 4 architectures and 13 data sets shows that FPC compresses and decompresses one to two orders of magnitude faster than the other algorithms at the same geometric-mean compression ratio. Moreover, FPC provides a guaranteed throughput as long as the prediction tables fit into the L1 data cache. For example, on a 1.6-GHz Itanium 2 server, the throughput is 670 Mbytes/s regardless of what data are being compressed.

keywords:
BZIP2; data compression; DFCM; double-precision floating-point data; floating point compression; FSD; geometric-mean compression ratio; GZIP; linear streams; lossless compression algorithm; PLMI; scientific data sets compression; scientific programs

rawabstract:
Many scientific programs exchange large quantities of double-precision data between processing nodes and with mass storage devices. Data compression can reduce the number of bytes that need to be transferred and stored. However, data compression is only likely to be employed in high-end computing environments if it does not impede the throughput. This paper describes and evaluates FPC, a fast lossless compression algorithm for linear streams of 64-bit floating-point data. FPC works well on hard-to-compress scientific data sets and meets the throughput demands of high-performance systems. A comparison with five lossless compression schemes, BZIP2, DFCM, FSD, GZIP, and PLMI, on 4 architectures and 13 data sets shows that FPC compresses and decompresses one to two orders of magnitude faster than the other algorithms at the same geometric-mean compression ratio. Moreover, FPC provides a guaranteed throughput as long as the prediction tables fit into the L1 data cache. For example, on a 1.6-GHz Itanium 2 server, the throughput is 670 Mbytes/s regardless of what data are being compressed.

entry:
@Article{Burtscher:2009:FHS,
  author =       "M. Burtscher and P. Ratanaworabhan",
  title =        "{FPC}: a High-Speed Compressor for Double-Precision
                 Floating-Point Data",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "1",
  pages =        "18--31",
  month =        jan,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.131",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4589203",
  abstract =     "Many scientific programs exchange large quantities of
                 double-precision data between processing nodes and with
                 mass storage devices. Data compression can reduce the
                 number of bytes that need to be transferred and stored.
                 However, data compression is only likely to be employed
                 in high-end computing environments if it does not
                 impede the throughput. This paper describes and
                 evaluates FPC, a fast lossless compression algorithm
                 for linear streams of 64-bit floating-point data. FPC
                 works well on hard-to-compress scientific data sets and
                 meets the throughput demands of high-performance
                 systems. A comparison with five lossless compression
                 schemes, BZIP2, DFCM, FSD, GZIP, and PLMI, on 4
                 architectures and 13 data sets shows that FPC
                 compresses and decompresses one to two orders of
                 magnitude faster than the other algorithms at the same
                 geometric-mean compression ratio. Moreover, FPC
                 provides a guaranteed throughput as long as the
                 prediction tables fit into the L1 data cache. For
                 example, on a 1.6-GHz Itanium 2 server, the throughput
                 is 670 Mbytes/s regardless of what data are being
                 compressed.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "BZIP2; data compression; DFCM; double-precision
                 floating-point data; floating point compression; FSD;
                 geometric-mean compression ratio; GZIP; linear streams;
                 lossless compression algorithm; PLMI; scientific data
                 sets compression; scientific programs",
}


bibtype: inproceedings
filename: fparith.bib
label: Cenk:2009:PMF
author: Murat Cenk and Cetin Kaya Koc and Ferruh Ozbudak
title: Polynomial Multiplication over Finite Fields Using Field Extensions and Interpolation
crossref: Bruguera:2009:PIS
pages: 84--91
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Murat Cenk and {\c{C}}etin Kaya Ko{\c{c}} and Ferruh {\"O}zbudak
rawtitle: Polynomial Multiplication over Finite Fields Using Field Extensions and Interpolation
abstract:
A method for polynomial multiplication over finite fields using field extensions and polynomial interpolation is introduced. The proposed method uses polynomial interpolation as Toom--Cook method together with field extensions. Furthermore, the proposed method can be used when Toom--Cook method cannot be applied directly. Explicit formulae improving the previous results in many cases are obtained.

rawabstract:
A method for polynomial multiplication over finite fields using field extensions and polynomial interpolation is introduced. The proposed method uses polynomial interpolation as Toom--Cook method together with field extensions. Furthermore, the proposed method can be used when Toom--Cook method cannot be applied directly. Explicit formulae improving the previous results in many cases are obtained.

entry:
@InProceedings{Cenk:2009:PMF,
  author =       "Murat Cenk and {\c{C}}etin Kaya Ko{\c{c}} and Ferruh
                 {\"O}zbudak",
  title =        "Polynomial Multiplication over Finite Fields Using
                 Field Extensions and Interpolation",
  crossref =     "Bruguera:2009:PIS",
  pages =        "84--91",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A method for polynomial multiplication over finite
                 fields using field extensions and polynomial
                 interpolation is introduced. The proposed method uses
                 polynomial interpolation as Toom--Cook method together
                 with field extensions. Furthermore, the proposed method
                 can be used when Toom--Cook method cannot be applied
                 directly. Explicit formulae improving the previous
                 results in many cases are obtained.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; correct rounding; floating-point
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: Chabert:2009:PEA
author: Gilles Chabert and Luc Jaulin
title: A Priori Error Analysis and Spring Arithmetic
journal: j-SIAM-J-SCI-COMP
volume: 31
number: 3
pages: 2214--2230
year: 2009
CODEN: SJOCE3
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Wed May 19 10:44:16 MDT 2010
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.19 10:44:16 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: Gilles Chabert and Luc Jaulin
rawtitle: A Priori Error Analysis and Spring Arithmetic
entry:
@Article{Chabert:2009:PEA,
  author =       "Gilles Chabert and Luc Jaulin",
  title =        "A Priori Error Analysis and Spring Arithmetic",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "31",
  number =       "3",
  pages =        "2214--2230",
  month =        "????",
  year =         "2009",
  CODEN =        "SJOCE3",
  DOI =          "",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Wed May 19 10:44:16 MDT 2010",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/31/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2009:BDF
author: Dongdong Chen and Yu Zhang and Younhee Choi and Moon Ho Lee and Seok-Bum Ko
title: A 32-bit Decimal Floating-Point Logarithmic Converter
crossref: Bruguera:2009:PIS
pages: 195--203
year: 2009
DOI: https://doi.org/10.1109/ARITH.2009.22
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: Dongdong Chen and Yu Zhang and Younhee Choi and Moon Ho Lee and Seok-Bum Ko
rawtitle: A 32-bit Decimal Floating-Point Logarithmic Converter
abstract:
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calculate accurate logarithms of 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. Redundant digit $ e_1 $ is obtained by look-up table in the first iteration and the rest redundant digits $ e_j $ are selected by rounding the scaled remainder during the succeeding iterations. The sequential architecture of the proposed 32-bit DFP logarithmic converter is implemented on Xilinx Virtex-II Pro P30 FPGA device and then synthesized with TMSC 0.18-$ mu $ m standard cell library. The implementation results indicate that the maximum frequency of the proposed architecture is 47.7 MHz in FPGA and 107.9 MHz in TMSC 0.18-$ mu $ m technology. The faithful 32-bit DFP logarithm results can be obtained in 18 cycles.

keywords:
ARITH-19; decimal floating-point; decimal logarithmic converter; digit-recurrence algorithm; selection by rounding.

rawabstract:
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calculate accurate logarithms of 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. Redundant digit $ e_1 $ is obtained by look-up table in the first iteration and the rest redundant digits $ e_j $ are selected by rounding the scaled remainder during the succeeding iterations. The sequential architecture of the proposed 32-bit DFP logarithmic converter is implemented on Xilinx Virtex-II Pro P30 FPGA device and then synthesized with TMSC 0.18-$ \mu $ m standard cell library. The implementation results indicate that the maximum frequency of the proposed architecture is 47.7 MHz in FPGA and 107.9 MHz in TMSC 0.18-$ \mu $ m technology. The faithful 32-bit DFP logarithm results can be obtained in 18 cycles.

entry:
@InProceedings{Chen:2009:BDF,
  author =       "Dongdong Chen and Yu Zhang and Younhee Choi and Moon
                 Ho Lee and Seok-Bum Ko",
  title =        "A 32-bit Decimal Floating-Point Logarithmic
                 Converter",
  crossref =     "Bruguera:2009:PIS",
  pages =        "195--203",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ARITH.2009.22",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a new design and implementation of
                 a 32-bit decimal floating-point (DFP) logarithmic
                 converter based on the digit-recurrence algorithm. The
                 converter can calculate accurate logarithms of 32-bit
                 DFP numbers which are defined in the IEEE 754-2008
                 standard. Redundant digit $ e_1 $ is obtained by
                 look-up table in the first iteration and the rest
                 redundant digits $ e_j $ are selected by rounding the
                 scaled remainder during the succeeding iterations. The
                 sequential architecture of the proposed 32-bit DFP
                 logarithmic converter is implemented on Xilinx
                 Virtex-II Pro P30 FPGA device and then synthesized with
                 TMSC 0.18-$ \mu $ m standard cell library. The
                 implementation results indicate that the maximum
                 frequency of the proposed architecture is 47.7 MHz in
                 FPGA and 107.9 MHz in TMSC 0.18-$ \mu $ m technology.
                 The faithful 32-bit DFP logarithm results can be
                 obtained in 18 cycles.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19; decimal floating-point; decimal logarithmic
                 converter; digit-recurrence algorithm; selection by
                 rounding.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2009:NDA
author: Dongdong Chen and Yu Zhang and D. Teng and K. Wahid and Moon Ho Lee and Seok-Bum Ko
title: A new decimal antilogarithmic converter
crossref: IEEE:2009:IIS
pages: 445--448
year: 2009
DOI: https://doi.org/10.1109/ISCAS.2009.5117781
bibdate: Thu Feb 17 08:34:31 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.17 08:34:31 ???
acknowledgement: ack-nhfb
rawauthor: Dongdong Chen and Yu Zhang and D. Teng and K. Wahid and Moon Ho Lee and Seok-Bum Ko
rawtitle: A new decimal antilogarithmic converter
entry:
@InProceedings{Chen:2009:NDA,
  author =       "Dongdong Chen and Yu Zhang and D. Teng and K. Wahid
                 and Moon Ho Lee and Seok-Bum Ko",
  title =        "A new decimal antilogarithmic converter",
  crossref =     "IEEE:2009:IIS",
  pages =        "445--448",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ISCAS.2009.5117781",
  bibdate =      "Thu Feb 17 08:34:31 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Cheng:2009:DSE
author: Chung-Kuan Cheng
title: Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders
crossref: Bruguera:2009:PIS
pages: 212--212
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
remark: Only abstract published.
acknowledgement: ack-nhfb
rawauthor: Chung-Kuan Cheng
rawtitle: Design Space Exploration for Power-Efficient Mixed-Radix {Ling} Adders
abstract:
We present an integer linear programming (ILP) method that optimizes generalized prefix Ling adders in terms of area, delay, and power. The contribution is listed in the following.par (1) We devise an ILP formulation based on logical effort models so that we can use ILP solver, CPLEX, to produce minimum power solutions with given structural, area and timing constraints. The formulation allows the adjustment of parameters and constraints, e.g. the radix numbers and the ratio of static and dynamic power. We implement the flow for the users to automatically synthesize the adders.par (2) We engineer sets of integer decision variables and linear constraints to depict the prefix topology, signal delay, and power characterization. Since the design space of prefix adders is large, optimal solutions are usually hard to generate without good formulations. We generate redundant constraints to prune the search space. The approach significantly reduces the execution time.par (3) We explore mixed radices for prefix topologies, i.e. GP cells have radices 2, 3, or 4, and a prefix network can contain cells of different radices. This mixed-radix feature expands the design space for better solutions. High-radix adders reduce logic levels and thus can serve for high performance applications. On the other hand, high-radix cells take more logical effort, longer parasitic delay, and more power consumption. These factors are all taken care of in the devised ILP formulation.par (4) We adopt the structure of Ling adders to produce faster sum and carry responses. The experiments show that Ling adders achieve better results than normal prefix adders.par (5) We apply hierarchical design methods to handle high bit-width modules. One weakness of ILP solver is the scaleability of computational time with the bit-width. We use a divide-and-conquer strategy to synthesize 64-bit adders.

rawabstract:
We present an integer linear programming (ILP) method that optimizes generalized prefix Ling adders in terms of area, delay, and power. The contribution is listed in the following.\par (1) We devise an ILP formulation based on logical effort models so that we can use ILP solver, CPLEX, to produce minimum power solutions with given structural, area and timing constraints. The formulation allows the adjustment of parameters and constraints, e.g. the radix numbers and the ratio of static and dynamic power. We implement the flow for the users to automatically synthesize the adders.\par (2) We engineer sets of integer decision variables and linear constraints to depict the prefix topology, signal delay, and power characterization. Since the design space of prefix adders is large, optimal solutions are usually hard to generate without good formulations. We generate redundant constraints to prune the search space. The approach significantly reduces the execution time.\par (3) We explore mixed radices for prefix topologies, i.e. GP cells have radices 2, 3, or 4, and a prefix network can contain cells of different radices. This mixed-radix feature expands the design space for better solutions. High-radix adders reduce logic levels and thus can serve for high performance applications. On the other hand, high-radix cells take more logical effort, longer parasitic delay, and more power consumption. These factors are all taken care of in the devised ILP formulation.\par (4) We adopt the structure of Ling adders to produce faster sum and carry responses. The experiments show that Ling adders achieve better results than normal prefix adders.\par (5) We apply hierarchical design methods to handle high bit-width modules. One weakness of ILP solver is the scaleability of computational time with the bit-width. We use a divide-and-conquer strategy to synthesize 64-bit adders.

entry:
@InProceedings{Cheng:2009:DSE,
  author =       "Chung-Kuan Cheng",
  title =        "Design Space Exploration for Power-Efficient
                 Mixed-Radix {Ling} Adders",
  crossref =     "Bruguera:2009:PIS",
  pages =        "212--212",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present an integer linear programming (ILP) method
                 that optimizes generalized prefix Ling adders in terms
                 of area, delay, and power. The contribution is listed
                 in the following.\par

                 (1) We devise an ILP formulation based on logical
                 effort models so that we can use ILP solver, CPLEX, to
                 produce minimum power solutions with given structural,
                 area and timing constraints. The formulation allows the
                 adjustment of parameters and constraints, e.g. the
                 radix numbers and the ratio of static and dynamic
                 power. We implement the flow for the users to
                 automatically synthesize the adders.\par

                 (2) We engineer sets of integer decision variables and
                 linear constraints to depict the prefix topology,
                 signal delay, and power characterization. Since the
                 design space of prefix adders is large, optimal
                 solutions are usually hard to generate without good
                 formulations. We generate redundant constraints to
                 prune the search space. The approach significantly
                 reduces the execution time.\par

                 (3) We explore mixed radices for prefix topologies,
                 i.e. GP cells have radices 2, 3, or 4, and a prefix
                 network can contain cells of different radices. This
                 mixed-radix feature expands the design space for better
                 solutions. High-radix adders reduce logic levels and
                 thus can serve for high performance applications. On
                 the other hand, high-radix cells take more logical
                 effort, longer parasitic delay, and more power
                 consumption. These factors are all taken care of in the
                 devised ILP formulation.\par

                 (4) We adopt the structure of Ling adders to produce
                 faster sum and carry responses. The experiments show
                 that Ling adders achieve better results than normal
                 prefix adders.\par

                 (5) We apply hierarchical design methods to handle high
                 bit-width modules. One weakness of ILP solver is the
                 scaleability of computational time with the bit-width.
                 We use a divide-and-conquer strategy to synthesize
                 64-bit adders.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
  remark =       "Only abstract published.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chevillard:2009:CFC
author: Sylvain Chevillard and Mioara Joldes and Christoph Lauter
title: Certified and Fast Computation of Supremum Norms of Approximation Errors
crossref: Bruguera:2009:PIS
pages: 169--176
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
acknowledgement: ack-nhfb
rawauthor: Sylvain Chevillard and Mioara Joldes and Christoph Lauter
rawtitle: Certified and Fast Computation of Supremum Norms of Approximation Errors
abstract:
In many numerical programs there is a need for a high-quality floating-point approximation of useful functions $f$, such as such as $ exp $, $ sin $, $ erf $. In the actual implementation, the function is replaced by a polynomial $p$, which leads to an approximation error (absolute or relative) $ epsilon = p - f $ or $ epsilon = p / f - 1 $. The tight yet certain bounding of this error is an important step towards safe implementations. The problem is difficult mainly because that approximation error is very small and the difference $ p - f $ is subject to high cancellation. Previous approaches for computing the supremum norm in this degenerate case, have proven to be unsafe, not sufficiently tight or too tedious in manual work. We present a safe and fast algorithm that computes a tight lower and upper bound for the supremum norms of approximation errors. The algorithm is based on a combination of several techniques, including enhanced interval arithmetic, automatic differentiation and isolation of the roots of a polynomial. We have implemented our algorithm and give timings on several examples.

keywords:
approximation error; ARITH-19; automatic/algorithmic differentiation; certified computation; elementary function; interval arithmetic; roots isolation technique.; supremum/infinity norm

rawabstract:
In many numerical programs there is a need for a high-quality floating-point approximation of useful functions $f$, such as such as $ \exp $, $ \sin $, $ \erf $. In the actual implementation, the function is replaced by a polynomial $p$, which leads to an approximation error (absolute or relative) $ \epsilon = p - f $ or $ \epsilon = p / f - 1 $. The tight yet certain bounding of this error is an important step towards safe implementations. The problem is difficult mainly because that approximation error is very small and the difference $ p - f $ is subject to high cancellation. Previous approaches for computing the supremum norm in this degenerate case, have proven to be unsafe, not sufficiently tight or too tedious in manual work. We present a safe and fast algorithm that computes a tight lower and upper bound for the supremum norms of approximation errors. The algorithm is based on a combination of several techniques, including enhanced interval arithmetic, automatic differentiation and isolation of the roots of a polynomial. We have implemented our algorithm and give timings on several examples.

entry:
@InProceedings{Chevillard:2009:CFC,
  author =       "Sylvain Chevillard and Mioara Joldes and Christoph
                 Lauter",
  title =        "Certified and Fast Computation of Supremum Norms of
                 Approximation Errors",
  crossref =     "Bruguera:2009:PIS",
  pages =        "169--176",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In many numerical programs there is a need for a
                 high-quality floating-point approximation of useful
                 functions $f$, such as such as $ \exp $, $ \sin $, $
                 \erf $. In the actual implementation, the function is
                 replaced by a polynomial $p$, which leads to an
                 approximation error (absolute or relative) $ \epsilon =
                 p - f $ or $ \epsilon = p / f - 1 $. The tight yet
                 certain bounding of this error is an important step
                 towards safe implementations. The problem is difficult
                 mainly because that approximation error is very small
                 and the difference $ p - f $ is subject to high
                 cancellation. Previous approaches for computing the
                 supremum norm in this degenerate case, have proven to
                 be unsafe, not sufficiently tight or too tedious in
                 manual work. We present a safe and fast algorithm that
                 computes a tight lower and upper bound for the supremum
                 norms of approximation errors. The algorithm is based
                 on a combination of several techniques, including
                 enhanced interval arithmetic, automatic differentiation
                 and isolation of the roots of a polynomial. We have
                 implemented our algorithm and give timings on several
                 examples.",
  acknowledgement = ack-nhfb,
  keywords =     "approximation error; ARITH-19; automatic/algorithmic
                 differentiation; certified computation; elementary
                 function; interval arithmetic; roots isolation
                 technique.; supremum/infinity norm",
}


bibtype: article
filename: fparith.bib
label: Cho:2009:AMD
author: H. Cho and E. E. Swartzlander
title: Adder and Multiplier Design in Quantum-Dot Cellular Automata
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 6
pages: 721--727
month: jun
monthnumber: 6
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.21
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:41 MDT 2011
bibtimestamp: 2011.07.04 11:37:41 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4760137
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Cho and E. E. Swartzlander
rawtitle: Adder and Multiplier Design in Quantum-Dot Cellular Automata
entry:
@Article{Cho:2009:AMD,
  author =       "H. Cho and E. E. Swartzlander",
  title =        "Adder and Multiplier Design in Quantum-Dot Cellular
                 Automata",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "6",
  pages =        "721--727",
  month =        jun,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.21",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4760137",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chouliaras:2009:CLF
author: V. A. Chouliaras and K. Manolopoulos and D. Reisis
title: A configurable length, Fused Multiply-Add floating point unit for a VLIW processor
crossref: Sezer:2009:IIS
pages: 93--96
year: 2009
DOI: https://doi.org/10.1109/SOCCON.2009.5398088
bibdate: Sun Feb 20 10:03:30 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:03:30 ???
acknowledgement: ack-nhfb
rawauthor: V. A. Chouliaras and K. Manolopoulos and D. Reisis
rawtitle: A configurable length, Fused Multiply-Add floating point unit for a {VLIW} processor
abstract:
The efficiency of fused multiply add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 $ mu $ m$^2$.

rawabstract:
The efficiency of fused multiply add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 $ \mu $ m$^2$.

entry:
@InProceedings{Chouliaras:2009:CLF,
  author =       "V. A. Chouliaras and K. Manolopoulos and D. Reisis",
  title =        "A configurable length, Fused Multiply-Add floating
                 point unit for a {VLIW} processor",
  crossref =     "Sezer:2009:IIS",
  pages =        "93--96",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/SOCCON.2009.5398088",
  bibdate =      "Sun Feb 20 10:03:30 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The efficiency of fused multiply add units plays a key
                 role in the processor's performance for a variety of
                 applications. A design keeping the advantages of the
                 FMA regarding the latency and the hardware utilization
                 and also improving the result's accuracy in both
                 normalized and denormalized numbers is the subject of
                 this work. The FMA unit has configurable latency and it
                 is integrated in a VLIW processor. The VLSI TSMC 0.13
                 implementation achieved an operating frequency of 232.6
                 MHz and a final post-routed area of 121900.478 $ \mu $
                 m$^2$.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Cilardo:2009:EBP
author: A. Cilardo
title: Efficient Bit-Parallel $ mathrm GF(2^m) $ Multiplier for a Large Class of Irreducible Pentanomials
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 7
pages: 1001--1008
month: jul
monthnumber: 7
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2009.16
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:42 MDT 2011
bibtimestamp: 2011.07.04 11:37:42 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4752811
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Cilardo
rawtitle:
Efficient Bit-Parallel {$ \mathrm {GF}(2^m) $} Multiplier for a Large Class of Irreducible Pentanomials

entry:
@Article{Cilardo:2009:EBP,
  author =       "A. Cilardo",
  title =        "Efficient Bit-Parallel {$ \mathrm {GF}(2^m) $}
                 Multiplier for a Large Class of Irreducible
                 Pentanomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "7",
  pages =        "1001--1008",
  month =        jul,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2009.16",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4752811",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Colberg:2009:HAS
author: Peter H. Colberg and Felix Hofling
journal: arXiv.org
pages: 1--12
day: 20
month: dec
monthnumber: 12
year: 2009
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in Comp. Phys. Comm. bf 182, 1120 (2011).
URL: http://arxiv.org/abs/0912.3824
acknowledgement: ack-nhfb
rawauthor: Peter H. Colberg and Felix H{\"o}fling
rawnote: Published in Comp. Phys. Comm. {\bf 182}, 1120 (2011).
title:
Highly accelerated simulations of glassy dynamics using GPUs: caveats on limited floating-point precision

abstract:
Modern graphics processing units (GPUs) provide impressive computing resources, which can be accessed conveniently through the CUDA programming interface. We describe how GPUs can be used to considerably speed up molecular dynamics (MD) simulations for system sizes ranging up to about 1 million particles. Particular emphasis is put on the numerical long-time stability in terms of energy and momentum conservation, and caveats on limited floating-point precision are issued. Strict energy conservation over $ 10^8 $ MD steps is obtained by double-single emulation of the floating-point arithmetic in accuracy-critical parts of the algorithm. For the slow dynamics of a supercooled binary Lennard-Jones mixture, we demonstrate that the use of single-floating point precision may result in quantitatively and even physically wrong results. For simulations of a Lennard-Jones fluid, the described implementation shows speedup factors of up to 80 compared to a serial implementation for the CPU, and a single GPU was found to compare with a parallelised MD simulation using 64 distributed cores.

subject:
Computational Physics (physics.comp-ph); Soft Condensed Matter (cond-mat.soft); Distributed, Parallel, and Cluster Computing (cs.DC)

rawabstract:
Modern graphics processing units (GPUs) provide impressive computing resources, which can be accessed conveniently through the CUDA programming interface. We describe how GPUs can be used to considerably speed up molecular dynamics (MD) simulations for system sizes ranging up to about 1 million particles. Particular emphasis is put on the numerical long-time stability in terms of energy and momentum conservation, and caveats on limited floating-point precision are issued. Strict energy conservation over $ 10^8 $ MD steps is obtained by double-single emulation of the floating-point arithmetic in accuracy-critical parts of the algorithm. For the slow dynamics of a supercooled binary Lennard-Jones mixture, we demonstrate that the use of single-floating point precision may result in quantitatively and even physically wrong results. For simulations of a Lennard-Jones fluid, the described implementation shows speedup factors of up to 80 compared to a serial implementation for the CPU, and a single GPU was found to compare with a parallelised MD simulation using 64 distributed cores.

rawtitle:
Highly accelerated simulations of glassy dynamics using {GPUs}: caveats on limited floating-point precision

entry:
@Article{Colberg:2009:HAS,
  author =       "Peter H. Colberg and Felix H{\"o}fling",
  title =        "Highly accelerated simulations of glassy dynamics
                 using {GPUs}: caveats on limited floating-point
                 precision",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--12",
  day =          "20",
  month =        dec,
  year =         "2009",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in Comp. Phys. Comm. {\bf 182}, 1120
                 (2011).",
  URL =          "http://arxiv.org/abs/0912.3824",
  abstract =     "Modern graphics processing units (GPUs) provide
                 impressive computing resources, which can be accessed
                 conveniently through the CUDA programming interface. We
                 describe how GPUs can be used to considerably speed up
                 molecular dynamics (MD) simulations for system sizes
                 ranging up to about 1 million particles. Particular
                 emphasis is put on the numerical long-time stability in
                 terms of energy and momentum conservation, and caveats
                 on limited floating-point precision are issued. Strict
                 energy conservation over $ 10^8 $ MD steps is obtained
                 by double-single emulation of the floating-point
                 arithmetic in accuracy-critical parts of the algorithm.
                 For the slow dynamics of a supercooled binary
                 Lennard-Jones mixture, we demonstrate that the use of
                 single-floating point precision may result in
                 quantitatively and even physically wrong results. For
                 simulations of a Lennard-Jones fluid, the described
                 implementation shows speedup factors of up to 80
                 compared to a serial implementation for the CPU, and a
                 single GPU was found to compare with a parallelised MD
                 simulation using 64 distributed cores.",
  acknowledgement = ack-nhfb,
  subject =      "Computational Physics (physics.comp-ph); Soft
                 Condensed Matter (cond-mat.soft); Distributed,
                 Parallel, and Cluster Computing (cs.DC)",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2009:IDF
author: Marius Cornea
title: IEEE 754-2008 Decimal Floating-Point for Intel Architecture Processors
crossref: Bruguera:2009:PIS
pages: 225--228
year: 2009
DOI: https://doi.org/10.1109/ARITH.2009.35
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: Marius Cornea
rawtitle: {IEEE 754-2008} Decimal Floating-Point for {Intel} Architecture Processors
abstract:
A brief description is provided of the decimal floating-point support available for Intel Architecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic [1]. Some performance results are included.

rawabstract:
A brief description is provided of the decimal floating-point support available for Intel Architecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic [1]. Some performance results are included.

entry:
@InProceedings{Cornea:2009:IDF,
  author =       "Marius Cornea",
  title =        "{IEEE 754-2008} Decimal Floating-Point for {Intel}
                 Architecture Processors",
  crossref =     "Bruguera:2009:PIS",
  pages =        "225--228",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ARITH.2009.35",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A brief description is provided of the decimal
                 floating-point support available for Intel Architecture
                 processors, compliant with the IEEE Standard 754-2008
                 for Floating-Point Arithmetic [1]. Some performance
                 results are included.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Cornea:2009:SII
author: M. Cornea and J. Harrison and C. Anderson and P. Tang and E. Schneider and E. Gvozdev
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 148--162
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.209
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4674342
fjournal: IEEE Transactions on Computers
remark: Extended version of ARITH-18 article cite Cornea:2007:SII.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Cornea and J. Harrison and C. Anderson and P. Tang and E. Schneider and E. Gvozdev
title:
A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format

abstract:
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6].

keywords:
binary-decimal conversion.; computer arithmetic; correct rounding; decimal floating-point; floating-point arithmetic; multiple-precision arithmetic

rawabstract:
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6].

rawtitle:
A Software Implementation of the {IEEE 754R} Decimal Floating-Point Arithmetic Using the Binary Encoding Format

entry:
@Article{Cornea:2009:SII,
  author =       "M. Cornea and J. Harrison and C. Anderson and P. Tang
                 and E. Schneider and E. Gvozdev",
  title =        "A Software Implementation of the {IEEE 754R} Decimal
                 Floating-Point Arithmetic Using the Binary Encoding
                 Format",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "148--162",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.209",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4674342",
  abstract =     "The IEEE Standard 754-1985 for Binary Floating-Point
                 Arithmetic [19] was revised [20], and an important
                 addition is the definition of decimal floating-point
                 arithmetic [8], [24]. This is intended mainly to
                 provide a robust reliable framework for financial
                 applications that are often subject to legal
                 requirements concerning rounding and precision of the
                 results, because the binary floating-point arithmetic
                 may introduce small but unacceptable errors. Using
                 binary floating-point calculations to emulate decimal
                 calculations in order to correct this issue has led to
                 the existence of numerous proprietary software
                 packages, each with its own characteristics and
                 capabilities. The IEEE 754R decimal arithmetic should
                 unify the ways decimal floating-point calculations are
                 carried out on various platforms. New algorithms and
                 properties are presented in this paper, which are used
                 in a software implementation of the IEEE 754R decimal
                 floating-point arithmetic, with emphasis on using
                 binary operations efficiently. The focus is on rounding
                 techniques for decimal values stored in binary format,
                 but algorithms are outlined for the more important or
                 interesting operations of addition, multiplication, and
                 division, including the case of nonhomogeneous
                 operands, as well as conversions between binary and
                 decimal floating-point formats. Performance results are
                 included for a wider range of operations, showing
                 promise that our approach is viable for applications
                 that require decimal floating-point calculations. This
                 paper extends an earlier publication [6].",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "binary-decimal conversion.; computer arithmetic;
                 correct rounding; decimal floating-point;
                 floating-point arithmetic; multiple-precision
                 arithmetic",
  remark =       "Extended version of ARITH-18 article
                 \cite{Cornea:2007:SII}.",
}


bibtype: article
filename: fparith.bib
label: Csuros:2009:ACF
author: Miklos Csuros
title: Approximate counting with a floating-point counter
journal: arXiv.org
pages: ??--??
day: 20
month: apr
monthnumber: 4
year: 2009
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0904.3062
subject: Data Structures and Algorithms (cs.DS)
acknowledgement: ack-nhfb
rawauthor: Miklos Csuros
rawtitle: Approximate counting with a floating-point counter
abstract:
Memory becomes a limiting factor in contemporary applications, such as analyses of the Webgraph and molecular sequences, when many objects need to be counted simultaneously. Robert Morris [Communications of the ACM, 21:840--842, 1978] proposed a probabilistic technique for approximate counting that is extremely space-efficient. The basic idea is to increment a counter containing the value $X$ with probability $ 2^-X$. As a result, the counter contains an approximation of $ lg n$ after $n$ probabilistic updates stored in $ lg lg n$ bits. Here we revisit the original idea of Morris, and introduce a binary floating-point counter that uses a $d$-bit significand in conjunction with a binary exponent. The counter yields a simple formula for an unbiased estimation of $n$ with a standard deviation of about $ 0.6 cdot n2^-d / 2$, and uses $ d + lg lg n$ bits. We analyze the floating-point counter's performance in a general framework that applies to any probabilistic counter, and derive practical formulas to assess its accuracy.

rawabstract:
Memory becomes a limiting factor in contemporary applications, such as analyses of the Webgraph and molecular sequences, when many objects need to be counted simultaneously. Robert Morris [Communications of the ACM, 21:840--842, 1978] proposed a probabilistic technique for approximate counting that is extremely space-efficient. The basic idea is to increment a counter containing the value $X$ with probability $ 2^{-X}$. As a result, the counter contains an approximation of $ \lg n$ after $n$ probabilistic updates stored in $ \lg \lg n$ bits. Here we revisit the original idea of Morris, and introduce a binary floating-point counter that uses a $d$-bit significand in conjunction with a binary exponent. The counter yields a simple formula for an unbiased estimation of $n$ with a standard deviation of about $ 0.6 \cdot n2^{-d / 2}$, and uses $ d + \lg \lg n$ bits. We analyze the floating-point counter's performance in a general framework that applies to any probabilistic counter, and derive practical formulas to assess its accuracy.

entry:
@Article{Csuros:2009:ACF,
  author =       "Miklos Csuros",
  title =        "Approximate counting with a floating-point counter",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "20",
  month =        apr,
  year =         "2009",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0904.3062",
  abstract =     "Memory becomes a limiting factor in contemporary
                 applications, such as analyses of the Webgraph and
                 molecular sequences, when many objects need to be
                 counted simultaneously. Robert Morris [Communications
                 of the ACM, 21:840--842, 1978] proposed a probabilistic
                 technique for approximate counting that is extremely
                 space-efficient. The basic idea is to increment a
                 counter containing the value $X$ with probability $
                 2^{-X}$. As a result, the counter contains an
                 approximation of $ \lg n$ after $n$ probabilistic
                 updates stored in $ \lg \lg n$ bits. Here we revisit
                 the original idea of Morris, and introduce a binary
                 floating-point counter that uses a $d$-bit significand
                 in conjunction with a binary exponent. The counter
                 yields a simple formula for an unbiased estimation of
                 $n$ with a standard deviation of about $ 0.6 \cdot
                 n2^{-d / 2}$, and uses $ d + \lg \lg n$ bits. We
                 analyze the floating-point counter's performance in a
                 general framework that applies to any probabilistic
                 counter, and derive practical formulas to assess its
                 accuracy.",
  acknowledgement = ack-nhfb,
  subject =      "Data Structures and Algorithms (cs.DS)",
}


bibtype: article
filename: fparith.bib
label: Daumas:2009:VRN
author: Marc Daumas and D. Lester and C. Muoz
title: Verified Real Number Calculations: a Library for Interval Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 2
pages: 226--237
month: feb
monthnumber: 2
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.213
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:39 MDT 2011
bibtimestamp: 2011.07.04 11:37:39 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4685896
fjournal: IEEE Transactions on Computers
keywords: interval arithmetic; proof checking; real number calculations; theorem proving
remark: Extended version of ARITH-18 article cite Daumas:2009:VRN.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Marc Daumas and D. Lester and C. Muoz
rawtitle: Verified Real Number Calculations: a Library for Interval Arithmetic
abstract:
Real number calculations on elementary functions are remarkably difficult to handle in mechanical proofs. In this paper, we show how these calculations can be performed within a theorem prover or proof assistant in a convenient and highly automated as well as interactive way. First, we formally establish upper and lower bounds for elementary functions. Then, based on these bounds, we develop a rational interval arithmetic where real number calculations take place in an algebraic setting. In order to reduce the dependency effect of interval arithmetic, we integrate two techniques: interval splitting and Taylor series expansions. This pragmatic approach has been developed, and formally verified, in a theorem prover. The formal development also includes a set of customizable strategies to automate proofs involving explicit calculations over real numbers. Our ultimate goal is to provide guaranteed proofs of numerical properties with minimal human theorem-prover interaction.

rawabstract:
Real number calculations on elementary functions are remarkably difficult to handle in mechanical proofs. In this paper, we show how these calculations can be performed within a theorem prover or proof assistant in a convenient and highly automated as well as interactive way. First, we formally establish upper and lower bounds for elementary functions. Then, based on these bounds, we develop a rational interval arithmetic where real number calculations take place in an algebraic setting. In order to reduce the dependency effect of interval arithmetic, we integrate two techniques: interval splitting and Taylor series expansions. This pragmatic approach has been developed, and formally verified, in a theorem prover. The formal development also includes a set of customizable strategies to automate proofs involving explicit calculations over real numbers. Our ultimate goal is to provide guaranteed proofs of numerical properties with minimal human theorem-prover interaction.

entry:
@Article{Daumas:2009:VRN,
  author =       "Marc Daumas and D. Lester and C. Muoz",
  title =        "Verified Real Number Calculations: a Library for
                 Interval Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "2",
  pages =        "226--237",
  month =        feb,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.213",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4685896",
  abstract =     "Real number calculations on elementary functions are
                 remarkably difficult to handle in mechanical proofs. In
                 this paper, we show how these calculations can be
                 performed within a theorem prover or proof assistant in
                 a convenient and highly automated as well as
                 interactive way. First, we formally establish upper and
                 lower bounds for elementary functions. Then, based on
                 these bounds, we develop a rational interval arithmetic
                 where real number calculations take place in an
                 algebraic setting. In order to reduce the dependency
                 effect of interval arithmetic, we integrate two
                 techniques: interval splitting and Taylor series
                 expansions. This pragmatic approach has been developed,
                 and formally verified, in a theorem prover. The formal
                 development also includes a set of customizable
                 strategies to automate proofs involving explicit
                 calculations over real numbers. Our ultimate goal is to
                 provide guaranteed proofs of numerical properties with
                 minimal human theorem-prover interaction.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "interval arithmetic; proof checking; real number
                 calculations; theorem proving",
  remark =       "Extended version of ARITH-18 article
                 \cite{Daumas:2009:VRN}.",
}


bibtype: article
filename: fparith.bib
label: Davida:2009:FAU
author: George Davida and Bruce Litow and Guangwu Xu
title: Fast arithmetics using Chinese remaindering
journal: j-INFO-PROC-LETT
volume: 109
number: 13
pages: 660--662
day: 15
month: jun
monthnumber: 6
year: 2009
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Thu Mar 31 15:53:33 MDT 2011
bibtimestamp: 2011.03.31 15:53:33 MDT
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: George Davida and Bruce Litow and Guangwu Xu
rawtitle: Fast arithmetics using {Chinese} remaindering
entry:
@Article{Davida:2009:FAU,
  author =       "George Davida and Bruce Litow and Guangwu Xu",
  title =        "Fast arithmetics using {Chinese} remaindering",
  journal =      j-INFO-PROC-LETT,
  volume =       "109",
  number =       "13",
  pages =        "660--662",
  day =          "15",
  month =        jun,
  year =         "2009",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Thu Mar 31 15:53:33 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: article
filename: fparith.bib
label: DeCaro:2009:DSM
author: Davide De Caro and Nicola Petra and Antonio G. M. Strollo
journal: j-IEEE-TRANS-CIRCUITS-SYST-1
volume: 56
number: 2
pages: 364--373
year: 2009
DOI: https://doi.org/10.1109/TCSI.2008.2001370
ISSN: 1549-8328 (print), 1558-0806 (electronic) OR 15498328 (print), 15580806 (electronic)
ISSNL: 1549-8328 OR 15498328
MRclass: 99-01
MRnumber: 3030492
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
fjournal: IEEE Transactions on Circuits and Systems. I. Regular Papers
ZMnumber: 1469.94241
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
rawauthor: Davide {De Caro} and Nicola Petra and Antonio G. M. Strollo
title:
Digital Synthesizer / Mixer With Hybrid CORDIC Multiplier Architecture: Error Analysis and Optimization

keywords:
94C30; Angle rotator; Circuits; CMOS technology; Computer architecture; CORDIC algorithm; Delay; digital downconverter; digital mixer; digital synthesizer; digital tuner; digital upconverter; direct digital frequency synthesizer (DDFS); Equations; Error analysis; Frequency synthesizers; mixer; modulator; quadrature modulator; Signal processing algorithms; Table lookup; Tuners

rawtitle:
Digital Synthesizer\slash Mixer With Hybrid {CORDIC} Multiplier Architecture: Error Analysis and Optimization

entry:
@Article{DeCaro:2009:DSM,
  author =       "Davide {De Caro} and Nicola Petra and Antonio G. M.
                 Strollo",
  title =        "Digital Synthesizer\slash Mixer With Hybrid {CORDIC}
                 Multiplier Architecture: Error Analysis and
                 Optimization",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "56",
  number =       "2",
  pages =        "364--373",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/TCSI.2008.2001370",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  MRclass =      "99-01",
  MRnumber =     "3030492",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  ZMnumber =     "1469.94241",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. I. Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
  keywords =     "94C30; Angle rotator; Circuits; CMOS technology;
                 Computer architecture; CORDIC algorithm; Delay; digital
                 downconverter; digital mixer; digital synthesizer;
                 digital tuner; digital upconverter; direct digital
                 frequency synthesizer (DDFS); Equations; Error
                 analysis; Frequency synthesizers; mixer; modulator;
                 quadrature modulator; Signal processing algorithms;
                 Table lookup; Tuners",
  ZBmath =       "7390012",
}


bibtype: book
filename: fparith.bib
label: Deschamps:2009:HIF
author: Jean-Pierre Deschamps and Jose Luis Imana and Gustavo D. Sutter
title: Hardware implementation of finite-field arithmetic
publisher: pub-MCGRAW-HILL
address: pub-MCGRAW-HILL:adr
pages: xiii + 347
year: 2009
ISBN: 0-07-154581-6 (hardcover) OR 0071545816 (hardcover)
ISBN13: 978-0-07-154581-5 (hardcover) OR 9780071545815 (hardcover)
LCCN: TK7895.E42 D466 2009
bibdate: Sat Sep 20 16:04:08 MDT 2014
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2014.09.20 16:04:08 MDT
series: Electronic engineering
acknowledgement: ack-nhfb
authordates: 1945--
rawauthor: Jean-Pierre Deschamps and Jos{\'e} Luis Ima{\~n}a and Gustavo D. Sutter
rawtitle: Hardware implementation of finite-field arithmetic
abstract:
Master cutting-edge electronic circuit synthesis and design with help from this detailed guide. Hardware Implementation of Finite-Field Arithmetic describes algorithms and circuits for executing finite-field operations, including addition, subtraction, multiplication, squaring, exponentiation, and division.par This comprehensive resource begins with an overview of mathematics, covering algebra, number theory, finite fields, and cryptography. The book then presents algorithms which can be executed and verified with actual input data. Logic schemes and VHDL models are described in such a way that the corresponding circuits can be easily simulated and synthesized. The book concludes with a real-world example of a finite-field application --- elliptic-curve cryptography. This is an essential guide for hardware engineers involved in the development of embedded systems.

subject:
Embedded computer systems; Design and construction; Field programmable gate arrays; Application-specific integrated circuits; Computer arithmetic

TOC:
1. Mathematical background / 1--24 2. Mod $m$ reduction / 25--60 3. Mod $m$ operations / 61--90 4. Operations over $rm GF(p)$ / 91--116 5. Operations over $Z_p[x] / f(x)$ / 117--138 6. Operations over $rm GF(p^n)$ / 139--162 7. Operations over $rm GF(2^m)$ --- Polynomial bases / 163--234 8. Operations over $rm GF(2^m)$ --- Normal bases / 235--268 9. Operations over $rm GF(2^m)$ --- Other bases / 269--286 10. An Example of Application --- Elliptic curve cryptography / 287--312 Appendix A. $p = 2^192 - 2^64 - 1$ / 313--318 Appendix B. Optical Extension Fields / 319--330 Appendix C. Binary Fields / 331--334 Appendix D. Ada versus VHDL / 337--340 Index / 341--347

rawabstract:
Master cutting-edge electronic circuit synthesis and design with help from this detailed guide. Hardware Implementation of Finite-Field Arithmetic describes algorithms and circuits for executing finite-field operations, including addition, subtraction, multiplication, squaring, exponentiation, and division.\par This comprehensive resource begins with an overview of mathematics, covering algebra, number theory, finite fields, and cryptography. The book then presents algorithms which can be executed and verified with actual input data. Logic schemes and VHDL models are described in such a way that the corresponding circuits can be easily simulated and synthesized. The book concludes with a real-world example of a finite-field application --- elliptic-curve cryptography. This is an essential guide for hardware engineers involved in the development of embedded systems.

rawTOC:
1. Mathematical background / 1--24 \\ 2. Mod $m$ reduction / 25--60 \\ 3. Mod $m$ operations / 61--90 \\ 4. Operations over ${\rm GF}(p)$ / 91--116 \\ 5. Operations over $Z_p[x] / f(x)$ / 117--138 \\ 6. Operations over ${\rm GF}(p^n)$ / 139--162 \\ 7. Operations over ${\rm GF}(2^m)$ --- Polynomial bases / 163--234 \\ 8. Operations over ${\rm GF}(2^m)$ --- Normal bases / 235--268 \\ 9. Operations over ${\rm GF}(2^m)$ --- Other bases / 269--286 \\ 10. An Example of Application --- Elliptic curve cryptography / 287--312 \\ Appendix A. $p = 2^{192} - 2^{64} - 1$ / 313--318 \\ Appendix B. Optical Extension Fields / 319--330 \\ Appendix C. Binary Fields / 331--334 \\ Appendix D. Ada versus VHDL / 337--340 \\ Index / 341--347

entry:
@Book{Deschamps:2009:HIF,
  author =       "Jean-Pierre Deschamps and Jos{\'e} Luis Ima{\~n}a and
                 Gustavo D. Sutter",
  title =        "Hardware implementation of finite-field arithmetic",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xiii + 347",
  year =         "2009",
  ISBN =         "0-07-154581-6 (hardcover)",
  ISBN-13 =      "978-0-07-154581-5 (hardcover)",
  LCCN =         "TK7895.E42 D466 2009",
  bibdate =      "Sat Sep 20 16:04:08 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  series =       "Electronic engineering",
  abstract =     "Master cutting-edge electronic circuit synthesis and
                 design with help from this detailed guide. Hardware
                 Implementation of Finite-Field Arithmetic describes
                 algorithms and circuits for executing finite-field
                 operations, including addition, subtraction,
                 multiplication, squaring, exponentiation, and
                 division.\par

                 This comprehensive resource begins with an overview of
                 mathematics, covering algebra, number theory, finite
                 fields, and cryptography. The book then presents
                 algorithms which can be executed and verified with
                 actual input data. Logic schemes and VHDL models are
                 described in such a way that the corresponding circuits
                 can be easily simulated and synthesized. The book
                 concludes with a real-world example of a finite-field
                 application --- elliptic-curve cryptography. This is an
                 essential guide for hardware engineers involved in the
                 development of embedded systems.",
  acknowledgement = ack-nhfb,
  author-dates = "1945--",
  subject =      "Embedded computer systems; Design and construction;
                 Field programmable gate arrays; Application-specific
                 integrated circuits; Computer arithmetic",
  tableofcontents = "1. Mathematical background / 1--24 \\
                 2. Mod $m$ reduction / 25--60 \\
                 3. Mod $m$ operations / 61--90 \\
                 4. Operations over ${\rm GF}(p)$ / 91--116 \\
                 5. Operations over $Z_p[x] / f(x)$ / 117--138 \\
                 6. Operations over ${\rm GF}(p^n)$ / 139--162 \\
                 7. Operations over ${\rm GF}(2^m)$ --- Polynomial bases
                 / 163--234 \\
                 8. Operations over ${\rm GF}(2^m)$ --- Normal bases /
                 235--268 \\
                 9. Operations over ${\rm GF}(2^m)$ --- Other bases /
                 269--286 \\
                 10. An Example of Application --- Elliptic curve
                 cryptography / 287--312 \\
                 Appendix A. $p = 2^{192} - 2^{64} - 1$ / 313--318 \\
                 Appendix B. Optical Extension Fields / 319--330 \\
                 Appendix C. Binary Fields / 331--334 \\
                 Appendix D. Ada versus VHDL / 337--340 \\
                 Index / 341--347",
}


bibtype: inproceedings
filename: fparith.bib
label: Dormiani:2009:DIR
author: P. Dormiani and M. D. Ercegovac and Jean-Michel Muller
title: Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
crossref: IEEE:2009:IICa
pages: 83--90
year: 2009
DOI: https://doi.org/10.1109/ASAP.2009.32
bibdate: Fri Dec 03 15:01:28 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.03 15:01:28 ???
acknowledgement: ack-nhfb
rawauthor: P. Dormiani and M. D. Ercegovac and Jean-Michel Muller
rawtitle: Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
abstract:
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1185 ALUTs, achieving a latency of 157 ns. The maximum clock frequency is 173.49 MHz.

keywords:
Altera Stratix II FPGA; digital arithmetic; field programmable gate arrays; frequency 173.49 MHz; integrated circuit design; logic design; operand prescaling; prescalers; prescaling tables; radix-4 complex division unit; table design

rawabstract:
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1185 ALUTs, achieving a latency of 157 ns. The maximum clock frequency is 173.49 MHz.

entry:
@InProceedings{Dormiani:2009:DIR,
  author =       "P. Dormiani and M. D. Ercegovac and Jean-Michel
                 Muller",
  title =        "Design and Implementation of a Radix-4 Complex
                 Division Unit with Prescaling",
  crossref =     "IEEE:2009:IICa",
  pages =        "83--90",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ASAP.2009.32",
  bibdate =      "Fri Dec 03 15:01:28 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a design and implementation of a radix-4
                 complex division unit with prescaling of the operands.
                 Specifically, we extend the treatment of the residual
                 bound and errors due to the use of truncated redundant
                 representation. The requirements for prescaling tables
                 are simplified and a detailed specification of the
                 table design is given. All principal components used in
                 the design are described and the proposed optimizations
                 are explained. The target platform for implementation
                 was an Altera Stratix II FPGA for which we report
                 timing and area requirements. For a precision of 36
                 bits, the implementation uses 1185 ALUTs, achieving a
                 latency of 157 ns. The maximum clock frequency is
                 173.49 MHz.",
  acknowledgement = ack-nhfb,
  keywords =     "Altera Stratix II FPGA; digital arithmetic; field
                 programmable gate arrays; frequency 173.49 MHz;
                 integrated circuit design; logic design; operand
                 prescaling; prescalers; prescaling tables; radix-4
                 complex division unit; table design",
}


bibtype: inproceedings
filename: fparith.bib
label: Dormiani:2009:LPT
author: Pouya Dormiani and Milo D. Ercegovac and Jean-Michel Muller
editor: Michael B. Matthews
title: Low precision table based complex reciprocal approximation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1803--1807
year: 2009
DOI: https://doi.org/10.1109/ACSSC.2009.5470209
ISBN: 1-4244-5827-7 OR 1424458277
ISBN13: 978-1-4244-5827-1 OR 9781424458271
ISSN: 1058-6393 OR 10586393
ISSNL: 1058-6393 OR 10586393
bibdate: Fri Sep 29 10:50:54 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:50:54 ???
acknowledgement: ack-nhfb
rawauthor: Pouya Dormiani and Milo D. Ercegovac and Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: Low precision table based complex reciprocal approximation
booktitle:
2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers. November 1--4, 2009. Pacific Grove, California

rawbooktitle:
{2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers. November 1--4, 2009. Pacific Grove, California}

entry:
@InProceedings{Dormiani:2009:LPT,
  author =       "Pouya Dormiani and Milo D. Ercegovac and Jean-Michel
                 Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{2009 Conference Record of the Forty-Third Asilomar
                 Conference on Signals, Systems and Computers. November
                 1--4, 2009. Pacific Grove, California}",
  title =        "Low precision table based complex reciprocal
                 approximation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1803--1807",
  year =         "2009",
  DOI =          "https://doi.org/10.1109/ACSSC.2009.5470209",
  ISBN =         "1-4244-5827-7",
  ISBN-13 =      "978-1-4244-5827-1",
  ISSN =         "1058-6393",
  ISSN-L =       "1058-6393",
  bibdate =      "Fri Sep 29 10:50:54 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Duff:2009:GMA
author: Bob Duff
title: Gem #26: the tt mod attribute
journal: j-SIGADA-LETTERS
volume: 29
number: 1
pages: 33--34
month: apr
monthnumber: 4
year: 2009
CODEN: AALEE5
DOI: https://doi.org/10.1145/1541788.1541795
ISSN: 1094-3641 (print), 1557-9476 (electronic) OR 10943641 (print), 15579476 (electronic)
ISSNL: 1094-3641 OR 10943641
bibdate: Mon Jun 21 14:03:13 MDT 2010
bibtimestamp: 2010.06.21 14:03:13 MDT
fjournal: ACM SIGAda Ada Letters
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/citation.cfm?id=J32
rawauthor: Bob Duff
rawtitle: Gem \#26: the {\tt mod} attribute
abstract:
Ada Gem #26 --- T'Mod can be used to convert signed integers to modular integers using modular (wraparound) arithmetic.

rawabstract:
Ada Gem \#26 --- T'Mod can be used to convert signed integers to modular integers using modular (wraparound) arithmetic.

entry:
@Article{Duff:2009:GMA,
  author =       "Bob Duff",
  title =        "Gem \#26: the {\tt mod} attribute",
  journal =      j-SIGADA-LETTERS,
  volume =       "29",
  number =       "1",
  pages =        "33--34",
  month =        apr,
  year =         "2009",
  CODEN =        "AALEE5",
  DOI =          "https://doi.org/10.1145/1541788.1541795",
  ISSN =         "1094-3641 (print), 1557-9476 (electronic)",
  ISSN-L =       "1094-3641",
  bibdate =      "Mon Jun 21 14:03:13 MDT 2010",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigada.bib",
  abstract =     "Ada Gem \#26 --- T'Mod can be used to convert signed
                 integers to modular integers using modular (wraparound)
                 arithmetic.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGAda Ada Letters",
  journal-URL =  "http://portal.acm.org/citation.cfm?id=J32",
}


bibtype: inproceedings
filename: fparith.bib
label: Edmonson:2009:IIS
author: William Edmonson and Guillaume Melquiond
title: IEEE Interval Standard Working Group --- P1788: Current Status
crossref: Bruguera:2009:PIS
pages: 231--234
year: 2009
bibdate: Fri Jun 12 12:34:25 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.12 12:34:25 ???
keywords: ARITH-19
acknowledgement: ack-nhfb
rawauthor: William Edmonson and Guillaume Melquiond
rawtitle: {IEEE Interval Standard Working Group --- P1788}: Current Status
abstract:
Late 2008, at SCAN 2008 in El Paso, TX, an effort to standardize interval computations was started by a working group of the IEEE Microprocessor Standards Committee, titled the Interval Arithmetic Working Group of the IEEE P1788 Standard. This paper describes the goals of this effort, the history of the working group, and how it relates to the IEEE 754 Standard. It gives a brief overview of the policies and procedures for constructing the standard, and its expected structure. It also presents some of the questions the group may have to solve in the future.

rawabstract:
Late 2008, at SCAN 2008 in El Paso, TX, an effort to standardize interval computations was started by a working group of the IEEE Microprocessor Standards Committee, titled the Interval Arithmetic Working Group of the IEEE P1788 Standard. This paper describes the goals of this effort, the history of the working group, and how it relates to the IEEE 754 Standard. It gives a brief overview of the policies and procedures for constructing the standard, and its expected structure. It also presents some of the questions the group may have to solve in the future.

entry:
@InProceedings{Edmonson:2009:IIS,
  author =       "William Edmonson and Guillaume Melquiond",
  title =        "{IEEE Interval Standard Working Group --- P1788}:
                 Current Status",
  crossref =     "Bruguera:2009:PIS",
  pages =        "231--234",
  year =         "2009",
  bibdate =      "Fri Jun 12 12:34:25 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Late 2008, at SCAN 2008 in El Paso, TX, an effort to
                 standardize interval computations was started by a
                 working group of the IEEE Microprocessor Standards
                 Committee, titled the Interval Arithmetic Working Group
                 of the IEEE P1788 Standard. This paper describes the
                 goals of this effort, the history of the working group,
                 and how it relates to the IEEE 754 Standard. It gives a
                 brief overview of the policies and procedures for
                 constructing the standard, and its expected structure.
                 It also presents some of the questions the group may
                 have to solve in the future.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-19",
}


bibtype: article
filename: fparith.bib
label: Enge:2009:CCP
author: Andreas Enge
title: The complexity of class polynomial computation via floating point approximations
journal: j-MATH-COMPUT
volume: 78
number: 266
pages: 1089--1107
month: apr
monthnumber: 4
year: 2009
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Fri May 14 06:20:58 MDT 2010
bibsource: http://www.ams.org/mcom/2009-78-266; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.14 06:20:58 MDT
fjournal: Mathematics of Computation
keywords: roots of elliptic curves
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Andreas Enge
rawtitle: The complexity of class polynomial computation via floating point approximations
URL:
http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/home.html; http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/S0025-5718-08-02200-X.pdf

entry:
@Article{Enge:2009:CCP,
  author =       "Andreas Enge",
  title =        "The complexity of class polynomial computation via
                 floating point approximations",
  journal =      j-MATH-COMPUT,
  volume =       "78",
  number =       "266",
  pages =        "1089--1107",
  month =        apr,
  year =         "2009",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Fri May 14 06:20:58 MDT 2010",
  bibsource =    "http://www.ams.org/mcom/2009-78-266;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/home.html;
                 http://www.ams.org/journals/mcom/2009-78-266/S0025-5718-08-02200-X/S0025-5718-08-02200-X.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "roots of elliptic curves",
}


bibtype: manual
filename: fparith.bib
label: Enge:2009:MLM
author: Andreas Enge and Philippe Theveny and Paul Zimmermann
title: texttt mpc --- a library for multiprecision complex arithmetic with exact rounding
organization: INRIA
address: France
edition: 0.8.1
pages: 1089--1107
month: dec
monthnumber: 12
year: 2009
bibdate: Sun May 2 09:31:32 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.05.02 09:31:32 ???
URL: http://mpc.multiprecision.org/
acknowledgement: ack-nhfb
rawauthor: Andreas Enge and Philippe Th{\'e}veny and Paul Zimmermann
rawtitle: {\texttt{mpc}} --- a library for multiprecision complex arithmetic with exact rounding
entry:
@Manual{Enge:2009:MLM,
  author =       "Andreas Enge and Philippe Th{\'e}veny and Paul
                 Zimmermann",
  title =        "{\texttt{mpc}} --- a library for multiprecision
                 complex arithmetic with exact rounding",
  organization = "INRIA",
  address =      "France",
  edition =      "0.8.1",
  month =        dec,
  year =         "2009",
  bibdate =      "Sun May 2 09:31:32 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mpc.multiprecision.org/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Erle:2009:DFP
author: Mark A. Erle and Brian J. Hickmann and Michael J. Schulte
title: Decimal Floating-Point Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 58
number: 7
pages: 902--916
month: jul
monthnumber: 7
year: 2009
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2008.218
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 11:37:42 MDT 2011
bibtimestamp: 2011.07.04 11:37:42 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711044
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Mark A. Erle and Brian J. Hickmann and Michael J. Schulte
rawtitle: Decimal Floating-Point Multiplication
abstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry-save addition and one that employs binary carry-save addition. The multiplier based on decimal carry-save addition favors a nonpipelined iterative implementation. The multiplier utilizing binary carry-save addition allows for an efficient pipelined implementation when latency and throughput are considered more important than area. Both designs comply with specifications for decimal multiplication given in the IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The multipliers extend previously published decimal fixed-point multipliers by adding several features, including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. Novel features of the multipliers include support for decimal floating-point numbers, on-the-fly generation of the sticky bit in the iterative design, early estimation of the shift amount, and efficient decimal rounding. Iterative and parallel decimal fixed-point and floating-point multipliers are compared in terms of their area, delay, latency, and throughput based on verified Verilog register-transfer-level models.

keywords:
arithmetic and logic units; binary coded decimal; computer arithmetic; decimal multiplication; floating-point arithmetic; general high-speed arithmetic; parallel multiplication; pipelined multiplication; serial multiplication

rawabstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry-save addition and one that employs binary carry-save addition. The multiplier based on decimal carry-save addition favors a nonpipelined iterative implementation. The multiplier utilizing binary carry-save addition allows for an efficient pipelined implementation when latency and throughput are considered more important than area. Both designs comply with specifications for decimal multiplication given in the IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The multipliers extend previously published decimal fixed-point multipliers by adding several features, including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. Novel features of the multipliers include support for decimal floating-point numbers, on-the-fly generation of the sticky bit in the iterative design, early estimation of the shift amount, and efficient decimal rounding. Iterative and parallel decimal fixed-point and floating-point multipliers are compared in terms of their area, delay, latency, and throughput based on verified Verilog register-transfer-level models.

entry:
@Article{Erle:2009:DFP,
  author =       "Mark A. Erle and Brian J. Hickmann and Michael J.
                 Schulte",
  title =        "Decimal Floating-Point Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "58",
  number =       "7",
  pages =        "902--916",
  month =        jul,
  year =         "2009",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2008.218",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 11:37:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4711044",
  abstract =     "Decimal multiplication is important in many commercial
                 applications including financial analysis, banking, tax
                 calculation, currency conversion, insurance, and
                 accounting. This paper presents the design of two
                 decimal floating-point multipliers: one whose partial
                 product accumulation strategy employs decimal
                 carry-save addition and one that employs binary
                 carry-save addition. The multiplier based on decimal
                 carry-save addition favors a nonpipelined iterative
                 implementation. The multiplier utilizing binary
                 carry-save addition allows for an efficient pipelined
                 implementation when latency and throughput are
                 considered more important than area. Both designs
                 comply with specifications for decimal multiplication
                 given in the IEEE 754 Standard for Floating-Point
                 Arithmetic (IEEE 754-2008). The multipliers extend
                 previously published decimal fixed-point multipliers by
                 adding several features, including exponent generation,
                 sticky bit generation, shifting of the intermediate
                 product, rounding, and exception detection and
                 handling. Novel features of the multipliers include
                 support for decimal floating-point numbers, on-the-fly
                 generation of the sticky bit in the iterative design,
                 early estimation of the shift amount, and efficient
                 decimal rounding. Iterative and parallel decimal
                 fixed-point and floating-point multipliers are compared
                 in terms of their area, delay, latency, and throughput
                 based on verified Verilog register-transfer-level
                 models.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic and logic units; binary coded decimal;
                 computer arithmetic; decimal multiplication;
                 floating-point arithmetic; general high-speed
                 arithmetic; parallel multiplication; pipelined
                 multiplication; serial multiplication",
}


