# bibtab

bibtype: techreport
filename: fparith.bib
label: McClellan:1993:AFP
author: Scott McClellan
title: Alternatives to floating point representation
type: Honors paper
number: 4
institution: United States Naval Academy Honors Paper. Dept. of Mathematics
pages: various
year: 1993
bibdate: Sat May 04 17:18:52 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.05.04 17:18:52 ???
keywords: Floating-point arithmetic.
remark: Honors paper--United States Naval Academy, 1993.
acknowledgement: ack-nhfb
rawauthor: Scott McClellan
rawtitle: Alternatives to floating point representation
entry:
@TechReport{McClellan:1993:AFP,
  author =       "Scott McClellan",
  title =        "Alternatives to floating point representation",
  type =         "Honors paper",
  number =       "4",
  institution =  "United States Naval Academy Honors Paper. Dept. of
                 Mathematics",
  pages =        "various",
  year =         "1993",
  bibdate =      "Sat May 04 17:18:52 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.",
  remark =       "Honors paper--United States Naval Academy, 1993.",
}


bibtype: article
filename: fparith.bib
label: McKeeman:1993:AOC
author: W. M. McKeeman
title: Avoiding Overflow in Constant Expression Evaluation
journal: j-JCLT
volume: 5
number: 1
pages: 27--31
month: sep
monthnumber: 9
year: 1993
ISSN: 1042-5721 OR 10425721
bibdate: Fri Nov 21 14:40:20 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.11.21 14:40:20 ???
fjournal: The Journal of C Language Translation
remark: Predicting overflow before it occurs
acknowledgement: ack-nhfb
rawauthor: W. M. McKeeman
rawtitle: Avoiding Overflow in Constant Expression Evaluation
entry:
@Article{McKeeman:1993:AOC,
  author =       "W. M. McKeeman",
  title =        "Avoiding Overflow in Constant Expression Evaluation",
  journal =      j-JCLT,
  volume =       "5",
  number =       "1",
  pages =        "27--31",
  month =        sep,
  year =         "1993",
  ISSN =         "1042-5721",
  bibdate =      "Fri Nov 21 14:40:20 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of {C} Language Translation",
  remark =       "Predicting overflow before it occurs",
}


bibtype: inproceedings
filename: fparith.bib
label: McQuillan:1993:NAV
author: S. E. McQuillan and J. V. McCanny and R. Hamill
title: New algorithms and VLSI architectures for SRT division and square root
crossref: Swartzlander:1993:SCA
pages: 80--86
year: 1993
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_McQuillan.pdf
keywords: ARITH-11
acknowledgement: ack-sfo
rawauthor: S. E. McQuillan and J. V. McCanny and R. Hamill
rawtitle: New algorithms and {VLSI} architectures for {SRT} division and square root
entry:
@InProceedings{McQuillan:1993:NAV,
  author =       "S. E. McQuillan and J. V. McCanny and R. Hamill",
  title =        "New algorithms and {VLSI} architectures for {SRT}
                 division and square root",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "80--86",
  year =         "1993",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_McQuillan.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "ARITH-11",
  summary =      "Radix two algorithms for SRT division and
                 square-rooting are developed. For these schemes, the
                 result digits and the residuals are computed
                 concurrently and the computations in adjacent rows are
                 overlapped. Consequently, their performance should
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Meier:1993:EMC
author: Willi Meier and Othmar Staffelbach
title: Efficient Multiplication on Certain Nonsupersingular Elliptic Curves
journal: j-LECT-NOTES-COMP-SCI
volume: 740
pages: 333--344
year: 1993
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Feb 5 11:48:51 MST 2002
bibtimestamp: 2002.02.05 11:48:51 MST
fjournal: Lecture Notes in Computer Science
keywords: CRYPTO; cryptology
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Willi Meier and Othmar Staffelbach
rawtitle: Efficient Multiplication on Certain Nonsupersingular Elliptic Curves
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t0740.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/0740/07400333.htm; http://link.springer-ny.com/link/service/series/0558/papers/0740/07400333.pdf

entry:
@Article{Meier:1993:EMC,
  author =       "Willi Meier and Othmar Staffelbach",
  title =        "Efficient Multiplication on Certain Nonsupersingular
                 Elliptic Curves",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "740",
  pages =        "333--344",
  year =         "1993",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Feb 5 11:48:51 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t0740.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/0740/07400333.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/0740/07400333.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "CRYPTO; cryptology",
}


bibtype: inproceedings
filename: fparith.bib
label: Mellott:1993:GMG
author: Jonathon D. Mellott and Jeremy C. Smith and Fred J. Taylor
title: The Gauss Machine: a Galois-Enhanced Quadratic Residue Number System Systolic Array
crossref: Swartzlander:1993:SCA
pages: 156--162
year: 1993
DOI: https://doi.org/10.1109/ARITH.1993.378097
bibdate: Sat Nov 17 09:46:07 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 09:46:07 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Mellott.pdf
keywords: ARITH-11; residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: Jonathon D. Mellott and Jeremy C. Smith and Fred J. Taylor
rawtitle: The {Gauss} Machine: a {Galois}-Enhanced Quadratic Residue Number System Systolic Array
entry:
@InProceedings{Mellott:1993:GMG,
  author =       "Jonathon D. Mellott and Jeremy C. Smith and Fred J.
                 Taylor",
  title =        "The {Gauss} Machine: a {Galois}-Enhanced Quadratic
                 Residue Number System Systolic Array",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "156--162",
  year =         "1993",
  DOI =          "https://doi.org/10.1109/ARITH.1993.378097",
  bibdate =      "Sat Nov 17 09:46:07 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Mellott.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11; residue arithmetic; residue number system",
  summary =      "The Gauss machine is a SIMD systolic array
                 architecture that takes advantage of the
                 Galois-enhanced residue number system (GEQRNS) to form
                 reduced-complexity arithmetic elements. The Gauss
                 machine is targeted at front-end signal and image
                 processing applications. A discrete prototype that
                 achieves a peak rating of 320 million complex
                 arithmetic operations per second while operating at 10
                 MHz has been constructed. A VLSI implementation of the
                 Gauss machine's processor cell has been created. The
                 VLSI implementation is implemented in 2.0-$\mu$m CMOS
                 and achieves greater than 20-MHz performance, using
                 less than 2.0-mm$^2$ die area. It is shown that
                 techniques for defect tolerance in RNS systolic arrays
                 can result in substantial yield enhancement, thereby
                 making larger than conventional (ULSI) systems
                 possible",
}


bibtype: inproceedings
filename: fparith.bib
label: Merrheim:1993:FEP
author: Xavier Merrheim and Jean-Michel Muller and Hong-Jin Yeh
title: Fast Evaluation of Polynomials and Inverses of Polynomials
crossref: Swartzlander:1993:SCA
pages: 186--192
year: 1993
bibdate: Sat Nov 17 09:46:07 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 09:46:07 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Merrheim.pdf
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: Xavier Merrheim and Jean-Michel Muller and Hong-Jin Yeh
rawtitle: Fast Evaluation of Polynomials and Inverses of Polynomials
entry:
@InProceedings{Merrheim:1993:FEP,
  author =       "Xavier Merrheim and Jean-Michel Muller and Hong-Jin
                 Yeh",
  title =        "Fast Evaluation of Polynomials and Inverses of
                 Polynomials",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "186--192",
  year =         "1993",
  bibdate =      "Sat Nov 17 09:46:07 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Merrheim.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: mastersthesis
filename: fparith.bib
label: Mesfin:1993:IHP
author: Biniam Mesfin
title: Implementation of a high performance floating point unit multiplier
type: Thesis (M.A.Sc.)
school: University of Windsor
address: Windsor, ON, Canada
pages: 186--192
year: 1993
ISBN: 0-315-78864-X OR 031578864X
ISBN13: 978-0-315-78864-0 OR 9780315788640
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: National Library of Canada = Bibliotheque nationale du Canada; Canadian theses = Theses canadiennes
remark: 3 microfiches. University Microfilms order no. UMI00399117
acknowledgement: ack-nhfb
rawauthor: Biniam Mesfin
rawtitle: Implementation of a high performance floating point unit multiplier
entry:
@MastersThesis{Mesfin:1993:IHP,
  author =       "Biniam Mesfin",
  title =        "Implementation of a high performance floating point
                 unit multiplier",
  type =         "Thesis ({M.A.Sc.})",
  school =       "University of Windsor",
  address =      "Windsor, ON, Canada",
  year =         "1993",
  ISBN =         "0-315-78864-X",
  ISBN-13 =      "978-0-315-78864-0",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "National Library of Canada = Bibliotheque nationale du
                 Canada; Canadian theses = Theses canadiennes",
  acknowledgement = ack-nhfb,
  remark =       "3 microfiches. University Microfilms order no.
                 UMI00399117",
}


bibtype: article
filename: fparith.bib
label: Metzger:1993:IFR
author: D. Metzger
journal: j-IEEE-TRANS-SIG-PROC
volume: 41
number: 1
pages: 449
month: jan
monthnumber: 1
year: 1993
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: D. Metzger
title:
Investigation of Finite Register Length Effects on Winograd FFT Computation Using Floating Point Math

rawtitle:
Investigation of Finite Register Length Effects on {Winograd} {FFT} Computation Using Floating Point Math

entry:
@Article{Metzger:1993:IFR,
  author =       "D. Metzger",
  title =        "Investigation of Finite Register Length Effects on
                 {Winograd} {FFT} Computation Using Floating Point
                 Math",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "41",
  number =       "1",
  pages =        "449",
  month =        jan,
  year =         "1993",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
}


bibtype: manual
filename: fparith.bib
label: MicrosoftCorporation:1993:PGM
author: Microsoft Corporation
title: Programmer's guides: Microsoft Visual C++ development system for Windows: version 1.0
organization: Microsoft Corp.
address: Redmond, WA, USA
pages: various
year: 1993
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: C++ (Computer program language); Microsoft Visual C++.
acknowledgement: ack-nhfb
rawauthor: {Microsoft Corporation}
rawtitle: Programmer's guides: {Microsoft Visual C++} development system for {Windows}: version 1.0
remark:
C++ tutorial: introduction to C++: a first look at C++; C++ enhancements to C; references; classes: introduction to classes; classes and dynamic memory allocation; more features of classes; inheritance and polymorphism; operator overloading and conversion functions; object-oriented design: fundamentals of object-oriented design; design example, a windowing class --- Class library user's guide for the Microsoft Foundation Class Library: introducing the class library; creating a new application with AppWizard; creating the document, view; constructing the user interface with App Studio; binding visual objects to code using ClassWizard; adding a dialog box; enhancing views, printing; adding context-sensitive help; general-prupose classes; CObject class; collections; files and serialization; diagnostics; exceptions; programming with VBX controls; OLE support --- Programming techniques: improving program performance: using precompiled headers; managing memory for 16-bit C programs; controlling floating-point math operations; special environments: programming for Windows; programming with mixed languages; writing portable C programs. [Section one of the book], the C++ tutorial, provides an introduction to the C++ language and object-oriented programming. [It] assumes [the reader is] familiar with C ldots [Section two] contains a tutorial for the Microsoft Foundation Class Library. The class library is a set of C++ classes that encapsulate the functionality of applications written for the Microsoft Windows operating system ldots [Section three], programming techniques, describes how to take advantage of the special features of Microsoft Visual C++. The topics covered ldots include language extensions, special-purpose library functions, and the interaction between programming strategies and compiler options. [This section] is divided into two parts. Part I, ``Improving Program Performance,'' helps [the reader] write more efficient programs ldots Part 2, ``Special Environments,'' covers techniques specific to certain programming situations. -Introds.

entry:
@Manual{MicrosoftCorporation:1993:PGM,
  author =       "{Microsoft Corporation}",
  title =        "Programmer's guides: {Microsoft Visual C++}
                 development system for {Windows}: version 1.0",
  organization = "Microsoft Corp.",
  address =      "Redmond, WA, USA",
  pages =        "various",
  year =         "1993",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "C++ (Computer program language); Microsoft Visual
                 C++.",
  remark =       "C++ tutorial: introduction to C++: a first look at
                 C++; C++ enhancements to C; references; classes:
                 introduction to classes; classes and dynamic memory
                 allocation; more features of classes; inheritance and
                 polymorphism; operator overloading and conversion
                 functions; object-oriented design: fundamentals of
                 object-oriented design; design example, a windowing
                 class --- Class library user's guide for the Microsoft
                 Foundation Class Library: introducing the class
                 library; creating a new application with AppWizard;
                 creating the document, view; constructing the user
                 interface with App Studio; binding visual objects to
                 code using ClassWizard; adding a dialog box; enhancing
                 views, printing; adding context-sensitive help;
                 general-prupose classes; CObject class; collections;
                 files and serialization; diagnostics; exceptions;
                 programming with VBX controls; OLE support ---
                 Programming techniques: improving program performance:
                 using precompiled headers; managing memory for 16-bit C
                 programs; controlling floating-point math operations;
                 special environments: programming for Windows;
                 programming with mixed languages; writing portable C
                 programs. [Section one of the book], the C++ tutorial,
                 provides an introduction to the C++ language and
                 object-oriented programming. [It] assumes [the reader
                 is] familiar with C \ldots{} [Section two] contains a
                 tutorial for the Microsoft Foundation Class Library.
                 The class library is a set of C++ classes that
                 encapsulate the functionality of applications written
                 for the Microsoft Windows operating system \ldots{}
                 [Section three], programming techniques, describes how
                 to take advantage of the special features of Microsoft
                 Visual C++. The topics covered \ldots{} include
                 language extensions, special-purpose library functions,
                 and the interaction between programming strategies and
                 compiler options. [This section] is divided into two
                 parts. Part I, ``Improving Program Performance,'' helps
                 [the reader] write more efficient programs \ldots{}
                 Part 2, ``Special Environments,'' covers techniques
                 specific to certain programming situations. -Introds.",
}


bibtype: article
filename: fparith.bib
label: Mikami:1993:RER
author: N. Mikami and M. Kobayashi and Y. Yokoyama
journal: j-IEEE-TRANS-SIG-PROC
volume: 41
number: 5
pages: 1953--1955
month: may
monthnumber: 5
year: 1993
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: N. Mikami and M. Kobayashi and Y. Yokoyama
title:
Roundoff-error reduction for evaluation of a function by polynomial approximation with error feedback in fixed-point arithmetic

rawtitle:
Roundoff-error reduction for evaluation of a function by polynomial approximation with error feedback in fixed-point arithmetic

entry:
@Article{Mikami:1993:RER,
  author =       "N. Mikami and M. Kobayashi and Y. Yokoyama",
  title =        "Roundoff-error reduction for evaluation of a function
                 by polynomial approximation with error feedback in
                 fixed-point arithmetic",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "41",
  number =       "5",
  pages =        "1953--1955",
  month =        may,
  year =         "1993",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "The relationship between Hornor's method for
                 polynomial evaluation and a first-order recursive
                 filter with error feedback (EFB) is described. It is
                 shown that EFB is a useful technique for reducing the
                 roundoff errors that occur in evaluating a \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Montuschi:1993:CSM
author: Paolo Montuschi and Luigi Ciminiera
title: $ n times n $ Carry-Save Multipliers without Final Addition
crossref: Swartzlander:1993:SCA
pages: 54--61
year: 1993
bibdate: Sat Nov 17 09:46:07 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 09:46:07 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Montuschi.pdf
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: Paolo Montuschi and Luigi Ciminiera
rawtitle: $ n \times n $ Carry-Save Multipliers without Final Addition
entry:
@InProceedings{Montuschi:1993:CSM,
  author =       "Paolo Montuschi and Luigi Ciminiera",
  title =        "$ n \times n $ Carry-Save Multipliers without Final
                 Addition",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "54--61",
  year =         "1993",
  bibdate =      "Sat Nov 17 09:46:07 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Montuschi.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: article
filename: fparith.bib
label: Montuschi:1993:RIT
author: P. Montuschi and L. Ciminiera
journal: j-IEEE-TRANS-COMPUT
volume: 42
number: 2
pages: 239--246
month: feb
monthnumber: 2
year: 1993
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.204797
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:58:47 MDT 2011
bibtimestamp: 2011.07.07 07:58:47 MDT
note: See remark cite Montuschi:1995:RRI.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=204797
fjournal: IEEE Transactions on Computers
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Montuschi and L. Ciminiera
rawnote: See remark \cite{Montuschi:1995:RRI}.
title:
Reducing iteration time when result digit is zero for radix $2$ SRT division and square root with redundant remainders

rawtitle:
Reducing iteration time when result digit is zero for radix $2$ {SRT} division and square root with redundant remainders

entry:
@Article{Montuschi:1993:RIT,
  author =       "P. Montuschi and L. Ciminiera",
  title =        "Reducing iteration time when result digit is zero for
                 radix $2$ {SRT} division and square root with redundant
                 remainders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "42",
  number =       "2",
  pages =        "239--246",
  month =        feb,
  year =         "1993",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.204797",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:58:47 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  note =         "See remark \cite{Montuschi:1995:RRI}.",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=204797",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "A new architecture is presented for shared radix 2
                 division and square root whose main characteristic is
                 the ability to avoid any addition/subtraction, when the
                 digit 0 has been selected. The solution presented uses
                 a redundant representation of the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Motteler:1993:APF
author: Frederick C. Motteler
title: Arbitrary Precision Floating-Point Arithmetic
journal: j-DDJ
volume: 18
number: 9
pages: 28, 30, 32, 34, 84, 86--87
month: sep
monthnumber: 9
year: 1993
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 03 09:15:43 1996
bibtimestamp: 1996.09.03 09:15:43 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
affiliation: Zetron Inc., Redmond, WA, USA
thesaurus: C listings; Digital arithmetic; Mathematics computing; Software portability; Subroutines
rawauthor: Frederick C. Motteler
rawtitle: Arbitrary Precision Floating-Point Arithmetic
bibsource:
http://www.ddj.com/index/author/index.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib; UnCover database

abstract:
The C library presented was developed with IEEE-754 compatibility and portability as its primary goals. Its first application was as part of a portable cross compiler. It is a general-purpose library that supports single, double, double-extended, and longer IEEE-754 like formats. The library has been ported to and tested on a variety of systems including CP/M, PCs running MS-DOS, PCs running Coherent, Sun 3s, Sparcstations (Sun's C compiler), and the IBM RS/6000 under AIX. The package is K and R, ANSI C, and C++ compatible. A table-driven tester included with the library checks if it has compiled properly. The tester also gives an idea of what the package is capable of doing.

keywords:
C library; Coherent; CP/M; Double-extended; Floating-point arithmetic; General-purpose library; IBM RS/6000; IEEE-754 compatibility; IEEE-754 like formats; MS-DOS; PCs; Portability; Portable cross compiler; Sparcstations; Sun 3s; Table-driven tester

rawabstract:
The C library presented was developed with IEEE-754 compatibility and portability as its primary goals. Its first application was as part of a portable cross compiler. It is a general-purpose library that supports single, double, double-extended, and longer IEEE-754 like formats. The library has been ported to and tested on a variety of systems including CP/M, PCs running MS-DOS, PCs running Coherent, Sun 3s, Sparcstations (Sun's C compiler), and the IBM RS/6000 under AIX. The package is K and R, ANSI C, and C++ compatible. A table-driven tester included with the library checks if it has compiled properly. The tester also gives an idea of what the package is capable of doing.

entry:
@Article{Motteler:1993:APF,
  author =       "Frederick C. Motteler",
  title =        "Arbitrary Precision Floating-Point Arithmetic",
  journal =      j-DDJ,
  volume =       "18",
  number =       "9",
  pages =        "28, 30, 32, 34, 84, 86--87",
  month =        sep,
  year =         "1993",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 03 09:15:43 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "The C library presented was developed with IEEE-754
                 compatibility and portability as its primary goals. Its
                 first application was as part of a portable cross
                 compiler. It is a general-purpose library that supports
                 single, double, double-extended, and longer IEEE-754
                 like formats. The library has been ported to and tested
                 on a variety of systems including CP/M, PCs running
                 MS-DOS, PCs running Coherent, Sun 3s, Sparcstations
                 (Sun's C compiler), and the IBM RS/6000 under AIX. The
                 package is K and R, ANSI C, and C++ compatible. A
                 table-driven tester included with the library checks if
                 it has compiled properly. The tester also gives an idea
                 of what the package is capable of doing.",
  acknowledgement = ack-nhfb,
  affiliation =  "Zetron Inc., Redmond, WA, USA",
  classification = "C5230 (Digital arithmetic methods); C7310
                 (Mathematics)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "C library; Coherent; CP/M; Double-extended;
                 Floating-point arithmetic; General-purpose library; IBM
                 RS/6000; IEEE-754 compatibility; IEEE-754 like formats;
                 MS-DOS; PCs; Portability; Portable cross compiler;
                 Sparcstations; Sun 3s; Table-driven tester",
  thesaurus =    "C listings; Digital arithmetic; Mathematics computing;
                 Software portability; Subroutines",
}


bibtype: misc
filename: fparith.bib
label: Ng:1993:FV
author: K-C Ng
title: FDLIBM Version 5.3
pages: 28, 30, 32, 34, 84, 86--87
year: 1993
bibdate: Thu Oct 17 06:21:14 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 06:21:14 ???
URL: http://www.netlib.org/fdlibm/readme
keywords: FDLIBM (Freely Distributable Math Library)
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: K-C Ng
rawtitle: {FDLIBM} Version 5.3
entry:
@Misc{Ng:1993:FV,
  author =       "K-C Ng",
  title =        "{FDLIBM} Version 5.3",
  howpublished = "Web site",
  year =         "1993",
  bibdate =      "Thu Oct 17 06:21:14 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.netlib.org/fdlibm/readme",
  acknowledgement = ack-nhfb,
  keywords =     "FDLIBM (Freely Distributable Math Library)",
}


bibtype: inproceedings
filename: fparith.bib
label: Nguyen:1993:LDR
author: Q. H. Nguyen and I. Kollar
title: Limited dynamic range of spectrum analysis due to roundoff errors of the FFT
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 47--50
year: 1993
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: Q. H. Nguyen and I. Kollar
rawtitle: Limited dynamic range of spectrum analysis due to roundoff errors of the {FFT}
booktitle:
Instrumentation and Measurement Technology Conference, 1993. IMTC/93. Conference Record., IEEE. 18--20 May 1993

rawbooktitle:
Instrumentation and Measurement Technology Conference, 1993. {IMTC/93}. Conference Record., {IEEE. 18--20} May 1993

entry:
@InProceedings{Nguyen:1993:LDR,
  author =       "Q. H. Nguyen and I. Kollar",
  booktitle =    "Instrumentation and Measurement Technology Conference,
                 1993. {IMTC/93}. Conference Record., {IEEE. 18--20} May
                 1993",
  title =        "Limited dynamic range of spectrum analysis due to
                 roundoff errors of the {FFT}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "47--50",
  year =         "1993",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Roundoff errors of the block-float fast Fourier
                 transform (FFT) are treated. Special emphasis is given
                 to the case when signals containing sine waves are
                 analyzed. In the detection and analysis of sine waves,
                 root-mean-square values and overall \ldots{}",
}


bibtype: article
filename: fparith.bib
label: North:1993:FPA
author: R. C. North and J. R. Zeidler and W. H. Ku and T. R. Albert
journal: j-IEEE-TRANS-SIG-PROC
volume: 41
number: 5
pages: 1809--1823
month: may
monthnumber: 5
year: 1993
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: R. C. North and J. R. Zeidler and W. H. Ku and T. R. Albert
title:
A floating-point arithmetic error analysis of direct and indirect coefficient updating techniques for adaptive lattice filters

rawtitle:
A floating-point arithmetic error analysis of direct and indirect coefficient updating techniques for adaptive lattice filters

entry:
@Article{North:1993:FPA,
  author =       "R. C. North and J. R. Zeidler and W. H. Ku and T. R.
                 Albert",
  title =        "A floating-point arithmetic error analysis of direct
                 and indirect coefficient updating techniques for
                 adaptive lattice filters",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "41",
  number =       "5",
  pages =        "1809--1823",
  month =        may,
  year =         "1993",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "The ways in which finite precision arithmetic effects
                 can deleteriously manifest themselves in both the
                 stochastic gradient and the recursive least squares
                 adaptive lattice filters are discussed. closed form
                 expressions are derived for the steady-state \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ozawa:1993:SAE
author: K. Ozawa and M. Miyazaki
title: A summation algorithm with error correction for parallel computers
journal: j-SYS-COMP-JAPAN
volume: 24
number: 7
pages: 62--68
year: 1993
CODEN: SCJAEP
ISSN: 0882-1666 (print), 1520-684X (electronic) OR 08821666 (print), 1520684X (electronic)
ISSNL: 0882-1666 OR 08821666
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Systems and computers in Japan
acknowledgement: ack-nhfb
affiliation: Coll. of Gen. Educ., Tohoku University, Sendai, Japan
thesaurus: computational complexity; error correction; parallel algorithms
rawauthor: K. Ozawa and M. Miyazaki
rawtitle: A summation algorithm with error correction for parallel computers
abstract:
Proposes an algorithm to accurately compute the sum of floating-point numbers on parallel computers. This algorithm is an extension of the well-known recursive doubling technique which computes the sum of n floating-point number in log/sub 2/n parallel steps. The time complexity of the present algorithm also is O(logn), and the space complexity is O(n). This algorithm enables a highly accurate result to be obtained with guarantee. The theoretical analysis and the numerical experiments on a parallel computer show that this algorithm is as accurate as Kahan's, which is the fastest and an accurate serial algorithm for the summation of the numbers, and also that the present algorithm is faster than Kahan's provided that two or more processors are available.

keywords:
accurate floating-point summation; correct rounding; error correction; floating-point numbers; guaranteed accuracy; parallel computation; parallel computers; recursive doubling; recursive doubling technique; round-off error analysis; space complexity; summation; summation algorithm; time complexity

rawabstract:
Proposes an algorithm to accurately compute the sum of floating-point numbers on parallel computers. This algorithm is an extension of the well-known recursive doubling technique which computes the sum of n floating-point number in log/sub 2/n parallel steps. The time complexity of the present algorithm also is O(logn), and the space complexity is O(n). This algorithm enables a highly accurate result to be obtained with guarantee. The theoretical analysis and the numerical experiments on a parallel computer show that this algorithm is as accurate as Kahan's, which is the fastest and an accurate serial algorithm for the summation of the numbers, and also that the present algorithm is faster than Kahan's provided that two or more processors are available.

entry:
@Article{Ozawa:1993:SAE,
  author =       "K. Ozawa and M. Miyazaki",
  title =        "A summation algorithm with error correction for
                 parallel computers",
  journal =      j-SYS-COMP-JAPAN,
  volume =       "24",
  number =       "7",
  pages =        "62--68",
  month =        "????",
  year =         "1993",
  CODEN =        "SCJAEP",
  ISSN =         "0882-1666 (print), 1520-684X (electronic)",
  ISSN-L =       "0882-1666",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Proposes an algorithm to accurately compute the sum of
                 floating-point numbers on parallel computers. This
                 algorithm is an extension of the well-known recursive
                 doubling technique which computes the sum of n
                 floating-point number in log/sub 2/n parallel steps.
                 The time complexity of the present algorithm also is
                 O(logn), and the space complexity is O(n). This
                 algorithm enables a highly accurate result to be
                 obtained with guarantee. The theoretical analysis and
                 the numerical experiments on a parallel computer show
                 that this algorithm is as accurate as Kahan's, which is
                 the fastest and an accurate serial algorithm for the
                 summation of the numbers, and also that the present
                 algorithm is faster than Kahan's provided that two or
                 more processors are available.",
  acknowledgement = ack-nhfb,
  affiliation =  "Coll. of Gen. Educ., Tohoku University, Sendai,
                 Japan",
  classification = "C4110 (Error analysis in numerical methods); C4240P
                 (Parallel programming and algorithm theory)",
  fjournal =     "Systems and computers in Japan",
  keywords =     "accurate floating-point summation; correct rounding;
                 error correction; floating-point numbers; guaranteed
                 accuracy; parallel computation; parallel computers;
                 recursive doubling; recursive doubling technique;
                 round-off error analysis; space complexity; summation;
                 summation algorithm; time complexity",
  thesaurus =    "computational complexity; error correction; parallel
                 algorithms",
}


bibtype: phdthesis
filename: fparith.bib
label: Pan:1993:TFVa
author: Jing Pan
type: Thesis (Ph.D.)
school: Computer Science Department, University of California, Davis
address: Davis, CA, USA
pages: 221
year: 1993
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Jing Pan
title:
Toward a formal verification of a floating-point coprocessor and its composition with a central processing unit

rawtitle:
Toward a formal verification of a floating-point coprocessor and its composition with a central processing unit

entry:
@PhdThesis{Pan:1993:TFVa,
  author =       "Jing Pan",
  title =        "Toward a formal verification of a floating-point
                 coprocessor and its composition with a central
                 processing unit",
  type =         "Thesis ({Ph.D.})",
  school =       "Computer Science Department, University of California,
                 Davis",
  address =      "Davis, CA, USA",
  pages =        "221",
  year =         "1993",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Pan:1993:TFVb
author: Jing Pan and K. N. Levitt and M. Archer and S. Kalvala
journal: j-IFIP-TRANS-A
volume: A20
pages: 427--447
year: 1993
CODEN: ITATEC
ISSN: 0926-5473 OR 09265473
bibdate: Tue Dec 12 09:27:13 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:27:13 MST
fjournal: IFIP Transactions. A. Computer Science and Technology
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, California University, Davis, CA, USA
thesaurus: Digital arithmetic; Formal verification; Microprocessor chips; Theorem proving
rawauthor: Jing Pan and K. N. Levitt and M. Archer and S. Kalvala
title:
Towards a formal verification of a floating point coprocessor and its composition with a central processing unit

note:
Higher Order Logic Theorem Proving and its Applications IFIP TC / WG10.2 International Workshop - HOL '92.

abstract:
The authors discuss verification (ultimately down to the microcode level) of a microprocessor that consists of a central processing unit that is the master of a floating point coprocessor; the design is drawn from the MC68881 floating point coprocessor slaved to the MC68000, but greatly simplified. The coprocessor in isolation is verified with respect to a specification that captures the IEEE floating point standard. In the authors system, CPU and floating point instructions are allowed to execute concurrently, but the appearance to the programmer of the composed system is that of a sequentially executing instruction stream. The CPU and floating point coprocessor communicate through the four-phase handshaking protocol. The verification involves reasoning about a form of behavioural abstraction wherein concurrently executing instruction steams are mapped to a sequential stream.

keywords:
Behavioural abstraction; Central processing unit; Concurrently executing instruction steams; Floating point coprocessor; Formal verification; Four-phase handshaking protocol; MC68000; MC68881; Microprocessor; Reasoning; Sequentially executing instruction stream; Specification

rawabstract:
The authors discuss verification (ultimately down to the microcode level) of a microprocessor that consists of a central processing unit that is the master of a floating point coprocessor; the design is drawn from the MC68881 floating point coprocessor slaved to the MC68000, but greatly simplified. The coprocessor in isolation is verified with respect to a specification that captures the IEEE floating point standard. In the authors system, CPU and floating point instructions are allowed to execute concurrently, but the appearance to the programmer of the composed system is that of a sequentially executing instruction stream. The CPU and floating point coprocessor communicate through the four-phase handshaking protocol. The verification involves reasoning about a form of behavioural abstraction wherein concurrently executing instruction steams are mapped to a sequential stream.

rawnote:
Higher Order Logic Theorem Proving and its Applications IFIP TC\slash WG10.2 International Workshop - HOL '92.

rawtitle:
Towards a formal verification of a floating point coprocessor and its composition with a central processing unit

entry:
@Article{Pan:1993:TFVb,
  author =       "Jing Pan and K. N. Levitt and M. Archer and S.
                 Kalvala",
  title =        "Towards a formal verification of a floating point
                 coprocessor and its composition with a central
                 processing unit",
  journal =      j-IFIP-TRANS-A,
  volume =       "A20",
  pages =        "427--447",
  month =        "????",
  year =         "1993",
  CODEN =        "ITATEC",
  ISSN =         "0926-5473",
  bibdate =      "Tue Dec 12 09:27:13 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Higher Order Logic Theorem Proving and its
                 Applications IFIP TC\slash WG10.2 International
                 Workshop - HOL '92.",
  abstract =     "The authors discuss verification (ultimately down to
                 the microcode level) of a microprocessor that consists
                 of a central processing unit that is the master of a
                 floating point coprocessor; the design is drawn from
                 the MC68881 floating point coprocessor slaved to the
                 MC68000, but greatly simplified. The coprocessor in
                 isolation is verified with respect to a specification
                 that captures the IEEE floating point standard. In the
                 authors system, CPU and floating point instructions are
                 allowed to execute concurrently, but the appearance to
                 the programmer of the composed system is that of a
                 sequentially executing instruction stream. The CPU and
                 floating point coprocessor communicate through the
                 four-phase handshaking protocol. The verification
                 involves reasoning about a form of behavioural
                 abstraction wherein concurrently executing instruction
                 steams are mapped to a sequential stream.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, California University,
                 Davis, CA, USA",
  classification = "C4210 (Formal logic); C5130 (Microprocessor chips);
                 C5230 (Digital arithmetic methods); C6110B (Software
                 engineering techniques)",
  confdate =     "21-24 Sept. 1992",
  conflocation = "Leuven, Belgium",
  fjournal =     "IFIP Transactions. A. Computer Science and
                 Technology",
  keywords =     "Behavioural abstraction; Central processing unit;
                 Concurrently executing instruction steams; Floating
                 point coprocessor; Formal verification; Four-phase
                 handshaking protocol; MC68000; MC68881; Microprocessor;
                 Reasoning; Sequentially executing instruction stream;
                 Specification",
  pubcountry =   "Netherlands",
  thesaurus =    "Digital arithmetic; Formal verification;
                 Microprocessor chips; Theorem proving",
}


bibtype: inproceedings
filename: fparith.bib
label: Panneerselvam:1993:MAF
author: G. Panneerselvam and B. Nowrouzian
title: Multiply-add fused RISC architectures for DSP applications
crossref: IEEE:1993:PIP
volume: 1
pages: 108--111
year: 1993
DOI: https://doi.org/10.1109/PACRIM.1993.407210
bibdate: Sun Feb 20 10:47:10 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:47:10 ???
acknowledgement: ack-nhfb
rawauthor: G. Panneerselvam and B. Nowrouzian
rawtitle: Multiply-add fused {RISC} architectures for {DSP} applications
abstract:
The development of a fixed-point bit-parallel multiply-add fused (MAF) architecture together with a corresponding VLSI implementation is presented. The proposed MAF implementation employs 1.2 CMOS technology. This MAF implementation finds a variety of practical applications in high-speed real-time digital signal processing. The MAF implementation employs a parallel modified Booth multiplier incorporating an array of carry-save adders for the addition of the intermediate partial products, and a hardware efficient carry-skip adder for carry propagation. The performance characteristics of the MAF implementation have been successfully verified by an HSPICE simulation at speeds of up to 100 MHz.

rawabstract:
The development of a fixed-point bit-parallel multiply-add fused (MAF) architecture together with a corresponding VLSI implementation is presented. The proposed MAF implementation employs 1.2 CMOS technology. This MAF implementation finds a variety of practical applications in high-speed real-time digital signal processing. The MAF implementation employs a parallel modified Booth multiplier incorporating an array of carry-save adders for the addition of the intermediate partial products, and a hardware efficient carry-skip adder for carry propagation. The performance characteristics of the MAF implementation have been successfully verified by an HSPICE simulation at speeds of up to 100 MHz.

entry:
@InProceedings{Panneerselvam:1993:MAF,
  author =       "G. Panneerselvam and B. Nowrouzian",
  title =        "Multiply-add fused {RISC} architectures for {DSP}
                 applications",
  crossref =     "IEEE:1993:PIP",
  volume =       "1",
  pages =        "108--111",
  year =         "1993",
  DOI =          "https://doi.org/10.1109/PACRIM.1993.407210",
  bibdate =      "Sun Feb 20 10:47:10 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The development of a fixed-point bit-parallel
                 multiply-add fused (MAF) architecture together with a
                 corresponding VLSI implementation is presented. The
                 proposed MAF implementation employs 1.2 CMOS
                 technology. This MAF implementation finds a variety of
                 practical applications in high-speed real-time digital
                 signal processing. The MAF implementation employs a
                 parallel modified Booth multiplier incorporating an
                 array of carry-save adders for the addition of the
                 intermediate partial products, and a hardware efficient
                 carry-skip adder for carry propagation. The performance
                 characteristics of the MAF implementation have been
                 successfully verified by an HSPICE simulation at speeds
                 of up to 100 MHz.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Parhami:1993:IAS
author: B. Parhami
title: On the implementation of arithmetic support functions for generalized signed-digit number systems
journal: j-IEEE-TRANS-COMPUT
volume: 42
number: 3
pages: 379--384
month: mar
monthnumber: 3
year: 1993
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.210182
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:58:48 MDT 2011
bibtimestamp: 2011.07.07 07:58:48 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=210182
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. Parhami
rawtitle: On the implementation of arithmetic support functions for generalized signed-digit number systems
entry:
@Article{Parhami:1993:IAS,
  author =       "B. Parhami",
  title =        "On the implementation of arithmetic support functions
                 for generalized signed-digit number systems",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "42",
  number =       "3",
  pages =        "379--384",
  month =        mar,
  year =         "1993",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.210182",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:58:48 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=210182",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Parker:1993:OHS
author: A. Parker
title: Optimization of high speed function generation using table-lookup
journal: j-TRANS-SOC-COMP-SIM
volume: 10
number: 2
pages: 105--114
month: jun
monthnumber: 6
year: 1993
CODEN: TSCSEV
ISSN: 0740-6797 OR 07406797
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Transactions of the Society for Computer Simulation
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Alabama University, Huntsville, AL, USA
thesaurus: Equivalence classes; Function evaluation; Symbol manipulation; Table lookup
rawauthor: A. Parker
rawtitle: Optimization of high speed function generation using table-lookup
abstract:
A process is presented for the use of generic operator optimization for the evaluation of unary floating point functions using table lookup. The process involves the identification of an underlying architecture and the symbolic-numeric optimization of operators to minimize a least-squares representation of total error. The approach is illustrated for the case of floating point division.

keywords:
Floating point division; High speed function generation; Least-squares representation; Symbolic-numeric optimization; Table lookup

rawabstract:
A process is presented for the use of generic operator optimization for the evaluation of unary floating point functions using table lookup. The process involves the identification of an underlying architecture and the symbolic-numeric optimization of operators to minimize a least-squares representation of total error. The approach is illustrated for the case of floating point division.

entry:
@Article{Parker:1993:OHS,
  author =       "A. Parker",
  title =        "Optimization of high speed function generation using
                 table-lookup",
  journal =      j-TRANS-SOC-COMP-SIM,
  volume =       "10",
  number =       "2",
  pages =        "105--114",
  month =        jun,
  year =         "1993",
  CODEN =        "TSCSEV",
  ISSN =         "0740-6797",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A process is presented for the use of generic operator
                 optimization for the evaluation of unary floating point
                 functions using table lookup. The process involves the
                 identification of an underlying architecture and the
                 symbolic-numeric optimization of operators to minimize
                 a least-squares representation of total error. The
                 approach is illustrated for the case of floating point
                 division.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Alabama
                 University, Huntsville, AL, USA",
  classification = "C1160 (Combinatorial mathematics); C4120 (Functional
                 analysis); C6130 (Data handling techniques)",
  fjournal =     "Transactions of the Society for Computer Simulation",
  keywords =     "Floating point division; High speed function
                 generation; Least-squares representation;
                 Symbolic-numeric optimization; Table lookup",
  thesaurus =    "Equivalence classes; Function evaluation; Symbol
                 manipulation; Table lookup",
}


bibtype: book
filename: fparith.bib
label: Pichat:1993:IDC
author: Michele Pichat and Jean Vignes
title: Ingenierie du controle de la precision des calculs sur ordinateur
publisher: Editions Technip
address: Paris, France
pages: xvii + 233
year: 1993
ISBN: 2-7108-0653-3 OR 2710806533
ISBN13: 978-2-7108-0653-0 OR 9782710806530
LCCN: TJ213 .P478 1993
bibdate: Wed Nov 24 12:28:18 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2004.11.24 12:28:18 ???
series: Collection Informatique
subject: Automatic control; Microcomputers
acknowledgement: ack-nhfb
rawauthor: Mich{\`e}le Pichat and Jean Vignes
rawtitle: Ing{\'e}nierie du contr{\^o}le de la pr{\'e}cision des calculs sur ordinateur
entry:
@Book{Pichat:1993:IDC,
  author =       "Mich{\`e}le Pichat and Jean Vignes",
  title =        "Ing{\'e}nierie du contr{\^o}le de la pr{\'e}cision des
                 calculs sur ordinateur",
  publisher =    "Editions Technip",
  address =      "Paris, France",
  pages =        "xvii + 233",
  year =         "1993",
  ISBN =         "2-7108-0653-3",
  ISBN-13 =      "978-2-7108-0653-0",
  LCCN =         "TJ213 .P478 1993",
  bibdate =      "Wed Nov 24 12:28:18 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  series =       "Collection Informatique",
  acknowledgement = ack-nhfb,
  subject =      "Automatic control; Microcomputers",
}


bibtype: article
filename: fparith.bib
label: Plauger:1993:FCE
author: P. J. Plauger
title: Floating-Point C Extensions
journal: j-CUJ
volume: 11
type: Standard C
number: 9
pages: 10--??
month: sep
monthnumber: 9
year: 1993
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: P. J. Plauger
rawtitle: Floating-Point {C} Extensions
entry:
@Article{Plauger:1993:FCE,
  author =       "P. J. Plauger",
  title =        "Floating-Point {C} Extensions",
  journal =      j-CUJ,
  volume =       "11",
  type =         "{Standard C}",
  number =       "9",
  pages =        "10--??",
  month =        sep,
  year =         "1993",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: book
filename: fparith.bib
label: Plauger:1993:PPIc
author: P. J. Plauger
title: Programming on Purpose III: Essays on Software Technology
volume: 3
publisher: pub-PHPTR
address: pub-PHPTR:adr
pages: viii + 224
year: 1993
ISBN: 0-13-328113-2 OR 0133281132
ISBN13: 978-0-13-328113-2 OR 9780133281132
LCCN: QA76.76.D47 P53 1994
bibdate: Wed Jul 6 14:26:01 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib
bibtimestamp: 1994.07.06 14:26:01 ???
acknowledgement: ack-nhfb
rawauthor: P. J. Plauger
rawtitle: Programming on Purpose {III}: Essays on Software Technology
remark:
Originally published in the author's monthly column in Computer language magazine, 1986-1992. Contents: Volume I: Essays on software design -- volume II: Essays on software people -- volume III: Essays on software technology.

TOC:
You Must Be Joking Computer Arithmetic Floating-Point Arithmetic The Central Folly Safe Math Do-It-Yourself Math Functions Locking the Barn Door Half a Secret It's (Almost) Alive The (Almost) Right Stuff Instant Lies What Meets the Eye Technicolor and Cinemascope What Meets the Ear Warm Fuzzies Font Follies Text Editors Approximating Functions Economizing Polynomials Technical Writing All I Want to Do Is Programming for the Billions All Sorts of Sorts Transforming Strings Books for Our Times Through the Grapevine List of Columns Bibliography Index

rawTOC:
You Must Be Joking \\ Computer Arithmetic \\ Floating-Point Arithmetic \\ The Central Folly \\ Safe Math \\ Do-It-Yourself Math Functions \\ Locking the Barn Door \\ Half a Secret \\ It's (Almost) Alive \\ The (Almost) Right Stuff \\ Instant Lies \\ What Meets the Eye \\ Technicolor and Cinemascope \\ What Meets the Ear \\ Warm Fuzzies \\ Font Follies \\ Text Editors \\ Approximating Functions \\ Economizing Polynomials \\ Technical Writing \\ All I Want to Do Is \\ Programming for the Billions \\ All Sorts of Sorts \\ Transforming Strings \\ Books for Our Times \\ Through the Grapevine \\ List of Columns \\ Bibliography \\ Index

entry:
@Book{Plauger:1993:PPIc,
  author =       "P. J. Plauger",
  title =        "Programming on Purpose {III}: Essays on Software
                 Technology",
  volume =       "3",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "viii + 224",
  year =         "1993",
  ISBN =         "0-13-328113-2",
  ISBN-13 =      "978-0-13-328113-2",
  LCCN =         "QA76.76.D47 P53 1994",
  bibdate =      "Wed Jul 6 14:26:01 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  price =        "US\$19.95",
  acknowledgement = ack-nhfb,
  libnote =      "Not yet in my library.",
  remark =       "Originally published in the author's monthly column in
                 Computer language magazine, 1986-1992. Contents: Volume
                 I: Essays on software design -- volume II: Essays on
                 software people -- volume III: Essays on software
                 technology.",
  tableofcontents = "You Must Be Joking \\
                 Computer Arithmetic \\
                 Floating-Point Arithmetic \\
                 The Central Folly \\
                 Safe Math \\
                 Do-It-Yourself Math Functions \\
                 Locking the Barn Door \\
                 Half a Secret \\
                 It's (Almost) Alive \\
                 The (Almost) Right Stuff \\
                 Instant Lies \\
                 What Meets the Eye \\
                 Technicolor and Cinemascope \\
                 What Meets the Ear \\
                 Warm Fuzzies \\
                 Font Follies \\
                 Text Editors \\
                 Approximating Functions \\
                 Economizing Polynomials \\
                 Technical Writing \\
                 All I Want to Do Is \\
                 Programming for the Billions \\
                 All Sorts of Sorts \\
                 Transforming Strings \\
                 Books for Our Times \\
                 Through the Grapevine \\
                 List of Columns \\
                 Bibliography \\
                 Index",
}


bibtype: article
filename: fparith.bib
label: Posch:1993:BKR
author: K. C. Posch and R. Posch
journal: j-COMPUTING
volume: 50
number: 2
pages: 93--104
year: 1993
CODEN: CMPTA2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 68M07 (11Y16)
MRnumber: 94e:68024
bibdate: Mon Oct 11 20:38:38 MDT 1999
bibtimestamp: 1999.10.11 20:38:38 MDT
fjournal: Computing: Archiv fur informatik und numerik
language: German
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: K. C. Posch and R. Posch
title:
Basiserweiterung mit einer Konvolutionssumme in Restklassenzahlensystemen. (German) [Base Extension Using a Convolution Sum in Residue Number Systems]

bibsource:
http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0010-485X; https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database; OCLC Contents1st database

rawtitle:
{Basiserweiterung mit einer Konvolutionssumme in Restklassenzahlensystemen}. ({German}) [{Base} Extension Using a Convolution Sum in Residue Number Systems]

entry:
@Article{Posch:1993:BKR,
  author =       "K. C. Posch and R. Posch",
  title =        "{Basiserweiterung mit einer Konvolutionssumme in
                 Restklassenzahlensystemen}. ({German}) [{Base}
                 Extension Using a Convolution Sum in Residue Number
                 Systems]",
  journal =      j-COMPUTING,
  volume =       "50",
  number =       "2",
  pages =        "93--104",
  year =         "1993",
  CODEN =        "CMPTA2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "68M07 (11Y16)",
  MRnumber =     "94e:68024",
  bibdate =      "Mon Oct 11 20:38:38 MDT 1999",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0010-485X;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database; OCLC Contents1st database",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  language =     "German",
}


bibtype: article
filename: fparith.bib
label: Pugh:1993:FPC
author: Kenneth Pugh
title: Floating Point Constants
journal: j-CUJ
volume: 11
type: Questions and Answers
number: 10
pages: 130--??
month: oct
monthnumber: 10
year: 1993
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: Kenneth Pugh
rawtitle: Floating Point Constants
entry:
@Article{Pugh:1993:FPC,
  author =       "Kenneth Pugh",
  title =        "Floating Point Constants",
  journal =      j-CUJ,
  volume =       "11",
  type =         "Questions and Answers",
  number =       "10",
  pages =        "130--??",
  month =        oct,
  year =         "1993",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: article
filename: fparith.bib
label: Reid:1993:LIA
author: John Reid
title: Language Independent Arithmetic (LIA) --- a Draft International Standard (DIS)
journal: j-SIGNUM
volume: 28
number: 1
pages: 2--7
month: jan
monthnumber: 1
year: 1993
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:23 MDT 2005
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 07:50:23 MDT
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nhfb
affiliation: Rutherford Appleton Lab., Didcot, UK
journalURL: https://dl.acm.org/loi/signum
thesaurus: Digital arithmetic; High level languages; Standards
rawauthor: John Reid
rawtitle: {Language Independent Arithmetic} ({LIA}) --- a {Draft International Standard} ({DIS})
note:
LIA is now an International Standard, ISO/IEC 10967-1:1994; it is ``92 pages of small print, densely mathematical, not counting 8 pages of front matter, and it is not available electronically.'' Its adoption has been rather controversial.

abstract:
The UK and US votes have been decided on the draft international standard ISO/IEC CD 10967-1:1992: language independent arithmetic-part 1: integer and floating point arithmetic. The stated goals of the draft are: to enhance the portability of numeric programs across a wide range of numeric architectures. To help programming languages express the semantics of their numerical types. It defines integer and (normalized and denormalized) floating point types. It defines integer and (normalized and denormalized) floating point types. It specifies the primitive computational operations with source and destination operands of the same type, comparison operations on two operands of the same type, and conversions from any arithmetic type to any other arithmetic type. The values of parameters define the exact arithmetic behaviour of any particular platform.

keywords:
International standard; Language independent arithmetic; Numeric architectures; Numeric programs; Portability; Programming languages

rawabstract:
The UK and US votes have been decided on the draft international standard ISO/IEC CD 10967-1:1992: language independent arithmetic-part 1: integer and floating point arithmetic. The stated goals of the draft are: to enhance the portability of numeric programs across a wide range of numeric architectures. To help programming languages express the semantics of their numerical types. It defines integer and (normalized and denormalized) floating point types. It defines integer and (normalized and denormalized) floating point types. It specifies the primitive computational operations with source and destination operands of the same type, comparison operations on two operands of the same type, and conversions from any arithmetic type to any other arithmetic type. The values of parameters define the exact arithmetic behaviour of any particular platform.

entry:
@Article{Reid:1993:LIA,
  author =       "John Reid",
  title =        "{Language Independent Arithmetic} ({LIA}) --- a {Draft
                 International Standard} ({DIS})",
  journal =      j-SIGNUM,
  volume =       "28",
  number =       "1",
  pages =        "2--7",
  month =        jan,
  year =         "1993",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:23 MDT 2005",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "LIA is now an International Standard, ISO/IEC
                 10967-1:1994; it is ``92 pages of small print, densely
                 mathematical, not counting 8 pages of front matter, and
                 it is not available electronically.'' Its adoption has
                 been rather controversial.",
  abstract =     "The UK and US votes have been decided on the draft
                 international standard ISO/IEC CD 10967-1:1992:
                 language independent arithmetic-part 1: integer and
                 floating point arithmetic. The stated goals of the
                 draft are: to enhance the portability of numeric
                 programs across a wide range of numeric architectures.
                 To help programming languages express the semantics of
                 their numerical types. It defines integer and
                 (normalized and denormalized) floating point types. It
                 defines integer and (normalized and denormalized)
                 floating point types. It specifies the primitive
                 computational operations with source and destination
                 operands of the same type, comparison operations on two
                 operands of the same type, and conversions from any
                 arithmetic type to any other arithmetic type. The
                 values of parameters define the exact arithmetic
                 behaviour of any particular platform.",
  acknowledgement = ack-nhfb,
  affiliation =  "Rutherford Appleton Lab., Didcot, UK",
  classification = "C5230 (Digital arithmetic methods); C6140D (High
                 level languages)",
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "International standard; Language independent
                 arithmetic; Numeric architectures; Numeric programs;
                 Portability; Programming languages",
  thesaurus =    "Digital arithmetic; High level languages; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Richardson:1993:ETR
author: S. E. Richardson
title: Exploiting trivial and redundant computation
crossref: Swartzlander:1993:SCA
pages: 220--227
year: 1993
bibdate: Thu Jun 20 10:16:15 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.06.20 10:16:15 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Richardson.pdf
keywords: ARITH-11
acknowledgement: ack-sfo
rawauthor: S. E. Richardson
rawtitle: Exploiting trivial and redundant computation
entry:
@InProceedings{Richardson:1993:ETR,
  author =       "S. E. Richardson",
  title =        "Exploiting trivial and redundant computation",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "220--227",
  year =         "1993",
  bibdate =      "Thu Jun 20 10:16:15 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Richardson.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: article
filename: fparith.bib
label: Ris:1993:WFP
author: Fred Ris and Ed Barkmeyer and Craig Schaffert and Peter Farkas
title: When Floating-Point Addition Isn't Commutative
journal: j-SIGNUM
volume: 28
number: 1
pages: 8--13
month: jan
monthnumber: 1
year: 1993
CODEN: SNEWD6
DOI: https://doi.org/10.1145/156301.156303
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:23 MDT 2005
bibtimestamp: 2005.04.12 07:50:23 MDT
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nhfb
affiliation: IBM Federal Syst. Co., Boulder, CO, USA
journalURL: https://dl.acm.org/loi/signum
thesaurus: Digital arithmetic; Standards
rawauthor: Fred Ris and Ed Barkmeyer and Craig Schaffert and Peter Farkas
rawtitle: When Floating-Point Addition Isn't Commutative
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
In the early 1980s, the IEEE floating-point standards (754 for binary formats adopted in 1985 and 854 for more general situations adopted in 1987) were developed. There are now many more-or-less IEEE 754 conformant products on the market. A fully compliant implementation must provide conforming representations of floating-point values, perform arithmetic operations as specified by the standard, provide four rounding modes and five exception flags defined by the standard, support infinities, NaNs, signed zeros, and unordered comparisons, and provide access to all these features from programming languages (as supported by the compiler and runtime library). Not surprisingly, very few implementations comply fully with the IEEE 754 standard in all respects. But one might imagine that if there were such compliance one could expect bit-for-bit identical results for a given algorithm executed on any conforming implementation. The paper explains why this is not always the case.

keywords:
Arithmetic operations; Conforming implementation; Exception flags; Floating-point addition; Floating-point values; IEEE 754; IEEE floating-point standards; Rounding modes

rawabstract:
In the early 1980s, the IEEE floating-point standards (754 for binary formats adopted in 1985 and 854 for more general situations adopted in 1987) were developed. There are now many more-or-less IEEE 754 conformant products on the market. A fully compliant implementation must provide conforming representations of floating-point values, perform arithmetic operations as specified by the standard, provide four rounding modes and five exception flags defined by the standard, support infinities, NaNs, signed zeros, and unordered comparisons, and provide access to all these features from programming languages (as supported by the compiler and runtime library). Not surprisingly, very few implementations comply fully with the IEEE 754 standard in all respects. But one might imagine that if there were such compliance one could expect bit-for-bit identical results for a given algorithm executed on any conforming implementation. The paper explains why this is not always the case.

entry:
@Article{Ris:1993:WFP,
  author =       "Fred Ris and Ed Barkmeyer and Craig Schaffert and
                 Peter Farkas",
  title =        "When Floating-Point Addition Isn't Commutative",
  journal =      j-SIGNUM,
  volume =       "28",
  number =       "1",
  pages =        "8--13",
  month =        jan,
  year =         "1993",
  CODEN =        "SNEWD6",
  DOI =          "https://doi.org/10.1145/156301.156303",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:23 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the early 1980s, the IEEE floating-point standards
                 (754 for binary formats adopted in 1985 and 854 for
                 more general situations adopted in 1987) were
                 developed. There are now many more-or-less IEEE 754
                 conformant products on the market. A fully compliant
                 implementation must provide conforming representations
                 of floating-point values, perform arithmetic operations
                 as specified by the standard, provide four rounding
                 modes and five exception flags defined by the standard,
                 support infinities, NaNs, signed zeros, and unordered
                 comparisons, and provide access to all these features
                 from programming languages (as supported by the
                 compiler and runtime library). Not surprisingly, very
                 few implementations comply fully with the IEEE 754
                 standard in all respects. But one might imagine that if
                 there were such compliance one could expect bit-for-bit
                 identical results for a given algorithm executed on any
                 conforming implementation. The paper explains why this
                 is not always the case.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "IBM Federal Syst. Co., Boulder, CO, USA",
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "Arithmetic operations; Conforming implementation;
                 Exception flags; Floating-point addition;
                 Floating-point values; IEEE 754; IEEE floating-point
                 standards; Rounding modes",
  thesaurus =    "Digital arithmetic; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Samani:1993:SVP
author: D. M. Samani and J. Ellinger and E. J. Powers and E. E. Swartzlander
crossref: IEEE:1993:PMS
pages: 1509--1514 vol.2
year: 1993
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Texas University, Austin, TX, USA
rawauthor: D. M. Samani and J. Ellinger and E. J. Powers and E. E. Swartzlander
title:
Simulation of variable precision IEEE floating point using C++ and its application in digital signal processor design

abstract:
We use a C++ class to transparently emulate variable-precision floating point arithmetic using standard arithmetic. This allows the determination of an algorithm's susceptibility to errors produced by finite-precision arithmetic and the determination of the minimum precision necessary for stability. The class, called Real, offers several advantages for many applications, e.g., ALU design, signal processing, systolic and lattice filter design, etc. Since it supports the IEEE floating point standard, it produces identical results on any compliant platform. An algorithm can be adapted for simulation with minimal effort and without interfering with normal operation. We also consider how the acceptance of the IEEE standard and the development of fast hardware for microcomputers have changed common assumptions about algorithm timing. Finally, we examine the potential use of the new floating point DSP chips for adaptive filtering. Historically, the computational requirements of adaptive filters confined implementations to specialized hardware or supercomputers. Today's DSP chips offer a relatively inexpensive alternative. We have implemented several adaptive filtering algorithms that are based on Least Squares estimation criterion on Motorola's DSP96002. Our experience indicates that the DSP96K is a viable medium for such algorithms and one can expect a ten-fold speed improvement over a i486 running at 50 MHz.

keywords:
Adaptive filtering; Algorithm timing; ALU design; C++ language; Digital signal processor design; DSP chips; Floating point arithmetic; IEEE standard; Lattice filter; Least squares estimation criterion; Motorola DSP96002; Real; Systolic filter; Variable precision IEEE floating point

thesaurus:
Adaptive filters; C language; Digital signal processing chips; Floating point arithmetic; Lattice filters; Least squares approximations; Systolic arrays

rawabstract:
We use a C++ class to transparently emulate variable-precision floating point arithmetic using standard arithmetic. This allows the determination of an algorithm's susceptibility to errors produced by finite-precision arithmetic and the determination of the minimum precision necessary for stability. The class, called Real, offers several advantages for many applications, e.g., ALU design, signal processing, systolic and lattice filter design, etc. Since it supports the IEEE floating point standard, it produces identical results on any compliant platform. An algorithm can be adapted for simulation with minimal effort and without interfering with normal operation. We also consider how the acceptance of the IEEE standard and the development of fast hardware for microcomputers have changed common assumptions about algorithm timing. Finally, we examine the potential use of the new floating point DSP chips for adaptive filtering. Historically, the computational requirements of adaptive filters confined implementations to specialized hardware or supercomputers. Today's DSP chips offer a relatively inexpensive alternative. We have implemented several adaptive filtering algorithms that are based on Least Squares estimation criterion on Motorola's DSP96002. Our experience indicates that the DSP96K is a viable medium for such algorithms and one can expect a ten-fold speed improvement over a i486 running at 50 MHz.

rawtitle:
Simulation of variable precision {IEEE} floating point using {C}++ and its application in digital signal processor design

entry:
@InProceedings{Samani:1993:SVP,
  author =       "D. M. Samani and J. Ellinger and E. J. Powers and E.
                 E. Swartzlander",
  title =        "Simulation of variable precision {IEEE} floating point
                 using {C}++ and its application in digital signal
                 processor design",
  crossref =     "IEEE:1993:PMS",
  pages =        "1509--1514 vol.2",
  year =         "1993",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We use a C++ class to transparently emulate
                 variable-precision floating point arithmetic using
                 standard arithmetic. This allows the determination of
                 an algorithm's susceptibility to errors produced by
                 finite-precision arithmetic and the determination of
                 the minimum precision necessary for stability. The
                 class, called Real, offers several advantages for many
                 applications, e.g., ALU design, signal processing,
                 systolic and lattice filter design, etc. Since it
                 supports the IEEE floating point standard, it produces
                 identical results on any compliant platform. An
                 algorithm can be adapted for simulation with minimal
                 effort and without interfering with normal operation.
                 We also consider how the acceptance of the IEEE
                 standard and the development of fast hardware for
                 microcomputers have changed common assumptions about
                 algorithm timing. Finally, we examine the potential use
                 of the new floating point DSP chips for adaptive
                 filtering. Historically, the computational requirements
                 of adaptive filters confined implementations to
                 specialized hardware or supercomputers. Today's DSP
                 chips offer a relatively inexpensive alternative. We
                 have implemented several adaptive filtering algorithms
                 that are based on Least Squares estimation criterion on
                 Motorola's DSP96002. Our experience indicates that the
                 DSP96K is a viable medium for such algorithms and one
                 can expect a ten-fold speed improvement over a i486
                 running at 50 MHz.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Texas
                 University, Austin, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); B1270F
                 (Digital filters); B6140 (Signal processing and
                 detection); C5135 (Digital signal processing chips);
                 C5220P (Parallel architecture); C5230 (Digital
                 arithmetic methods); C5240 (Digital filters); C5260
                 (Digital signal processing); C6140D (High level
                 languages)",
  keywords =     "Adaptive filtering; Algorithm timing; ALU design; C++
                 language; Digital signal processor design; DSP chips;
                 Floating point arithmetic; IEEE standard; Lattice
                 filter; Least squares estimation criterion; Motorola
                 DSP96002; Real; Systolic filter; Variable precision
                 IEEE floating point",
  thesaurus =    "Adaptive filters; C language; Digital signal
                 processing chips; Floating point arithmetic; Lattice
                 filters; Least squares approximations; Systolic
                 arrays",
}


bibtype: inproceedings
filename: fparith.bib
label: Sarma:1993:MAR
author: D. D. Sarma and D. W. Matula
title: Measuring the Accuracy of ROM Reciprocal Tables
crossref: Swartzlander:1993:SCA
pages: 95--102
year: 1993
bibdate: Wed Nov 14 18:47:17 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.14 18:47:17 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Sarma.pdf
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: D. D. Sarma and D. W. Matula
rawtitle: Measuring the Accuracy of {ROM} Reciprocal Tables
entry:
@InProceedings{Sarma:1993:MAR,
  author =       "D. D. Sarma and D. W. Matula",
  title =        "Measuring the Accuracy of {ROM} Reciprocal Tables",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "95--102",
  year =         "1993",
  bibdate =      "Wed Nov 14 18:47:17 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Sarma.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: article
filename: fparith.bib
label: Scannell:1993:DMM
author: Robert K. Scannell and John K. Hagge
title: Development of a Multichip Module DSP
journal: j-COMPUTER
volume: 26
number: 4
pages: 13--21
month: apr
monthnumber: 4
year: 1993
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Tue May 14 16:20:44 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.05.14 16:20:44 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Rockwell Int., Anaheim, CA, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
thesaurus: Digital signal processing chips; Multichip modules
rawauthor: Robert K. Scannell and John K. Hagge
rawtitle: Development of a Multichip Module {DSP}
abstract:
A highly modular processor architecture based on off-the-shelf components supports an MCM design implementation that delivers 400 million floating-point operations per second in a 75-gram package.

keywords:
Cost; Highly modular processor architecture; Interconnect-substrate design; MCM package assembly; Multichip module DSP; Signal processor packaging design; Size; Weight

rawabstract:
A highly modular processor architecture based on off-the-shelf components supports an MCM design implementation that delivers 400 million floating-point operations per second in a 75-gram package.

entry:
@Article{Scannell:1993:DMM,
  author =       "Robert K. Scannell and John K. Hagge",
  title =        "Development of a Multichip Module {DSP}",
  journal =      j-COMPUTER,
  volume =       "26",
  number =       "4",
  pages =        "13--21",
  month =        apr,
  year =         "1993",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Tue May 14 16:20:44 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A highly modular processor architecture based on
                 off-the-shelf components supports an MCM design
                 implementation that delivers 400 million floating-point
                 operations per second in a 75-gram package.",
  acknowledgement = ack-nhfb,
  affiliation =  "Rockwell Int., Anaheim, CA, USA",
  classification = "B0170J (Product packaging); B1265F (Microprocessors
                 and microcomputers); B2220J (Hybrid integrated
                 circuits); B2570 (Semiconductor integrated circuits);
                 C5135 (Digital signal processing chips)",
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Cost; Highly modular processor architecture;
                 Interconnect-substrate design; MCM package assembly;
                 Multichip module DSP; Signal processor packaging
                 design; Size; Weight",
  thesaurus =    "Digital signal processing chips; Multichip modules",
}


bibtype: article
filename: fparith.bib
label: Schorn:1993:AAR
author: Peter Schorn
title: An Axiomatic Approach to Robust Geometric Programs
journal: j-J-SYMBOLIC-COMP
volume: 16
number: 2
pages: 155--166 (or 155--165??)
month: aug
monthnumber: 8
year: 1993
CODEN: JSYCEH
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
MRclass: 68U07
MRnumber: 94k:68196
bibdate: Sat May 10 15:54:09 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.05.10 15:54:09 MDT
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
classcodes: C4260 (Computational geometry); C1180 (Optimisation techniques)
corpsource: Inst. fur Theor. Inf., Eidgenossische Tech. Hochschule, Zurich, Switzerland
journalURL: http://www.sciencedirect.com/science/journal/07477171
treatment: T Theoretical or Mathematical
rawauthor: Peter Schorn
rawtitle: An Axiomatic Approach to Robust Geometric Programs
keywords:
axiomatic approach; computational geometry; digital arithmetic; floating point arithmetic; geometric; imprecise primitives; non-trivial; plane sweep algorithm; primitives; programming; robust geometric programs

entry:
@Article{Schorn:1993:AAR,
  author =       "Peter Schorn",
  title =        "An Axiomatic Approach to Robust Geometric Programs",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "16",
  number =       "2",
  pages =        "155--166 (or 155--165??)",
  month =        aug,
  year =         "1993",
  CODEN =        "JSYCEH",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  MRclass =      "68U07",
  MRnumber =     "94k:68196",
  bibdate =      "Sat May 10 15:54:09 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classcodes =   "C4260 (Computational geometry); C1180 (Optimisation
                 techniques)",
  corpsource =   "Inst. fur Theor. Inf., Eidgenossische Tech.
                 Hochschule, Zurich, Switzerland",
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
  keywords =     "axiomatic approach; computational geometry; digital
                 arithmetic; floating point arithmetic; geometric;
                 imprecise primitives; non-trivial; plane sweep
                 algorithm; primitives; programming; robust geometric
                 programs",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1993:ERC
author: M. Schulte and E. Swartzlander
title: Exact rounding of certain elementary functions
crossref: Swartzlander:1993:SCA
pages: 138--145
year: 1993
bibdate: Thu Jun 20 10:16:17 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.06.20 10:16:17 ???
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Texas University, Austin, TX, USA
thesaurus: Floating point arithmetic; Function evaluation
rawauthor: M. Schulte and E. Swartzlander
rawtitle: Exact rounding of certain elementary functions
URL:
http://mesa.ece.wisc.edu/publications/cp_1993-01.pdf; http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Schulte.pdf

abstract:
An algorithm is described which produces exactly rounded results for the functions of reciprocal, square root, 2/sup x/, and log 2/sup x/. Hardware designs based on this algorithm are presented for floating point numbers with 16- and 24-b significands. These designs use a polynomial approximation in which coefficients are originally selected based on the Chebyshev series approximation and are then adjusted to ensure exactly rounded results for all inputs. To reduce the number of terms in the approximation, the input interval is divided into subintervals of equal size and different coefficients are used for each subinterval. For floating point numbers with 16-b significands, the exactly rounded value of the function can be computed in 51 ns on a 20-mm/sup 2/ chip. For floating point numbers with 24-b significands, the functions can be computed in 80 ns on a 98-mm/sup 2/ chip.

keywords:
ARITH-11; Elementary functions; Exact rounding; Floating point numbers; Polynomial approximation; Reciprocal; Rounded results; Square root

rawabstract:
An algorithm is described which produces exactly rounded results for the functions of reciprocal, square root, 2/sup x/, and log 2/sup x/. Hardware designs based on this algorithm are presented for floating point numbers with 16- and 24-b significands. These designs use a polynomial approximation in which coefficients are originally selected based on the Chebyshev series approximation and are then adjusted to ensure exactly rounded results for all inputs. To reduce the number of terms in the approximation, the input interval is divided into subintervals of equal size and different coefficients are used for each subinterval. For floating point numbers with 16-b significands, the exactly rounded value of the function can be computed in 51 ns on a 20-mm/sup 2/ chip. For floating point numbers with 24-b significands, the functions can be computed in 80 ns on a 98-mm/sup 2/ chip.

entry:
@InProceedings{Schulte:1993:ERC,
  author =       "M. Schulte and E. Swartzlander",
  title =        "Exact rounding of certain elementary functions",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "138--145",
  year =         "1993",
  bibdate =      "Thu Jun 20 10:16:17 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1993-01.pdf;
                 http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Schulte.pdf",
  abstract =     "An algorithm is described which produces exactly
                 rounded results for the functions of reciprocal, square
                 root, 2/sup x/, and log 2/sup x/. Hardware designs
                 based on this algorithm are presented for floating
                 point numbers with 16- and 24-b significands. These
                 designs use a polynomial approximation in which
                 coefficients are originally selected based on the
                 Chebyshev series approximation and are then adjusted to
                 ensure exactly rounded results for all inputs. To
                 reduce the number of terms in the approximation, the
                 input interval is divided into subintervals of equal
                 size and different coefficients are used for each
                 subinterval. For floating point numbers with 16-b
                 significands, the exactly rounded value of the function
                 can be computed in 51 ns on a 20-mm/sup 2/ chip. For
                 floating point numbers with 24-b significands, the
                 functions can be computed in 80 ns on a 98-mm/sup 2/
                 chip.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Texas
                 University, Austin, TX, USA",
  classification = "C4120 (Functional analysis); C5230 (Digital
                 arithmetic methods)",
  confdate =     "29 June--2 July 1993",
  conflocation = "Windsor, Ont., Canada",
  confsponsor =  "IEEE Comput. Soc.; IEEE Tech. Committee on VLSI;
                 Natural Sci. and Eng. Res.; Council of Canada",
  keywords =     "ARITH-11; Elementary functions; Exact rounding;
                 Floating point numbers; Polynomial approximation;
                 Reciprocal; Rounded results; Square root",
  thesaurus =    "Floating point arithmetic; Function evaluation",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1993:PHD
author: M. J. Schulte and E. E. Swartzlander, Jr.
title: Parallel Hardware Designs for Correctly Rounded Elementary Functions
crossref: Corliss:1993:AIC
pages: 65--87 (or 65--88??)
year: 1993
bibdate: Tue Oct 22 13:37:58 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.22 13:37:58 ???
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and E. E. {Swartzlander, Jr.}
rawtitle: Parallel Hardware Designs for Correctly Rounded Elementary Functions
entry:
@InProceedings{Schulte:1993:PHD,
  author =       "M. J. Schulte and E. E. {Swartzlander, Jr.}",
  title =        "Parallel Hardware Designs for Correctly Rounded
                 Elementary Functions",
  crossref =     "Corliss:1993:AIC",
  pages =        "65--87 (or 65--88??)",
  year =         "1993",
  bibdate =      "Tue Oct 22 13:37:58 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1993:TMC
author: M. J. Schulte and E. E. Swartzlander, Jr.
title: Truncated Multiplication with Correction Constant
crossref: Eggermont:1993:VSP
pages: 388--396
year: 1993
bibdate: Sun Mar 04 10:38:15 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 10:38:15 ???
URL: http://mesa.ece.wisc.edu/publications/cp_1993-02.pdf
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and E. E. {Swartzlander, Jr.}
rawtitle: Truncated Multiplication with Correction Constant
entry:
@InProceedings{Schulte:1993:TMC,
  author =       "M. J. Schulte and E. E. {Swartzlander, Jr.}",
  title =        "Truncated Multiplication with Correction Constant",
  crossref =     "Eggermont:1993:VSP",
  pages =        "388--396",
  year =         "1993",
  bibdate =      "Sun Mar 04 10:38:15 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_1993-02.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Schwarz:1993:HRAa
author: E. Schwarz
title: High-radix algorithms for high-order arithmetic operations
type: Technical Report
number: CSL-TR-93-559
institution: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: 388--396
month: jan
monthnumber: 1
year: 1993
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
acknowledgement: ack-sfo
rawauthor: E. Schwarz
rawtitle: High-radix algorithms for high-order arithmetic operations
entry:
@TechReport{Schwarz:1993:HRAa,
  author =       "E. Schwarz",
  title =        "High-radix algorithms for high-order arithmetic
                 operations",
  type =         "Technical Report",
  number =       "CSL-TR-93-559",
  institution =  "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  month =        jan,
  year =         "1993",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: phdthesis
filename: fparith.bib
label: Schwarz:1993:HRAb
author: Eric Mark Schwarz
title: High-radix algorithms for high-order arithmetic operations
type: Thesis (Ph.D.)
school: Department of Electrical Engineering, Stanford University
address: Stanford, CA, USA
pages: 224
month: apr
monthnumber: 4
year: 1993
bibdate: Mon Jan 07 22:38:06 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.01.07 22:38:06 ???
remark: AAT 9317816. ProQuest document ID 746798521.
acknowledgement: ack-nhfb
rawauthor: Eric Mark Schwarz
rawtitle: High-radix algorithms for high-order arithmetic operations
abstract:
Many common algorithms for high-order arithmetic operations require an initial approximation. The Newton--Raphson algorithm starts with an approximation and then quadratically converges on the solution. The initial approximation determines the number of iterations of the algorithm and is typically implemented as a look-up table in the form of a ROM or PLA. A novel method is suggested which describes high-order arithmetic operations with a partial product array. This method applies to the operations of division, reciprocal, square root, natural logarithm, exponential, and trigonometric functions. The partial product array of Boolean elements which describes the operation can be summed on an existing floating-point multiplier. The hardware needed is only the logic gates to create the Boolean elements in the array and a multiplexor, and the latency is that of the multiplier. Thus, by reusing a floating-point multiplier, a high-precision approximation to a high-order arithmetic operation can be implemented with a low marginal cost.par This dissertation describes the implementation and shows a method for deriving partial product arrays to approximate arithmetic operations. Then the proposed method is applied and evaluated for several operations. The proposed method yields a minimum approximation of twelve bits correct for the reciprocal operation and sixteen bits for the square root operation. The proposed method is shown to be as small as 0.05% the size (in gates) of an equivalent precision look-up table and has up to four times the accuracy (in bits) as an equivalent latency polynomial approximation. Also, three new iterative algorithms to increase the precision of the approximations and a theoretical analysis of the partial product array representation are detailed. Thus, high-radix algorithms of many arithmetic operations are possible at low cost.

keywords:
division; elementary functions; exponential; logarithm; PPA (partial product array); reciprocal square root; square root

rawabstract:
Many common algorithms for high-order arithmetic operations require an initial approximation. The Newton--Raphson algorithm starts with an approximation and then quadratically converges on the solution. The initial approximation determines the number of iterations of the algorithm and is typically implemented as a look-up table in the form of a ROM or PLA. A novel method is suggested which describes high-order arithmetic operations with a partial product array. This method applies to the operations of division, reciprocal, square root, natural logarithm, exponential, and trigonometric functions. The partial product array of Boolean elements which describes the operation can be summed on an existing floating-point multiplier. The hardware needed is only the logic gates to create the Boolean elements in the array and a multiplexor, and the latency is that of the multiplier. Thus, by reusing a floating-point multiplier, a high-precision approximation to a high-order arithmetic operation can be implemented with a low marginal cost.\par This dissertation describes the implementation and shows a method for deriving partial product arrays to approximate arithmetic operations. Then the proposed method is applied and evaluated for several operations. The proposed method yields a minimum approximation of twelve bits correct for the reciprocal operation and sixteen bits for the square root operation. The proposed method is shown to be as small as 0.05\% the size (in gates) of an equivalent precision look-up table and has up to four times the accuracy (in bits) as an equivalent latency polynomial approximation. Also, three new iterative algorithms to increase the precision of the approximations and a theoretical analysis of the partial product array representation are detailed. Thus, high-radix algorithms of many arithmetic operations are possible at low cost.

entry:
@PhdThesis{Schwarz:1993:HRAb,
  author =       "Eric Mark Schwarz",
  title =        "High-radix algorithms for high-order arithmetic
                 operations",
  type =         "Thesis ({Ph.D.})",
  school =       "Department of Electrical Engineering, Stanford
                 University",
  address =      "Stanford, CA, USA",
  pages =        "224",
  month =        apr,
  year =         "1993",
  bibdate =      "Mon Jan 07 22:38:06 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Many common algorithms for high-order arithmetic
                 operations require an initial approximation. The
                 Newton--Raphson algorithm starts with an approximation
                 and then quadratically converges on the solution. The
                 initial approximation determines the number of
                 iterations of the algorithm and is typically
                 implemented as a look-up table in the form of a ROM or
                 PLA. A novel method is suggested which describes
                 high-order arithmetic operations with a partial product
                 array. This method applies to the operations of
                 division, reciprocal, square root, natural logarithm,
                 exponential, and trigonometric functions. The partial
                 product array of Boolean elements which describes the
                 operation can be summed on an existing floating-point
                 multiplier. The hardware needed is only the logic gates
                 to create the Boolean elements in the array and a
                 multiplexor, and the latency is that of the multiplier.
                 Thus, by reusing a floating-point multiplier, a
                 high-precision approximation to a high-order arithmetic
                 operation can be implemented with a low marginal
                 cost.\par

                 This dissertation describes the implementation and
                 shows a method for deriving partial product arrays to
                 approximate arithmetic operations. Then the proposed
                 method is applied and evaluated for several operations.
                 The proposed method yields a minimum approximation of
                 twelve bits correct for the reciprocal operation and
                 sixteen bits for the square root operation. The
                 proposed method is shown to be as small as 0.05\% the
                 size (in gates) of an equivalent precision look-up
                 table and has up to four times the accuracy (in bits)
                 as an equivalent latency polynomial approximation.
                 Also, three new iterative algorithms to increase the
                 precision of the approximations and a theoretical
                 analysis of the partial product array representation
                 are detailed. Thus, high-radix algorithms of many
                 arithmetic operations are possible at low cost.",
  acknowledgement = ack-nhfb,
  keywords =     "division; elementary functions; exponential;
                 logarithm; PPA (partial product array); reciprocal
                 square root; square root",
  remark =       "AAT 9317816. ProQuest document ID 746798521.",
}


bibtype: inproceedings
filename: fparith.bib
label: Schwarz:1993:HSA
author: Eric M. Schwarz and Michael J. Flynn
title: Hardware starting approximation for the square root operation
crossref: Swartzlander:1993:SCA
pages: 103--111
year: 1993
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Schwarz.pdf
keywords: ARITH-11
acknowledgement: ack-sfo
rawauthor: Eric M. Schwarz and Michael J. Flynn
rawtitle: Hardware starting approximation for the square root operation
entry:
@InProceedings{Schwarz:1993:HSA,
  author =       "Eric M. Schwarz and Michael J. Flynn",
  title =        "Hardware starting approximation for the square root
                 operation",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "103--111",
  year =         "1993",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Schwarz.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "ARITH-11",
  summary =      "A method for obtaining high-precision approximations
                 of high-order arithmetic operations is presented. These
                 approximations provide an accurate starting
                 approximation for high-precision iterative algorithms,
                 which translates into few iterations and \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Schwarz:1993:PHR
author: E. M. Schwarz and M. J. Flynn
title: Parallel high-radix nonrestoring division
journal: j-IEEE-TRANS-COMPUT
volume: 42
number: 10
pages: 1234--1246
month: oct
monthnumber: 10
year: 1993
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.257709
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:58:51 MDT 2011
bibtimestamp: 2011.07.07 07:58:51 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=257709
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. M. Schwarz and M. J. Flynn
rawtitle: Parallel high-radix nonrestoring division
entry:
@Article{Schwarz:1993:PHR,
  author =       "E. M. Schwarz and M. J. Flynn",
  title =        "Parallel high-radix nonrestoring division",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "42",
  number =       "10",
  pages =        "1234--1246",
  month =        oct,
  year =         "1993",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.257709",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:58:51 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=257709",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: techreport
filename: fparith.bib
label: Schwarz:1993:UFM
author: Eric Mark Schwarz and M. J. (Michael J.) Flynn
title: Using a floating-point multiplier's internals for high-radix division and square root
type: Technical report
number: CSL-TR-93-554
institution: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: iv + 45
year: 1993
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer arithmetic.
acknowledgement: ack-nhfb
rawauthor: Eric Mark Schwarz and M. J. (Michael J.) Flynn
rawtitle: Using a floating-point multiplier's internals for high-radix division and square root
remark:
``January 1993.'' Abstract: ``A method for obtaining high-precision approximations of high-order arithmetic operations at low-cost is presented in this study. Specifically, high-precision approximations of the reciprocal (12 bits worst case) and square root (16 bits) operations are obtained using the internal hardware of a floating-point multiplier without the use of look-up tables. The additional combinatorial logic necessary is very small due to the reuse of existing hardware. These low-cost high-precision approximations are used by iterative algorithms to perform the operations of division and square root. The method presented also applies to several other high-order arithmetic operations. Thus, high-radix algorithms for high-order arithmetic operations such as division and square root are possible at low-cost.''

entry:
@TechReport{Schwarz:1993:UFM,
  author =       "Eric Mark Schwarz and M. J. (Michael J.) Flynn",
  title =        "Using a floating-point multiplier's internals for
                 high-radix division and square root",
  type =         "Technical report",
  number =       "CSL-TR-93-554",
  institution =  "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  pages =        "iv + 45",
  year =         "1993",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer arithmetic.",
  remark =       "``January 1993.'' Abstract: ``A method for obtaining
                 high-precision approximations of high-order arithmetic
                 operations at low-cost is presented in this study.
                 Specifically, high-precision approximations of the
                 reciprocal (12 bits worst case) and square root (16
                 bits) operations are obtained using the internal
                 hardware of a floating-point multiplier without the use
                 of look-up tables. The additional combinatorial logic
                 necessary is very small due to the reuse of existing
                 hardware. These low-cost high-precision approximations
                 are used by iterative algorithms to perform the
                 operations of division and square root. The method
                 presented also applies to several other high-order
                 arithmetic operations. Thus, high-radix algorithms for
                 high-order arithmetic operations such as division and
                 square root are possible at low-cost.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Shanbhag:1993:REAa
author: N. R. Shanbhag and K. K. Parhi
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS '93, 3--6 May 1993
title: Roundoff error analysis of the pipelined ADPCM coder
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 886--889
year: 1993
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: N. R. Shanbhag and K. K. Parhi
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS '93}, 3--6 May 1993
rawtitle: Roundoff error analysis of the pipelined {ADPCM} coder
entry:
@InProceedings{Shanbhag:1993:REAa,
  author =       "N. R. Shanbhag and K. K. Parhi",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS '93}, 3--6 May 1993",
  title =        "Roundoff error analysis of the pipelined {ADPCM}
                 coder",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "886--889",
  year =         "1993",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Not \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Shanbhag:1993:REAb
author: N. R. Shanbhag and K. K. Parhi
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS '93, 3--6 May 1993
title: Roundoff error analysis of the pipelined ADPCM coder
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 886--889
year: 1993
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: N. R. Shanbhag and K. K. Parhi
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS '93}, 3--6 May 1993
rawtitle: Roundoff error analysis of the pipelined {ADPCM} coder
entry:
@InProceedings{Shanbhag:1993:REAb,
  author =       "N. R. Shanbhag and K. K. Parhi",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS '93}, 3--6 May 1993",
  title =        "Roundoff error analysis of the pipelined {ADPCM}
                 coder",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "886--889",
  year =         "1993",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Roundoff error analysis of a pipelined adaptive
                 differential pulse code modulation (ADPCM) coder is
                 presented. The pipelined coder has been developed by
                 employing the relaxed look-ahead technique. It is shown
                 that the precision of the quantized \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Shand:1993:FIR
author: M. Shand and J. Vuillemin
title: Fast Implementations of RSA Cryptography
crossref: Swartzlander:1993:SCA
pages: 252--259
year: 1993
bibdate: Wed Nov 14 18:47:51 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.14 18:47:51 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Shand.pdf
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: M. Shand and J. Vuillemin
rawtitle: Fast Implementations of {RSA} Cryptography
entry:
@InProceedings{Shand:1993:FIR,
  author =       "M. Shand and J. Vuillemin",
  title =        "Fast Implementations of {RSA} Cryptography",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "252--259",
  year =         "1993",
  bibdate =      "Wed Nov 14 18:47:51 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Shand.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: book
filename: fparith.bib
label: Shannon:1993:CES
author: Claude Elwood Shannon and N. J. A. (Neil James Alexander) Sloane and A. D. (Aaron D.) Wyner
title: Claude Elwood Shannon: collected papers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: xliv + 924
year: 1993
ISBN: 0-7803-0434-9 OR 0780304349
ISBN13: 978-0-7803-0434-5 OR 9780780304345
LCCN: TK5101 .S448 1993
bibdate: Sat Nov 20 09:04:51 MST 2010
bibsource: catalog.princeton.edu:7090/voyager; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.11.20 09:04:51 MST
subject: telecommunication; information theory; computers
acknowledgement: ack-nhfb
authordates: Claude Elwood Shannon (1916--2001)
rawauthor: Claude Elwood Shannon and N. J. A. (Neil James Alexander) Sloane and A. D. (Aaron D.) Wyner
rawtitle: {Claude Elwood Shannon}: collected papers
entry:
@Book{Shannon:1993:CES,
  author =       "Claude Elwood Shannon and N. J. A. (Neil James
                 Alexander) Sloane and A. D. (Aaron D.) Wyner",
  title =        "{Claude Elwood Shannon}: collected papers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xliv + 924",
  year =         "1993",
  ISBN =         "0-7803-0434-9",
  ISBN-13 =      "978-0-7803-0434-5",
  LCCN =         "TK5101 .S448 1993",
  bibdate =      "Sat Nov 20 09:04:51 MST 2010",
  bibsource =    "catalog.princeton.edu:7090/voyager;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  author-dates = "Claude Elwood Shannon (1916--2001)",
  subject =      "telecommunication; information theory; computers",
}


bibtype: article
filename: fparith.bib
label: Sharp:1993:PRN
author: W. E. Sharp and Carter Bays
title: A portable random number generator for single-precision floating-point arithmetic
journal: j-COMP-GEOSCI
volume: 19
number: 4
pages: 593--??
month: apr
monthnumber: 4
year: 1993
CODEN: CGEODT, CGOSDN
ISSN: 0098-3004 (print), 1873-7803 (electronic) OR 00983004 (print), 18737803 (electronic)
ISSNL: 0098-3004 OR 00983004
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Computers and Geosciences
acknowledgement: ack-nhfb
rawauthor: W. E. Sharp and Carter Bays
rawtitle: A portable random number generator for single-precision floating-point arithmetic
entry:
@Article{Sharp:1993:PRN,
  author =       "W. E. Sharp and Carter Bays",
  title =        "A portable random number generator for
                 single-precision floating-point arithmetic",
  journal =      j-COMP-GEOSCI,
  volume =       "19",
  number =       "4",
  pages =        "593--??",
  month =        apr,
  year =         "1993",
  CODEN =        "CGEODT, CGOSDN",
  ISSN =         "0098-3004 (print), 1873-7803 (electronic)",
  ISSN-L =       "0098-3004",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Geosciences",
}


bibtype: inproceedings
filename: fparith.bib
label: Shirayanagi:1993:MCM
author: Kiyoshi Shirayanagi
title: An algorithm to compute floating point Grobner bases
crossref: Lee:1993:MCM
pages: 95--106
year: 1993
MRclass: 68Q40 (13P10 68Q25)
MRnumber: 94j:68129
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
acknowledgement: ack-nhfb
rawauthor: Kiyoshi Shirayanagi
rawtitle: An algorithm to compute floating point {Gr{\"o}bner} bases
entry:
@InProceedings{Shirayanagi:1993:MCM,
  author =       "Kiyoshi Shirayanagi",
  title =        "An algorithm to compute floating point {Gr{\"o}bner}
                 bases",
  crossref =     "Lee:1993:MCM",
  pages =        "95--106",
  year =         "1993",
  MRclass =      "68Q40 (13P10 68Q25)",
  MRnumber =     "94j:68129",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Shute:1993:AAB
author: Malcolm J. Shute
title: Abotec: an automatic back-of-the-envelope calculator
journal: j-SIGPLAN
volume: 28
number: 8
pages: 90--98
month: aug
monthnumber: 8
year: 1993
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:40 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:16:40 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Manchester University, UK
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
thesaurus: CAD; High level languages; Mathematics computing
rawauthor: Malcolm J. Shute
rawtitle: {Abotec}: an automatic back-of-the-envelope calculator
abstract:
The trial-and-error method, iteratively applied, is invariably involved in any kind of design work, with much back-of-the-envelope calculation to guide the process. In this, the `what-if' game is a very useful tactic in the search for unexpected solutions in complex design spaces, made all the more effective by the availability of automated interpreters. These are needed to perform the tedious re-calculation of the model each time a change is made to a small part. In the financial world, the interpreter generally takes the form of the spread-sheet, of which Quattro is a fine example; in mathematics it takes the form of packages such as Mathematica. Neither of these is ideally tailored for engineering design, and so Abotec was developed when the author had need of such a tool. There are four main characteristics which fit Abotec for its purpose: it works with floating-point numbers throughout; it uses a richer than normal set of arithmetic operators and functions; it uses mnemonic labelling throughout; and, most importantly it treats all variables as having an upper and lower bound.

keywords:
Abotec; Arithmetic operators; Automated interpreters; Automatic back-of-the-envelope calculator; Back-of-the-envelope calculation; Complex design spaces; Design work; Engineering design; Floating-point numbers; Mnemonic labelling; Re-calculation; Trial-and-error method; Unexpected solutions; What-if

rawabstract:
The trial-and-error method, iteratively applied, is invariably involved in any kind of design work, with much back-of-the-envelope calculation to guide the process. In this, the `what-if' game is a very useful tactic in the search for unexpected solutions in complex design spaces, made all the more effective by the availability of automated interpreters. These are needed to perform the tedious re-calculation of the model each time a change is made to a small part. In the financial world, the interpreter generally takes the form of the spread-sheet, of which Quattro is a fine example; in mathematics it takes the form of packages such as Mathematica. Neither of these is ideally tailored for engineering design, and so Abotec was developed when the author had need of such a tool. There are four main characteristics which fit Abotec for its purpose: it works with floating-point numbers throughout; it uses a richer than normal set of arithmetic operators and functions; it uses mnemonic labelling throughout; and, most importantly it treats all variables as having an upper and lower bound.

entry:
@Article{Shute:1993:AAB,
  author =       "Malcolm J. Shute",
  title =        "{Abotec}: an automatic back-of-the-envelope
                 calculator",
  journal =      j-SIGPLAN,
  volume =       "28",
  number =       "8",
  pages =        "90--98",
  month =        aug,
  year =         "1993",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:40 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The trial-and-error method, iteratively applied, is
                 invariably involved in any kind of design work, with
                 much back-of-the-envelope calculation to guide the
                 process. In this, the `what-if' game is a very useful
                 tactic in the search for unexpected solutions in
                 complex design spaces, made all the more effective by
                 the availability of automated interpreters. These are
                 needed to perform the tedious re-calculation of the
                 model each time a change is made to a small part. In
                 the financial world, the interpreter generally takes
                 the form of the spread-sheet, of which Quattro is a
                 fine example; in mathematics it takes the form of
                 packages such as Mathematica. Neither of these is
                 ideally tailored for engineering design, and so Abotec
                 was developed when the author had need of such a tool.
                 There are four main characteristics which fit Abotec
                 for its purpose: it works with floating-point numbers
                 throughout; it uses a richer than normal set of
                 arithmetic operators and functions; it uses mnemonic
                 labelling throughout; and, most importantly it treats
                 all variables as having an upper and lower bound.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Manchester University,
                 UK",
  classification = "C6140D (High level languages); C7310 (Mathematics);
                 C7400 (Engineering)",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "Abotec; Arithmetic operators; Automated interpreters;
                 Automatic back-of-the-envelope calculator;
                 Back-of-the-envelope calculation; Complex design
                 spaces; Design work; Engineering design; Floating-point
                 numbers; Mnemonic labelling; Re-calculation;
                 Trial-and-error method; Unexpected solutions; What-if",
  thesaurus =    "CAD; High level languages; Mathematics computing",
}


bibtype: article
filename: fparith.bib
label: Smith:1993:PFC
author: Ross Smith and Gerald Sobelman and George Luk and Koichi Suda and Jeff Bracken
title: A Programmable Floating-Point Cell for Systolic Signal Processing
journal: j-J-VLSI-SIGNAL-PROC
volume: 5
number: 1
pages: 75--84
month: jan
monthnumber: 1
year: 1993
CODEN: JVSPED
DOI: https://doi.org/10.1007/BF01880273
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Ross Smith and Gerald Sobelman and George Luk and Koichi Suda and Jeff Bracken
rawtitle: A Programmable Floating-Point Cell for Systolic Signal Processing
abstract:
The FPC controller and the AMD Am29325 32-bit floating-point mathematics processor form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique architectural features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-bit instruction word that allows concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams.

rawabstract:
The FPC controller and the AMD Am29325 32-bit floating-point mathematics processor form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique architectural features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-bit instruction word that allows concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams.

entry:
@Article{Smith:1993:PFC,
  author =       "Ross Smith and Gerald Sobelman and George Luk and
                 Koichi Suda and Jeff Bracken",
  title =        "A Programmable Floating-Point Cell for Systolic Signal
                 Processing",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "5",
  number =       "1",
  pages =        "75--84",
  month =        jan,
  year =         "1993",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/BF01880273",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The FPC controller and the AMD Am29325 32-bit
                 floating-point mathematics processor form a two-chip
                 cell designed for one- or two-dimensional systolic
                 arrays which can be used to implement a wide variety of
                 signal processing applications. The FPC controls the
                 Am29325, routes data to and from it, and routes data
                 and control to other cells in the array. Unique
                 architectural features include two interchangeable data
                 memories, an input port which can be used as either a
                 local or global port, and a 32-bit instruction word
                 that allows concurrent use of all cell resources.
                 Additional features include a program memory, two data
                 streams, and three control streams.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: article
filename: fparith.bib
label: Smith:1993:VFP
author: William Smith
title: Varying Floating-Point Precision
journal: j-CUJ
volume: 11
number: 7
pages: 87--??
month: jul
monthnumber: 7
year: 1993
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: William Smith
rawtitle: Varying Floating-Point Precision
entry:
@Article{Smith:1993:VFP,
  author =       "William Smith",
  title =        "Varying Floating-Point Precision",
  journal =      j-CUJ,
  volume =       "11",
  number =       "7",
  pages =        "87--??",
  month =        jul,
  year =         "1993",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: article
filename: fparith.bib
label: Smith:1993:WDF
author: William Smith
title: Windows, DLLs, and Floating Point Types
journal: j-CUJ
volume: 11
number: 9
pages: 21--??
month: sep
monthnumber: 9
year: 1993
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: William Smith
rawtitle: Windows, {DLLs}, and Floating Point Types
entry:
@Article{Smith:1993:WDF,
  author =       "William Smith",
  title =        "Windows, {DLLs}, and Floating Point Types",
  journal =      j-CUJ,
  volume =       "11",
  number =       "9",
  pages =        "21--??",
  month =        sep,
  year =         "1993",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: inproceedings
filename: fparith.bib
label: Soulas:1993:AMC
author: T. Soulas and D. Villeger and V. G. Oklobdzija
title: An ASIC macro cell multiplier for complex numbers
crossref: IEEE:1993:PEC
pages: 589--593
year: 1993
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Ecole Superieure d'Ingenieurs en Electrotech. et Electron., Noisy le Grand, France
rawauthor: T. Soulas and D. Villeger and V. G. Oklobdzija
rawtitle: An {ASIC} macro cell multiplier for complex numbers
abstract:
An architecture for ASIC macro cell implementing a complex number multiplier with applications in a digital signal processing ASIC chip is described. The complex numbers are packed into one 32-bit word. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree. The regular Wallace tree and the tree of 4:2 adders for the complex multiplier implementation are compared. The authors took advantage of 4:2 adders in implementing the combined bit compression tree for each part. This design resulted in a more compact wiring structure and balanced delays resulting in faster multiplier circuit. The number of adders was also decreased.

keywords:
32 Bit; ASIC macro cell multiplier; Balanced delays; CMOS; Combined bit compression tree; Compact wiring structure; Complex numbers; Digital signal processing ASIC chip; Floating point number representation; Shared Booth encoding; Wallace tree

thesaurus:
Application specific integrated circuits; Cellular arrays; CMOS logic circuits; Digital signal processing chips; Floating point arithmetic; Integrated circuit design; Logic arrays; Logic CAD; Multiplying circuits

rawabstract:
An architecture for ASIC macro cell implementing a complex number multiplier with applications in a digital signal processing ASIC chip is described. The complex numbers are packed into one 32-bit word. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree. The regular Wallace tree and the tree of 4:2 adders for the complex multiplier implementation are compared. The authors took advantage of 4:2 adders in implementing the combined bit compression tree for each part. This design resulted in a more compact wiring structure and balanced delays resulting in faster multiplier circuit. The number of adders was also decreased.

entry:
@InProceedings{Soulas:1993:AMC,
  author =       "T. Soulas and D. Villeger and V. G. Oklobdzija",
  title =        "An {ASIC} macro cell multiplier for complex numbers",
  crossref =     "IEEE:1993:PEC",
  pages =        "589--593",
  year =         "1993",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An architecture for ASIC macro cell implementing a
                 complex number multiplier with applications in a
                 digital signal processing ASIC chip is described. The
                 complex numbers are packed into one 32-bit word. The
                 design is unique and combines shared Booth encoding for
                 the real and imaginary parts including only one
                 combined modified Wallace tree. The regular Wallace
                 tree and the tree of 4:2 adders for the complex
                 multiplier implementation are compared. The authors
                 took advantage of 4:2 adders in implementing the
                 combined bit compression tree for each part. This
                 design resulted in a more compact wiring structure and
                 balanced delays resulting in faster multiplier circuit.
                 The number of adders was also decreased.",
  acknowledgement = ack-nhfb,
  affiliation =  "Ecole Superieure d'Ingenieurs en Electrotech. et
                 Electron., Noisy le Grand, France",
  classification = "B1130B (Computer-aided circuit analysis and design);
                 B1265B (Logic circuits); B1265F (Microprocessors and
                 microcomputers); B2570D (CMOS integrated circuits);
                 C5120 (Logic and switching circuits); C5135 (Digital
                 signal processing chips); C5210B (Computer-aided logic
                 design); C5230 (Digital arithmetic methods); C7410D
                 (Electronic engineering computing)",
  confsponsor =  "IEEE; EDA Assoc.; AEIA, Spain; AFCET, France; AICA,
                 Italy; Bull SA, France; CEC ESPRIT Basic Research",
  keywords =     "32 Bit; ASIC macro cell multiplier; Balanced delays;
                 CMOS; Combined bit compression tree; Compact wiring
                 structure; Complex numbers; Digital signal processing
                 ASIC chip; Floating point number representation; Shared
                 Booth encoding; Wallace tree",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Application specific integrated circuits; Cellular
                 arrays; CMOS logic circuits; Digital signal processing
                 chips; Floating point arithmetic; Integrated circuit
                 design; Logic arrays; Logic CAD; Multiplying circuits",
}


bibtype: article
filename: fparith.bib
label: Subramaniam:1993:PPP
author: Ramesh Subramaniam and Kiran Kundargi and J. Dahms
title: Programming The Pentium Processor
journal: j-DDJ
volume: 18
number: 6
pages: 34, 36, 38, 40--42
month: jun
monthnumber: 6
year: 1993
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 03 09:15:41 1996
bibtimestamp: 1996.09.03 09:15:41 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
affiliation: Intel, Santa Clara, CA, USA
rawauthor: Ramesh Subramaniam and Kiran Kundargi and J. Dahms
rawtitle: Programming The {Pentium} Processor
abstract:
Intel's recent entry into the 32-bit microprocessor race ups the performance ante. Our authors discuss the Pentium's superscalar, pipelined architecture, focusing on floating-point code. John Dahms shares some of his experiences in writing a Pentium-aware compiler.

keywords:
32 Bit; 32-Bit microprocessor; Floating-point code; High performance architecture; Intel Pentium; Pentium-aware compiler; Programming; Superscalar pipelined architecture

thesaurus:
Computer architecture; Microprocessor chips; Microprogramming; Pipeline processing; Program compilers

rawabstract:
Intel's recent entry into the 32-bit microprocessor race ups the performance ante. Our authors discuss the Pentium's superscalar, pipelined architecture, focusing on floating-point code. John Dahms shares some of his experiences in writing a Pentium-aware compiler.

entry:
@Article{Subramaniam:1993:PPP,
  author =       "Ramesh Subramaniam and Kiran Kundargi and J. Dahms",
  title =        "Programming The {Pentium} Processor",
  journal =      j-DDJ,
  volume =       "18",
  number =       "6",
  pages =        "34, 36, 38, 40--42",
  month =        jun,
  year =         "1993",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 03 09:15:41 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "Intel's recent entry into the 32-bit microprocessor
                 race ups the performance ante. Our authors discuss the
                 Pentium's superscalar, pipelined architecture, focusing
                 on floating-point code. John Dahms shares some of his
                 experiences in writing a Pentium-aware compiler.",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel, Santa Clara, CA, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C6110 (Systems analysis and
                 programming); C6150C (Compilers, interpreters and other
                 processors)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "32 Bit; 32-Bit microprocessor; Floating-point code;
                 High performance architecture; Intel Pentium;
                 Pentium-aware compiler; Programming; Superscalar
                 pipelined architecture",
  thesaurus =    "Computer architecture; Microprocessor chips;
                 Microprogramming; Pipeline processing; Program
                 compilers",
}


bibtype: inproceedings
filename: fparith.bib
label: Swartzlander:1993:FSC
author: Earl Swartzlander and Mary Jane Irwin and Graham Jullien
title: Foreword: 11th Symposium on Computer Arithmetic, Windsor, Ontario, Canada, June 29--July 2, 1993
crossref: Swartzlander:1993:SCA
pages: v--v
year: 1993
bibdate: Sat Nov 17 09:46:07 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 09:46:07 ???
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: Earl Swartzlander and Mary Jane Irwin and Graham Jullien
rawtitle: Foreword: {11th Symposium on Computer Arithmetic, Windsor, Ontario, Canada, June 29--July 2, 1993}
URL:
http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_contents.pdf; http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_foreword.pdf; http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_preface.pdf

entry:
@InProceedings{Swartzlander:1993:FSC,
  author =       "Earl Swartzlander and Mary Jane Irwin and Graham
                 Jullien",
  title =        "Foreword: {11th Symposium on Computer Arithmetic,
                 Windsor, Ontario, Canada, June 29--July 2, 1993}",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "v--v",
  year =         "1993",
  bibdate =      "Sat Nov 17 09:46:07 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_contents.pdf;
                 http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_foreword.pdf;
                 http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_preface.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:1993:MMA
author: N. Takagi
title: Modular Multiplication Algorithm with Triangle Addition
crossref: Swartzlander:1993:SCA
pages: 272--276
year: 1993
bibdate: Wed Nov 14 18:48:15 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.14 18:48:15 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Takagi.pdf
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: N. Takagi
rawtitle: Modular Multiplication Algorithm with Triangle Addition
entry:
@InProceedings{Takagi:1993:MMA,
  author =       "N. Takagi",
  title =        "Modular Multiplication Algorithm with Triangle
                 Addition",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "272--276",
  year =         "1993",
  bibdate =      "Wed Nov 14 18:48:15 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Takagi.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: article
filename: fparith.bib
label: Thompson:1993:CCQ
author: William J. Thompson
title: Cutting Corners: Quick Square Roots and Trig Functions
journal: j-COMPUT-PHYS
volume: 7
number: 1
pages: 18--??
month: jan
monthnumber: 1
year: 1993
CODEN: CPHYE2
DOI: https://doi.org/10.1063/1.4823136
ISSN: 0894-1866 (print), 1558-4208 (electronic) OR 08941866 (print), 15584208 (electronic)
ISSNL: 0894-1866 OR 08941866
bibdate: Wed Apr 10 08:45:39 MDT 2019
bibtimestamp: 2019.04.10 08:45:39 MDT
URL: https://aip.scitation.org/doi/10.1063/1.4823136
fjournal: Computers in Physics
acknowledgement: ack-nhfb
ajournal: Comput. Phys
journalURL: https://aip.scitation.org/journal/cip
rawauthor: William J. Thompson
rawtitle: Cutting Corners: Quick Square Roots and Trig Functions
bibsource:
https://www.math.utah.edu/pub/tex/bib/computphys.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Thompson:1993:CCQ,
  author =       "William J. Thompson",
  title =        "Cutting Corners: Quick Square Roots and Trig
                 Functions",
  journal =      j-COMPUT-PHYS,
  volume =       "7",
  number =       "1",
  pages =        "18--??",
  month =        jan,
  year =         "1993",
  CODEN =        "CPHYE2",
  DOI =          "https://doi.org/10.1063/1.4823136",
  ISSN =         "0894-1866 (print), 1558-4208 (electronic)",
  ISSN-L =       "0894-1866",
  bibdate =      "Wed Apr 10 08:45:39 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computphys.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://aip.scitation.org/doi/10.1063/1.4823136",
  acknowledgement = ack-nhfb,
  ajournal =     "Comput. Phys",
  fjournal =     "Computers in Physics",
  journal-URL =  "https://aip.scitation.org/journal/cip",
}


bibtype: manual
filename: fparith.bib
label: TI:1993:ITC
organization: Texas Instruments Incorporated
address: S.l
pages: iv + 15
year: 1993
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
remark: ``SCAA005'' --- back cover.
acknowledgement: ack-nhfb
title:
Interfacing TI clocked FIFOs with TI floating-point digital signal processors: first-in, first-out technology

keywords:
Computer input-output equipment.; Signal processing --- Digital techniques --- Equipment and; supplies.

rawtitle:
Interfacing {TI} clocked {FIFOs} with {TI} floating-point digital signal processors: first-in, first-out technology

entry:
@Manual{TI:1993:ITC,
  title =        "Interfacing {TI} clocked {FIFOs} with {TI}
                 floating-point digital signal processors: first-in,
                 first-out technology",
  organization = "Texas Instruments Incorporated",
  address =      "S.l",
  pages =        "iv + 15",
  year =         "1993",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer input-output equipment.; Signal processing
                 --- Digital techniques --- Equipment and; supplies.",
  remark =       "``SCAA005'' --- back cover.",
}


bibtype: misc
filename: fparith.bib
label: TI:1993:ITT
title: Inside technology today 32-bit floating point multi-port DSP / produced by Texas Instruments
address: Dallas, TX, USA
pages: iv + 15
year: 1993
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
note: 1 videocassette
keywords: Computer --- Circuits.; Electronic calculating machines circuits.
acknowledgement: ack-nhfb
key: TI '1993
rawnote: 1 videocassette
howpublished:
VHS format. High-speed, multi-port DSPs can be used in parallel processing applications to really enhance computation time and power. A popular 6-port floating point DSP and high speed design integration and applications are described in this tape.

rawtitle:
Inside technology today 32-bit floating point multi-port {DSP} \slash{} produced by {Texas Instruments}

entry:
@Misc{TI:1993:ITT,
  key =          "TI '1993",
  title =        "Inside technology today 32-bit floating point
                 multi-port {DSP} \slash{} produced by {Texas
                 Instruments}",
  howpublished = "VHS format. High-speed, multi-port DSPs can be used in
                 parallel processing applications to really enhance
                 computation time and power. A popular 6-port floating
                 point DSP and high speed design integration and
                 applications are described in this tape.",
  address =      "Dallas, TX, USA",
  year =         "1993",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "1 videocassette",
  acknowledgement = ack-nhfb,
  keywords =     "Computer --- Circuits.; Electronic calculating
                 machines circuits.",
  publication =  "Texas Instruments Inc.",
}


bibtype: article
filename: fparith.bib
label: Timmermann:1993:GFR
author: D. Timmermann and B. Rix and B. Hosticka
journal: j-ELECTRONIK
volume: 20
pages: 142--146
year: 1993
CODEN: EKRKAR
ISSN: 0013-5658 OR 00135658
bibdate: Fri Dec 08 13:05:00 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 13:05:00 ???
fjournal: Elektronik
acknowledgement: ack-nj
rawauthor: D. Timmermann and B. Rix and B. Hosticka
title:
Gleitkommaprozessor fur rechenintensive Echtzeitanwendungen toenglish Floating-point Processor for Computationally Intensive Real-Time Use endtoenglish 

rawtitle:
{Gleitkommaprozessor f{\"u}r rechenintensive Echtzeitanwendungen} \toenglish {Floating-point Processor for Computationally Intensive Real-Time Use} \endtoenglish

entry:
@Article{Timmermann:1993:GFR,
  author =       "D. Timmermann and B. Rix and B. Hosticka",
  title =        "{Gleitkommaprozessor f{\"u}r rechenintensive
                 Echtzeitanwendungen} \toenglish {Floating-point
                 Processor for Computationally Intensive Real-Time Use}
                 \endtoenglish",
  journal =      j-ELECTRONIK,
  volume =       "20",
  number =       "??",
  pages =        "142--146",
  month =        "????",
  year =         "1993",
  CODEN =        "EKRKAR",
  ISSN =         "0013-5658",
  bibdate =      "Fri Dec 08 13:05:00 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Elektronik",
}


bibtype: article
filename: fparith.bib
label: Tiwari:1993:NCP
author: Neeraj Tiwari and A. K. Nigam
title: A note on constructive procedure for unbiased controlled rounding
journal: j-STAT-PROB-LETT
volume: 18
number: 5
pages: 415--420
day: 2
month: dec
monthnumber: 12
year: 1993
CODEN: SPLTDC
ISSN: 0167-7152 (print), 1879-2103 (electronic) OR 01677152 (print), 18792103 (electronic)
ISSNL: 0167-7152 OR 01677152
bibdate: Sun Jun 1 11:14:48 MDT 2014
bibtimestamp: 2014.06.01 11:14:48 MDT
URL: http://www.sciencedirect.com/science/article/pii/016771529390036I
fjournal: Statistics & Probability Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01677152
rawauthor: Neeraj Tiwari and A. K. Nigam
rawtitle: A note on constructive procedure for unbiased controlled rounding
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/statproblett1990.bib

entry:
@Article{Tiwari:1993:NCP,
  author =       "Neeraj Tiwari and A. K. Nigam",
  title =        "A note on constructive procedure for unbiased
                 controlled rounding",
  journal =      j-STAT-PROB-LETT,
  volume =       "18",
  number =       "5",
  pages =        "415--420",
  day =          "2",
  month =        dec,
  year =         "1993",
  CODEN =        "SPLTDC",
  ISSN =         "0167-7152 (print), 1879-2103 (electronic)",
  ISSN-L =       "0167-7152",
  bibdate =      "Sun Jun 1 11:14:48 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/statproblett1990.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/016771529390036I",
  acknowledgement = ack-nhfb,
  fjournal =     "Statistics \& Probability Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01677152",
}


bibtype: article
filename: fparith.bib
label: Tsuji:1993:FNS
author: Kumiko Tsuji
journal: Surikaisekikenkyusho Kokyuroku
volume: 831
pages: 33--45
year: 1993
MRclass: 65G05
MRnumber: 95a:65083
bibdate: Fri Dec 8 08:24:11 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:11 ???
acknowledgement: ack-nhfb
rawauthor: Kumiko Tsuji
title:
Floating-point number solutions in a simple linear equation with addition algorithm. Numerical calculation methods with guaranteed accuracy and their applications (Japanese) (Kyoto, 1992)

rawtitle:
Floating-point number solutions in a simple linear equation with addition algorithm. Numerical calculation methods with guaranteed accuracy and their applications ({Japanese}) ({Kyoto}, 1992)

entry:
@Article{Tsuji:1993:FNS,
  author =       "Kumiko Tsuji",
  title =        "Floating-point number solutions in a simple linear
                 equation with addition algorithm. Numerical calculation
                 methods with guaranteed accuracy and their applications
                 ({Japanese}) ({Kyoto}, 1992)",
  journal =      "S{\=u}rikaisekikenky{\=u}sho K{\=o}ky{\=u}roku",
  volume =       "831",
  pages =        "33--45",
  year =         "1993",
  MRclass =      "65G05",
  MRnumber =     "95a:65083",
  bibdate =      "Fri Dec 8 08:24:11 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Turner:1993:CSA
author: P. R. Turner
title: Complex SLI arithmetic: Representation, algorithms and analysis
crossref: Swartzlander:1993:SCA
pages: 18--25
year: 1993
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Turner.pdf
acknowledgement: ack-nhfb
affiliation: Department of Math., US Naval Acad., Annapolis, MD, USA
thesaurus: Floating point arithmetic
rawauthor: P. R. Turner
rawtitle: Complex {SLI} arithmetic: Representation, algorithms and analysis
abstract:
The extension of the SLI (symmetric level index) system to complex numbers and arithmetic is discussed. The natural form for representation of complex quantities in SLI is in the modulus-argument form, and this can be sensibly packed into a single 64-b word for the equivalent of the 32-b real SLI representation. The arithmetic algorithms prove to be very slightly more complicated than for real SLI arithmetic. The representation, the arithmetic algorithms, and the control of errors within these algorithms are described.

keywords:
ARITH-11; Arithmetic algorithms; Complex numbers; Modulus-argument form; Representation; SLI; SLI arithmetic; Symmetric level index

rawabstract:
The extension of the SLI (symmetric level index) system to complex numbers and arithmetic is discussed. The natural form for representation of complex quantities in SLI is in the modulus-argument form, and this can be sensibly packed into a single 64-b word for the equivalent of the 32-b real SLI representation. The arithmetic algorithms prove to be very slightly more complicated than for real SLI arithmetic. The representation, the arithmetic algorithms, and the control of errors within these algorithms are described.

entry:
@InProceedings{Turner:1993:CSA,
  author =       "P. R. Turner",
  title =        "Complex {SLI} arithmetic: Representation, algorithms
                 and analysis",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "18--25",
  year =         "1993",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Turner.pdf",
  abstract =     "The extension of the SLI (symmetric level index)
                 system to complex numbers and arithmetic is discussed.
                 The natural form for representation of complex
                 quantities in SLI is in the modulus-argument form, and
                 this can be sensibly packed into a single 64-b word for
                 the equivalent of the 32-b real SLI representation. The
                 arithmetic algorithms prove to be very slightly more
                 complicated than for real SLI arithmetic. The
                 representation, the arithmetic algorithms, and the
                 control of errors within these algorithms are
                 described.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Math., US Naval Acad., Annapolis, MD,
                 USA",
  classification = "C5230 (Digital arithmetic methods)",
  keywords =     "ARITH-11; Arithmetic algorithms; Complex numbers;
                 Modulus-argument form; Representation; SLI; SLI
                 arithmetic; Symmetric level index",
  thesaurus =    "Floating point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Vassiliadis:1993:CHW
author: S. Vassiliadis and E. M. Schwarz
title: Correction to ``Hard-wired multipliers with encoded partial products''
journal: j-IEEE-TRANS-COMPUT
volume: 42
number: 1
pages: 127--127
month: jan
monthnumber: 1
year: 1993
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.192224
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:58:47 MDT 2011
bibtimestamp: 2011.07.07 07:58:47 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=192224
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Vassiliadis and E. M. Schwarz
rawtitle: Correction to {``Hard-wired multipliers with encoded partial products''}
entry:
@Article{Vassiliadis:1993:CHW,
  author =       "S. Vassiliadis and E. M. Schwarz",
  title =        "Correction to {``Hard-wired multipliers with encoded
                 partial products''}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "42",
  number =       "1",
  pages =        "127--127",
  month =        jan,
  year =         "1993",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.192224",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:58:47 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=192224",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Veselic:1993:FPH
author: Kresimir Veselic and Ivan Slapnicar
title: Floating-Point Perturbations of Hermitian Matrices
journal: j-LINEAR-ALGEBRA-APPL
volume: 195
pages: 81--116
month: dec
monthnumber: 12
year: 1993
CODEN: LAAPAW
ISSN: 0024-3795 (print), 1873-1856 (electronic) OR 00243795 (print), 18731856 (electronic)
ISSNL: 0024-3795 OR 00243795
MRclass: 65F15 (15A18 15A57)
MRnumber: 94m:65066
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Linear Algebra and its Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00243795
rawauthor: Kre{\v{s}}imir Veseli{\'c} and Ivan Slapni{\v{c}}ar
rawtitle: Floating-Point Perturbations of {Hermitian} Matrices
entry:
@Article{Veselic:1993:FPH,
  author =       "Kre{\v{s}}imir Veseli{\'c} and Ivan Slapni{\v{c}}ar",
  title =        "Floating-Point Perturbations of {Hermitian} Matrices",
  journal =      j-LINEAR-ALGEBRA-APPL,
  volume =       "195",
  number =       "??",
  pages =        "81--116",
  month =        dec,
  year =         "1993",
  CODEN =        "LAAPAW",
  ISSN =         "0024-3795 (print), 1873-1856 (electronic)",
  ISSN-L =       "0024-3795",
  MRclass =      "65F15 (15A18 15A57)",
  MRnumber =     "94m:65066",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Linear Algebra and its Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00243795",
}


bibtype: article
filename: fparith.bib
label: Vignes:1993:SAR
author: J. Vignes
title: A stochastic arithmetic for reliable scientific computation
journal: j-MATH-COMPUT-SIMUL
volume: 35
number: 3
pages: 233--261
month: sep
monthnumber: 9
year: 1993
CODEN: MCSIDR
DOI: https://doi.org/10.1016/0378-4754(93)90003-D
ISSN: 0378-4754 (print), 1872-7166 (electronic) OR 03784754 (print), 18727166 (electronic)
ISSNL: 0378-4754 OR 03784754
bibdate: Thu Mar 24 20:56:34 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.24 20:56:34 ???
URL: http://portal.acm.org/citation.cfm?id=165789.165792
fjournal: Mathematics and Computers in Simulation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03784754
rawauthor: J. Vignes
rawtitle: A stochastic arithmetic for reliable scientific computation
entry:
@Article{Vignes:1993:SAR,
  author =       "J. Vignes",
  title =        "A stochastic arithmetic for reliable scientific
                 computation",
  journal =      j-MATH-COMPUT-SIMUL,
  volume =       "35",
  number =       "3",
  pages =        "233--261",
  month =        sep,
  year =         "1993",
  CODEN =        "MCSIDR",
  DOI =          "https://doi.org/10.1016/0378-4754(93)90003-D",
  ISSN =         "0378-4754 (print), 1872-7166 (electronic)",
  ISSN-L =       "0378-4754",
  bibdate =      "Thu Mar 24 20:56:34 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://portal.acm.org/citation.cfm?id=165789.165792",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematics and Computers in Simulation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03784754",
}


bibtype: article
filename: fparith.bib
label: vonNeumann:1993:FDR
author: John von Neumann
title: First Draft of a Report on the EDVAC
journal: j-IEEE-ANN-HIST-COMPUT
volume: 15
number: 4
pages: 28--75
month: oct
monthnumber: 10
year: 1993
CODEN: IAHCEX
ISSN: 1058-6180 (print), 1934-1547 (electronic) OR 10586180 (print), 19341547 (electronic)
ISSNL: 1058-6180 OR 10586180
bibdate: Thu Jul 12 06:22:55 MDT 2001
bibtimestamp: 2001.07.12 06:22:55 MDT
note: Edited and corrected by Michael D. Godfrey.
fjournal: IEEE Annals of the History of Computing
keywords: floating-point arithmetic; rounding
acknowledgement: ack-nhfb
ajournal: IEEE Ann. Hist. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=85
rawauthor: John von Neumann
rawnote: Edited and corrected by Michael D. Godfrey.
rawtitle: First Draft of a Report on the {EDVAC}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeeannhistcomput.bib

URL:
http://dlib.computer.org/an/books/an1993/pdf/a4027.pdf; http://www.computer.org/annals/an1993/a4027abs.htm

entry:
@Article{vonNeumann:1993:FDR,
  author =       "John von Neumann",
  title =        "First Draft of a Report on the {EDVAC}",
  journal =      j-IEEE-ANN-HIST-COMPUT,
  volume =       "15",
  number =       "4",
  pages =        "28--75",
  month =        oct # "\slash " # dec,
  year =         "1993",
  CODEN =        "IAHCEX",
  ISSN =         "1058-6180 (print), 1934-1547 (electronic)",
  ISSN-L =       "1058-6180",
  bibdate =      "Thu Jul 12 06:22:55 MDT 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeeannhistcomput.bib",
  note =         "Edited and corrected by Michael D. Godfrey.",
  URL =          "http://dlib.computer.org/an/books/an1993/pdf/a4027.pdf;
                 http://www.computer.org/annals/an1993/a4027abs.htm",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Ann. Hist. Comput.",
  fjournal =     "IEEE Annals of the History of Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=85",
  keywords =     "floating-point arithmetic; rounding",
  xxpages =      "27--??",
}


bibtype: article
filename: fparith.bib
label: Vornberger:1993:BBM
author: Cal Vornberger
journal: j-BYTE
volume: 18
number: 13
pages: 165--166, 168
month: dec
monthnumber: 12
year: 1993
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 16:34:03 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 16:34:03 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
thesaurus: Business graphics; Desktop publishing
rawauthor: Cal Vornberger
title:
Beyond Bit Maps: Multiple floating objects deliver new power and flexibility to bit-map image processing. Micrografx Picture Publisher 4.0 and Fractal Design Painter X2 feature object layers and other useful innovations

keywords:
Bit maps; Ease of use; Fractal design painterX2; Functionality; Micrografx; Object technology; Picture Publisher 4.0

rawtitle:
Beyond Bit Maps: Multiple floating objects deliver new power and flexibility to bit-map image processing. {Micrografx Picture Publisher} 4.0 and {Fractal Design Painter X2} feature object layers and other useful innovations

entry:
@Article{Vornberger:1993:BBM,
  author =       "Cal Vornberger",
  title =        "Beyond Bit Maps: Multiple floating objects deliver new
                 power and flexibility to bit-map image processing.
                 {Micrografx Picture Publisher} 4.0 and {Fractal Design
                 Painter X2} feature object layers and other useful
                 innovations",
  journal =      j-BYTE,
  volume =       "18",
  number =       "13",
  pages =        "165--166, 168",
  month =        dec,
  year =         "1993",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 16:34:03 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "D2010 (Business and professional); D2020 (Design and
                 graphics)",
  fjournal =     "BYTE Magazine",
  keywords =     "Bit maps; Ease of use; Fractal design painterX2;
                 Functionality; Micrografx; Object technology; Picture
                 Publisher 4.0",
  thesaurus =    "Business graphics; Desktop publishing",
}


bibtype: article
filename: fparith.bib
label: Walter:1993:SMM
author: C. D. Walter
title: Systolic modular multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 42
number: 3
pages: 376--378
month: mar
monthnumber: 3
year: 1993
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.210181
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:58:48 MDT 2011
bibtimestamp: 2011.07.07 07:58:48 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=210181
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. D. Walter
rawtitle: Systolic modular multiplication
entry:
@Article{Walter:1993:SMM,
  author =       "C. D. Walter",
  title =        "Systolic modular multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "42",
  number =       "3",
  pages =        "376--378",
  month =        mar,
  year =         "1993",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.210181",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:58:48 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=210181",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wang:1993:SAC
author: Chin-Liang Wang and Jung-Lung Lin
title: A systolic architecture for computing inverses and divisions in finite fields $ mathrm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 42
number: 9
pages: 1141--1146
month: sep
monthnumber: 9
year: 1993
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.241603
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:58:51 MDT 2011
bibtimestamp: 2011.07.07 07:58:51 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=241603
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Chin-Liang Wang and Jung-Lung Lin
rawtitle:
A systolic architecture for computing inverses and divisions in finite fields {$ \mathrm {GF}(2^m) $}

entry:
@Article{Wang:1993:SAC,
  author =       "Chin-Liang Wang and Jung-Lung Lin",
  title =        "A systolic architecture for computing inverses and
                 divisions in finite fields {$ \mathrm {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "42",
  number =       "9",
  pages =        "1141--1146",
  month =        sep,
  year =         "1993",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.241603",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:58:51 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=241603",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Wei:1993:CTA
author: D.-Y. D. Wei and J. H. Kim and T. R. N. Rao
title: Complete tests in algorithm-based fault-tolerant matrix operation on processor arrays
crossref: Lombardi:1993:PII
pages: 255--262
year: 1993
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Center for Adv. Comput. Studies, University of Southwestern Louisiana, Lafayette, LA, USA
rawauthor: D.-Y. D. Wei and J. H. Kim and T. R. N. Rao
rawtitle: Complete tests in algorithm-based fault-tolerant matrix operation on processor arrays
abstract:
Recently, F. T. Assaad and S. Dutt (1992) proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the thresholded test in their approach is still not avoidable in the floating-point additions involved in matrix multiplication and the number of error detections decrease with the increase in the dynamic range of data, which is not totally satisfactory. The authors present an effective method, called concurrent floating-point checksum (CFPC) test, which provides very convincing error detection/correction capabilities for the part of floating-point addition with a minimum time latency and hardware overhead.

keywords:
concurrent floating-point checksum; error correction; error detections; fault-tolerant matrix; floating-point additions; floating-point matrix-matrix multiplication; floating-point testing; hardware overhead; hybrid checksum test; minimum time latency; processor arrays; thresholded test

thesaurus:
Computational complexity; Error correction; Error detection; Fault tolerant computing; Floating point arithmetic; Logic arrays; Logic testing; Matrix multiplication

rawabstract:
Recently, F. T. Assaad and S. Dutt (1992) proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the thresholded test in their approach is still not avoidable in the floating-point additions involved in matrix multiplication and the number of error detections decrease with the increase in the dynamic range of data, which is not totally satisfactory. The authors present an effective method, called concurrent floating-point checksum (CFPC) test, which provides very convincing error detection/correction capabilities for the part of floating-point addition with a minimum time latency and hardware overhead.

entry:
@InProceedings{Wei:1993:CTA,
  author =       "D.-Y. D. Wei and J. H. Kim and T. R. N. Rao",
  title =        "Complete tests in algorithm-based fault-tolerant
                 matrix operation on processor arrays",
  crossref =     "Lombardi:1993:PII",
  pages =        "255--262",
  year =         "1993",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Recently, F. T. Assaad and S. Dutt (1992) proposed the
                 hybrid checksum test method for the floating-point
                 matrix-matrix multiplication in ABFT environment, by
                 which the error coverage can be greatly increased.
                 However, the thresholded test in their approach is
                 still not avoidable in the floating-point additions
                 involved in matrix multiplication and the number of
                 error detections decrease with the increase in the
                 dynamic range of data, which is not totally
                 satisfactory. The authors present an effective method,
                 called concurrent floating-point checksum (CFPC) test,
                 which provides very convincing error
                 detection/correction capabilities for the part of
                 floating-point addition with a minimum time latency and
                 hardware overhead.",
  acknowledgement = ack-nhfb,
  affiliation =  "Center for Adv. Comput. Studies, University of
                 Southwestern Louisiana, Lafayette, LA, USA",
  classification = "B0290H (Linear algebra); B1265 (Digital
                 electronics); B6120B (Codes); C4140 (Linear algebra);
                 C5210 (Logic design methods); C5230 (Digital arithmetic
                 methods); C6130 (Data handling techniques)",
  keywords =     "concurrent floating-point checksum; error correction;
                 error detections; fault-tolerant matrix; floating-point
                 additions; floating-point matrix-matrix multiplication;
                 floating-point testing; hardware overhead; hybrid
                 checksum test; minimum time latency; processor arrays;
                 thresholded test",
  thesaurus =    "Computational complexity; Error correction; Error
                 detection; Fault tolerant computing; Floating point
                 arithmetic; Logic arrays; Logic testing; Matrix
                 multiplication",
}


bibtype: book
filename: fparith.bib
label: Weste:1993:PCV
author: Neil H. E. Weste and Kamran Eshraghian
title: Principles of CMOS VLSI Design: a Systems Perspective
publisher: pub-AW
address: pub-AW:adr
edition: Second
pages: xxii + 713
year: 1993
ISBN: 0-201-53376-6 OR 0201533766
ISBN13: 978-0-201-53376-7 OR 9780201533767
LCCN: TK7874 .W46 1993
bibdate: Mon Sep 16 16:32:31 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.09.16 16:32:31 ???
acknowledgement: ack-nhfb
rawauthor: Neil H. E. Weste and Kamran Eshraghian
rawtitle: Principles of {CMOS VLSI} Design: a Systems Perspective
entry:
@Book{Weste:1993:PCV,
  author =       "Neil H. E. Weste and Kamran Eshraghian",
  title =        "Principles of {CMOS VLSI} Design: a Systems
                 Perspective",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  edition =      "Second",
  pages =        "xxii + 713",
  year =         "1993",
  ISBN =         "0-201-53376-6",
  ISBN-13 =      "978-0-201-53376-7",
  LCCN =         "TK7874 .W46 1993",
  bibdate =      "Mon Sep 16 16:32:31 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Williams:1993:BFM
author: Al Williams
title: Bit Floating-Point Math
journal: j-DDJ
volume: 18
number: 6
pages: 70--??
month: jun
monthnumber: 6
year: 1993
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
rawauthor: Al Williams
rawtitle: Bit Floating-Point Math
abstract:
This approach to floating-point math uses 32-bit instructions. Although Al uses the 80386 as an example, these techniques can be applied to other 32-bit processors as well.

rawabstract:
This approach to floating-point math uses 32-bit instructions. Although Al uses the 80386 as an example, these techniques can be applied to other 32-bit processors as well.

entry:
@Article{Williams:1993:BFM,
  author =       "Al Williams",
  title =        "Bit Floating-Point Math",
  journal =      j-DDJ,
  volume =       "18",
  number =       "6",
  pages =        "70--??",
  month =        jun,
  year =         "1993",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This approach to floating-point math uses 32-bit
                 instructions. Although Al uses the 80386 as an example,
                 these techniques can be applied to other 32-bit
                 processors as well.",
  acknowledgement = ack-nhfb,
  fjournal =     "Dr. Dobb's Journal of Software Tools",
}


bibtype: article
filename: fparith.bib
label: Williams:1993:FM
author: Al Williams
title: 32-bit floating-point math
journal: j-DDJ
volume: 18
number: 6
pages: 70, 72, 74, 76, 80
month: jun
monthnumber: 6
year: 1993
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 10 08:57:56 MDT 1996
bibtimestamp: 1996.09.10 08:57:56 MDT
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
thesaurus: Digital arithmetic; Microprocessor chips
rawauthor: Al Williams
rawtitle: 32-bit floating-point math
abstract:
This approach to floating-point math uses 32-bit instructions. Although Al uses the 80386 as an example, these techniques can be applied to other 32-bit processors as well.

keywords:
32 Bit; 32-Bit instructions; 32-Bit processors; 386 Instruction set; 80386; Floating-point mathematics

entry:
@Article{Williams:1993:FM,
  author =       "Al Williams",
  title =        "32-bit floating-point math",
  journal =      j-DDJ,
  volume =       "18",
  number =       "6",
  pages =        "70, 72, 74, 76, 80",
  month =        jun,
  year =         "1993",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 10 08:57:56 MDT 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "This approach to floating-point math uses 32-bit
                 instructions. Although Al uses the 80386 as an example,
                 these techniques can be applied to other 32-bit
                 processors as well.",
  acknowledgement = ack-nhfb,
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "32 Bit; 32-Bit instructions; 32-Bit processors; 386
                 Instruction set; 80386; Floating-point mathematics",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Wrzyszcz:1993:DDCa
author: A. Wrzyszcz and D. Caban and E. L. Dagless
title: Design of a discrete cosine transform circuit using the residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 584--588
year: 1993
DOI: https://doi.org/10.1109/EDAC.1993.386412
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Wrzyszcz and D. Caban and E. L. Dagless
rawtitle: Design of a discrete cosine transform circuit using the residue number system
booktitle:
Proceedings. [4th] European Conference on Design Automation, 1993, with the European Event in ASIC Design

rawbooktitle:
Proceedings. [4th] European Conference on Design Automation, 1993, with the European Event in {ASIC} Design

entry:
@InProceedings{Wrzyszcz:1993:DDCa,
  author =       "A. Wrzyszcz and D. Caban and E. L. Dagless",
  booktitle =    "Proceedings. [4th] European Conference on Design
                 Automation, 1993, with the European Event in {ASIC}
                 Design",
  title =        "Design of a discrete cosine transform circuit using
                 the residue number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "584--588",
  year =         "1993",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EDAC.1993.386412",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The design of an integrated circuit aimed at efficient
                 discrete cosine transform computation is presented.
                 High performance is obtained through the use of
                 pipelining and residue arithmetic. An approach to
                 high-speed modular multiplication employing \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Wrzyszcz:1993:DDCb
author: A. Wrzyszcz and D. Caban and E. L. Dagless
title: Design of a discrete cosine transform circuit using the residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 584--588
year: 1993
DOI: https://doi.org/10.1109/EDAC.1993.386412
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Wrzyszcz and D. Caban and E. L. Dagless
rawtitle: Design of a discrete cosine transform circuit using the residue number system
booktitle:
Proceedings. [4th] European Conference on Design Automation, 1993, with the European Event in ASIC Design

rawbooktitle:
Proceedings. [4th] European Conference on Design Automation, 1993, with the European Event in {ASIC} Design

entry:
@InProceedings{Wrzyszcz:1993:DDCb,
  author =       "A. Wrzyszcz and D. Caban and E. L. Dagless",
  booktitle =    "Proceedings. [4th] European Conference on Design
                 Automation, 1993, with the European Event in {ASIC}
                 Design",
  title =        "Design of a discrete cosine transform circuit using
                 the residue number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "584--588",
  year =         "1993",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EDAC.1993.386412",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The design of an integrated circuit aimed at efficient
                 discrete cosine transform computation is presented.
                 High performance is obtained through the use of
                 pipelining and residue arithmetic. An approach to
                 high-speed modular multiplication employing \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Zeng:1993:CFA
author: Chuan-Qing Zeng and Kousuke Tsukamoto and Takeo Miyata
title: Charge-balancing floating-point analogue-to-digital converter using acyclic conversion
journal: j-INT-J-ELECTRON
volume: 74
number: 5
pages: 705--??
month: may
monthnumber: 5
year: 1993
CODEN: IJELA2
ISSN: 0020-7217 (print), 1362-3060 (electronic) OR 00207217 (print), 13623060 (electronic)
ISSNL: 0020-7217 OR 00207217
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: International Journal of Electronics Theoretical & Experimental
acknowledgement: ack-nhfb
rawauthor: Chuan-Qing Zeng and Kousuke Tsukamoto and Takeo Miyata
rawtitle: Charge-balancing floating-point analogue-to-digital converter using acyclic conversion
entry:
@Article{Zeng:1993:CFA,
  author =       "Chuan-Qing Zeng and Kousuke Tsukamoto and Takeo
                 Miyata",
  title =        "Charge-balancing floating-point analogue-to-digital
                 converter using acyclic conversion",
  journal =      j-INT-J-ELECTRON,
  volume =       "74",
  number =       "5",
  pages =        "705--??",
  month =        may,
  year =         "1993",
  CODEN =        "IJELA2",
  ISSN =         "0020-7217 (print), 1362-3060 (electronic)",
  ISSN-L =       "0020-7217",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Electronics Theoretical \&
                 Experimental",
}


bibtype: article
filename: fparith.bib
label: Zhang:1993:EAP
author: C. N. Zhang and B. Shirazi and D. Y. Y. Yun
title: An Efficient Algorithm and Parallel Implementations for Binary and Residue Number Systems
journal: j-J-SYMBOLIC-COMP
volume: 15
number: 4
pages: 451--462
month: apr
monthnumber: 4
year: 1993
CODEN: JSYCEH
DOI: https://doi.org/10.1006/jsco.1993.1030
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
MRclass: 65G10 (65Y05)
MRnumber: 94j:65066
MRreviewer: De Ren Wang
bibdate: Sat May 10 15:54:09 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.05.10 15:54:09 MDT
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
classcodes: C7310 (Mathematics); C7410D (Electronic engineering)
corpsource: Department of Computer Science, Regina University, Sask., Canada
journalURL: http://www.sciencedirect.com/science/journal/07477171
treatment: A Application; P Practical
rawauthor: C. N. Zhang and B. Shirazi and D. Y. Y. Yun
rawtitle: An Efficient Algorithm and Parallel Implementations for Binary and Residue Number Systems
abstract:
Arithmetic units based on a Residue Number System (RNS) are fast and simple, and therefore attractive for use in digital signal processing and symbolic computation applications. However, RNS suffers from overheads of converting numbers to and from residue system. We present a new simple and uniform computation formula for both conversion from RNS to binary and vice versa. Two levels of parallelism for VLSI hardware design of the proposed algorithm are introduced.

keywords:
algorithm; binary number systems; circuit CAD; computation; digital signal processing; parallel implementations; parallelism; residue number systems; symbol manipulation; symbolic; VLSI; VLSI hardware design

rawabstract:
Arithmetic units based on a Residue Number System (RNS) are fast and simple, and therefore attractive for use in digital signal processing and symbolic computation applications. However, RNS suffers from overheads of converting numbers to and from residue system. We present a new simple and uniform computation formula for both conversion from RNS to binary and vice versa. Two levels of parallelism for VLSI hardware design of the proposed algorithm are introduced.

entry:
@Article{Zhang:1993:EAP,
  author =       "C. N. Zhang and B. Shirazi and D. Y. Y. Yun",
  title =        "An Efficient Algorithm and Parallel Implementations
                 for Binary and Residue Number Systems",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "15",
  number =       "4",
  pages =        "451--462",
  month =        apr,
  year =         "1993",
  CODEN =        "JSYCEH",
  DOI =          "https://doi.org/10.1006/jsco.1993.1030",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  MRclass =      "65G10 (65Y05)",
  MRnumber =     "94j:65066",
  MRreviewer =   "De Ren Wang",
  bibdate =      "Sat May 10 15:54:09 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Arithmetic units based on a Residue Number System
                 (RNS) are fast and simple, and therefore attractive for
                 use in digital signal processing and symbolic
                 computation applications. However, RNS suffers from
                 overheads of converting numbers to and from residue
                 system. We present a new simple and uniform computation
                 formula for both conversion from RNS to binary and vice
                 versa. Two levels of parallelism for VLSI hardware
                 design of the proposed algorithm are introduced.",
  acknowledgement = ack-nhfb,
  classcodes =   "C7310 (Mathematics); C7410D (Electronic engineering)",
  corpsource =   "Department of Computer Science, Regina University,
                 Sask., Canada",
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
  keywords =     "algorithm; binary number systems; circuit CAD;
                 computation; digital signal processing; parallel
                 implementations; parallelism; residue number systems;
                 symbol manipulation; symbolic; VLSI; VLSI hardware
                 design",
  treatment =    "A Application; P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Zuras:1993:SML
author: D. Zuras
title: On Squaring and Multiplying Large Integers
crossref: Swartzlander:1993:SCA
pages: 260--271
year: 1993
bibdate: Sat Nov 17 09:46:07 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 09:46:07 ???
URL: http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Zuras.pdf
keywords: ARITH-11
acknowledgement: ack-nhfb
rawauthor: D. Zuras
rawtitle: On Squaring and Multiplying Large Integers
entry:
@InProceedings{Zuras:1993:SML,
  author =       "D. Zuras",
  title =        "On Squaring and Multiplying Large Integers",
  crossref =     "Swartzlander:1993:SCA",
  pages =        "260--271",
  year =         "1993",
  bibdate =      "Sat Nov 17 09:46:07 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith11/papers/ARITH11_Zuras.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-11",
}


bibtype: book
filename: fparith.bib
label: Zuse:1993:CML
author: Konrad Zuse
title: The Computer, My Life
publisher: pub-SV
address: pub-SV:adr
pages: 245
year: 1993
ISBN: 3-540-56453-5 (Berlin), 0-387-56453-5 (New York) OR 3540564535 (Berlin), 0387564535 (New York)
LCCN: TK7885.22.Z87 A3 1993
bibdate: Mon Nov 4 07:46:57 MST 2002
bibtimestamp: 2002.11.04 07:46:57 MST
keywords: computer engineers --- Germany --- biography; computers --- Germany --- history; Zuse, Konrad
acknowledgement: ack-nhfb
rawauthor: Konrad Zuse
rawtitle: The Computer, My Life
ISBN13:
978-3-540-56453-9 (Berlin), 978-0-387-56453-1 (New York) OR 9783540564539 (Berlin), 9780387564531 (New York)

TOC:
1: Ancestors and parents --- Early childhood memories --- School days --- Metropolis --- Abitur / 1 2: Studies (not without detours and byways) and general studies --- First inventions --- The emph Akademische Verein Motiv --- Student life between science and politics / 15 3: The early years of the computer and a digression on its prehistory --- Colleagues remember --- From mechanics to electromechanics --- Schreyer's electronic computing machine --- First outside contacts --- Thoughts on the future / 33 4: Outbreak of the war and first callup --- Structural engineer in aircraft construction --- The Z2 and Z3 --- Second callup --- emph Zuse Ingenieurburo und Apparatebau, Berlin --- The first process computer / 55 5: Origins of the Z4 --- News from the United States --- Attempt at a PhD dissertation --- Computing machine for logic operations --- Final months of the war in Berlin --- The evacuation --- Z4 completed in Gottingen --- Final war days in the Allgau / 75 6: End of the war --- Refugees in Hinterstein --- The emph Plankalkul --- The computing universe --- Automation and self-reproducing systems --- A logarithmic computing machine --- Computer development in Germany and the United States --- Move to Hopferau near Fussen --- The mill of the Patent Office / 95 7: The emph Zuse-Ingenieurburo, Hopferau bei Fussen --- First business partners: IBM and Remington Rand --- The first pipelining design --- Founding of ZUSE KG in Neukirchen --- The Z4 in the ETH in Zurich --- The computer in Europe: taking stock --- Lost opportunities --- The first German contract: the Z5 / 113 8: The partners leave --- Computing machine for land use zoning --- Electronics gains acceptance --- First funds from the emph Deutsche Forschungsgemeinschaft --- Losing one's way (and possibly a lost opportunity) --- The array processor --- Custom work for geodesics --- The Graphomat Z64 --- Growth and crisis of ZUSE KG --- The end / 133 9: Free for science (again) --- Honors --- A look to the future / 157 Appendices 1: From Forms to Program Control / 185 2: Construction of Devices / 190 3: On Computer Architecture / 210 4: On the Plan Calculus / 211 5: Lecture on the Occasion of the Award of the Honorary Doctorate by the Technical University of Berlin (Extract) / 222 6: The Computer Did Not Fall From Heaven / 225 Notes / 229 References / 231 Name Index / 235 Subject Index / 239 Computer Index / 245

rawTOC:
1: Ancestors and parents --- Early childhood memories --- School days --- Metropolis --- Abitur / 1 \\ 2: Studies (not without detours and byways) and general studies --- First inventions --- The \emph{Akademische Verein Motiv} --- Student life between science and politics / 15 \\ 3: The early years of the computer and a digression on its prehistory --- Colleagues remember --- From mechanics to electromechanics --- Schreyer's electronic computing machine --- First outside contacts --- Thoughts on the future / 33 \\ 4: Outbreak of the war and first callup --- Structural engineer in aircraft construction --- The Z2 and Z3 --- Second callup --- \emph{Zuse Ingenieurb{\"u}ro und Apparatebau, Berlin} --- The first process computer / 55 \\ 5: Origins of the Z4 --- News from the United States --- Attempt at a PhD dissertation --- Computing machine for logic operations --- Final months of the war in Berlin --- The evacuation --- Z4 completed in G{\"o}ttingen --- Final war days in the Allg{\"a}u / 75 \\ 6: End of the war --- Refugees in Hinterstein --- The \emph{Plankalk{\"u}l} --- The computing universe --- Automation and self-reproducing systems --- A logarithmic computing machine --- Computer development in Germany and the United States --- Move to Hopferau near F{\"u}ssen --- The mill of the Patent Office / 95 \\ 7: The \emph{Zuse-Ingenieurb{\"u}ro, Hopferau bei F{\"u}ssen} --- First business partners: IBM and Remington Rand --- The first pipelining design --- Founding of ZUSE KG in Neukirchen --- The Z4 in the ETH in Z{\"u}rich --- The computer in Europe: taking stock --- Lost opportunities --- The first German contract: the Z5 / 113 \\ 8: The partners leave --- Computing machine for land use zoning --- Electronics gains acceptance --- First funds from the \emph{Deutsche Forschungsgemeinschaft} --- Losing one's way (and possibly a lost opportunity) --- The array processor --- Custom work for geodesics --- The Graphomat Z64 --- Growth and crisis of ZUSE KG --- The end / 133 \\ 9: Free for science (again) --- Honors --- A look to the future / 157 \\ Appendices \\ 1: From Forms to Program Control / 185 \\ 2: Construction of Devices / 190 \\ 3: On Computer Architecture / 210 \\ 4: On the Plan Calculus / 211 \\ 5: Lecture on the Occasion of the Award of the Honorary Doctorate by the Technical University of Berlin (Extract) / 222 \\ 6: The Computer Did Not Fall From Heaven / 225 \\ Notes / 229 \\ References / 231 \\ Name Index / 235 \\ Subject Index / 239 \\ Computer Index / 245

entry:
@Book{Zuse:1993:CML,
  author =       "Konrad Zuse",
  title =        "The Computer, My Life",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "245",
  year =         "1993",
  ISBN =         "3-540-56453-5 (Berlin), 0-387-56453-5 (New York)",
  ISBN-13 =      "978-3-540-56453-9 (Berlin), 978-0-387-56453-1 (New
                 York)",
  LCCN =         "TK7885.22.Z87 A3 1993",
  bibdate =      "Mon Nov 4 07:46:57 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/annhistcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "computer engineers --- Germany --- biography;
                 computers --- Germany --- history; Zuse, Konrad",
  tableofcontents = "1: Ancestors and parents --- Early childhood
                 memories --- School days --- Metropolis --- Abitur / 1
                 \\
                 2: Studies (not without detours and byways) and general
                 studies --- First inventions --- The \emph{Akademische
                 Verein Motiv} --- Student life between science and
                 politics / 15 \\
                 3: The early years of the computer and a digression on
                 its prehistory --- Colleagues remember --- From
                 mechanics to electromechanics --- Schreyer's electronic
                 computing machine --- First outside contacts ---
                 Thoughts on the future / 33 \\
                 4: Outbreak of the war and first callup --- Structural
                 engineer in aircraft construction --- The Z2 and Z3 ---
                 Second callup --- \emph{Zuse Ingenieurb{\"u}ro und
                 Apparatebau, Berlin} --- The first process computer /
                 55 \\
                 5: Origins of the Z4 --- News from the United States
                 --- Attempt at a PhD dissertation --- Computing machine
                 for logic operations --- Final months of the war in
                 Berlin --- The evacuation --- Z4 completed in
                 G{\"o}ttingen --- Final war days in the Allg{\"a}u / 75
                 \\
                 6: End of the war --- Refugees in Hinterstein --- The
                 \emph{Plankalk{\"u}l} --- The computing universe ---
                 Automation and self-reproducing systems --- A
                 logarithmic computing machine --- Computer development
                 in Germany and the United States --- Move to Hopferau
                 near F{\"u}ssen --- The mill of the Patent Office / 95
                 \\
                 7: The \emph{Zuse-Ingenieurb{\"u}ro, Hopferau bei
                 F{\"u}ssen} --- First business partners: IBM and
                 Remington Rand --- The first pipelining design ---
                 Founding of ZUSE KG in Neukirchen --- The Z4 in the ETH
                 in Z{\"u}rich --- The computer in Europe: taking stock
                 --- Lost opportunities --- The first German contract:
                 the Z5 / 113 \\
                 8: The partners leave --- Computing machine for land
                 use zoning --- Electronics gains acceptance --- First
                 funds from the \emph{Deutsche Forschungsgemeinschaft}
                 --- Losing one's way (and possibly a lost opportunity)
                 --- The array processor --- Custom work for geodesics
                 --- The Graphomat Z64 --- Growth and crisis of ZUSE KG
                 --- The end / 133 \\
                 9: Free for science (again) --- Honors --- A look to
                 the future / 157 \\
                 Appendices \\
                 1: From Forms to Program Control / 185 \\
                 2: Construction of Devices / 190 \\
                 3: On Computer Architecture / 210 \\
                 4: On the Plan Calculus / 211 \\
                 5: Lecture on the Occasion of the Award of the Honorary
                 Doctorate by the Technical University of Berlin
                 (Extract) / 222 \\
                 6: The Computer Did Not Fall From Heaven / 225 \\
                 Notes / 229 \\
                 References / 231 \\
                 Name Index / 235 \\
                 Subject Index / 239 \\
                 Computer Index / 245",
}


bibtype: article
filename: fparith.bib
label: Agarwal:1994:EFP
author: R. C. Agarwal and F. G. Gustavson and M. Zubair
title: Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms
journal: j-IBM-JRD
volume: 38
number: 5
pages: 563--576
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Tue Mar 25 14:26:59 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.03.25 14:26:59 MST
URL: http://www.almaden.ibm.com/journal/rd38-5.html#eight
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
corpsource: Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
treatment: P Practical
rawauthor: R. C. Agarwal and F. G. Gustavson and M. Zubair
rawtitle: Exploiting functional parallelism of {POWER2} to design high-performance numerical algorithms
abstract:
We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine --- in this case, the new POWER2* machines from the RS / 6000 family of RISC processors. The algorithmic features that we emphasize are functional parallelism, cache/register blocking, algorithmic prefetching, loop unrolling, and algorithmic restructuring. The architectural features of the POWER2 machine that we describe and that lead to high performance are multiple functional units, high bandwidth between registers, cache, and memory, a large number of fixed- and floating-point registers, and a large cache and TLB (translation lookaside buffer). The paper gives two examples that illustrate how the algorithms and architectural features interplay to produce high-performance codes. They are BLAS (basic linear algebra subroutines) and narrow-band matrix routines. These routines are included in ESSL (Engineering and Scientific Subroutine Library); an overview of ESSL is also given in this paper.

keywords:
algorithmic; Algorithmic prefetching; algorithmic restructuring; Algorithmic restructuring; algorithms; and Scientific Subroutine Library; basic linear algebra; Basic linear algebra subroutines; BLAS; cache/register blocking; Cache/register blocking; computations; Engineering; Engineering and Scientific Subroutine Library; ESSL; floating-point registers; Floating-point registers; functional parallelism; Functional parallelism; high-performance codes; High-performance codes; high-performance numerical; High-performance numerical algorithms; IBM computers; loop unrolling; Loop unrolling; mathematics computing; multiple functional units; Multiple functional units; narrow-band matrix routines; Narrow-band matrix routines; numerically intensive; Numerically intensive computations; parallel algorithms; POWER2 workstations; prefetching; processors; reduced instruction set computing; RISC; RISC processors; RS/6000 family; software libraries; subroutines; translation lookaside buffer; Translation lookaside buffer; workstations

classcodes:
C7310 (Mathematics computing); C5430 (Microcomputers); C6140B (Machine-oriented languages); C6110P (Parallel programming)

thesaurus:
IBM computers; Mathematics computing; Parallel algorithms; Reduced instruction set computing; Software libraries; Workstations

rawabstract:
We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine --- in this case, the new POWER2* machines from the RS\slash 6000 family of RISC processors. The algorithmic features that we emphasize are functional parallelism, cache/register blocking, algorithmic prefetching, loop unrolling, and algorithmic restructuring. The architectural features of the POWER2 machine that we describe and that lead to high performance are multiple functional units, high bandwidth between registers, cache, and memory, a large number of fixed- and floating-point registers, and a large cache and TLB (translation lookaside buffer). The paper gives two examples that illustrate how the algorithms and architectural features interplay to produce high-performance codes. They are BLAS (basic linear algebra subroutines) and narrow-band matrix routines. These routines are included in ESSL (Engineering and Scientific Subroutine Library); an overview of ESSL is also given in this paper.

entry:
@Article{Agarwal:1994:EFP,
  author =       "R. C. Agarwal and F. G. Gustavson and M. Zubair",
  title =        "Exploiting functional parallelism of {POWER2} to
                 design high-performance numerical algorithms",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "563--576",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#eight",
  abstract =     "We describe the algorithms and architecture approach
                 to produce high-performance codes for numerically
                 intensive computations. In this approach, for a given
                 computation, we design algorithms so that they perform
                 optimally when run on a target machine --- in this
                 case, the new POWER2* machines from the RS\slash 6000
                 family of RISC processors. The algorithmic features
                 that we emphasize are functional parallelism,
                 cache/register blocking, algorithmic prefetching, loop
                 unrolling, and algorithmic restructuring. The
                 architectural features of the POWER2 machine that we
                 describe and that lead to high performance are multiple
                 functional units, high bandwidth between registers,
                 cache, and memory, a large number of fixed- and
                 floating-point registers, and a large cache and TLB
                 (translation lookaside buffer). The paper gives two
                 examples that illustrate how the algorithms and
                 architectural features interplay to produce
                 high-performance codes. They are BLAS (basic linear
                 algebra subroutines) and narrow-band matrix routines.
                 These routines are included in ESSL (Engineering and
                 Scientific Subroutine Library); an overview of ESSL is
                 also given in this paper.",
  acknowledgement = ack-nhfb,
  affiliation =  "Res. Div., IBM Thomas J. Watson Res. Center, Yorktown
                 Heights, NY, USA",
  classcodes =   "C7310 (Mathematics computing); C5430 (Microcomputers);
                 C6140B (Machine-oriented languages); C6110P (Parallel
                 programming)",
  classification = "C5430 (Microcomputers); C6110P (Parallel
                 programming); C6140B (Machine-oriented languages);
                 C7310 (Mathematics computing)",
  corpsource =   "Res. Div., IBM Thomas J. Watson Res. Center, Yorktown
                 Heights, NY, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "algorithmic; Algorithmic prefetching; algorithmic
                 restructuring; Algorithmic restructuring; algorithms;
                 and Scientific Subroutine Library; basic linear
                 algebra; Basic linear algebra subroutines; BLAS;
                 cache/register blocking; Cache/register blocking;
                 computations; Engineering; Engineering and Scientific
                 Subroutine Library; ESSL; floating-point registers;
                 Floating-point registers; functional parallelism;
                 Functional parallelism; high-performance codes;
                 High-performance codes; high-performance numerical;
                 High-performance numerical algorithms; IBM computers;
                 loop unrolling; Loop unrolling; mathematics computing;
                 multiple functional units; Multiple functional units;
                 narrow-band matrix routines; Narrow-band matrix
                 routines; numerically intensive; Numerically intensive
                 computations; parallel algorithms; POWER2 workstations;
                 prefetching; processors; reduced instruction set
                 computing; RISC; RISC processors; RS/6000 family;
                 software libraries; subroutines; translation lookaside
                 buffer; Translation lookaside buffer; workstations",
  thesaurus =    "IBM computers; Mathematics computing; Parallel
                 algorithms; Reduced instruction set computing; Software
                 libraries; Workstations",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1994:C
author: Anonymous
title: Corrigenda
journal: j-TOMS
volume: 20
number: 4
pages: 553--553
month: dec
monthnumber: 12
year: 1994
CODEN: ACMSCU
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Mar 14 16:17:03 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.03.14 16:17:03 ???
note: See cite Hull:1994:ICE
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-rfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: Anonymous
rawnote: See \cite{Hull:1994:ICE}
rawtitle: Corrigenda
entry:
@Article{Anonymous:1994:C,
  author =       "Anonymous",
  title =        "Corrigenda",
  journal =      j-TOMS,
  volume =       "20",
  number =       "4",
  pages =        "553--553",
  month =        dec,
  year =         "1994",
  CODEN =        "ACMSCU",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Mar 14 16:17:03 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Hull:1994:ICE}",
  acknowledgement = ack-rfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  xxURL =        "Missing from ACM Digital Library",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1994:FPa
author: Anonymous
title: Floating Point
journal: j-COMPUT-AIDED-ENG
volume: 13
number: 6
pages: 65--??
month: jun
monthnumber: 6
year: 1994
CODEN: CCAEDJ
ISSN: 0733-3536 (print), 2162-1365 (electronic) OR 07333536 (print), 21621365 (electronic)
ISSNL: 0733-3536 OR 07333536
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
abstract: Interactive Analysis Presentations.
fjournal: Computer-aided engineering: CAE
acknowledgement: ack-nhfb
rawabstract: Interactive Analysis Presentations.
rawauthor: Anonymous
rawtitle: Floating Point
entry:
@Article{Anonymous:1994:FPa,
  author =       "Anonymous",
  title =        "Floating Point",
  journal =      j-COMPUT-AIDED-ENG,
  volume =       "13",
  number =       "6",
  pages =        "65--??",
  month =        jun,
  year =         "1994",
  CODEN =        "CCAEDJ",
  ISSN =         "0733-3536 (print), 2162-1365 (electronic)",
  ISSN-L =       "0733-3536",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Interactive Analysis Presentations.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer-aided engineering: CAE",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1994:FPb
author: Anonymous
title: Floating Point
journal: j-COMPUT-AIDED-ENG
volume: 13
number: 7
pages: 85--??
month: jul
monthnumber: 7
year: 1994
CODEN: CCAEDJ
ISSN: 0733-3536 (print), 2162-1365 (electronic) OR 07333536 (print), 21621365 (electronic)
ISSNL: 0733-3536 OR 07333536
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
abstract: The Misplaced Value of CE.
fjournal: Computer-aided engineering: CAE
acknowledgement: ack-nhfb
rawabstract: The Misplaced Value of CE.
rawauthor: Anonymous
rawtitle: Floating Point
entry:
@Article{Anonymous:1994:FPb,
  author =       "Anonymous",
  title =        "Floating Point",
  journal =      j-COMPUT-AIDED-ENG,
  volume =       "13",
  number =       "7",
  pages =        "85--??",
  month =        jul,
  year =         "1994",
  CODEN =        "CCAEDJ",
  ISSN =         "0733-3536 (print), 2162-1365 (electronic)",
  ISSN-L =       "0733-3536",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Misplaced Value of CE.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer-aided engineering: CAE",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1994:FPc
author: Anonymous
title: Floating Point
journal: j-COMPUT-AIDED-ENG
volume: 13
number: 10
pages: 122--??
month: oct
monthnumber: 10
year: 1994
CODEN: CCAEDJ
ISSN: 0733-3536 (print), 2162-1365 (electronic) OR 07333536 (print), 21621365 (electronic)
ISSNL: 0733-3536 OR 07333536
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
abstract: Integration's Relational Dimension.
fjournal: Computer-aided engineering: CAE
acknowledgement: ack-nhfb
rawabstract: Integration's Relational Dimension.
rawauthor: Anonymous
rawtitle: Floating Point
entry:
@Article{Anonymous:1994:FPc,
  author =       "Anonymous",
  title =        "Floating Point",
  journal =      j-COMPUT-AIDED-ENG,
  volume =       "13",
  number =       "10",
  pages =        "122--??",
  month =        oct,
  year =         "1994",
  CODEN =        "CCAEDJ",
  ISSN =         "0733-3536 (print), 2162-1365 (electronic)",
  ISSN-L =       "0733-3536",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Integration's Relational Dimension.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer-aided engineering: CAE",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1994:SCSa
author: Anonymous
journal: New electronics
volume: 27
number: 4
pages: 7--??
day: 1
month: apr
monthnumber: 4
year: 1994
ISSN: 0047-9624 OR 00479624
bibdate: Fri Aug 23 08:32:16 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; UnCover library database
bibtimestamp: 1996.08.23 08:32:16 MDT
acknowledgement: ack-nhfb
rawauthor: Anonymous
title:
Single chip supercomputer: Vector processing is key to high performance in floating point calculations

rawtitle:
Single chip supercomputer: Vector processing is key to high performance in floating point calculations

entry:
@Article{Anonymous:1994:SCSa,
  author =       "Anonymous",
  title =        "Single chip supercomputer: Vector processing is key to
                 high performance in floating point calculations",
  journal =      "New electronics",
  volume =       "27",
  number =       "4",
  pages =        "7--??",
  day =          "1",
  month =        apr,
  year =         "1994",
  ISSN =         "0047-9624",
  bibdate =      "Fri Aug 23 08:32:16 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover library database",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Anonymous:1994:SPF
author: Anonymous
title: Signal Path: Floating-point tactics
journal: j-ELECTRONIC-ENG-TIMES
number: 807
pages: 78--??
month: jul
monthnumber: 7
year: 1994
ISSN: 0192-1541 OR 01921541
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Electronic engineering times
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Signal Path: Floating-point tactics
entry:
@Article{Anonymous:1994:SPF,
  author =       "Anonymous",
  title =        "Signal Path: Floating-point tactics",
  journal =      j-ELECTRONIC-ENG-TIMES,
  volume =       "??",
  number =       "807",
  pages =        "78--??",
  month =        jul,
  year =         "1994",
  ISSN =         "0192-1541",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronic engineering times",
}


bibtype: book
filename: fparith.bib
label: Anonymous:1994:SRT
author: Anonymous
title: The Square Root of Two to 5 million digits
volume: 129
publisher: pub-PROJECT-GUTENBERG
address: pub-PROJECT-GUTENBERG:adr
pages: 78--??
year: 1994
bibdate: Sun Jan 24 10:00:27 MST 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.01.24 10:00:27 MST
series: ser-PROJECT-GUTENBERG
URL: ftp://uiarchive.cso.uiuc.edu/pub/etext/gutenberg/etext94/2sqrt10a.zip
subject: Mathematical constants.
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: The Square Root of Two to 5 million digits
entry:
@Book{Anonymous:1994:SRT,
  author =       "Anonymous",
  title =        "The Square Root of Two to 5 million digits",
  volume =       "129",
  publisher =    pub-PROJECT-GUTENBERG,
  address =      pub-PROJECT-GUTENBERG:adr,
  year =         "1994",
  bibdate =      "Sun Jan 24 10:00:27 MST 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-PROJECT-GUTENBERG,
  URL =          "ftp://uiarchive.cso.uiuc.edu/pub/etext/gutenberg/etext94/2sqrt10a.zip",
  acknowledgement = ack-nhfb # " and " # ack-st,
  subject =      "Mathematical constants.",
  url-contents = "ZIP",
}


bibtype: book
filename: fparith.bib
label: Apple:1994:IMP
author: Apple Computers, Inc.
title: Inside Macintosh: PowerPC Numerics
publisher: pub-AW
address: pub-AW:adr
pages: xx + 300
year: 1994
ISBN: 0-201-40728-0 OR 0201407280
ISBN13: 978-0-201-40728-0 OR 9780201407280
LCCN: QA76.8.M3 I5622 1994
bibdate: Wed Sep 07 21:08:51 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 21:08:51 ???
acknowledgement: ack-nj
rawauthor: {Apple Computers, Inc.}
rawtitle: Inside {Macintosh}: {PowerPC Numerics}
entry:
@Book{Apple:1994:IMP,
  author =       "{Apple Computers, Inc.}",
  title =        "Inside {Macintosh}: {PowerPC Numerics}",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xx + 300",
  year =         "1994",
  ISBN =         "0-201-40728-0",
  ISBN-13 =      "978-0-201-40728-0",
  LCCN =         "QA76.8.M3 I5622 1994",
  bibdate =      "Wed Sep 07 21:08:51 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$28.95",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Bajard:1994:BNH
author: J.-C. Bajard and S. Kla and Jean-Michel Muller
title: BKM: a New Hardware Algorithm for Complex Elementary Functions
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 955--963
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295857
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J.-C. Bajard and S. Kla and Jean-Michel Muller
rawtitle: {BKM}: a New Hardware Algorithm for Complex Elementary Functions
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{Bajard:1994:BNH,
  author =       "J.-C. Bajard and S. Kla and Jean-Michel Muller",
  title =        "{BKM}: a New Hardware Algorithm for Complex Elementary
                 Functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "955--963",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295857",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Bajard:1994:SOL
author: J.-C. Bajard and J. Duprat and S. Kla and J.-M. Muller
title: Some Operators for On-Line Radix-2 Computations
journal: j-J-PAR-DIST-COMP
volume: 22
number: 2
pages: 336--345
month: aug
monthnumber: 8
year: 1994
CODEN: JPDCER
DOI: https://doi.org/10.1006/jpdc.1994.1093
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Thu Mar 9 09:18:55 MST 2000
bibtimestamp: 2000.03.09 09:18:55 MST
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Lab. LIP, Ecole Normale Superieure de Lyon, France
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: P Practical
rawauthor: J.-C. Bajard and J. Duprat and S. Kla and J.-M. Muller
rawtitle: Some Operators for On-Line Radix-2 Computations
bibsource:
http://www.idealibrary.com/servlet/useragent?func=showAllIssues&curIssueID=jpdc; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1093/production; http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1093/production/pdf

keywords:
bit-level representation; Borrow-Save; delay; digital arithmetic; online radix-2 computations; operators; optimal online; radix-2 digits; representation

entry:
@Article{Bajard:1994:SOL,
  author =       "J.-C. Bajard and J. Duprat and S. Kla and J.-M.
                 Muller",
  title =        "Some Operators for On-Line Radix-2 Computations",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "22",
  number =       "2",
  pages =        "336--345",
  month =        aug,
  year =         "1994",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1006/jpdc.1994.1093",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Thu Mar 9 09:18:55 MST 2000",
  bibsource =    "http://www.idealibrary.com/servlet/useragent?func=showAllIssues&curIssueID=jpdc;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1093/production;
                 http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1093/production/pdf",
  acknowledgement = ack-nhfb,
  classification = "C5230 (Digital arithmetic methods)",
  corpsource =   "Lab. LIP, Ecole Normale Superieure de Lyon, France",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "bit-level representation; Borrow-Save; delay; digital
                 arithmetic; online radix-2 computations; operators;
                 optimal online; radix-2 digits; representation",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Barsi:1994:TOM
author: Ferruccio Barsi and M. Cristina Pinotti
title: Time optimal mixed radix conversion for residue number applications
journal: j-COMP-J
volume: 37
number: 10
pages: 907--916
year: 1994
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Jul 21 09:54:19 MDT 1999
bibtimestamp: 1999.07.21 09:54:19 MDT
URL: http://www3.oup.co.uk/computer_journal/Volume_37/Issue_10/Vol37_10.body.html#AbstractBarsi
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Dipartimento di Matematica, Perugia University, Italy
corpsource: Dipartimento di Matematica, Perugia University, Italy
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Computational complexity; Residue number systems; Table lookup; VLSI
treatment: P Practical
rawauthor: Ferruccio Barsi and M. Cristina Pinotti
rawtitle: Time optimal mixed radix conversion for residue number applications
bibsource:
http://www3.oup.co.uk/computer_journal/Volume_37/Issue_10/Vol37_10.index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
applications; asymptotic conversion time; Chinese Remainder Theorem; computational complexity; constructive VLSI design; Constructive VLSI design; conventional logic; Conventional logic; logic circuitry; Logic circuitry; lookup; lookup table implementations; Lookup table implementations; mixed radix; Mixed radix notation; notation; practical ECL IC; Practical ECL IC; residue integer conversion; Residue integer conversion; residue number; Residue number applications; residue number systems; residue-to-weighted system; Residue-to-weighted system asymptotic conversion time; table; time optimal mixed radix conversion; Time optimal mixed radix conversion; VLSI

classcodes:
B2570 (Semiconductor integrated circuits); C5230 (Digital arithmetic methods); C6130 (Data handling techniques); C4240C (Computational complexity)

entry:
@Article{Barsi:1994:TOM,
  author =       "Ferruccio Barsi and M. Cristina Pinotti",
  title =        "Time optimal mixed radix conversion for residue number
                 applications",
  journal =      j-COMP-J,
  volume =       "37",
  number =       "10",
  pages =        "907--916",
  month =        "????",
  year =         "1994",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Jul 21 09:54:19 MDT 1999",
  bibsource =    "http://www3.oup.co.uk/computer_journal/Volume_37/Issue_10/Vol37_10.index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/Volume_37/Issue_10/Vol37_10.body.html#AbstractBarsi",
  acknowledgement = ack-nhfb,
  affiliation =  "Dipartimento di Matematica, Perugia University,
                 Italy",
  author-1-adr = "Dipartimento at Matematica, Universita di Perugia, Via
                 Vanvitelli, 061OO Perugia, Italy",
  author-2-adr = "Istituto di Elaborazione dell'Informazione del CNR,
                 Via S. Maria 46, 56100 Pisa, Italy",
  classcodes =   "B2570 (Semiconductor integrated circuits); C5230
                 (Digital arithmetic methods); C6130 (Data handling
                 techniques); C4240C (Computational complexity)",
  classification = "B2570 (Semiconductor integrated circuits); C4240C
                 (Computational complexity); C5230 (Digital arithmetic
                 methods); C6130 (Data handling techniques)",
  corpsource =   "Dipartimento di Matematica, Perugia University,
                 Italy",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "applications; asymptotic conversion time; Chinese
                 Remainder Theorem; computational complexity;
                 constructive VLSI design; Constructive VLSI design;
                 conventional logic; Conventional logic; logic
                 circuitry; Logic circuitry; lookup; lookup table
                 implementations; Lookup table implementations; mixed
                 radix; Mixed radix notation; notation; practical ECL
                 IC; Practical ECL IC; residue integer conversion;
                 Residue integer conversion; residue number; Residue
                 number applications; residue number systems;
                 residue-to-weighted system; Residue-to-weighted system
                 asymptotic conversion time; table; time optimal mixed
                 radix conversion; Time optimal mixed radix conversion;
                 VLSI",
  thesaurus =    "Computational complexity; Residue number systems;
                 Table lookup; VLSI",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Bartolucci:1994:REC
author: M. Bartolucci and G. R. Sechi
journal: j-MICROPROC-MICROPROG
volume: 40
number: 10-12
pages: 833--839
month: dec
monthnumber: 12
year: 1994
CODEN: MMICDT
ISSN: 0165-6074 (print), 1878-7061 (electronic) OR 01656074 (print), 18787061 (electronic)
ISSNL: 0165-6074 OR 01656074
bibdate: Thu Dec 14 15:33:45 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 15:33:45 ???
note: 20th Annual Euromicro Conference. System Architecture and Integration.
fjournal: Microprocessing and Microprogramming
acknowledgement: ack-nhfb
affiliation: Istituto di Fisica Cosmica e Tecnologie Relative, CNR, Milano, Italy
journalURL: https://www.sciencedirect.com/journal/microprocessing-and-microprogramming/issues
thesaurus: Algebra; Error detection; Floating point arithmetic; Roundoff errors
rawauthor: M. Bartolucci and G. R. Sechi
rawnote: 20th Annual Euromicro Conference. System Architecture and Integration.
title:
Rounding error in the computation of opposite sign floating point number parametric addition: a case study

abstract:
Presents a study about rounding errors arising in the addition of opposite-sign floating-point operands. The algebraic study of the adder functionalities provides the possibility of modifying the hardware in order to measure the rounding error effect in terms of error size and incoming rate.

keywords:
Adder functionalities; Algebraic properties; Case study; Computational units; Error size; Errors detection; Errors elimination; Floating-point operands; Hardware modification; High-speed floating point operators; Incoming rate; Opposite-sign floating-point number parametric addition; Real time applications; Rounding error

rawabstract:
Presents a study about rounding errors arising in the addition of opposite-sign floating-point operands. The algebraic study of the adder functionalities provides the possibility of modifying the hardware in order to measure the rounding error effect in terms of error size and incoming rate.

rawtitle:
Rounding error in the computation of opposite sign floating point number parametric addition: a case study

entry:
@Article{Bartolucci:1994:REC,
  author =       "M. Bartolucci and G. R. Sechi",
  title =        "Rounding error in the computation of opposite sign
                 floating point number parametric addition: a case
                 study",
  journal =      j-MICROPROC-MICROPROG,
  volume =       "40",
  number =       "10-12",
  pages =        "833--839",
  month =        dec,
  year =         "1994",
  CODEN =        "MMICDT",
  ISSN =         "0165-6074 (print), 1878-7061 (electronic)",
  ISSN-L =       "0165-6074",
  bibdate =      "Thu Dec 14 15:33:45 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "20th Annual Euromicro Conference. System Architecture
                 and Integration.",
  abstract =     "Presents a study about rounding errors arising in the
                 addition of opposite-sign floating-point operands. The
                 algebraic study of the adder functionalities provides
                 the possibility of modifying the hardware in order to
                 measure the rounding error effect in terms of error
                 size and incoming rate.",
  acknowledgement = ack-nhfb,
  affiliation =  "Istituto di Fisica Cosmica e Tecnologie Relative, CNR,
                 Milano, Italy",
  classification = "C1110 (Algebra); C5230 (Digital arithmetic
                 methods)",
  confdate =     "Sept. 1994",
  conflocation = "Liverpool, UK",
  fjournal =     "Microprocessing and Microprogramming",
  journal-URL =  "https://www.sciencedirect.com/journal/microprocessing-and-microprogramming/issues",
  keywords =     "Adder functionalities; Algebraic properties; Case
                 study; Computational units; Error size; Errors
                 detection; Errors elimination; Floating-point operands;
                 Hardware modification; High-speed floating point
                 operators; Incoming rate; Opposite-sign floating-point
                 number parametric addition; Real time applications;
                 Rounding error",
  pubcountry =   "Netherlands",
  thesaurus =    "Algebra; Error detection; Floating point arithmetic;
                 Roundoff errors",
}


bibtype: article
filename: fparith.bib
label: Bauer:1994:MDS
author: F. L. Bauer
title: Multiplication and dual system
journal: j-INFORMATIK-SPEKTRUM
volume: 17
number: 4
pages: 245--250
month: aug
monthnumber: 8
year: 1994
CODEN: INSKDW
ISSN: 0170-6012 (print), 1432-122X (electronic) OR 01706012 (print), 1432122X (electronic)
ISSNL: 0170-6012 OR 01706012
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Informatik Spektrum
language: German
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/287
thesaurus: Digital arithmetic; History; Multiplying circuits
rawauthor: F. L. Bauer
rawtitle: Multiplication and dual system
abstract:
A history of methods of multiplication is introduced with a table showing the assignments of Greek and Hebrew letters to the units, tens and hundreds up to 900, with no zero. The ancient Egyptian method using decimal-to-binary conversion with addition of successive even multiples of the multiplicand is explained. Napier's (1617) method of `numeri locales' is described with the aid of a multiplication table for algebraic symbols each representing a different power of 2. The application of these principles in electronic computing circuits is discussed with reference to Braun's (1963) full-adder correction circuit and Wallace's (1964) cascaded half-adders. Progress from the 8*8 field multiplier chips of 1971 to the floating-point 1.2 mu m CMOS 56*56 RISC multiplier of 1989 is summarised.

keywords:
Algebraic symbols; Cascaded half-adders; decimal floating-point arithmetic; Decimal-to-binary conversion; Egyptian method; Electronic computing circuits; Floating-point; Full-adder correction circuit; Multiplication; Multiplier chips; Numeri locales; RISC

rawabstract:
A history of methods of multiplication is introduced with a table showing the assignments of Greek and Hebrew letters to the units, tens and hundreds up to 900, with no zero. The ancient Egyptian method using decimal-to-binary conversion with addition of successive even multiples of the multiplicand is explained. Napier's (1617) method of `numeri locales' is described with the aid of a multiplication table for algebraic symbols each representing a different power of 2. The application of these principles in electronic computing circuits is discussed with reference to Braun's (1963) full-adder correction circuit and Wallace's (1964) cascaded half-adders. Progress from the 8*8 field multiplier chips of 1971 to the floating-point 1.2 mu m CMOS 56*56 RISC multiplier of 1989 is summarised.

entry:
@Article{Bauer:1994:MDS,
  author =       "F. L. Bauer",
  title =        "Multiplication and dual system",
  journal =      j-INFORMATIK-SPEKTRUM,
  volume =       "17",
  number =       "4",
  pages =        "245--250",
  month =        aug,
  year =         "1994",
  CODEN =        "INSKDW",
  ISSN =         "0170-6012 (print), 1432-122X (electronic)",
  ISSN-L =       "0170-6012",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A history of methods of multiplication is introduced
                 with a table showing the assignments of Greek and
                 Hebrew letters to the units, tens and hundreds up to
                 900, with no zero. The ancient Egyptian method using
                 decimal-to-binary conversion with addition of
                 successive even multiples of the multiplicand is
                 explained. Napier's (1617) method of `numeri locales'
                 is described with the aid of a multiplication table for
                 algebraic symbols each representing a different power
                 of 2. The application of these principles in electronic
                 computing circuits is discussed with reference to
                 Braun's (1963) full-adder correction circuit and
                 Wallace's (1964) cascaded half-adders. Progress from
                 the 8*8 field multiplier chips of 1971 to the
                 floating-point 1.2 mu m CMOS 56*56 RISC multiplier of
                 1989 is summarised.",
  acknowledgement = ack-nhfb,
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "Informatik Spektrum",
  journal-URL =  "http://link.springer.com/journal/287",
  keywords =     "Algebraic symbols; Cascaded half-adders; decimal
                 floating-point arithmetic; Decimal-to-binary
                 conversion; Egyptian method; Electronic computing
                 circuits; Floating-point; Full-adder correction
                 circuit; Multiplication; Multiplier chips; Numeri
                 locales; RISC",
  language =     "German",
  pubcountry =   "Germany",
  thesaurus =    "Digital arithmetic; History; Multiplying circuits",
}


bibtype: phdthesis
filename: fparith.bib
label: Bewick:1994:FMA
author: Gary Bewick
title: Fast Multiplication: Algorithms and Implementations
type: Ph.D. thesis
school: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: 170
month: feb
monthnumber: 2
year: 1994
bibdate: Mon Dec 24 09:59:22 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.12.24 09:59:22 ???
note: Also issued as report CSL-TR-94-617
acknowledgement: ack-nhfb
rawauthor: Gary Bewick
rawnote: Also issued as report CSL-TR-94-617
rawtitle: Fast Multiplication: Algorithms and Implementations
entry:
@PhdThesis{Bewick:1994:FMA,
  author =       "Gary Bewick",
  title =        "Fast Multiplication: Algorithms and Implementations",
  type =         "{Ph.D.} thesis",
  school =       "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  pages =        "170",
  month =        feb,
  year =         "1994",
  bibdate =      "Mon Dec 24 09:59:22 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Also issued as report CSL-TR-94-617",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: BrinchHansen:1994:MLD
author: Per Brinch Hansen
title: Multiple-length Division Revisited: a Tour of the Minefield
journal: j-SPE
volume: 24
number: 6
pages: 579--601
month: jun
monthnumber: 6
year: 1994
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.4380240605
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Fri Nov 28 17:07:54 2003
bibtimestamp: 2003.11.28 17:07:54 ???
URL: http://brinch-hansen.net/papers/1994b.pdf
fjournal: Software --- Practice and Experience
keywords: algorithms; multiple-length integer division
acknowledgement: ack-nj
ajournal: Softw. Pract. Exp.
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 30 Oct 2006
rawauthor: Per {Brinch Hansen}
rawtitle: Multiple-length Division Revisited: a Tour of the Minefield
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/bibnet/authors/h/hansen-per-brinch.bib; https://www.math.utah.edu/pub/tex/bib/cryptography1990.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/litprog.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

note:
This paper derives an algorithm for division of long integers, and implements it as a literate program, although without identifier cross-references. See also related work on division cite BrinchHansen:1995:LDA,Regener:1984:MID .

abstract:
Long division of natural numbers plays a crucial role in Cobol arithmetic, cryptography, and primality testing. Only a handful of textbooks discuss the theory and practice of long division, and none of them do it satisfactorily. This tutorial attempts to fill this surprising gap in the literature on computer algorithms. We illustrate the subtleties of long division by examples, define the problem concisely, summarize the theory, and develop a complete Pascal algorithm using a consistent terminology.

rawabstract:
Long division of natural numbers plays a crucial role in Cobol arithmetic, cryptography, and primality testing. Only a handful of textbooks discuss the theory and practice of long division, and none of them do it satisfactorily. This tutorial attempts to fill this surprising gap in the literature on computer algorithms. We illustrate the subtleties of long division by examples, define the problem concisely, summarize the theory, and develop a complete Pascal algorithm using a consistent terminology.

rawnote:
This paper derives an algorithm for division of long integers, and implements it as a literate program, although without identifier cross-references. See also related work on division \cite{BrinchHansen:1995:LDA,Regener:1984:MID} .

entry:
@Article{BrinchHansen:1994:MLD,
  author =       "Per {Brinch Hansen}",
  title =        "Multiple-length Division Revisited: a Tour of the
                 Minefield",
  journal =      j-SPE,
  volume =       "24",
  number =       "6",
  pages =        "579--601",
  month =        jun,
  year =         "1994",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.4380240605",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Fri Nov 28 17:07:54 2003",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/bibnet/authors/h/hansen-per-brinch.bib;
                 https://www.math.utah.edu/pub/tex/bib/cryptography1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/litprog.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "This paper derives an algorithm for division of long
                 integers, and implements it as a literate program,
                 although without identifier cross-references. See also
                 related work on division
                 \cite{BrinchHansen:1995:LDA,Regener:1984:MID} .",
  URL =          "http://brinch-hansen.net/papers/1994b.pdf",
  abstract =     "Long division of natural numbers plays a crucial role
                 in Cobol arithmetic, cryptography, and primality
                 testing. Only a handful of textbooks discuss the theory
                 and practice of long division, and none of them do it
                 satisfactorily. This tutorial attempts to fill this
                 surprising gap in the literature on computer
                 algorithms. We illustrate the subtleties of long
                 division by examples, define the problem concisely,
                 summarize the theory, and develop a complete Pascal
                 algorithm using a consistent terminology.",
  acknowledgement = ack-nj # " and " # ack-mfc # " and " # ack-nhfb,
  ajournal =     "Softw. Pract. Exp.",
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "algorithms; multiple-length integer division",
  onlinedate =   "30 Oct 2006",
}


bibtype: inproceedings
filename: fparith.bib
label: Brosgol:1994:ISD
author: Benjamin M. Brosgol and Robert I. Eachus and David E. Emery
title: Information Systems Development in Ada
crossref: ACM:1994:AAW
pages: 2--16
year: 1994
bibdate: Fri Nov 28 16:05:55 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 16:05:55 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-mfc
rawauthor: Benjamin M. Brosgol and Robert I. Eachus and David E. Emery
rawtitle: Information Systems Development in {Ada}
abstract:
In this paper we survey how to use Ada (both Ada 83 and Ada 9X) for IS applications, with a focus on two principal issues: Specification of the information architecture of an IS application, and Programming techniques relevant to financial and related applications.par We cover both the language features and the supplemental packages for IS development. Special attention will be paid to the Ada Decimal-Associated Reusabilia (`ADAR') components for Ada 83 and transitioning to Ada 9X.

rawabstract:
In this paper we survey how to use Ada (both Ada 83 and Ada 9X) for IS applications, with a focus on two principal issues: Specification of the information architecture of an IS application, and Programming techniques relevant to financial and related applications.\par We cover both the language features and the supplemental packages for IS development. Special attention will be paid to the Ada Decimal-Associated Reusabilia (`ADAR') components for Ada 83 and transitioning to Ada 9X.

entry:
@InProceedings{Brosgol:1994:ISD,
  author =       "Benjamin M. Brosgol and Robert I. Eachus and David E.
                 Emery",
  title =        "Information Systems Development in {Ada}",
  crossref =     "ACM:1994:AAW",
  pages =        "2--16",
  year =         "1994",
  bibdate =      "Fri Nov 28 16:05:55 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we survey how to use Ada (both Ada 83
                 and Ada 9X) for IS applications, with a focus on two
                 principal issues: Specification of the information
                 architecture of an IS application, and Programming
                 techniques relevant to financial and related
                 applications.\par

                 We cover both the language features and the
                 supplemental packages for IS development. Special
                 attention will be paid to the Ada Decimal-Associated
                 Reusabilia (`ADAR') components for Ada 83 and
                 transitioning to Ada 9X.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: mastersthesis
filename: fparith.bib
label: Bull:1994:SFF
author: Nathan Lee Bull
title: A study of frequency-sampling filters realized on floating-point digital signal processors
type: Thesis (M.S.)
school: University of Tennessee, Knoxville
address: Knoxville, TN, USA
pages: vii + 56
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital filters (Mathematics)
acknowledgement: ack-nhfb
rawauthor: Nathan Lee Bull
rawtitle: A study of frequency-sampling filters realized on floating-point digital signal processors
entry:
@MastersThesis{Bull:1994:SFF,
  author =       "Nathan Lee Bull",
  title =        "A study of frequency-sampling filters realized on
                 floating-point digital signal processors",
  type =         "Thesis ({M.S.})",
  school =       "University of Tennessee, Knoxville",
  address =      "Knoxville, TN, USA",
  pages =        "vii + 56",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics)",
}


bibtype: article
filename: fparith.bib
label: Carr:1994:IRM
author: S. Carr and K. Kennedy
title: Improving the Ratio of Memory Operations in Floating-Point Operations in Loops
journal: j-TOPLAS
volume: 16
number: 6
pages: 1768--1810
month: nov
monthnumber: 11
year: 1994
CODEN: ATPSDT
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Michigan Technol. University, Houghton, MI, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawauthor: S. Carr and K. Kennedy
rawtitle: Improving the Ratio of Memory Operations in Floating-Point Operations in Loops
abstract:
Over the past decade, microprocessor design strategies have focused on increasing the computational power on a single chip. Because computations often require more data from cache per floating-point operation than a machine can deliver and because operations are pipelined, idle computational cycles are common when scientific applications are executed. To overcome these bottlenecks, programmers have learned to use a coding style that ensures a better balance between memory references and floating-point operations. In our view, this is a step in the wrong direction because it makes programs more machine-specific. A programmer should not be required to write a new program version for each new machine; instead, the task of specializing a program to a target machine should be left to the compiler. But is our view practical? Can a sophisticated optimizing compiler obviate the need for the myriad of programming tricks that have found their way into practice to improve the performance of the memory hierarchy? In this paper we attempt to answer that question. To do so, we develop and evaluate techniques that automatically restructure program loops to achieve high performance on specific target architectures. These methods attempt to balance computation and memory accesses and seek to eliminate or reduce pipeline interlock. To do this, they estimate statically the balance between memory operations and floating-point operations for each loop in a particular program and use these estimates to determine whether to apply various loop transformations. Experiments with our automatic techniques show that integer-factor speedups are possible on kernels. Additionally, the estimate of the balance between memory operations and computation, and the application of the estimate are very accurate-experiments reveal little difference between the balance achieved by our automatic system and that possible by hand optimization.

keywords:
Bottlenecks; Floating-point operations; Integer-factor speedups; Memory operations; Memory references; Microprocessor design strategies; Pipeline interlock; Program loops; Sophisticated optimizing compiler

thesaurus:
Floating point arithmetic; Optimising compilers; Pipeline processing; Program control structures; Storage management

rawabstract:
Over the past decade, microprocessor design strategies have focused on increasing the computational power on a single chip. Because computations often require more data from cache per floating-point operation than a machine can deliver and because operations are pipelined, idle computational cycles are common when scientific applications are executed. To overcome these bottlenecks, programmers have learned to use a coding style that ensures a better balance between memory references and floating-point operations. In our view, this is a step in the wrong direction because it makes programs more machine-specific. A programmer should not be required to write a new program version for each new machine; instead, the task of specializing a program to a target machine should be left to the compiler. But is our view practical? Can a sophisticated optimizing compiler obviate the need for the myriad of programming tricks that have found their way into practice to improve the performance of the memory hierarchy? In this paper we attempt to answer that question. To do so, we develop and evaluate techniques that automatically restructure program loops to achieve high performance on specific target architectures. These methods attempt to balance computation and memory accesses and seek to eliminate or reduce pipeline interlock. To do this, they estimate statically the balance between memory operations and floating-point operations for each loop in a particular program and use these estimates to determine whether to apply various loop transformations. Experiments with our automatic techniques show that integer-factor speedups are possible on kernels. Additionally, the estimate of the balance between memory operations and computation, and the application of the estimate are very accurate-experiments reveal little difference between the balance achieved by our automatic system and that possible by hand optimization.

entry:
@Article{Carr:1994:IRM,
  author =       "S. Carr and K. Kennedy",
  title =        "Improving the Ratio of Memory Operations in
                 Floating-Point Operations in Loops",
  journal =      j-TOPLAS,
  volume =       "16",
  number =       "6",
  pages =        "1768--1810",
  month =        nov,
  year =         "1994",
  CODEN =        "ATPSDT",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Over the past decade, microprocessor design strategies
                 have focused on increasing the computational power on a
                 single chip. Because computations often require more
                 data from cache per floating-point operation than a
                 machine can deliver and because operations are
                 pipelined, idle computational cycles are common when
                 scientific applications are executed. To overcome these
                 bottlenecks, programmers have learned to use a coding
                 style that ensures a better balance between memory
                 references and floating-point operations. In our view,
                 this is a step in the wrong direction because it makes
                 programs more machine-specific. A programmer should not
                 be required to write a new program version for each new
                 machine; instead, the task of specializing a program to
                 a target machine should be left to the compiler. But is
                 our view practical? Can a sophisticated optimizing
                 compiler obviate the need for the myriad of programming
                 tricks that have found their way into practice to
                 improve the performance of the memory hierarchy? In
                 this paper we attempt to answer that question. To do
                 so, we develop and evaluate techniques that
                 automatically restructure program loops to achieve high
                 performance on specific target architectures. These
                 methods attempt to balance computation and memory
                 accesses and seek to eliminate or reduce pipeline
                 interlock. To do this, they estimate statically the
                 balance between memory operations and floating-point
                 operations for each loop in a particular program and
                 use these estimates to determine whether to apply
                 various loop transformations. Experiments with our
                 automatic techniques show that integer-factor speedups
                 are possible on kernels. Additionally, the estimate of
                 the balance between memory operations and computation,
                 and the application of the estimate are very
                 accurate-experiments reveal little difference between
                 the balance achieved by our automatic system and that
                 possible by hand optimization.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Michigan Technol.
                 University, Houghton, MI, USA",
  classification = "C5230 (Digital arithmetic methods); C6120 (File
                 organisation); C6150C (Compilers, interpreters and
                 other processors)",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
  keywords =     "Bottlenecks; Floating-point operations; Integer-factor
                 speedups; Memory operations; Memory references;
                 Microprocessor design strategies; Pipeline interlock;
                 Program loops; Sophisticated optimizing compiler",
  thesaurus =    "Floating point arithmetic; Optimising compilers;
                 Pipeline processing; Program control structures;
                 Storage management",
}


bibtype: mastersthesis
filename: fparith.bib
label: Chandramouli:1994:DSP
author: V. Chandramouli
title: Design of a self-timed, pipelined, floating point multiplier in gallium arsenide
type: Thesis (M.S.)
school: Department of Computer Science, University of Utah
address: Salt Lake City, UT, USA
pages: xiii + 121
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Computer architecture.; Gallium arsenide semiconductors.
acknowledgement: ack-nhfb
rawauthor: V. Chandramouli
rawtitle: Design of a self-timed, pipelined, floating point multiplier in gallium arsenide
entry:
@MastersThesis{Chandramouli:1994:DSP,
  author =       "V. Chandramouli",
  title =        "Design of a self-timed, pipelined, floating point
                 multiplier in gallium arsenide",
  type =         "Thesis ({M.S.})",
  school =       "Department of Computer Science, University of Utah",
  address =      "Salt Lake City, UT, USA",
  pages =        "xiii + 121",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture.; Gallium arsenide
                 semiconductors.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1994:EDU
author: Sau-Gee Chen and Chieh-Chih Li
title: Efficient designs of unified $2$'s complement division and square root algorithm and architecture
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 943--947
year: 1994
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: Sau-Gee Chen and Chieh-Chih Li
rawtitle: Efficient designs of unified $2$'s complement division and square root algorithm and architecture
booktitle:
Proceedings of TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: `Frontiers of Computer Technology'

rawbooktitle:
Proceedings of {TENCON '94}. {IEEE} Region 10's Ninth Annual International Conference. Theme: `Frontiers of Computer Technology'

entry:
@InProceedings{Chen:1994:EDU,
  author =       "Sau-Gee Chen and Chieh-Chih Li",
  booktitle =    "Proceedings of {TENCON '94}. {IEEE} Region 10's Ninth
                 Annual International Conference. Theme: `Frontiers of
                 Computer Technology'",
  title =        "Efficient designs of unified $2$'s complement division
                 and square root algorithm and architecture",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "943--947",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Efficient unified 2's complement division and square
                 root algorithm, and their architectures are proposed in
                 this work. The designs are high speed, small area and
                 high compatibility. The architectures provide bit level
                 pipelined operation, as well \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chesneaux:1994:ERS
author: J.-M. Chesneaux
title: The equality relations in scientific computing
journal: j-NUMER-ALGORITHMS
volume: 7
number: 2-4
pages: 129--143
month: jul
monthnumber: 7
year: 1994
CODEN: NUALEG
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
affiliation: Laboratoire MASI, Universite Pierre et Marie Curie, Paris, France
journalURL: http://link.springer.com/journal/11075
thesaurus: Digital arithmetic; Mathematics computing; Roundoff errors
rawauthor: J.-M. Chesneaux
rawtitle: The equality relations in scientific computing
abstract:
The equality relation (more generally, the ordering relations) in floating point arithmetic is the exact translation of the mathematical equality relation. Because of the propagation of round-off errors, the floating point arithmetic is not the exact representation of the theoretical arithmetic which is continuous on the real numbers. This leads to some incoherence when the equality concept is used in floating point arithmetic. A well known example is the detection of a zero element in the pivoting column and equation when applying Gaussian elimination, which is almost impossible in floating point arithmetic. The author begins by showing the inadequacy of the equality relation used in floating point arithmetic (the author calls it floating point equality), and then introduces two new concepts stochastic numbers and the equality relation between such numbers which is called the stochastic equality. It is shown how these concepts allow recovery of the coherence between the arithmetic operators and the ordering relations that was missing in floating point computations.

keywords:
Arithmetic operators; Equality relations; Floating point arithmetic; Floating point equality; Gaussian elimination; Ordering relations; Pivoting column; Round-off errors; Scientific computing; Stochastic equality; Stochastic numbers; Zero element

rawabstract:
The equality relation (more generally, the ordering relations) in floating point arithmetic is the exact translation of the mathematical equality relation. Because of the propagation of round-off errors, the floating point arithmetic is not the exact representation of the theoretical arithmetic which is continuous on the real numbers. This leads to some incoherence when the equality concept is used in floating point arithmetic. A well known example is the detection of a zero element in the pivoting column and equation when applying Gaussian elimination, which is almost impossible in floating point arithmetic. The author begins by showing the inadequacy of the equality relation used in floating point arithmetic (the author calls it floating point equality), and then introduces two new concepts stochastic numbers and the equality relation between such numbers which is called the stochastic equality. It is shown how these concepts allow recovery of the coherence between the arithmetic operators and the ordering relations that was missing in floating point computations.

entry:
@Article{Chesneaux:1994:ERS,
  author =       "J.-M. Chesneaux",
  title =        "The equality relations in scientific computing",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "7",
  number =       "2-4",
  pages =        "129--143",
  month =        jul,
  year =         "1994",
  CODEN =        "NUALEG",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The equality relation (more generally, the ordering
                 relations) in floating point arithmetic is the exact
                 translation of the mathematical equality relation.
                 Because of the propagation of round-off errors, the
                 floating point arithmetic is not the exact
                 representation of the theoretical arithmetic which is
                 continuous on the real numbers. This leads to some
                 incoherence when the equality concept is used in
                 floating point arithmetic. A well known example is the
                 detection of a zero element in the pivoting column and
                 equation when applying Gaussian elimination, which is
                 almost impossible in floating point arithmetic. The
                 author begins by showing the inadequacy of the equality
                 relation used in floating point arithmetic (the author
                 calls it floating point equality), and then introduces
                 two new concepts stochastic numbers and the equality
                 relation between such numbers which is called the
                 stochastic equality. It is shown how these concepts
                 allow recovery of the coherence between the arithmetic
                 operators and the ordering relations that was missing
                 in floating point computations.",
  acknowledgement = ack-nhfb,
  affiliation =  "Laboratoire MASI, Universit{\'e} Pierre et Marie
                 Curie, Paris, France",
  classification = "C5230 (Digital arithmetic methods); C7310
                 (Mathematics)",
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  keywords =     "Arithmetic operators; Equality relations; Floating
                 point arithmetic; Floating point equality; Gaussian
                 elimination; Ordering relations; Pivoting column;
                 Round-off errors; Scientific computing; Stochastic
                 equality; Stochastic numbers; Zero element",
  pubcountry =   "Switzerland",
  thesaurus =    "Digital arithmetic; Mathematics computing; Roundoff
                 errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Chren:1994:ALIa
author: W. A. Chren, Jr.
booktitle: Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994
title: Area and latency improvements for direct digital synthesis using the residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 269--273
year: 1994
DOI: https://doi.org/10.1109/MWSCAS.1994.519237
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. A. {Chren, Jr.}
rawbooktitle: Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994
rawtitle: Area and latency improvements for direct digital synthesis using the residue number system
entry:
@InProceedings{Chren:1994:ALIa,
  author =       "W. A. {Chren, Jr.}",
  booktitle =    "Proceedings of the 37th Midwest Symposium on Circuits
                 and Systems, 1994",
  title =        "Area and latency improvements for direct digital
                 synthesis using the residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "269--273",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.1994.519237",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Two residue number system-based direct digital
                 synthesizers are presented. The High-Agility Direct
                 Synthesizer exhibits a frequency switching latency
                 which is reduced by as much as 50\% below that of
                 traditional, binary number system-based designs.
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Chren:1994:ALIb
author: W. A. Chren, Jr.
title: Area and latency improvements for direct digital synthesis using the residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 269--273
year: 1994
DOI: https://doi.org/10.1109/MWSCAS.1994.519237
ISBN: 0-7803-2428-5 OR 0780324285
ISBN13: 978-0-7803-2428-2 OR 9780780324282
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: W. A. {Chren, Jr.}
rawtitle: Area and latency improvements for direct digital synthesis using the residue number system
booktitle:
Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994. 3--5 August 1994, Lafayette, LA, USA

rawbooktitle:
Proceedings of the 37th Midwest Symposium on Circuits and Systems, 1994. 3--5 August 1994, Lafayette, {LA}, {USA}

entry:
@InProceedings{Chren:1994:ALIb,
  author =       "W. A. {Chren, Jr.}",
  booktitle =    "Proceedings of the 37th Midwest Symposium on Circuits
                 and Systems, 1994. 3--5 August 1994, Lafayette, {LA},
                 {USA}",
  title =        "Area and latency improvements for direct digital
                 synthesis using the residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "269--273",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.1994.519237",
  ISBN =         "0-7803-2428-5",
  ISBN-13 =      "978-0-7803-2428-2",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Two residue number system-based direct digital
                 synthesizers are presented. The High-Agility Direct
                 Synthesizer exhibits a frequency switching latency
                 which is reduced by as much as 50\% below that of
                 traditional, binary number system-based designs. The
                 Reduced Area Direct Synthesizer has a chip area which
                 is reduced by more than 40\%. The area reduction is due
                 primarily to the decomposition of the sine ROM into
                 several small look-up tables, while the latency
                 reduction is due to the shortening of the carry paths
                 in the phase accumulator",
}


bibtype: incollection
filename: fparith.bib
label: Clarke:1994:RAC
author: C. T. Clarke and G. R. Nudd
title: A redundant arithmetic CORDIC system with a unit scale factor
publisher: Oxford: Clarendon Press
pages: 63--71
year: 1994
ISBN: 0-19-853480-9 OR 0198534809
ISBN13: 978-0-19-853480-8 OR 9780198534808
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
keywords: 65T40,65D20,33B10
ZMnumber: 0852.65141
acknowledgement: ack-nhfb
rawauthor: C. T. Clarke and G. R. Nudd
rawtitle: A redundant arithmetic {CORDIC} system with a unit scale factor
booktitle:
Mathematics in signal processing III. Based on the proceedings of the third IMA conference on signal processing, University of Warwick, Coventry, UK, December 15-17, 1992

rawbooktitle:
Mathematics in signal processing {III}. Based on the proceedings of the third {IMA} conference on signal processing, University of Warwick, Coventry, {UK}, December 15-17, 1992

entry:
@InCollection{Clarke:1994:RAC,
  author =       "C. T. Clarke and G. R. Nudd",
  booktitle =    "Mathematics in signal processing {III}. Based on the
                 proceedings of the third {IMA} conference on signal
                 processing, University of Warwick, Coventry, {UK},
                 December 15-17, 1992",
  title =        "A redundant arithmetic {CORDIC} system with a unit
                 scale factor",
  publisher =    "Oxford: Clarendon Press",
  pages =        "63--71",
  year =         "1994",
  ISBN =         "0-19-853480-9",
  ISBN-13 =      "978-0-19-853480-8",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  ZMnumber =     "0852.65141",
  acknowledgement = ack-nhfb,
  keywords =     "65T40,65D20,33B10",
  ZBmath =       "922639",
}


bibtype: article
filename: fparith.bib
label: Cortadella:1994:HRD
author: J. Cortadella and T. Lang
title: High-Radix Division and Square-Root with Speculation
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 919--931
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295854
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295854
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. Cortadella and T. Lang
rawtitle: High-Radix Division and Square-Root with Speculation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{Cortadella:1994:HRD,
  author =       "J. Cortadella and T. Lang",
  title =        "High-Radix Division and Square-Root with Speculation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "919--931",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295854",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295854",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  summary =      "The speed of high-radix digit-recurrence dividers and
                 square-root units is mainly determined by the
                 complexity of the result-digit selection. We present a
                 scheme in which a simpler function speculates the
                 result digit, and, when this speculation is \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Dallaway:1994:DAC
author: Richard Z. Dallaway
title: Dynamics of Arithmetic: a Connectionist View of Arithmetic Skills
type: Technical report
number: CSRP 306
institution: Univerity of Sussex
address: Brighton, UK
pages: 159
month: feb
monthnumber: 2
year: 1994
ISSN: 1350-3162 OR 13503162
bibdate: Fri Nov 28 16:36:28 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 16:36:28 ???
acknowledgement: ack-mfc
rawauthor: Richard Z. Dallaway
rawtitle: Dynamics of Arithmetic: a Connectionist View of Arithmetic Skills
entry:
@TechReport{Dallaway:1994:DAC,
  author =       "Richard Z. Dallaway",
  title =        "Dynamics of Arithmetic: a Connectionist View of
                 Arithmetic Skills",
  type =         "Technical report",
  number =       "CSRP 306",
  institution =  "Univerity of Sussex",
  address =      "Brighton, UK",
  pages =        "159",
  month =        feb,
  year =         "1994",
  ISSN =         "1350-3162",
  bibdate =      "Fri Nov 28 16:36:28 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: DasSarma:1994:MAR
author: D. DasSarma and D. W. Matula
title: Measuring the Accuracy of ROM Reciprocal Tables
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 932--940
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295855
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. DasSarma and D. W. Matula
rawtitle: Measuring the Accuracy of {ROM} Reciprocal Tables
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{DasSarma:1994:MAR,
  author =       "D. DasSarma and D. W. Matula",
  title =        "Measuring the Accuracy of {ROM} Reciprocal Tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "932--940",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295855",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Daumas:1994:FAR
author: Marc Daumas and C. Mazenc and X. Merrheim and J. M. Muller
title: Fast and accurate range reduction for computation of the elementary functions
crossref: Ames:1994:IPI
pages: ??--??
year: 1994
bibdate: Sat Jun 25 08:57:47 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.25 08:57:47 ???
keywords: range reduction
acknowledgement: ack-nhfb
rawauthor: Marc Daumas and C. Mazenc and X. Merrheim and J. M. Muller
rawtitle: Fast and accurate range reduction for computation of the elementary functions
entry:
@InProceedings{Daumas:1994:FAR,
  author =       "Marc Daumas and C. Mazenc and X. Merrheim and J. M.
                 Muller",
  title =        "Fast and accurate range reduction for computation of
                 the elementary functions",
  crossref =     "Ames:1994:IPI",
  pages =        "??--??",
  year =         "1994",
  bibdate =      "Sat Jun 25 08:57:47 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "range reduction",
}


bibtype: article
filename: fparith.bib
label: Daumas:1994:RFP
author: Marc Daumas and David W. Matula
title: Rounding of floating point intervals
journal: j-INTERVAL-COMP
volume: 4
pages: 28--45
year: 1994
ISSN: 0135-4868 OR 01354868
MRclass: 65G10 (65G05)
MRnumber: 1 332 074
bibdate: Fri Dec 8 08:24:03 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:03 ???
fjournal: Interval Computations = Interval'nye vychisleniia
acknowledgement: ack-nhfb
rawauthor: Marc Daumas and David W. Matula
rawtitle: Rounding of floating point intervals
entry:
@Article{Daumas:1994:RFP,
  author =       "Marc Daumas and David W. Matula",
  title =        "Rounding of floating point intervals",
  journal =      j-INTERVAL-COMP,
  volume =       "4",
  pages =        "28--45",
  year =         "1994",
  ISSN =         "0135-4868",
  MRclass =      "65G10 (65G05)",
  MRnumber =     "1 332 074",
  bibdate =      "Fri Dec 8 08:24:03 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Interval Computations = Interval'nye vychisleniia",
  xxnote =       "SCAN-93 (Vienna, 1993)",
}


bibtype: article
filename: fparith.bib
label: De:1994:FPA
author: M. De and B. P. Sinha
title: Fast parallel algorithm for ternary multiplication using multivalued $ I^2 L $ technology
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 5
pages: 603--607
month: may
monthnumber: 5
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.280807
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:55 MDT 2011
bibtimestamp: 2011.07.07 07:13:55 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=280807
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. De and B. P. Sinha
rawtitle: Fast parallel algorithm for ternary multiplication using multivalued {$ I^2 L $} technology
entry:
@Article{De:1994:FPA,
  author =       "M. De and B. P. Sinha",
  title =        "Fast parallel algorithm for ternary multiplication
                 using multivalued {$ I^2 L $} technology",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "5",
  pages =        "603--607",
  month =        may,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.280807",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=280807",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: delaSerna:1994:TBF
author: A. E. de la Serna and M. A. Soderstrand
booktitle: Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, 1994
title: Trade-off between FPGA resource utilization and roundoff error in optimized CSD FIR digital filters
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 187--191
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: A. E. de la Serna and M. A. Soderstrand
rawbooktitle: Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, 1994
rawtitle:
Trade-off between {FPGA} resource utilization and roundoff error in optimized {CSD} {FIR} digital filters

entry:
@InProceedings{delaSerna:1994:TBF,
  author =       "A. E. de la Serna and M. A. Soderstrand",
  booktitle =    "Conference Record of the Twenty-Eighth Asilomar
                 Conference on Signals, Systems and Computers, 1994",
  title =        "Trade-off between {FPGA} resource utilization and
                 roundoff error in optimized {CSD} {FIR} digital
                 filters",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "187--191",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "In this paper, we investigate the trade off between
                 filter order and bits of coefficient precision in
                 fixed-coefficient FIR digital filters utilizing
                 canonical signed digit (CSD) coefficient
                 representation. We demonstrate that the use of
                 optimized \ldots{}",
}


bibtype: article
filename: fparith.bib
label: delRosario:1994:HIM
author: J. M. del Rosario and A. N. Choudhary
title: High-performance I/O for massively parallel computers: problems and prospects
journal: j-COMPUTER
volume: 27
number: 3
pages: 59--68
month: mar
monthnumber: 3
year: 1994
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Fri Sep 13 16:03:42 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.13 16:03:42 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Syracuse University, NY, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: J. M. del Rosario and A. N. Choudhary
rawtitle: High-performance {I/O} for massively parallel computers: problems and prospects
keywords:
Access patterns; Compilers; File systems; Floating-point operations per second; Hardware technology; High-performance I/O; High-performance storage systems; High-speed networking; I/O infrastructure; Language interfaces; Massive parallel processing; Massively parallel computers; Networking technology; Operating systems; Parallel I/O problem; Powerful supercomputers; Resource-management approaches; Runtime system; Teraflops barrier; Visualization systems

thesaurus:
Computer networks; Input-output programs; Network operating systems; Parallel machines; Parallel programming

entry:
@Article{delRosario:1994:HIM,
  author =       "J. M. del Rosario and A. N. Choudhary",
  title =        "High-performance {I/O} for massively parallel
                 computers: problems and prospects",
  journal =      j-COMPUTER,
  volume =       "27",
  number =       "3",
  pages =        "59--68",
  month =        mar,
  year =         "1994",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Fri Sep 13 16:03:42 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Syracuse
                 University, NY, USA",
  classification = "B6210L (Computer communications); C5440
                 (Multiprocessor systems and techniques); C5620
                 (Computer networks and techniques); C6110P (Parallel
                 programming); C6150N (Distributed systems)",
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Access patterns; Compilers; File systems;
                 Floating-point operations per second; Hardware
                 technology; High-performance I/O; High-performance
                 storage systems; High-speed networking; I/O
                 infrastructure; Language interfaces; Massive parallel
                 processing; Massively parallel computers; Networking
                 technology; Operating systems; Parallel I/O problem;
                 Powerful supercomputers; Resource-management
                 approaches; Runtime system; Teraflops barrier;
                 Visualization systems",
  thesaurus =    "Computer networks; Input-output programs; Network
                 operating systems; Parallel machines; Parallel
                 programming",
}


bibtype: techreport
filename: fparith.bib
label: Demmel:1994:CPBa
author: James Demmel and Inderjit Dhillon and Huan Ren
title: On the correctness of parallel bisection in floating point
type: Report
number: UCB/CSD 94/805
institution: Computer Science Division (EECS), University of California
address: Berkeley, CA, USA
pages: 38
month: mar
monthnumber: 3
year: 1994
bibdate: Thu Aug 23 06:41:11 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.08.23 06:41:11 ???
note: Also known as LAPACK Working Note number 70.
URL: http://www.neglib.org/lapack/lawns/lawn70.ps
acknowledgement: ack-nhfb
rawauthor: James Demmel and Inderjit Dhillon and Huan Ren
rawnote: Also known as LAPACK Working Note number 70.
rawtitle: On the correctness of parallel bisection in floating point
entry:
@TechReport{Demmel:1994:CPBa,
  author =       "James Demmel and Inderjit Dhillon and Huan Ren",
  title =        "On the correctness of parallel bisection in floating
                 point",
  type =         "Report",
  number =       "UCB/CSD 94/805",
  institution =  "Computer Science Division (EECS), University of
                 California",
  address =      "Berkeley, CA, USA",
  pages =        "38",
  month =        mar,
  year =         "1994",
  bibdate =      "Thu Aug 23 06:41:11 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Also known as LAPACK Working Note number 70.",
  URL =          "http://www.neglib.org/lapack/lawns/lawn70.ps",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Demmel:1994:CPBb
author: James Demmel and Inderjit Dhillon and Huan Ren
title: On the Correctness of Parallel Bisection in Floating Point
type: LAPACK Working Note
number: 70
institution: inst-UT-CS
address: inst-UT-CS:adr
pages: 38
month: mar
monthnumber: 3
year: 1994
bibdate: Fri Apr 22 17:06:37 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.22 17:06:37 ???
note: UT-CS-94-228, March 1994.
URL: http://www.netlib.org/lapack/lawns/lawn70.ps; http://www.netlib.org/lapack/lawnspdf/lawn70.pdf
acknowledgement: ack-nhfb
rawauthor: James Demmel and Inderjit Dhillon and Huan Ren
rawnote: UT-CS-94-228, March 1994.
rawtitle: On the Correctness of Parallel Bisection in Floating Point
entry:
@TechReport{Demmel:1994:CPBb,
  author =       "James Demmel and Inderjit Dhillon and Huan Ren",
  title =        "On the Correctness of Parallel Bisection in Floating
                 Point",
  type =         "LAPACK Working Note",
  number =       "70",
  institution =  inst-UT-CS,
  address =      inst-UT-CS:adr,
  month =        mar,
  year =         "1994",
  bibdate =      "Fri Apr 22 17:06:37 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "UT-CS-94-228, March 1994.",
  URL =          "http://www.netlib.org/lapack/lawns/lawn70.ps;
                 http://www.netlib.org/lapack/lawnspdf/lawn70.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Demmel:1994:FNA
author: James W. Demmel and Xiaoye Li
title: Faster Numerical Algorithms via Exception Handling
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 983--992
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295860
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
note: This is an expanded version of cite Demmel:1993:FNA.
URL: http://www.cs.berkeley.edu/~xiaoye/ieee.ps.gz
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: James W. Demmel and Xiaoye Li
rawnote: This is an expanded version of \cite{Demmel:1993:FNA}.
rawtitle: Faster Numerical Algorithms via Exception Handling
entry:
@Article{Demmel:1994:FNA,
  author =       "James W. Demmel and Xiaoye Li",
  title =        "Faster Numerical Algorithms via Exception Handling",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "983--992",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295860",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  note =         "This is an expanded version of
                 \cite{Demmel:1993:FNA}.",
  URL =          "http://www.cs.berkeley.edu/~xiaoye/ieee.ps.gz",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimauro:1994:DFNa
author: G. Dimauro and S. Impedovo and G. Pirlo
booktitle: Proceedings of the 20th EUROMICRO Conference, EUROMICRO 94. System Architecture and Integration
title: The `diagonal function' in non-redundant residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 590--596
year: 1994
DOI: https://doi.org/10.1109/EURMIC.1994.390354
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. Dimauro and S. Impedovo and G. Pirlo
rawbooktitle: Proceedings of the 20th {EUROMICRO} Conference, {EUROMICRO 94}. System Architecture and Integration
rawtitle: The `diagonal function' in non-redundant residue number system
entry:
@InProceedings{Dimauro:1994:DFNa,
  author =       "G. Dimauro and S. Impedovo and G. Pirlo",
  booktitle =    "Proceedings of the 20th {EUROMICRO} Conference,
                 {EUROMICRO 94}. System Architecture and Integration",
  title =        "The `diagonal function' in non-redundant residue
                 number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "590--596",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EURMIC.1994.390354",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Although the `diagonal function' of a Residue Number
                 System has been recently introduced as a powerful tool
                 to perform non modular operations, its implementation
                 is generally realized using an additional modulus
                 external to the set of system moduli. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimauro:1994:DFNb
author: G. Dimauro and S. Impedovo and G. Pirlo
booktitle: EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference
title: The `diagonal function' in non-redundant residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 590--596
year: 1994
DOI: https://doi.org/10.1109/EURMIC.1994.390354
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: G. Dimauro and S. Impedovo and G. Pirlo
rawbooktitle: {EUROMICRO 94}. System Architecture and Integration. Proceedings of the 20th {EUROMICRO} Conference
rawtitle: The `diagonal function' in non-redundant residue number system
entry:
@InProceedings{Dimauro:1994:DFNb,
  author =       "G. Dimauro and S. Impedovo and G. Pirlo",
  booktitle =    "{EUROMICRO 94}. System Architecture and Integration.
                 Proceedings of the 20th {EUROMICRO} Conference",
  title =        "The `diagonal function' in non-redundant residue
                 number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "590--596",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/EURMIC.1994.390354",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Although the `diagonal function' of a Residue Number
                 System has been recently introduced as a powerful tool
                 to perform non modular operations, its implementation
                 is generally realized using an additional modulus
                 external to the set of system moduli. \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Edelman:1994:W
author: Alan Edelman
title: When is $ x star (1 / x) neq 1 $ ?
pages: 590--596
day: 7
month: dec
monthnumber: 12
year: 1994
bibdate: Wed Aug 07 15:04:56 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 15:04:56 ???
URL: https://math.mit.edu/~edelman/homepage/papers/ieee.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: Alan Edelman
rawtitle: When is $ x \star (1 / x) \neq 1 $ ?
entry:
@Misc{Edelman:1994:W,
  author =       "Alan Edelman",
  title =        "When is $ x \star (1 / x) \neq 1 $ ?",
  howpublished = "Web document",
  day =          "7",
  month =        dec,
  year =         "1994",
  bibdate =      "Wed Aug 07 15:04:56 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://math.mit.edu/~edelman/homepage/papers/ieee.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Ercegovac:1994:DSR
author: Milos D. (Dragutin) Ercegovac and Tomas Lang
title: Division and square root: digit-recurrence algorithms and implementations
publisher: pub-KLUWER
address: pub-KLUWER:adr
pages: x + 230
year: 1994
ISBN: 0-7923-9438-0 OR 0792394380
ISBN13: 978-0-7923-9438-9 OR 9780792394389
LCCN: QA76.9.C62 E73 1994
bibdate: Fri Mar 27 09:46:24 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.03.27 09:46:24 ???
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. (Dragutin) Ercegovac and Tomas Lang
rawtitle: Division and square root: digit-recurrence algorithms and implementations
entry:
@Book{Ercegovac:1994:DSR,
  author =       "Milo{\v{s}} D. (Dragutin) Ercegovac and Tomas Lang",
  title =        "Division and square root: digit-recurrence algorithms
                 and implementations",
  publisher =    pub-KLUWER,
  address =      pub-KLUWER:adr,
  pages =        "x + 230",
  year =         "1994",
  ISBN =         "0-7923-9438-0",
  ISBN-13 =      "978-0-7923-9438-9",
  LCCN =         "QA76.9.C62 E73 1994",
  bibdate =      "Fri Mar 27 09:46:24 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ercegovac:1994:VHR
author: M. D. Ercegovac and T. Lang and P. Montuschi
title: Very-High Radix Division with Prescaling and Selection by Rounding
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 909--918
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295853
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295853
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. D. Ercegovac and T. Lang and P. Montuschi
rawtitle: Very-High Radix Division with Prescaling and Selection by Rounding
entry:
@Article{Ercegovac:1994:VHR,
  author =       "M. D. Ercegovac and T. Lang and P. Montuschi",
  title =        "Very-High Radix Division with Prescaling and Selection
                 by Rounding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "909--918",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295853",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295853",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  summary =      "A division algorithm in which the quotient-digit
                 selection is performed by rounding the shifted residual
                 in carry-save form is presented. To allow the use of
                 this simple function, the divisor (and dividend) is
                 prescaled to a range close to one. The \ldots{}",
  xxtitle =      "Very high radix division with selection by rounding
                 and prescaling",
}


bibtype: article
filename: fparith.bib
label: Fagin:1994:FPG
author: B. Fagin and C. Renard
title: Field Programmable Gate Arrays and Floating Point Arithmetic
journal: j-IEEE-TRANS-VLSI-SYST
volume: 2
number: 3
pages: 365--367
month: sep
monthnumber: 9
year: 1994
CODEN: IEVSE9
DOI: https://doi.org/10.1109/92.311646
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, US Air Force Acad., Colorado Springs, CO, USA
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: B. Fagin and C. Renard
rawtitle: Field Programmable Gate Arrays and Floating Point Arithmetic
abstract:
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.

keywords:
Addition; Architectural correlation; Area costs; Field programmable gate arrays; Floating point arithmetic; Floating-point adder; Floating-point multiplier; FPGA; IEEE Standard 754 compliance; Multiplication; Time costs

thesaurus:
Adders; Application specific integrated circuits; Digital arithmetic; Logic arrays; Multiplying circuits

rawabstract:
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.

entry:
@Article{Fagin:1994:FPG,
  author =       "B. Fagin and C. Renard",
  title =        "Field Programmable Gate Arrays and Floating Point
                 Arithmetic",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "2",
  number =       "3",
  pages =        "365--367",
  month =        sep,
  year =         "1994",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/92.311646",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present empirical results describing the
                 implementation of an IEEE Standard 754 compliant
                 floating-point adder/multiplier using field
                 programmable gate arrays. The use of FPGA's permits
                 fast and accurate quantitative evaluation of a variety
                 of circuit design tradeoffs for addition and
                 multiplication. PPGA's also permit accurate assessments
                 of the area and time costs associated with various
                 features of the IEEE floating-point standard, including
                 rounding and gradual underflow. These costs are
                 analyzed, along with the effects of architectural
                 correlation, a phenomenon that occurs when the cost of
                 combining architectural features exceeds the sum of
                 separate implementation. We conclude with an assessment
                 of the strengths and weaknesses of using FPGA's for
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, US Air Force Acad.,
                 Colorado Springs, CO, USA",
  classification = "B1265B (Logic circuits); B2570 (Semiconductor
                 integrated circuits); C5120 (Logic and switching
                 circuits); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  keywords =     "Addition; Architectural correlation; Area costs; Field
                 programmable gate arrays; Floating point arithmetic;
                 Floating-point adder; Floating-point multiplier; FPGA;
                 IEEE Standard 754 compliance; Multiplication; Time
                 costs",
  summary =      "We present empirical results describing the
                 implementation of an IEEE Standard 754 compliant
                 floating-point adder/multiplier using field
                 programmable gate arrays. The use of FPGA's permits
                 fast and accurate quantitative evaluation of a variety
                 of \ldots{}",
  thesaurus =    "Adders; Application specific integrated circuits;
                 Digital arithmetic; Logic arrays; Multiplying
                 circuits",
}


bibtype: book
filename: fparith.bib
label: Farquhar:1994:MPH
author: Erin Farquhar and Philip Bruce
title: The MIPS Programmer's Handbook
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
pages: viii + 408
year: 1994
ISBN: 1-55860-297-6 OR 1558602976
ISBN13: 978-1-55860-297-7 OR 9781558602977
LCCN: QA76.6 .F375 1994
bibdate: Fri May 13 18:21:14 1994
bibtimestamp: 1994.05.13 18:21:14 ???
acknowledgement: ack-nhfb
rawauthor: Erin Farquhar and Philip Bruce
rawtitle: The {MIPS} Programmer's Handbook
abstract:
A hands-on view of the highly successful MIPS family of microprocessors, written for programmers developing systems applications for the MIPS platform. The MIPS Programmer's Handbook describes the MIPS architecture from the perspective of assembly- and C-language programmers, with special emphasis on issues related to embedded applications. Engineers writing system-level programs for MIPS-based embedded systems will find the topic selection especially useful including the sections on software conventions, initializing the processor in a bare machine environment, and writing exception handlers. For convenient use, the instruction set reference is presented with only one page per instruction. The authors focus on the instructions available to assembly-language programmers, rather than on the hardware-level instruction set documented in data books released by vendors of the MIPS processor. Provides enough detail for anyone doing serious system-level programming. Also included are ten complete program examples, with line-by-line explanations.

TOC:
1: Introduction 2: Software Conventions 3: Initialization 4: Exceptions 5: Instruction Set Reference A: Overview of the MIPS1 Architecture B: Instruction Summary C: Prologue and Epilogue Templates D: Include Files E: Libraries F: Vendors of MIPS Products

rawabstract:
A hands-on view of the highly successful MIPS family of microprocessors, written for programmers developing systems applications for the MIPS platform. The MIPS Programmer's Handbook describes the MIPS architecture from the perspective of assembly- and C-language programmers, with special emphasis on issues related to embedded applications. Engineers writing system-level programs for MIPS-based embedded systems will find the topic selection especially useful including the sections on software conventions, initializing the processor in a bare machine environment, and writing exception handlers. For convenient use, the instruction set reference is presented with only one page per instruction. The authors focus on the instructions available to assembly-language programmers, rather than on the hardware-level instruction set documented in data books released by vendors of the MIPS processor. Provides enough detail for anyone doing serious system-level programming. Also included are ten complete program examples, with line-by-line explanations.

rawTOC:
1: Introduction \\ 2: Software Conventions \\ 3: Initialization \\ 4: Exceptions \\ 5: Instruction Set Reference \\ A: Overview of the MIPS1 Architecture \\ B: Instruction Summary \\ C: Prologue and Epilogue Templates \\ D: Include Files \\ E: Libraries \\ F: Vendors of MIPS Products

entry:
@Book{Farquhar:1994:MPH,
  author =       "Erin Farquhar and Philip Bruce",
  title =        "The {MIPS} Programmer's Handbook",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "viii + 408",
  year =         "1994",
  ISBN =         "1-55860-297-6",
  ISBN-13 =      "978-1-55860-297-7",
  LCCN =         "QA76.6 .F375 1994",
  bibdate =      "Fri May 13 18:21:14 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$36.95",
  abstract =     "A hands-on view of the highly successful MIPS family
                 of microprocessors, written for programmers developing
                 systems applications for the MIPS platform. The MIPS
                 Programmer's Handbook describes the MIPS architecture
                 from the perspective of assembly- and C-language
                 programmers, with special emphasis on issues related to
                 embedded applications. Engineers writing system-level
                 programs for MIPS-based embedded systems will find the
                 topic selection especially useful including the
                 sections on software conventions, initializing the
                 processor in a bare machine environment, and writing
                 exception handlers. For convenient use, the instruction
                 set reference is presented with only one page per
                 instruction. The authors focus on the instructions
                 available to assembly-language programmers, rather than
                 on the hardware-level instruction set documented in
                 data books released by vendors of the MIPS processor.
                 Provides enough detail for anyone doing serious
                 system-level programming. Also included are ten
                 complete program examples, with line-by-line
                 explanations.",
  acknowledgement = ack-nhfb,
  libnote =      "Not yet in my library.",
  tableofcontents = "1: Introduction \\
                 2: Software Conventions \\
                 3: Initialization \\
                 4: Exceptions \\
                 5: Instruction Set Reference \\
                 A: Overview of the MIPS1 Architecture \\
                 B: Instruction Summary \\
                 C: Prologue and Epilogue Templates \\
                 D: Include Files \\
                 E: Libraries \\
                 F: Vendors of MIPS Products",
}


bibtype: inproceedings
filename: fparith.bib
label: FiallosAguilar:1994:HPA
author: M. Fiallos-Aguilar
title: High precision arithmetic units for fine-grain massively parallel computing
crossref: IEEE:1994:PFI
pages: 403--407
year: 1994
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Lab. LIP-IMAG, Ecole Normale Superieure de Lyon, France
thesaurus: Digital arithmetic; Parallel architectures; Pipeline arithmetic
rawauthor: M. Fiallos-Aguilar
rawtitle: High precision arithmetic units for fine-grain massively parallel computing
abstract:
In this paper we deal with new high precision arithmetic units (AUs). These AUs are specialized in the computation of one arithmetic operation (division, addition, etc.), but when hundreds of them are interconnected by a reconfigurable network, a parallel architecture that uses massive digit-level pipelining between floating-point arithmetic units (allowing fast computation of scientific jobs) becomes interesting. In this paper we present several new AUs for the fast computation of arithmetic expressions that will be used on a high precision massively parallel computer. (6 Refs.)

keywords:
Arithmetic units; Fine-grain; Floating-point arithmetic units; High precision; Massively parallel computing; Parallel architecture

rawabstract:
In this paper we deal with new high precision arithmetic units (AUs). These AUs are specialized in the computation of one arithmetic operation (division, addition, etc.), but when hundreds of them are interconnected by a reconfigurable network, a parallel architecture that uses massive digit-level pipelining between floating-point arithmetic units (allowing fast computation of scientific jobs) becomes interesting. In this paper we present several new AUs for the fast computation of arithmetic expressions that will be used on a high precision massively parallel computer. (6 Refs.)

entry:
@InProceedings{FiallosAguilar:1994:HPA,
  author =       "M. Fiallos-Aguilar",
  title =        "High precision arithmetic units for fine-grain
                 massively parallel computing",
  crossref =     "IEEE:1994:PFI",
  pages =        "403--407",
  year =         "1994",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we deal with new high precision
                 arithmetic units (AUs). These AUs are specialized in
                 the computation of one arithmetic operation (division,
                 addition, etc.), but when hundreds of them are
                 interconnected by a reconfigurable network, a parallel
                 architecture that uses massive digit-level pipelining
                 between floating-point arithmetic units (allowing fast
                 computation of scientific jobs) becomes interesting. In
                 this paper we present several new AUs for the fast
                 computation of arithmetic expressions that will be used
                 on a high precision massively parallel computer. (6
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Lab. LIP-IMAG, Ecole Normale Superieure de Lyon,
                 France",
  classification = "C5220P (Parallel architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "Arithmetic units; Fine-grain; Floating-point
                 arithmetic units; High precision; Massively parallel
                 computing; Parallel architecture",
  thesaurus =    "Digital arithmetic; Parallel architectures; Pipeline
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: Gander:1994:AFP
author: H. Gander and M. Vincze and J. P. Prenninger
title: Application of a Floating Point Digital Signal Processor to the Control of a Laser Tracking System
journal: j-IEEE-TRANS-CONTROL-SYST-TECHNOL
volume: 2
number: 4
pages: 290--298
month: dec
monthnumber: 12
year: 1994
CODEN: IETTE2
ISSN: 1063-6536 (print), 1558-0865 (electronic) OR 10636536 (print), 15580865 (electronic)
ISSNL: 1063-6536 OR 10636536
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Control Systems Technology
acknowledgement: ack-nhfb
rawauthor: H. Gander and M. Vincze and J. P. Prenninger
rawtitle: Application of a Floating Point Digital Signal Processor to the Control of a Laser Tracking System
entry:
@Article{Gander:1994:AFP,
  author =       "H. Gander and M. Vincze and J. P. Prenninger",
  title =        "Application of a Floating Point Digital Signal
                 Processor to the Control of a Laser Tracking System",
  journal =      j-IEEE-TRANS-CONTROL-SYST-TECHNOL,
  volume =       "2",
  number =       "4",
  pages =        "290--298",
  month =        dec,
  year =         "1994",
  CODEN =        "IETTE2",
  ISSN =         "1063-6536 (print), 1558-0865 (electronic)",
  ISSN-L =       "1063-6536",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Control Systems Technology",
  summary =      "Laser tracking systems represent the most promising
                 technique for dynamic position measurement of
                 industrial robots. The Institute of Flexible Automation
                 at the Vienna University of Technology a new tracking
                 algorithm has been developed. It is shown \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Gerber:1994:DPH
author: S. Gerber and M. Goessel
title: Detection of permanent hardware faults of a floating point adder by pseudoduplication
crossref: Echtle:1994:PFI
pages: 327--335
year: 1994
DOI: https://doi.org/10.1007/3-540-58426-9_139
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Max-Planck-Society Fault-Tolerant Comput. Group, Potsdam University, Germany
thesaurus: Adders; Digital simulation; Fault location; Floating point arithmetic; Logic CAD; Logic testing
rawauthor: S. Gerber and M. Goessel
rawtitle: Detection of permanent hardware faults of a floating point adder by pseudoduplication
abstract:
In this paper the detection of hardware faults by pseudoduplication for a special floating point adder is investigated. For a special floating point adder all single stuck-at-0/1 faults are injected. In a first simulation experiment for random input patterns all the faults are determined which can be detected by pseudoduplication. In a second experiment for sequences of random input vectors with different length the probability to detect an arbitrary single fault is determined.

keywords:
Arbitrary single fault; Floating point adder; Permanent hardware faults; Probability; Pseudoduplication; Random input patterns; Stuck at faults

rawabstract:
In this paper the detection of hardware faults by pseudoduplication for a special floating point adder is investigated. For a special floating point adder all single stuck-at-0/1 faults are injected. In a first simulation experiment for random input patterns all the faults are determined which can be detected by pseudoduplication. In a second experiment for sequences of random input vectors with different length the probability to detect an arbitrary single fault is determined.

entry:
@InProceedings{Gerber:1994:DPH,
  author =       "S. Gerber and M. Goessel",
  title =        "Detection of permanent hardware faults of a floating
                 point adder by pseudoduplication",
  crossref =     "Echtle:1994:PFI",
  pages =        "327--335",
  year =         "1994",
  DOI =          "https://doi.org/10.1007/3-540-58426-9_139",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper the detection of hardware faults by
                 pseudoduplication for a special floating point adder is
                 investigated. For a special floating point adder all
                 single stuck-at-0/1 faults are injected. In a first
                 simulation experiment for random input patterns all the
                 faults are determined which can be detected by
                 pseudoduplication. In a second experiment for sequences
                 of random input vectors with different length the
                 probability to detect an arbitrary single fault is
                 determined.",
  acknowledgement = ack-nhfb,
  affiliation =  "Max-Planck-Society Fault-Tolerant Comput. Group,
                 Potsdam University, Germany",
  classification = "B1130B (Computer-aided circuit analysis and design);
                 B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5210B (Computer-aided logic design); C7410D
                 (Electronic engineering computing)",
  keywords =     "Arbitrary single fault; Floating point adder;
                 Permanent hardware faults; Probability;
                 Pseudoduplication; Random input patterns; Stuck at
                 faults",
  thesaurus =    "Adders; Digital simulation; Fault location; Floating
                 point arithmetic; Logic CAD; Logic testing",
}


bibtype: article
filename: fparith.bib
label: Granlund:1994:DII
author: Torbjorn Granlund and Peter L. Montgomery
title: Division by invariant integers using multiplication
journal: j-SIGPLAN
volume: 29
number: 6
pages: 61--72
month: jun
monthnumber: 6
year: 1994
CODEN: SINODQ
DOI: https://doi.org/10.1145/178243.178249
ISBN: 0-89791-598-4 OR 0897915984
ISBN13: 978-0-89791-598-4 OR 9780897915984
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:51 MST 2003
bibtimestamp: 2003.12.14 09:16:51 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Cygnus Support, Mountain View, CA, USA
annote: Published as part of the Proceedings of PLDI'94.
corpsource: Cygnus Support, Mountain View, CA, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: T Theoretical or Mathematical
rawauthor: Torbj{\"o}rn Granlund and Peter L. Montgomery
rawtitle: Division by invariant integers using multiplication
bibsource:
http://portal.acm.org/; http://www.acm.org/pubs/contents/proceedings/pldi/178243/index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psa4.gz; ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psl.gz; http://www.acm.org:80/pubs/citations/proceedings/pldi/178243/p61-granlund/

abstract:
Integer division remains expensive on today's processors as the cost of integer multiplication declines. We present code sequences for division by arbitrary nonzero integer constants and run-time invariants using integer multiplication. The algorithms assume a two's complement architecture. Most also require that the upper half of an integer product be quickly accessible. We treat unsigned division, signed division where the quotient rounds towards zero, signed division where the quotient rounds towards $ - infty $, and division where the result is known a priori to be exact. We give some implementation results using the C compiler GCC.

keywords:
algorithms; Arbitrary nonzero integer constants; arbitrary nonzero integer constants; C compiler; Code sequences; code sequences; digital arithmetic; Floating point arithmetic; floating point arithmetic; GCC; Integer division; integer division; Integer multiplication; integer multiplication; Invariant integers; invariant integers; mathematics computing; Multiplication; multiplication; performance; program; program compilers; programming; reduced instruction set computing; RISC processors; Run-time invariants; run-time invariants; Signed division; signed division; Two's complement architecture; two's complement architecture; Unsigned division; unsigned division

subject:
bf G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic. bf F.2.1 Theory of Computation, ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY, Numerical Algorithms and Problems. bf D.3.4 Software, PROGRAMMING LANGUAGES, Processors, Compilers.

thesaurus:
Digital arithmetic; Mathematics computing; Program compilers; Programming; Reduced instruction set computing

rawabstract:
Integer division remains expensive on today's processors as the cost of integer multiplication declines. We present code sequences for division by arbitrary nonzero integer constants and run-time invariants using integer multiplication. The algorithms assume a two's complement architecture. Most also require that the upper half of an integer product be quickly accessible. We treat unsigned division, signed division where the quotient rounds towards zero, signed division where the quotient rounds towards $ - \infty $, and division where the result is known a priori to be exact. We give some implementation results using the C compiler GCC.

entry:
@Article{Granlund:1994:DII,
  author =       "Torbj{\"o}rn Granlund and Peter L. Montgomery",
  title =        "Division by invariant integers using multiplication",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "6",
  pages =        "61--72",
  month =        jun,
  year =         "1994",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/178243.178249",
  ISBN =         "0-89791-598-4",
  ISBN-13 =      "978-0-89791-598-4",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:51 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 http://www.acm.org/pubs/contents/proceedings/pldi/178243/index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psa4.gz;
                 ftp://ftp.cwi.nl/pub/pmontgom/divcnst.psl.gz;
                 http://www.acm.org:80/pubs/citations/proceedings/pldi/178243/p61-granlund/",
  abstract =     "Integer division remains expensive on today's
                 processors as the cost of integer multiplication
                 declines. We present code sequences for division by
                 arbitrary nonzero integer constants and run-time
                 invariants using integer multiplication. The algorithms
                 assume a two's complement architecture. Most also
                 require that the upper half of an integer product be
                 quickly accessible. We treat unsigned division, signed
                 division where the quotient rounds towards zero, signed
                 division where the quotient rounds towards $ - \infty
                 $, and division where the result is known a priori to
                 be exact. We give some implementation results using the
                 C compiler GCC.",
  acknowledgement = ack-nhfb,
  affiliation =  "Cygnus Support, Mountain View, CA, USA",
  annote =       "Published as part of the Proceedings of PLDI'94.",
  classification = "C5230 (Digital arithmetic methods); C6110 (Systems
                 analysis and programming); C6150C (Compilers,
                 interpreters and other processors)",
  confdate =     "20-24 June 1994",
  conflocation = "Orlando, FL, USA",
  confsponsor =  "ACM",
  conftitle =    "ACM SIGPLAN '94 Conference on Programming Language
                 Design and Implementation (PLDI)",
  corpsource =   "Cygnus Support, Mountain View, CA, USA",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "algorithms; Arbitrary nonzero integer constants;
                 arbitrary nonzero integer constants; C compiler; Code
                 sequences; code sequences; digital arithmetic; Floating
                 point arithmetic; floating point arithmetic; GCC;
                 Integer division; integer division; Integer
                 multiplication; integer multiplication; Invariant
                 integers; invariant integers; mathematics computing;
                 Multiplication; multiplication; performance; program;
                 program compilers; programming; reduced instruction set
                 computing; RISC processors; Run-time invariants;
                 run-time invariants; Signed division; signed division;
                 Two's complement architecture; two's complement
                 architecture; Unsigned division; unsigned division",
  sponsororg =   "ACM",
  subject =      "{\bf G.1.0} Mathematics of Computing, NUMERICAL
                 ANALYSIS, General, Computer arithmetic. {\bf F.2.1}
                 Theory of Computation, ANALYSIS OF ALGORITHMS AND
                 PROBLEM COMPLEXITY, Numerical Algorithms and Problems.
                 {\bf D.3.4} Software, PROGRAMMING LANGUAGES,
                 Processors, Compilers.",
  thesaurus =    "Digital arithmetic; Mathematics computing; Program
                 compilers; Programming; Reduced instruction set
                 computing",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Grosse:1994:IRS
author: Eric Grosse and John D. Hobby
title: Improved rounding for spline coefficients and knots
journal: j-MATH-COMPUT
volume: 63
number: 207
pages: 175--194
month: jul
monthnumber: 7
year: 1994
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
MRclass: 65D07
MRnumber: 94j:65019
bibdate: Tue Mar 25 15:38:13 MST 1997
bibtimestamp: 1997.03.25 15:38:13 MST
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
affiliation: Comput. Sci. Res., AT&T Bell Labs., Murray Hill, NJ, USA
ajournal: Math. Comput.
corpsource: Comput. Sci. Res., AT&T Bell Labs., Murray Hill, NJ, USA
journalURL: http://www.ams.org/mcom/
treatment: T Theoretical or Mathematical
rawauthor: Eric Grosse and John D. Hobby
rawtitle: Improved rounding for spline coefficients and knots
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp1990.bib

keywords:
affine model; algorithm; error; error analysis; infinite-precision value; knot; knots; Lovasz basis reduction; optimal full-precision free-; parameterized spline; quadratic error model; rounding; roundoff errors; spline coefficients; splines (mathematics)

classcodes:
B0290F (Interpolation and function approximation); B0290B (Error analysis in numerical methods); C4130 (Interpolation and function approximation); C4110 (Error analysis in numerical methods)

entry:
@Article{Grosse:1994:IRS,
  author =       "Eric Grosse and John D. Hobby",
  title =        "Improved rounding for spline coefficients and knots",
  journal =      j-MATH-COMPUT,
  volume =       "63",
  number =       "207",
  pages =        "175--194",
  month =        jul,
  year =         "1994",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  MRclass =      "65D07",
  MRnumber =     "94j:65019",
  bibdate =      "Tue Mar 25 15:38:13 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp1990.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Comput. Sci. Res., AT\&T Bell Labs., Murray Hill, NJ,
                 USA",
  ajournal =     "Math. Comput.",
  classcodes =   "B0290F (Interpolation and function approximation);
                 B0290B (Error analysis in numerical methods); C4130
                 (Interpolation and function approximation); C4110
                 (Error analysis in numerical methods)",
  corpsource =   "Comput. Sci. Res., AT\&T Bell Labs., Murray Hill, NJ,
                 USA",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "affine model; algorithm; error; error analysis;
                 infinite-precision value; knot; knots; Lovasz basis
                 reduction; optimal full-precision free-; parameterized
                 spline; quadratic error model; rounding; roundoff
                 errors; spline coefficients; splines (mathematics)",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Hahn:1994:UDF
author: H. Hahn and D. Timmermann and B. J. Hosticka and B. Rix
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 11
pages: 1339--1344
month: nov
monthnumber: 11
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.324568
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:58 MDT 2011
bibtimestamp: 2011.07.07 07:13:58 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=324568
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Hahn and D. Timmermann and B. J. Hosticka and B. Rix
title:
A unified and division-free CORDIC argument reduction method with unlimited convergence domain including inverse hyperbolic functions

rawtitle:
A unified and division-free {CORDIC} argument reduction method with unlimited convergence domain including inverse hyperbolic functions

entry:
@Article{Hahn:1994:UDF,
  author =       "H. Hahn and D. Timmermann and B. J. Hosticka and B.
                 Rix",
  title =        "A unified and division-free {CORDIC} argument
                 reduction method with unlimited convergence domain
                 including inverse hyperbolic functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "11",
  pages =        "1339--1344",
  month =        nov,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.324568",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:58 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=324568",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Hartwig:1994:FPA
author: F. Hartwig and A. Lacroix
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS '94, 2 June 1994
title: Floating point addition errors and their effect on the roundoff noise in digital signal processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 121--124
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: F. Hartwig and A. Lacroix
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS '94}, 2 June 1994
rawtitle: Floating point addition errors and their effect on the roundoff noise in digital signal processing
entry:
@InProceedings{Hartwig:1994:FPA,
  author =       "F. Hartwig and A. Lacroix",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS '94}, 2 June 1994",
  title =        "Floating point addition errors and their effect on the
                 roundoff noise in digital signal processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "121--124",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "An improved adder model is derived which takes into
                 account correlations between signal and error. For
                 different adder strategies is shown the influence of
                 the improved adder model on the estimated of the
                 resulting \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Hauser:1994:PEH
author: John R. Hauser
title: Programmed exception handling: research project
type: Master of Science, Plan II
school: Department of Computer Science, University of California, Berkeley
address: Berkeley, CA, USA
pages: 82
year: 1994
LCCN: T7.49.1994 H286
bibdate: Mon Feb 18 12:39:53 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.18 12:39:53 ???
acknowledgement: ack-nhfb
rawauthor: John R. Hauser
rawtitle: Programmed exception handling: research project
entry:
@MastersThesis{Hauser:1994:PEH,
  author =       "John R. Hauser",
  title =        "Programmed exception handling: research project",
  type =         "{Master of Science, Plan II}",
  school =       "Department of Computer Science, University of
                 California, Berkeley",
  address =      "Berkeley, CA, USA",
  pages =        "82",
  year =         "1994",
  LCCN =         "T7.49.1994 H286",
  bibdate =      "Mon Feb 18 12:39:53 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hegland:1994:SSP
author: Markus Hegland
journal: j-NUM-MATH
volume: 68
number: 4
pages: 507--547
year: 1994
CODEN: NUMMA7
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
MRclass: 65T20 (65Y05)
MRnumber: 96e:65082
bibdate: Mon May 26 11:49:34 MDT 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.05.26 11:49:34 MDT
fjournal: Numerische Mathematik
acknowledgement: ack-nhfb
corpsource: Centre for Math. Anal. and its Applications, Australian Nat. University, Canberra, ACT, Australia
journalURL: http://link.springer.com/journal/211
treatment: A Application; P Practical; T Theoretical or Mathematical
rawauthor: Markus Hegland
title:
A self-sorting in-place fast Fourier transform algorithm suitable for vector and parallel processing

keywords:
data analysis; distributed memory computers; fast Fourier transforms; floating point pipelines; Fujitsu VP2200; index digit permutations; mathematics computing; matrix recursions; parallel processing; self-sorting in-place fast Fourier transform algorithm; splitting formulas; uniformly long vector lengths; vector processing; vector processor systems

rawtitle:
A self-sorting in-place fast {Fourier} transform algorithm suitable for vector and parallel processing

entry:
@Article{Hegland:1994:SSP,
  author =       "Markus Hegland",
  title =        "A self-sorting in-place fast {Fourier} transform
                 algorithm suitable for vector and parallel processing",
  journal =      j-NUM-MATH,
  volume =       "68",
  number =       "4",
  pages =        "507--547",
  year =         "1994",
  CODEN =        "NUMMA7",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  MRclass =      "65T20 (65Y05)",
  MRnumber =     "96e:65082",
  bibdate =      "Mon May 26 11:49:34 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B0290Z (Other numerical methods); C4190 (Other
                 numerical methods); C5220P (Parallel architecture);
                 C5440 (Multiprocessing systems); C7310 (Mathematics
                 computing)",
  corpsource =   "Centre for Math. Anal. and its Applications,
                 Australian Nat. University, Canberra, ACT, Australia",
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
  keywords =     "data analysis; distributed memory computers; fast
                 Fourier transforms; floating point pipelines; Fujitsu
                 VP2200; index digit permutations; mathematics
                 computing; matrix recursions; parallel processing;
                 self-sorting in-place fast Fourier transform algorithm;
                 splitting formulas; uniformly long vector lengths;
                 vector processing; vector processor systems",
  treatment =    "A Application; P Practical; T Theoretical or
                 Mathematical",
}


bibtype: article
filename: fparith.bib
label: Hemkumar:1994:RLC
author: N. D. Hemkumar and J. R. Cavallaro
title: Redundant and On-Line CORDIC for Unitary Transformations
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 941--954
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295856
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: N. D. Hemkumar and J. R. Cavallaro
rawtitle: Redundant and On-Line {CORDIC} for Unitary Transformations
bibsource:
https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib; OCLC Proceedings database

entry:
@Article{Hemkumar:1994:RLC,
  author =       "N. D. Hemkumar and J. R. Cavallaro",
  title =        "Redundant and On-Line {CORDIC} for Unitary
                 Transformations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "941--954",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295856",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Hester:1994:PPP
author: P. D. Hester and W. J. Filip
title: Preface: Power2 and PowerPC Architecture and Implementation
journal: j-IBM-JRD
volume: 38
number: 5
pages: 490--491
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Mon Feb 12 08:14:00 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.02.12 08:14:00 ???
URL: http://www.almaden.ibm.com/journal/rd38-5.html#one
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: P. D. Hester and W. J. Filip
rawtitle: Preface: {Power2} and {PowerPC} Architecture and Implementation
abstract:
During the four years since the RISC System / 6000* (RS / 6000) announcement in February of 1990, IBM* has strengthened its product line with microprocessor enhancements, increased memory capacity, improved graphics, greatly expanded I/O adapters, and new AIX* and compiler releases. In 1991, IBM began planning for future RS / 6000 systems that would span the range from small, battery-operated products to very large supercomputers and mainframes. As the first step toward achieving this ``palmtop to teraFLOPS'' goal with a single architecture, IBM investigated further optimizations for the original POWER Architecture*. This effort led to the creation of the PowerPC* alliance (IBM Corporation, Motorola*, Inc., and Apple* Computer Corporation) and the definition of the PowerPC Architecture*. Today, the single-chip PowerPC 601* processor is the basis of IBM's entry systems. A more aggressively superscalar version of the original POWER processor, the multichip POWER2* processor, is exploited in our current IBM high-end RISC systems. As technology continues to advance, PowerPC implementations will provide the basis for high-performance 64-bit super servers. This special issue of the IBM Journal of Research and Development focuses on the POWER2 and PowerPC portions of IBM's wide-ranging announcement in the Fall of 1993. The new POWER2 processor nearly doubles the performance of the earlier high-end models. The PowerPC 601 processor was introduced in the RISC System / 6000 Model 250, the first system in the industry to use the PowerPC Architecture created by the strategic IBM/Motorola/Apple alliance. These workstations achieved industry-leading performance and price/performance on virtually every industry-standard benchmark, including SPECint92*, SPECfp92*, Linpack, TPP, TPC-A*, and TPC-C*. Compared to the 1990 offerings, SPEC performance nearly quadrupled, transaction performance improved by a factor of almost five, maximum memory capacity quadrupled, and the maximum disk capacity grew by an order of magnitude. The POWER2 design exploits both multichip technology and a larger die size to execute up to six instructions (eight operations) per clock cycle. Many of the higher-performance POWER2-based systems provide peak execution rates in excess of a half billion operations per second. The paper by White and Dhawan provides an overview of the POWER2 design. Shippy and Griffith describe the dual fixed-point unit design, the data cache unit, and the storage control unit. Hicks, Fry, and Harvey describe the dual floating-point unit design. Barreh et al. describe hardware strategies to minimize compare-branch penalties in the instruction cache unit. Welbon et al. describe a POWER2 hardware performance- monitoring facility which provides execution characteristics that can identify opportunities for application performance improvement. This facility can also be used to gather information crucial to future design decisions. Two performance papers conclude the POWER2 portion of this issue. Franklin et al. analyze some of the key POWER2 hardware contributions to performance on the commercial workloads. Agarwal, Gustavson, and Zubair relate their experiences with optimizing the high-performance Engineering/Scientific Subroutine Library (ESSL) for the POWER2 implementation. While POWER2 and PowerPC implementations provide the opportunity for high-performance systems, optimizing software is also key in delivering end-user performance. Blainey describes aspects of the TOBEY compiler, with special emphasis on instruction scheduling for the RS / 6000 products. Heisch describes TDPR, a prototype version of FDPR, a program restructuring tool which improves application performance by placing frequently executed code blocks so as to minimize instruction cache misses and branch penalties. IBM and the PowerPC alliance are currently developing a family of five PowerPC designs. IBM and Motorola designers at the Somerset Design Center in Austin will optimize single-chip implementations of the PowerPC Architecture for high-volume products. The high-end requirements of the large server and workstation products will be addressed with multichip PowerPC implementations from IBM.par IBM entry-level workstation products introduced the PowerPC 601 microprocessor, the first member of the PowerPC family. The goal for the PowerPC 601 designers was to quickly bring PowerPC to the market. Vaden et al. describe the microarchitecture and performance aspects of the PowerPC 601 processor. Brodnax et al. discuss the PowerPC 601 circuitry and chip implementation details. Future products are planned that will incorporate the PowerPC 603*, PowerPC 604*, and the 64-bit PowerPC 620* implementations as they become available. In addition, the price and price/performance of the PowerPC family enable lower-cost ``RISC PCs'' to be built using PowerPC microprocessors. These ``RISC PCs'' will be developed by the IBM POWER Personal Systems Division.par The PowerPC and POWER2 systems signify a major milestone in IBM's commitment to the ``palmtops to teraFLOPS'' strategy. The PowerPC 601 chip extends the entry products further into the high-volume market by providing exceptional performance in a low-cost single-chip microprocessor. The high-end POWER2 implementation extracts the maximum performance achievable in today's technology, thrusting the IBM RISC processors into the supercomputing and large-server environments. IBM POWER Parallel Systems extends the RS / 6000 processing capability by providing IBM POWER Parallel SP2* systems with up to 512 POWER/POWER2 nodes. In addition to scalability, four-way High Availability Cluster Multi-Processor (HACMP) systems provide the reliability/availability that one would expect from mainframe-class systems by supporting a ``no single point of failure'' capability, even when one processor is off line. This impressive base of processing technology complements a commitment to high-performance compilers and strong graphics offerings.par This robust product line addresses the cost-driven requirements of the entry workstation market, the transaction and server requirements of the commercial market, and the computation-intensive requirements of the technical market. These hardware offerings result from a team effort by many dedicated and talented individuals from around the world. Their expertise and skill in a wide range of disciplines were key to achieving this significant step toward the goal of a comprehensive architecture. We want to thank all those involved in continuing the success of the RISC System / 6000 line.

rawabstract:
During the four years since the RISC System\slash 6000* (RS\slash 6000) announcement in February of 1990, IBM* has strengthened its product line with microprocessor enhancements, increased memory capacity, improved graphics, greatly expanded I/O adapters, and new AIX* and compiler releases. In 1991, IBM began planning for future RS\slash 6000 systems that would span the range from small, battery-operated products to very large supercomputers and mainframes. As the first step toward achieving this ``palmtop to teraFLOPS'' goal with a single architecture, IBM investigated further optimizations for the original POWER Architecture*. This effort led to the creation of the PowerPC* alliance (IBM Corporation, Motorola*, Inc., and Apple* Computer Corporation) and the definition of the PowerPC Architecture*. Today, the single-chip PowerPC 601* processor is the basis of IBM's entry systems. A more aggressively superscalar version of the original POWER processor, the multichip POWER2* processor, is exploited in our current IBM high-end RISC systems. As technology continues to advance, PowerPC implementations will provide the basis for high-performance 64-bit super servers. This special issue of the IBM Journal of Research and Development focuses on the POWER2 and PowerPC portions of IBM's wide-ranging announcement in the Fall of 1993. The new POWER2 processor nearly doubles the performance of the earlier high-end models. The PowerPC 601 processor was introduced in the RISC System\slash 6000 Model 250, the first system in the industry to use the PowerPC Architecture created by the strategic IBM/Motorola/Apple alliance. These workstations achieved industry-leading performance and price/performance on virtually every industry-standard benchmark, including SPECint92*, SPECfp92*, Linpack, TPP, TPC-A*, and TPC-C*. Compared to the 1990 offerings, SPEC performance nearly quadrupled, transaction performance improved by a factor of almost five, maximum memory capacity quadrupled, and the maximum disk capacity grew by an order of magnitude. The POWER2 design exploits both multichip technology and a larger die size to execute up to six instructions (eight operations) per clock cycle. Many of the higher-performance POWER2-based systems provide peak execution rates in excess of a half billion operations per second. The paper by White and Dhawan provides an overview of the POWER2 design. Shippy and Griffith describe the dual fixed-point unit design, the data cache unit, and the storage control unit. Hicks, Fry, and Harvey describe the dual floating-point unit design. Barreh et al. describe hardware strategies to minimize compare-branch penalties in the instruction cache unit. Welbon et al. describe a POWER2 hardware performance- monitoring facility which provides execution characteristics that can identify opportunities for application performance improvement. This facility can also be used to gather information crucial to future design decisions. Two performance papers conclude the POWER2 portion of this issue. Franklin et al. analyze some of the key POWER2 hardware contributions to performance on the commercial workloads. Agarwal, Gustavson, and Zubair relate their experiences with optimizing the high-performance Engineering/Scientific Subroutine Library (ESSL) for the POWER2 implementation. While POWER2 and PowerPC implementations provide the opportunity for high-performance systems, optimizing software is also key in delivering end-user performance. Blainey describes aspects of the TOBEY compiler, with special emphasis on instruction scheduling for the RS\slash 6000 products. Heisch describes TDPR, a prototype version of FDPR, a program restructuring tool which improves application performance by placing frequently executed code blocks so as to minimize instruction cache misses and branch penalties. IBM and the PowerPC alliance are currently developing a family of five PowerPC designs. IBM and Motorola designers at the Somerset Design Center in Austin will optimize single-chip implementations of the PowerPC Architecture for high-volume products. The high-end requirements of the large server and workstation products will be addressed with multichip PowerPC implementations from IBM.\par IBM entry-level workstation products introduced the PowerPC 601 microprocessor, the first member of the PowerPC family. The goal for the PowerPC 601 designers was to quickly bring PowerPC to the market. Vaden et al. describe the microarchitecture and performance aspects of the PowerPC 601 processor. Brodnax et al. discuss the PowerPC 601 circuitry and chip implementation details. Future products are planned that will incorporate the PowerPC 603*, PowerPC 604*, and the 64-bit PowerPC 620* implementations as they become available. In addition, the price and price/performance of the PowerPC family enable lower-cost ``RISC PCs'' to be built using PowerPC microprocessors. These ``RISC PCs'' will be developed by the IBM POWER Personal Systems Division.\par The PowerPC and POWER2 systems signify a major milestone in IBM's commitment to the ``palmtops to teraFLOPS'' strategy. The PowerPC 601 chip extends the entry products further into the high-volume market by providing exceptional performance in a low-cost single-chip microprocessor. The high-end POWER2 implementation extracts the maximum performance achievable in today's technology, thrusting the IBM RISC processors into the supercomputing and large-server environments. IBM POWER Parallel Systems extends the RS\slash 6000 processing capability by providing IBM POWER Parallel SP2* systems with up to 512 POWER/POWER2 nodes. In addition to scalability, four-way High Availability Cluster Multi-Processor (HACMP) systems provide the reliability/availability that one would expect from mainframe-class systems by supporting a ``no single point of failure'' capability, even when one processor is off line. This impressive base of processing technology complements a commitment to high-performance compilers and strong graphics offerings.\par This robust product line addresses the cost-driven requirements of the entry workstation market, the transaction and server requirements of the commercial market, and the computation-intensive requirements of the technical market. These hardware offerings result from a team effort by many dedicated and talented individuals from around the world. Their expertise and skill in a wide range of disciplines were key to achieving this significant step toward the goal of a comprehensive architecture. We want to thank all those involved in continuing the success of the RISC System\slash 6000 line.

entry:
@Article{Hester:1994:PPP,
  author =       "P. D. Hester and W. J. Filip",
  title =        "Preface: {Power2} and {PowerPC} Architecture and
                 Implementation",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "490--491",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Mon Feb 12 08:14:00 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#one",
  abstract =     "During the four years since the RISC System\slash
                 6000* (RS\slash 6000) announcement in February of 1990,
                 IBM* has strengthened its product line with
                 microprocessor enhancements, increased memory capacity,
                 improved graphics, greatly expanded I/O adapters, and
                 new AIX* and compiler releases. In 1991, IBM began
                 planning for future RS\slash 6000 systems that would
                 span the range from small, battery-operated products to
                 very large supercomputers and mainframes. As the first
                 step toward achieving this ``palmtop to teraFLOPS''
                 goal with a single architecture, IBM investigated
                 further optimizations for the original POWER
                 Architecture*. This effort led to the creation of the
                 PowerPC* alliance (IBM Corporation, Motorola*, Inc.,
                 and Apple* Computer Corporation) and the definition of
                 the PowerPC Architecture*. Today, the single-chip
                 PowerPC 601* processor is the basis of IBM's entry
                 systems. A more aggressively superscalar version of the
                 original POWER processor, the multichip POWER2*
                 processor, is exploited in our current IBM high-end
                 RISC systems. As technology continues to advance,
                 PowerPC implementations will provide the basis for
                 high-performance 64-bit super servers. This special
                 issue of the IBM Journal of Research and Development
                 focuses on the POWER2 and PowerPC portions of IBM's
                 wide-ranging announcement in the Fall of 1993. The new
                 POWER2 processor nearly doubles the performance of the
                 earlier high-end models. The PowerPC 601 processor was
                 introduced in the RISC System\slash 6000 Model 250, the
                 first system in the industry to use the PowerPC
                 Architecture created by the strategic
                 IBM/Motorola/Apple alliance. These workstations
                 achieved industry-leading performance and
                 price/performance on virtually every industry-standard
                 benchmark, including SPECint92*, SPECfp92*, Linpack,
                 TPP, TPC-A*, and TPC-C*. Compared to the 1990
                 offerings, SPEC performance nearly quadrupled,
                 transaction performance improved by a factor of almost
                 five, maximum memory capacity quadrupled, and the
                 maximum disk capacity grew by an order of magnitude.
                 The POWER2 design exploits both multichip technology
                 and a larger die size to execute up to six instructions
                 (eight operations) per clock cycle. Many of the
                 higher-performance POWER2-based systems provide peak
                 execution rates in excess of a half billion operations
                 per second. The paper by White and Dhawan provides an
                 overview of the POWER2 design. Shippy and Griffith
                 describe the dual fixed-point unit design, the data
                 cache unit, and the storage control unit. Hicks, Fry,
                 and Harvey describe the dual floating-point unit
                 design. Barreh et al. describe hardware strategies to
                 minimize compare-branch penalties in the instruction
                 cache unit. Welbon et al. describe a POWER2 hardware
                 performance- monitoring facility which provides
                 execution characteristics that can identify
                 opportunities for application performance improvement.
                 This facility can also be used to gather information
                 crucial to future design decisions. Two performance
                 papers conclude the POWER2 portion of this issue.
                 Franklin et al. analyze some of the key POWER2 hardware
                 contributions to performance on the commercial
                 workloads. Agarwal, Gustavson, and Zubair relate their
                 experiences with optimizing the high-performance
                 Engineering/Scientific Subroutine Library (ESSL) for
                 the POWER2 implementation. While POWER2 and PowerPC
                 implementations provide the opportunity for
                 high-performance systems, optimizing software is also
                 key in delivering end-user performance. Blainey
                 describes aspects of the TOBEY compiler, with special
                 emphasis on instruction scheduling for the RS\slash
                 6000 products. Heisch describes TDPR, a prototype
                 version of FDPR, a program restructuring tool which
                 improves application performance by placing frequently
                 executed code blocks so as to minimize instruction
                 cache misses and branch penalties. IBM and the PowerPC
                 alliance are currently developing a family of five
                 PowerPC designs. IBM and Motorola designers at the
                 Somerset Design Center in Austin will optimize
                 single-chip implementations of the PowerPC Architecture
                 for high-volume products. The high-end requirements of
                 the large server and workstation products will be
                 addressed with multichip PowerPC implementations from
                 IBM.\par

                 IBM entry-level workstation products introduced the
                 PowerPC 601 microprocessor, the first member of the
                 PowerPC family. The goal for the PowerPC 601 designers
                 was to quickly bring PowerPC to the market. Vaden et
                 al. describe the microarchitecture and performance
                 aspects of the PowerPC 601 processor. Brodnax et al.
                 discuss the PowerPC 601 circuitry and chip
                 implementation details. Future products are planned
                 that will incorporate the PowerPC 603*, PowerPC 604*,
                 and the 64-bit PowerPC 620* implementations as they
                 become available. In addition, the price and
                 price/performance of the PowerPC family enable
                 lower-cost ``RISC PCs'' to be built using PowerPC
                 microprocessors. These ``RISC PCs'' will be developed
                 by the IBM POWER Personal Systems Division.\par

                 The PowerPC and POWER2 systems signify a major
                 milestone in IBM's commitment to the ``palmtops to
                 teraFLOPS'' strategy. The PowerPC 601 chip extends the
                 entry products further into the high-volume market by
                 providing exceptional performance in a low-cost
                 single-chip microprocessor. The high-end POWER2
                 implementation extracts the maximum performance
                 achievable in today's technology, thrusting the IBM
                 RISC processors into the supercomputing and
                 large-server environments. IBM POWER Parallel Systems
                 extends the RS\slash 6000 processing capability by
                 providing IBM POWER Parallel SP2* systems with up to
                 512 POWER/POWER2 nodes. In addition to scalability,
                 four-way High Availability Cluster Multi-Processor
                 (HACMP) systems provide the reliability/availability
                 that one would expect from mainframe-class systems by
                 supporting a ``no single point of failure'' capability,
                 even when one processor is off line. This impressive
                 base of processing technology complements a commitment
                 to high-performance compilers and strong graphics
                 offerings.\par

                 This robust product line addresses the cost-driven
                 requirements of the entry workstation market, the
                 transaction and server requirements of the commercial
                 market, and the computation-intensive requirements of
                 the technical market. These hardware offerings result
                 from a team effort by many dedicated and talented
                 individuals from around the world. Their expertise and
                 skill in a wide range of disciplines were key to
                 achieving this significant step toward the goal of a
                 comprehensive architecture. We want to thank all those
                 involved in continuing the success of the RISC
                 System\slash 6000 line.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}


bibtype: article
filename: fparith.bib
label: Hicks:1994:PFU
author: T. N. Hicks and R. E. Fry and P. E. Harvey
title: POWER2 floating-point unit: Architecture and implementation
journal: j-IBM-JRD
volume: 38
number: 5
pages: 525--536
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: T. N. Hicks and R. E. Fry and P. E. Harvey
rawtitle: {POWER2} floating-point unit: Architecture and implementation
abstract:
The POWER2 floating-point unit (FPU) extends the concept of the innovative multiply-add fused (MAF) ALU of the RISC System/6000 processor to provide a floating-point unit that sets new standards, not only for computation capability but for data throughput and processor flexibility. The POWERS FPU achieves a performance (MFLOPS) rate never accomplished before by a personal workstation machine by: (1) integrating dual generic MAF ALUs, (2) doubling the instruction bandwidth and quadrupling the data bandwidth over that of the POWER FPU, (3) adding support for additional functions, and (4) using dynamic instruction scheduling techniques to maximize instruction-level parallelism not only among its own internal units but with the rest of the CPU.

keywords:
Data bandwidth; Dynamic instruction scheduling; Floating-point unit; Instruction bandwidth; Instruction-level parallelism; Multiply add fused arithmetic logic unit; POWER2; RISC System/6000 processor

thesaurus:
Floating point arithmetic; Microprocessor chips; Parallel architectures; Parallel processing; Reduced instruction set computing

rawabstract:
The POWER2 floating-point unit (FPU) extends the concept of the innovative multiply-add fused (MAF) ALU of the RISC System/6000 processor to provide a floating-point unit that sets new standards, not only for computation capability but for data throughput and processor flexibility. The POWERS FPU achieves a performance (MFLOPS) rate never accomplished before by a personal workstation machine by: (1) integrating dual generic MAF ALUs, (2) doubling the instruction bandwidth and quadrupling the data bandwidth over that of the POWER FPU, (3) adding support for additional functions, and (4) using dynamic instruction scheduling techniques to maximize instruction-level parallelism not only among its own internal units but with the rest of the CPU.

entry:
@Article{Hicks:1994:PFU,
  author =       "T. N. Hicks and R. E. Fry and P. E. Harvey",
  title =        "{POWER2} floating-point unit: Architecture and
                 implementation",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "525--536",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The POWER2 floating-point unit (FPU) extends the
                 concept of the innovative multiply-add fused (MAF) ALU
                 of the RISC System/6000 processor to provide a
                 floating-point unit that sets new standards, not only
                 for computation capability but for data throughput and
                 processor flexibility. The POWERS FPU achieves a
                 performance (MFLOPS) rate never accomplished before by
                 a personal workstation machine by: (1) integrating dual
                 generic MAF ALUs, (2) doubling the instruction
                 bandwidth and quadrupling the data bandwidth over that
                 of the POWER FPU, (3) adding support for additional
                 functions, and (4) using dynamic instruction scheduling
                 techniques to maximize instruction-level parallelism
                 not only among its own internal units but with the rest
                 of the CPU.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel architecture);
                 C5230 (Digital arithmetic methods)",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "Data bandwidth; Dynamic instruction scheduling;
                 Floating-point unit; Instruction bandwidth;
                 Instruction-level parallelism; Multiply add fused
                 arithmetic logic unit; POWER2; RISC System/6000
                 processor",
  thesaurus =    "Floating point arithmetic; Microprocessor chips;
                 Parallel architectures; Parallel processing; Reduced
                 instruction set computing",
}


bibtype: inproceedings
filename: fparith.bib
label: Hilker:1994:NMM
author: S. Hilker and N. Phan and D. Rainey
title: A 3.4 ns 0.8 mu m BiCMOS 53*53 b multiplier tree
crossref: Wuorinen:1994:IIS
pages: 292--293
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: IBM Corp., Rochester, MN, USA
rawauthor: S. Hilker and N. Phan and D. Rainey
rawtitle: A 3.4 ns 0.8 mu m {BiCMOS} 53*53 b multiplier tree
abstract:
A 53*53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 mu m n-well BiCMOS with 115 AA gate oxide, 0.45 mu m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.

keywords:
0.8 Micron; 200 MHz; 3.4 Ns; 3.6 V; 400 MFLOPS; 5 W; Effective channel length; Floating-point unit; IEEE double precision multiply-add operations; Latency; Multiplier tree; Multiply-add fused dataflow; N-well BiCMOS; Pipelined stages; Power dissipation; RISC processor

thesaurus:
BiCMOS integrated circuits; Digital arithmetic; Multiplying circuits; Parallel processing; Pipeline processing; Reduced instruction set computing

rawabstract:
A 53*53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 mu m n-well BiCMOS with 115 AA gate oxide, 0.45 mu m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.

entry:
@InProceedings{Hilker:1994:NMM,
  author =       "S. Hilker and N. Phan and D. Rainey",
  title =        "A 3.4 ns 0.8 mu m {BiCMOS} 53*53 b multiplier tree",
  crossref =     "Wuorinen:1994:IIS",
  pages =        "292--293",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 53*53 b multiplier tree with 3.4 ns latency, 10
                 mm/sup 2/ active area, and 5 W power dissipation at 200
                 MHz and 3.6 V supply is implemented in 0.8 mu m n-well
                 BiCMOS with 115 AA gate oxide, 0.45 mu m effective
                 channel length, and 4 levels of metal. This 3.4ns
                 low-latency multiplier is for a floating-point unit
                 (FPU) on a BiCMOS RISC processor capable of performing
                 IEEE double precision multiply-add operations in three
                 pipelined stages at 200MHz (15ns latency, 5ns
                 throughput, 400MFLOPs peak rate) using multiply-add
                 fused dataflow.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Rochester, MN, USA",
  classification = "B1265B (Logic circuits); B2570K (Mixed technology
                 integrated circuits); C5120 (Logic and switching
                 circuits); C5220P (Parallel architecture); C5230
                 (Digital arithmetic methods)",
  keywords =     "0.8 Micron; 200 MHz; 3.4 Ns; 3.6 V; 400 MFLOPS; 5 W;
                 Effective channel length; Floating-point unit; IEEE
                 double precision multiply-add operations; Latency;
                 Multiplier tree; Multiply-add fused dataflow; N-well
                 BiCMOS; Pipelined stages; Power dissipation; RISC
                 processor",
  numericalindex = "Time 3.4E-09 s; Size 8.0E-07 m; Power 5.0E+00 W;
                 Frequency 2.0E+08 Hz; Voltage 3.6E+00 V; Computer speed
                 4.0E+08 FLOPS",
  thesaurus =    "BiCMOS integrated circuits; Digital arithmetic;
                 Multiplying circuits; Parallel processing; Pipeline
                 processing; Reduced instruction set computing",
}


bibtype: book
filename: fparith.bib
label: Hill:1994:GPL
author: Patricia Hill
title: The Godel Programming Language
publisher: pub-MIT
address: pub-MIT:adr
pages: xx + 348
year: 1994
ISBN: 0-262-08229-2 OR 0262082292
ISBN13: 978-0-262-08229-7 OR 9780262082297
LCCN: QA76.73.G17H55 1994
bibdate: Thu Sep 15 07:47:50 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.15 07:47:50 ???
acknowledgement: ack-nhfb
rawauthor: Patricia Hill
rawtitle: The {G{\"o}del} Programming Language
note:
Section 13.3 (pp. 206--218) defines floating-point numbers and standard functions conforming to Version 4.0 (August 1992) of the Language Independent Arithmetic Standard (LIAS) ISO / IEC CD 10967-1:1992 (JTC1/SC22/WG11 N318, ANSI X3T3 92-064). It also conforms to the ANSI / IEEE Standard for Binary Floating-Point Arithmetic 754-1985.

rawnote:
Section 13.3 (pp. 206--218) defines floating-point numbers and standard functions conforming to Version 4.0 (August 1992) of the Language Independent Arithmetic Standard (LIAS) ISO\slash IEC CD 10967-1:1992 (JTC1/SC22/WG11 N318, ANSI X3T3 92-064). It also conforms to the ANSI\slash IEEE Standard for Binary Floating-Point Arithmetic 754-1985.

entry:
@Book{Hill:1994:GPL,
  author =       "Patricia Hill",
  title =        "The {G{\"o}del} Programming Language",
  publisher =    pub-MIT,
  address =      pub-MIT:adr,
  pages =        "xx + 348",
  year =         "1994",
  ISBN =         "0-262-08229-2",
  ISBN-13 =      "978-0-262-08229-7",
  LCCN =         "QA76.73.G17H55 1994",
  bibdate =      "Thu Sep 15 07:47:50 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Section 13.3 (pp. 206--218) defines floating-point
                 numbers and standard functions conforming to Version
                 4.0 (August 1992) of the Language Independent
                 Arithmetic Standard (LIAS) ISO\slash IEC CD
                 10967-1:1992 (JTC1/SC22/WG11 N318, ANSI X3T3 92-064).
                 It also conforms to the ANSI\slash IEEE Standard for
                 Binary Floating-Point Arithmetic 754-1985.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Hopkins:1994:CEM
author: Tim Hopkins and John Slater
title: A Comment on the Eispack Machine Epsilon Routine
type: Technical Report
number: 18-94
institution: University of Kent, Computing Laboratory, University of Kent
address: Canterbury, UK
pages: xx + 348
year: 1994
bibdate: Tue Apr 12 12:00:52 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 12:00:52 ???
URL: http://www.cs.kent.ac.uk/pubs/1994/74/content.ps.gz
acknowledgement: ack-nhfb
rawauthor: Tim Hopkins and John Slater
rawtitle: A Comment on the {Eispack} Machine Epsilon Routine
entry:
@TechReport{Hopkins:1994:CEM,
  author =       "Tim Hopkins and John Slater",
  title =        "A Comment on the {Eispack} Machine Epsilon Routine",
  type =         "Technical Report",
  number =       "18-94",
  institution =  "University of Kent, Computing Laboratory, University
                 of Kent",
  address =      "Canterbury, UK",
  year =         "1994",
  bibdate =      "Tue Apr 12 12:00:52 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.kent.ac.uk/pubs/1994/74/content.ps.gz",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Horvath:1994:PPM
author: Tamas Horvath and Spyros S. Magliveras and Tran van Trung
title: A Parallel Permutation Multiplier for a PGM Crypto-Chip
journal: j-LECT-NOTES-COMP-SCI
volume: 839
pages: 108--113
year: 1994
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Feb 5 11:49:18 MST 2002
bibtimestamp: 2002.02.05 11:49:18 MST
fjournal: Lecture Notes in Computer Science
keywords: CRYPTO; cryptology; IACR; IEEE
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Tam{\'a}s Horv{\'a}th and Spyros S. Magliveras and Tran van Trung
rawtitle: A Parallel Permutation Multiplier for a {PGM} Crypto-Chip
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t0839.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/0839/08390108.htm; http://link.springer-ny.com/link/service/series/0558/papers/0839/08390108.pdf

entry:
@Article{Horvath:1994:PPM,
  author =       "Tam{\'a}s Horv{\'a}th and Spyros S. Magliveras and
                 Tran van Trung",
  title =        "A Parallel Permutation Multiplier for a {PGM}
                 Crypto-Chip",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "839",
  pages =        "108--113",
  year =         "1994",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Feb 5 11:49:18 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t0839.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/0839/08390108.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/0839/08390108.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "CRYPTO; cryptology; IACR; IEEE",
}


bibtype: article
filename: fparith.bib
label: Hsu:1994:CPF
author: Chau-Yun Hsu and Jui Chi Yao
title: Comparative performance of fast cosine transform with fixed-point roundoff error analysis
journal: j-IEEE-TRANS-SIG-PROC
volume: 42
number: 5
pages: 1256--1259
month: may
monthnumber: 5
year: 1994
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Chau-Yun Hsu and Jui Chi Yao
rawtitle: Comparative performance of fast cosine transform with fixed-point roundoff error analysis
entry:
@Article{Hsu:1994:CPF,
  author =       "Chau-Yun Hsu and Jui Chi Yao",
  title =        "Comparative performance of fast cosine transform with
                 fixed-point roundoff error analysis",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "42",
  number =       "5",
  pages =        "1256--1259",
  month =        may,
  year =         "1994",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "Suitable scaling schemes are chosen for the Lee's and
                 the Hou's (1984) fast DCT algorithms, and the relative
                 fixed-point roundoff error analyses are carried out,
                 respectively. The average output signal-to-noise ratio
                 are then calculated, and it is \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hsu:1994:NFP
author: Chau-Yun Hsu
title: Novel fixed-point roundoff analysis of the decimation-in-time FHT
journal: j-IEEE-TRANS-SIG-PROC
volume: 42
number: 1
pages: 206--208
month: jan
monthnumber: 1
year: 1994
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Chau-Yun Hsu
rawtitle: Novel fixed-point roundoff analysis of the decimation-in-time {FHT}
entry:
@Article{Hsu:1994:NFP,
  author =       "Chau-Yun Hsu",
  title =        "Novel fixed-point roundoff analysis of the
                 decimation-in-time {FHT}",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "42",
  number =       "1",
  pages =        "206--208",
  month =        jan,
  year =         "1994",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "A least upper bound for the increasing factor of the
                 magnitude of the decimation-in-time fast Hartley
                 transform (FHT) in fixed-point arithmetic is developed
                 and a new scaling model for the roundoff analysis in
                 the fixed-point arithmetic computation \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hull:1994:ICE
author: T. E. Hull and Thomas F. Fairgrieve and Ping Tak Peter Tang
title: Implementing Complex Elementary Functions Using Exception Handling
journal: j-TOMS
volume: 20
number: 2
pages: 215--244
month: jun
monthnumber: 6
year: 1994
CODEN: ACMSCU
DOI: https://doi.org/10.1145/178365.178404
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Mar 21 15:10:29 1995
bibtimestamp: 1995.03.21 15:10:29 ???
URL: http://www.acm.org/pubs/citations/journals/toms/1994-20-2/p215-hull/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: algorithms; complex elementary functions; design; implementation
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: T. E. Hull and Thomas F. Fairgrieve and Ping Tak Peter Tang
rawtitle: Implementing Complex Elementary Functions Using Exception Handling
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

note:
See correction cite Anonymous:1994:C, and improved analysis, tightened bounds, and exhibition of worst cases for complex square roots cite Jeannerod:2017:REC.

abstract:
Algorithms are developed for reliable and accurate evaluations of the complex elementary functions required in Fortran 77 and Fortran 90, namely cabs, csqrt, cexp, clog, csin, and ccos. The algorithms are presented in a pseudocode that has a convenient exception-handling facility. A tight error bound is derived for each algorithm. Corresponding Fortran programs for an IEEE environment have also been developed to illustrate the practicality of the algorithms, and these programs have been tested very carefully to help confirm the correctness of the algorithms and their error bounds. The results are of these tests are included in the paper, but the Fortran programs are not; the programs are available from Fairgrieve, (tff@cs.toronto.edu).

subject:
G.1.0 [Numerical Analysis]: General--error analysis; numerical algorithms; G.1.2 [Numerical Analysis]: Approximation--elementary function approximation; G.4 [Mathematics of Computing]: Mathematical Software--algorithm analysis; reliability and robustness; verification

rawabstract:
Algorithms are developed for reliable and accurate evaluations of the complex elementary functions required in Fortran 77 and Fortran 90, namely cabs, csqrt, cexp, clog, csin, and ccos. The algorithms are presented in a pseudocode that has a convenient exception-handling facility. A tight error bound is derived for each algorithm. Corresponding Fortran programs for an IEEE environment have also been developed to illustrate the practicality of the algorithms, and these programs have been tested very carefully to help confirm the correctness of the algorithms and their error bounds. The results are of these tests are included in the paper, but the Fortran programs are not; the programs are available from Fairgrieve, (tff@cs.toronto.edu).

rawnote:
See correction \cite{Anonymous:1994:C}, and improved analysis, tightened bounds, and exhibition of worst cases for complex square roots \cite{Jeannerod:2017:REC}.

entry:
@Article{Hull:1994:ICE,
  author =       "T. E. Hull and Thomas F. Fairgrieve and Ping Tak Peter
                 Tang",
  title =        "Implementing Complex Elementary Functions Using
                 Exception Handling",
  journal =      j-TOMS,
  volume =       "20",
  number =       "2",
  pages =        "215--244",
  month =        jun,
  year =         "1994",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/178365.178404",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Mar 21 15:10:29 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "See correction \cite{Anonymous:1994:C}, and improved
                 analysis, tightened bounds, and exhibition of worst
                 cases for complex square roots
                 \cite{Jeannerod:2017:REC}.",
  URL =          "http://www.acm.org/pubs/citations/journals/toms/1994-20-2/p215-hull/",
  abstract =     "Algorithms are developed for reliable and accurate
                 evaluations of the complex elementary functions
                 required in Fortran 77 and Fortran 90, namely cabs,
                 csqrt, cexp, clog, csin, and ccos. The algorithms are
                 presented in a pseudocode that has a convenient
                 exception-handling facility. A tight error bound is
                 derived for each algorithm. Corresponding Fortran
                 programs for an IEEE environment have also been
                 developed to illustrate the practicality of the
                 algorithms, and these programs have been tested very
                 carefully to help confirm the correctness of the
                 algorithms and their error bounds. The results are of
                 these tests are included in the paper, but the Fortran
                 programs are not; the programs are available from
                 Fairgrieve, (tff@cs.toronto.edu).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "algorithms; complex elementary functions; design;
                 implementation",
  subject =      "G.1.0 [Numerical Analysis]: General--error analysis;
                 numerical algorithms; G.1.2 [Numerical Analysis]:
                 Approximation--elementary function approximation; G.4
                 [Mathematics of Computing]: Mathematical
                 Software--algorithm analysis; reliability and
                 robustness; verification",
}


