# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Kaul:2019:OFF
author: Himanshu Kaul and Mark Anders and Sanu Mathew and Seongjong Kim and Ram Krishnamurthy
title: Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators
crossref: Takagi:2019:ISC
pages: 84--87
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00021
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Himanshu Kaul and Mark Anders and Sanu Mathew and Seongjong Kim and Ram Krishnamurthy
rawtitle: Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators
abstract:
This paper describes optimizations for the critical maximum exponent and alignment operations, with scalability for many-term fused floating-point dot-product units. The impact of these optimizations is quantified for up to 32-term BFloat16 weight/activation inputs with single-precision dot-product output, targeted for machine learning accelerators. Area and energy efficiency results are compared across performance targets, design parameters, and data statistics.

keywords:
32-term BFloat16 weight inputs; Adders; alignment operation; ARITH-26; Computer architecture; critical maximum exponent operation; deep neural networks; dot-product; Energy efficiency; floating point arithmetic; floating-point; Hardware; learning (artificial intelligence); Machine learning; machine learning; machine learning accelerators; neural nets; Optimization; optimized fused floating-point many-term dot-product hardware; single-precision dot-product output; Throughput

rawabstract:
This paper describes optimizations for the critical maximum exponent and alignment operations, with scalability for many-term fused floating-point dot-product units. The impact of these optimizations is quantified for up to 32-term BFloat16 weight/activation inputs with single-precision dot-product output, targeted for machine learning accelerators. Area and energy efficiency results are compared across performance targets, design parameters, and data statistics.

entry:
@InProceedings{Kaul:2019:OFF,
  author =       "Himanshu Kaul and Mark Anders and Sanu Mathew and
                 Seongjong Kim and Ram Krishnamurthy",
  title =        "Optimized Fused Floating-Point Many-Term Dot-Product
                 Hardware for Machine Learning Accelerators",
  crossref =     "Takagi:2019:ISC",
  pages =        "84--87",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00021",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes optimizations for the critical
                 maximum exponent and alignment operations, with
                 scalability for many-term fused floating-point
                 dot-product units. The impact of these optimizations is
                 quantified for up to 32-term BFloat16 weight/activation
                 inputs with single-precision dot-product output,
                 targeted for machine learning accelerators. Area and
                 energy efficiency results are compared across
                 performance targets, design parameters, and data
                 statistics.",
  acknowledgement = ack-nhfb,
  keywords =     "32-term BFloat16 weight inputs; Adders; alignment
                 operation; ARITH-26; Computer architecture; critical
                 maximum exponent operation; deep neural networks;
                 dot-product; Energy efficiency; floating point
                 arithmetic; floating-point; Hardware; learning
                 (artificial intelligence); Machine learning; machine
                 learning; machine learning accelerators; neural nets;
                 Optimization; optimized fused floating-point many-term
                 dot-product hardware; single-precision dot-product
                 output; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Kim:2019:CEI
author: HyunJin Kim and Min Soo Kim and Alberto A. Del Barrio and Nader Bagherzadeh
title: A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
crossref: Takagi:2019:ISC
pages: 108--111
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00029
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: HyunJin Kim and Min Soo Kim and Alberto A. {Del Barrio} and Nader Bagherzadeh
rawtitle: A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
abstract:
This paper proposes a cost-efficient approximate logarithmic multiplication for convolutional neural networks (CNNs), where two truncated logarithmic multipliers are connected for error correction. The proposed iterative logarithmic multiplication achieves low and unbiased average error while the hardware cost is significantly reduced by utilizing the truncated Mitchell multiplier and approximating error terms from the first stage. The proposed design has error characteristics that are suitable for neural network inferences, and the experiments on contemporary CNNs show that the proposed multiplier does not cause significant degradation on accuracy compared to exact multiplication.

keywords:
Adders; approximate multiplier; ARITH-26; convolutional neural nets; convolutional neural network; convolutional neural networks; Convolutional neural networks; cost-efficient approximate logarithmic multiplication; Delays; Detectors; Digital arithmetic; error correction; Hardware; iterative methods; iterative truncated logarithmic multiplication; logarithmic multiplication; Mitchell multiplier; neural network inferences; truncated logarithmic multipliers; truncated Mitchell multiplier

rawabstract:
This paper proposes a cost-efficient approximate logarithmic multiplication for convolutional neural networks (CNNs), where two truncated logarithmic multipliers are connected for error correction. The proposed iterative logarithmic multiplication achieves low and unbiased average error while the hardware cost is significantly reduced by utilizing the truncated Mitchell multiplier and approximating error terms from the first stage. The proposed design has error characteristics that are suitable for neural network inferences, and the experiments on contemporary CNNs show that the proposed multiplier does not cause significant degradation on accuracy compared to exact multiplication.

entry:
@InProceedings{Kim:2019:CEI,
  author =       "HyunJin Kim and Min Soo Kim and Alberto A. {Del
                 Barrio} and Nader Bagherzadeh",
  title =        "A Cost-Efficient Iterative Truncated Logarithmic
                 Multiplication for Convolutional Neural Networks",
  crossref =     "Takagi:2019:ISC",
  pages =        "108--111",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00029",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper proposes a cost-efficient approximate
                 logarithmic multiplication for convolutional neural
                 networks (CNNs), where two truncated logarithmic
                 multipliers are connected for error correction. The
                 proposed iterative logarithmic multiplication achieves
                 low and unbiased average error while the hardware cost
                 is significantly reduced by utilizing the truncated
                 Mitchell multiplier and approximating error terms from
                 the first stage. The proposed design has error
                 characteristics that are suitable for neural network
                 inferences, and the experiments on contemporary CNNs
                 show that the proposed multiplier does not cause
                 significant degradation on accuracy compared to exact
                 multiplication.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; approximate multiplier; ARITH-26;
                 convolutional neural nets; convolutional neural
                 network; convolutional neural networks; Convolutional
                 neural networks; cost-efficient approximate logarithmic
                 multiplication; Delays; Detectors; Digital arithmetic;
                 error correction; Hardware; iterative methods;
                 iterative truncated logarithmic multiplication;
                 logarithmic multiplication; Mitchell multiplier; neural
                 network inferences; truncated logarithmic multipliers;
                 truncated Mitchell multiplier",
}


bibtype: article
filename: fparith.bib
label: Kim:2019:EMA
author: M. S. Kim and A. A. D. Barrio and L. T. Oliveira and R. Hermida and N. Bagherzadeh
title: Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 660--675
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2880742
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. S. Kim and A. A. D. Barrio and L. T. Oliveira and R. Hermida and N. Bagherzadeh
rawtitle: Efficient {Mitchell}'s Approximate Log Multipliers for Convolutional Neural Networks
keywords:
approximate log multipliers; Approximation algorithms; approximation theory; Arithmetic and logic units; CNN; computer vision; convolutional neural nets; convolutional neural networks; Convolutional neural networks; customizable design; customizable log multiplier; Degradation; design techniques; efficient shift amount calculation; Energy consumption; energy consumption reduction; energy-efficient approximate multipliers; exact zero computation; floating point arithmetic; fully-parallel LOD; ImageNet ILSVRC2012 dataset; Logic gates; low-power design; machine learning; multiplying circuits; object recognition; power aware computing; probability; Training

entry:
@Article{Kim:2019:EMA,
  author =       "M. S. Kim and A. A. D. Barrio and L. T. Oliveira and
                 R. Hermida and N. Bagherzadeh",
  title =        "Efficient {Mitchell}'s Approximate Log Multipliers for
                 Convolutional Neural Networks",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "660--675",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2880742",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "approximate log multipliers; Approximation algorithms;
                 approximation theory; Arithmetic and logic units; CNN;
                 computer vision; convolutional neural nets;
                 convolutional neural networks; Convolutional neural
                 networks; customizable design; customizable log
                 multiplier; Degradation; design techniques; efficient
                 shift amount calculation; Energy consumption; energy
                 consumption reduction; energy-efficient approximate
                 multipliers; exact zero computation; floating point
                 arithmetic; fully-parallel LOD; ImageNet ILSVRC2012
                 dataset; Logic gates; low-power design; machine
                 learning; multiplying circuits; object recognition;
                 power aware computing; probability; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Klower:2019:PAF
author: Milan Klower and Peter D. Duben and Tim N. Palmer
title: Posits as an Alternative to Floats for Weather and Climate Models
crossref: Gustafson:2019:CPC
pages: 1:1--1:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316281
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
acknowledgement: ack-nhfb
articleno: 2
rawauthor: Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N. Palmer
rawtitle: Posits as an Alternative to Floats for Weather and Climate Models
keywords:
Computational fluid dynamics, floating point, computer arithmetic, posits, reduced precision, climate projections, weather forecast

entry:
@InProceedings{Klower:2019:PAF,
  author =       "Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N.
                 Palmer",
  title =        "Posits as an Alternative to Floats for Weather and
                 Climate Models",
  crossref =     "Gustafson:2019:CPC",
  pages =        "1:1--1:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316281",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  keywords =     "Computational fluid dynamics, floating point, computer
                 arithmetic, posits, reduced precision, climate
                 projections, weather forecast",
  location =     "Singapore, Singapore",
  numpages =     "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Kostic:2019:UNV
author: Dusan Kostic and Shay Gueron
title: Using the New VPMADD Instructions for the New Post Quantum Key Encapsulation Mechanism SIKE
crossref: Takagi:2019:ISC
pages: 215--218
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00050
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Dusan Kostic and Shay Gueron
rawtitle: Using the New {VPMADD} Instructions for the New Post Quantum Key Encapsulation Mechanism {SIKE}
abstract:
This paper demonstrates the use of new processor instructions VPMADD, intended to appear in the coming generation of Intel processors (codename ``Cannon Lake''), in order to accelerate the newly proposed key encapsulation mechanism (KEM) named SIKE. SIKE is one of the submissions to the NIST standardization process on post-quantum cryptography, and is based on pseudo-random walks in supersingular isogeny graphs. While very small keys are the main advantage of SIKE, its extreme computational intensiveness makes it one of the slowest KEM proposals. Performance optimizations are needed. We address here the ``Level 1'' parameters that target 64-bit quantum security, and deemed sufficient for the NIST standardization effort. Thus, we focus on SIKE503 that operates over Fp2 with a 503-bit prime p. These short operands pose a significant challenge on using VPMADD effectively. We demonstrate several optimization methods to accelerate Fp, Fp2, and the elliptic curve arithmetic, and predict a potential speedup by a factor of 1.72x.

keywords:
ARITH-26; codename CannonLake; Computer architecture; Encapsulation; extreme computational intensiveness; Intel processors; KEM proposals; key encapsulation mechanism; NIST; NIST standardization effort; NIST standardization process; Optimization; post quantum key encapsulation mechanism SIKE; post-quantum cryptography; processor instructions VPMADD; Proposals; pseudorandom walks; Quantum computing; quantum cryptography; quantum security; Registers; SIKE503; supersingular isogeny graphs; VPMADD instructions; VPMADD processor instructions, software optimization, post quantum cryptography, supersingular isogeny

rawabstract:
This paper demonstrates the use of new processor instructions VPMADD, intended to appear in the coming generation of Intel processors (codename ``Cannon Lake''), in order to accelerate the newly proposed key encapsulation mechanism (KEM) named SIKE. SIKE is one of the submissions to the NIST standardization process on post-quantum cryptography, and is based on pseudo-random walks in supersingular isogeny graphs. While very small keys are the main advantage of SIKE, its extreme computational intensiveness makes it one of the slowest KEM proposals. Performance optimizations are needed. We address here the ``Level 1'' parameters that target 64-bit quantum security, and deemed sufficient for the NIST standardization effort. Thus, we focus on SIKE503 that operates over Fp2 with a 503-bit prime p. These short operands pose a significant challenge on using VPMADD effectively. We demonstrate several optimization methods to accelerate Fp, Fp2, and the elliptic curve arithmetic, and predict a potential speedup by a factor of 1.72x.

entry:
@InProceedings{Kostic:2019:UNV,
  author =       "Dusan Kostic and Shay Gueron",
  title =        "Using the New {VPMADD} Instructions for the New Post
                 Quantum Key Encapsulation Mechanism {SIKE}",
  crossref =     "Takagi:2019:ISC",
  pages =        "215--218",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00050",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper demonstrates the use of new processor
                 instructions VPMADD, intended to appear in the coming
                 generation of Intel processors (codename ``Cannon
                 Lake''), in order to accelerate the newly proposed key
                 encapsulation mechanism (KEM) named SIKE. SIKE is one
                 of the submissions to the NIST standardization process
                 on post-quantum cryptography, and is based on
                 pseudo-random walks in supersingular isogeny graphs.
                 While very small keys are the main advantage of SIKE,
                 its extreme computational intensiveness makes it one of
                 the slowest KEM proposals. Performance optimizations
                 are needed. We address here the ``Level 1'' parameters
                 that target 64-bit quantum security, and deemed
                 sufficient for the NIST standardization effort. Thus,
                 we focus on SIKE503 that operates over Fp2 with a
                 503-bit prime p. These short operands pose a
                 significant challenge on using VPMADD effectively. We
                 demonstrate several optimization methods to accelerate
                 Fp, Fp2, and the elliptic curve arithmetic, and predict
                 a potential speedup by a factor of 1.72x.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; codename CannonLake; Computer architecture;
                 Encapsulation; extreme computational intensiveness;
                 Intel processors; KEM proposals; key encapsulation
                 mechanism; NIST; NIST standardization effort; NIST
                 standardization process; Optimization; post quantum key
                 encapsulation mechanism SIKE; post-quantum
                 cryptography; processor instructions VPMADD; Proposals;
                 pseudorandom walks; Quantum computing; quantum
                 cryptography; quantum security; Registers; SIKE503;
                 supersingular isogeny graphs; VPMADD instructions;
                 VPMADD processor instructions, software optimization,
                 post quantum cryptography, supersingular isogeny",
}


bibtype: inproceedings
filename: fparith.bib
label: Kouya:2019:PEE
author: Tomonori Kouya
crossref: Takagi:2019:ISC
pages: 120--123
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00032
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Tomonori Kouya
title:
Performance Evaluation of an Efficient Double-Double BLAS1 Function With Error-Free Transformation and its Application to Explicit Extrapolation Methods

abstract:
Error-free transformation (EFT) has been recently applied to solve ill-conditioned problems. This transformation can reduce the number of arithmetic operations required compared to multiple precision arithmetic. In this study, we implement double-double (DD) BLAS1 functions with EFT and propose the application of the approach to explicit extrapolation methods for solving initial value problems of ordinary differential equations (ODEs). The presented routines can be effective for a large system of linear ODEs, especially when a harmonic sequence is used.

keywords:
ARITH-26; arithmetic operations; BLAS1 functions; Convergence; differential equations; efficient double-double BLAS1 function; EFT; error-free transformation; error-free transformation, extrapolation, ordinary differential equation; explicit extrapolation methods; extrapolation; Extrapolation; floating point arithmetic; Harmonic analysis; harmonic sequence; ill-conditioned problems; initial value problems; Libraries; mathematics computing; multiple precision arithmetic; ordinary differential equations; performance evaluation; Silicon; Standards

rawabstract:
Error-free transformation (EFT) has been recently applied to solve ill-conditioned problems. This transformation can reduce the number of arithmetic operations required compared to multiple precision arithmetic. In this study, we implement double-double (DD) BLAS1 functions with EFT and propose the application of the approach to explicit extrapolation methods for solving initial value problems of ordinary differential equations (ODEs). The presented routines can be effective for a large system of linear ODEs, especially when a harmonic sequence is used.

rawtitle:
Performance Evaluation of an Efficient Double-Double {BLAS1} Function With Error-Free Transformation and its Application to Explicit Extrapolation Methods

entry:
@InProceedings{Kouya:2019:PEE,
  author =       "Tomonori Kouya",
  title =        "Performance Evaluation of an Efficient Double-Double
                 {BLAS1} Function With Error-Free Transformation and its
                 Application to Explicit Extrapolation Methods",
  crossref =     "Takagi:2019:ISC",
  pages =        "120--123",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00032",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Error-free transformation (EFT) has been recently
                 applied to solve ill-conditioned problems. This
                 transformation can reduce the number of arithmetic
                 operations required compared to multiple precision
                 arithmetic. In this study, we implement double-double
                 (DD) BLAS1 functions with EFT and propose the
                 application of the approach to explicit extrapolation
                 methods for solving initial value problems of ordinary
                 differential equations (ODEs). The presented routines
                 can be effective for a large system of linear ODEs,
                 especially when a harmonic sequence is used.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic operations; BLAS1 functions;
                 Convergence; differential equations; efficient
                 double-double BLAS1 function; EFT; error-free
                 transformation; error-free transformation,
                 extrapolation, ordinary differential equation; explicit
                 extrapolation methods; extrapolation; Extrapolation;
                 floating point arithmetic; Harmonic analysis; harmonic
                 sequence; ill-conditioned problems; initial value
                 problems; Libraries; mathematics computing; multiple
                 precision arithmetic; ordinary differential equations;
                 performance evaluation; Silicon; Standards",
}


bibtype: article
filename: fparith.bib
label: Kulisch:2019:MSI
author: Ulrich Kulisch
title: Mathematics and Speed for Interval Arithmetic: A Complement to IEEE 1788
journal: j-TOMS
volume: 45
number: 1
pages: 5:1--5:22
month: mar
monthnumber: 3
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3264448
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon May 6 18:23:42 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2019.05.06 18:23:42 MDT
URL: https://dl.acm.org/citation.cfm?id=3264448
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 5
journalURL: https://dl.acm.org/loi/toms
rawauthor: Ulrich Kulisch
rawtitle: Mathematics and Speed for Interval Arithmetic: A Complement to {IEEE 1788}
abstract:
After a short introduction, the article begins with an axiomatic definition of rounded arithmetic. The concepts of rounding and of rounded arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set IR of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the arithmetic operations of floating-point intervals of IF, which are executable on the computer. Arithmetic for intervals of IF forms an exception free calculus, i.e., arithmetic operations for intervals of IF always lead to intervals of IF again. Later sections are concerned with programming support and hardware for interval arithmetic. Both are a must and absolutely necessary to move interval arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval arithmetic. Section 9 illustrates that interval arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

rawabstract:
After a short introduction, the article begins with an axiomatic definition of rounded arithmetic. The concepts of rounding and of rounded arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set {\=I}R of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the arithmetic operations of floating-point intervals of {\=I}F, which are executable on the computer. Arithmetic for intervals of {\=I}F forms an exception free calculus, i.e., arithmetic operations for intervals of {\=I}F always lead to intervals of {\=I}F again. Later sections are concerned with programming support and hardware for interval arithmetic. Both are a must and absolutely necessary to move interval arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval arithmetic. Section 9 illustrates that interval arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

entry:
@Article{Kulisch:2019:MSI,
  author =       "Ulrich Kulisch",
  title =        "Mathematics and Speed for Interval Arithmetic: A
                 Complement to {IEEE 1788}",
  journal =      j-TOMS,
  volume =       "45",
  number =       "1",
  pages =        "5:1--5:22",
  month =        mar,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3264448",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon May 6 18:23:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3264448",
  abstract =     "After a short introduction, the article begins with an
                 axiomatic definition of rounded arithmetic. The
                 concepts of rounding and of rounded arithmetic
                 operations are defined in an axiomatic manner fully
                 independent of special data formats and encodings.
                 Basic properties of floating-point and interval
                 arithmetic can directly be derived from this abstract
                 mathematical model. Interval operations are defined as
                 set operations for elements of the set {\=I}R of closed
                 and connected sets of real numbers. As such, they form
                 an algebraically closed subset of the powerset of the
                 real numbers. This property leads to explicit formulas
                 for the arithmetic operations of floating-point
                 intervals of {\=I}F, which are executable on the
                 computer. Arithmetic for intervals of {\=I}F forms an
                 exception free calculus, i.e., arithmetic operations
                 for intervals of {\=I}F always lead to intervals of
                 {\=I}F again. Later sections are concerned with
                 programming support and hardware for interval
                 arithmetic. Both are a must and absolutely necessary to
                 move interval arithmetic more into the center of
                 scientific computing. With some minor hardware
                 additions, interval operations can be made as fast as
                 simple floating-point operations. In vector and matrix
                 spaces for real, complex, and interval data, the dot
                 product is a fundamental arithmetic operation.
                 Computing the dot product of two vectors with
                 floating-point components exactly substantially speeds
                 up floating-point and interval arithmetic as well as
                 the accuracy of the computed result. Hardware needed
                 for the exact dot product is very modest. The exact dot
                 product is essential for long real and long interval
                 arithmetic. Section 9 illustrates that interval
                 arithmetic as developed in this article already has a
                 long tradition. Products based on these ideas have been
                 available since 1980. Implementing what the article
                 advocates would have a profound effect on mathematical
                 software. Modern processor architecture from Intel, for
                 example, comes quite close to what is requested in this
                 article.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Laguna:2019:FDF
author: Ignacio Laguna
editor: IEEE / ACM
title: FPChecker: Detecting Floating-Point Exceptions in GPU Applications
publisher: pub-ACM
address: pub-ACM:adr
pages: 1126--1129
month: nov
monthnumber: 11
year: 2019
DOI: https://doi.org/10.1109/ase.2019.00118
ISBN: 1-72812-508-1 OR 1728125081
ISBN13: 978-1-72812-508-4 OR 9781728125084
LCCN: QA76.758 .Z566 2019
bibdate: Mon Sep 11 07:07:01 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:07:01 ???
acknowledgement: ack-nhfb
bookpages: xxxv + 1296
rawauthor: Ignacio Laguna
raweditor: IEEE\slash ACM
rawtitle: {FPChecker}: Detecting Floating-Point Exceptions in {GPU} Applications
booktitle:
ASE'19: 34th IEEE / ACM International Conference on Automated Software Engineering, San Diego, California, November 10--15, 2019

abstract:
Floating-point arithmetic is widely used in applications from several fields including scientific computing, machine learning, graphics, and finance. Many of these applications are rapidly adopting the use of GPUs to speedup computations. GPUs, however, have limited support to detect floating-point exceptions, which hinders the development of reliable applications in GPU-based systems. We present FPCHECKER, the first tool to automatically detect floating-point exceptions in GPU applications. FPCHECKER uses the clang / LLVM compiler to instrument GPU kernels and to detect exceptions at runtime. Once an exception is detected, it reports to the programmer the code location of the exception as well as other useful information. The programmer can then use this report to avoid the exception, e.g., by modifying the application algorithm or changing the input. We present the design of FPCHECKER, an evaluation of the overhead of the tool, and a real-world case scenario on which the tool is used to identify a hidden exception. The slowdown of FPCHECKER is moderate and the code is publicly available as open source.

rawabstract:
Floating-point arithmetic is widely used in applications from several fields including scientific computing, machine learning, graphics, and finance. Many of these applications are rapidly adopting the use of GPUs to speedup computations. GPUs, however, have limited support to detect floating-point exceptions, which hinders the development of reliable applications in GPU-based systems. We present FPCHECKER, the first tool to automatically detect floating-point exceptions in GPU applications. FPCHECKER uses the clang\slash LLVM compiler to instrument GPU kernels and to detect exceptions at runtime. Once an exception is detected, it reports to the programmer the code location of the exception as well as other useful information. The programmer can then use this report to avoid the exception, e.g., by modifying the application algorithm or changing the input. We present the design of FPCHECKER, an evaluation of the overhead of the tool, and a real-world case scenario on which the tool is used to identify a hidden exception. The slowdown of FPCHECKER is moderate and the code is publicly available as open source.

rawbooktitle:
{ASE'19: 34th IEEE\slash ACM International Conference on Automated Software Engineering, San Diego, California, November 10--15, 2019}

entry:
@InProceedings{Laguna:2019:FDF,
  author =       "Ignacio Laguna",
  editor =       "IEEE\slash ACM",
  booktitle =    "{ASE'19: 34th IEEE\slash ACM International Conference
                 on Automated Software Engineering, San Diego,
                 California, November 10--15, 2019}",
  title =        "{FPChecker}: Detecting Floating-Point Exceptions in
                 {GPU} Applications",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  bookpages =    "xxxv + 1296",
  pages =        "1126--1129",
  month =        nov,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ase.2019.00118",
  ISBN =         "1-72812-508-1",
  ISBN-13 =      "978-1-72812-508-4",
  LCCN =         "QA76.758 .Z566 2019",
  bibdate =      "Mon Sep 11 07:07:01 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating-point arithmetic is widely used in
                 applications from several fields including scientific
                 computing, machine learning, graphics, and finance.
                 Many of these applications are rapidly adopting the use
                 of GPUs to speedup computations. GPUs, however, have
                 limited support to detect floating-point exceptions,
                 which hinders the development of reliable applications
                 in GPU-based systems. We present FPCHECKER, the first
                 tool to automatically detect floating-point exceptions
                 in GPU applications. FPCHECKER uses the clang\slash
                 LLVM compiler to instrument GPU kernels and to detect
                 exceptions at runtime. Once an exception is detected,
                 it reports to the programmer the code location of the
                 exception as well as other useful information. The
                 programmer can then use this report to avoid the
                 exception, e.g., by modifying the application algorithm
                 or changing the input. We present the design of
                 FPCHECKER, an evaluation of the overhead of the tool,
                 and a real-world case scenario on which the tool is
                 used to identify a hidden exception. The slowdown of
                 FPCHECKER is moderate and the code is publicly
                 available as open source.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Laguna:2019:GPD
author: Ignacio Laguna and Paul C. Wood and Ranvijay Singh and Saurabh Bagchi
title: GPUMixer: Performance-Driven Floating-Point Tuning for GPU Scientific Applications
type: Report
institution: Lawrence Livermore National Laboratory
address: Livermore CA 94550, USA
pages: 1126--1129
year: 2019
bibdate: Tue Aug 06 05:54:23 2019
bibtimestamp: 2019.08.06 05:54:23 ???
remark: Best paper award at the 33rd ISC High Performance conference held June 16--20, 2019.
acknowledgement: ack-nhfb
rawauthor: Ignacio Laguna and Paul C. Wood and Ranvijay Singh and Saurabh Bagchi
rawtitle: {GPUMixer}: Performance-Driven Floating-Point Tuning for {GPU} Scientific Applications
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/multithreading.bib; https://www.math.utah.edu/pub/tex/bib/pvm.bib

URL:
http://lagunaresearch.org/docs/isc-2019.pdf; https://www.hpcwire.com/2019/08/05/llnl-purdue-researchers-harness-gpu-mixed-precision-for-accuracy-performance-tradeoff/

abstract:
We present GPUMixer, a tool to perform mixed-precision floating-point tuning on scientific GPU applications. While precision tuning techniques are available, they are designed for serial programs and are accuracy-driven, i.e., they consider configurations that satisfy accuracy constraints, but these configurations may degrade performance. GPUMixer, in contrast, presents a performance-driven approach for tuning. We introduce a novel static analysis that finds Fast Imprecise Sets (FISets), sets of operations on low precision that minimize type conversions, which often yield performance speedups. To estimate the relative error introduced by GPU mixed-precision, we propose shadow computations analysis for GPUs, the first of this class for multi-threaded applications. GPUMixer obtains performance improvements of up to 46.4% of the ideal speedup in comparison to only 20.7% found by state-of-the-art methods.

rawabstract:
We present GPUMixer, a tool to perform mixed-precision floating-point tuning on scientific GPU applications. While precision tuning techniques are available, they are designed for serial programs and are accuracy-driven, i.e., they consider configurations that satisfy accuracy constraints, but these configurations may degrade performance. GPUMixer, in contrast, presents a performance-driven approach for tuning. We introduce a novel static analysis that finds Fast Imprecise Sets (FISets), sets of operations on low precision that minimize type conversions, which often yield performance speedups. To estimate the relative error introduced by GPU mixed-precision, we propose shadow computations analysis for GPUs, the first of this class for multi-threaded applications. GPUMixer obtains performance improvements of up to 46.4\% of the ideal speedup in comparison to only 20.7\% found by state-of-the-art methods.

entry:
@TechReport{Laguna:2019:GPD,
  author =       "Ignacio Laguna and Paul C. Wood and Ranvijay Singh and
                 Saurabh Bagchi",
  title =        "{GPUMixer}: Performance-Driven Floating-Point Tuning
                 for {GPU} Scientific Applications",
  type =         "Report",
  institution =  "Lawrence Livermore National Laboratory",
  address =      "Livermore CA 94550, USA",
  year =         "2019",
  bibdate =      "Tue Aug 06 05:54:23 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/multithreading.bib;
                 https://www.math.utah.edu/pub/tex/bib/pvm.bib",
  URL =          "http://lagunaresearch.org/docs/isc-2019.pdf;
                 https://www.hpcwire.com/2019/08/05/llnl-purdue-researchers-harness-gpu-mixed-precision-for-accuracy-performance-tradeoff/",
  abstract =     "We present GPUMixer, a tool to perform mixed-precision
                 floating-point tuning on scientific GPU applications.
                 While precision tuning techniques are available, they
                 are designed for serial programs and are
                 accuracy-driven, i.e., they consider configurations
                 that satisfy accuracy constraints, but these
                 configurations may degrade performance. GPUMixer, in
                 contrast, presents a performance-driven approach for
                 tuning. We introduce a novel static analysis that finds
                 Fast Imprecise Sets (FISets), sets of operations on low
                 precision that minimize type conversions, which often
                 yield performance speedups. To estimate the relative
                 error introduced by GPU mixed-precision, we propose
                 shadow computations analysis for GPUs, the first of
                 this class for multi-threaded applications. GPUMixer
                 obtains performance improvements of up to 46.4\% of the
                 ideal speedup in comparison to only 20.7\% found by
                 state-of-the-art methods.",
  acknowledgement = ack-nhfb,
  remark =       "Best paper award at the 33rd ISC High Performance
                 conference held June 16--20, 2019.",
}


bibtype: article
filename: fparith.bib
label: Lange:2019:SEP
author: Marko Lange and Siegfried M. Rump
title: Sharp estimates for perturbation errors in summations
journal: j-MATH-COMPUT
volume: 88
number: 315
pages: 349--368
month: jul
monthnumber: 7
year: 2019
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3355
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Tue Jul 14 06:45:34 MDT 2020
bibtimestamp: 2020.07.14 06:45:34 MDT
fjournal: Mathematics of Computation
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Marko Lange and Siegfried M. Rump
rawtitle: Sharp estimates for perturbation errors in summations
bibsource:
http://www.ams.org/mcom/2019-88-315; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5; https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5/S0025-5718-2018-03355-5.pdf; https://www.ams.org/mathscinet/search/authors.html?mrauthid=1082372; https://www.ams.org/mathscinet/search/authors.html?mrauthid=151815

entry:
@Article{Lange:2019:SEP,
  author =       "Marko Lange and Siegfried M. Rump",
  title =        "Sharp estimates for perturbation errors in
                 summations",
  journal =      j-MATH-COMPUT,
  volume =       "88",
  number =       "315",
  pages =        "349--368",
  month =        jul,
  year =         "2019",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3355",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Tue Jul 14 06:45:34 MDT 2020",
  bibsource =    "http://www.ams.org/mcom/2019-88-315;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5;
                 https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5/S0025-5718-2018-03355-5.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=1082372;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=151815",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Lee:2019:EES
author: Jinsu Lee and Juhyoung Lee and Donghyeon Han and Jinmook Lee and Gwangtae Park and Hoi-Jun Yoo
journal: IEEE Solid-State Circuits Letters
volume: 2
number: 11
pages: 232--235
year: 2019
DOI: https://doi.org/10.1109/LSSC.2019.2937440
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Jinsu Lee and Juhyoung Lee and Donghyeon Han and Jinmook Lee and Gwangtae Park and Hoi-Jun Yoo
title:
An Energy-Efficient Sparse Deep-Neural-Network Learning Accelerator With Fine-Grained Mixed Precision of FP8--FP16

keywords:
Accelerators; Arrays; deep learning (DL); deep-neural network (DNN); Energy efficiency; energy efficient; Hardware; Memory management; Solid state circuits; Throughput; Training; training

rawtitle:
An Energy-Efficient Sparse Deep-Neural-Network Learning Accelerator With Fine-Grained Mixed Precision of {FP8--FP16}

entry:
@Article{Lee:2019:EES,
  author =       "Jinsu Lee and Juhyoung Lee and Donghyeon Han and
                 Jinmook Lee and Gwangtae Park and Hoi-Jun Yoo",
  title =        "An Energy-Efficient Sparse Deep-Neural-Network
                 Learning Accelerator With Fine-Grained Mixed Precision
                 of {FP8--FP16}",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "2",
  number =       "11",
  pages =        "232--235",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/LSSC.2019.2937440",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accelerators; Arrays; deep learning (DL); deep-neural
                 network (DNN); Energy efficiency; energy efficient;
                 Hardware; Memory management; Solid state circuits;
                 Throughput; Training; training",
}


bibtype: inproceedings
filename: fparith.bib
label: Lee:2019:LWS
author: Jinsu Lee and Juhyoung Lee and Donghyeon Han and Jinmook Lee and Gwangtae Park and Hoi-Jun Yoo
booktitle: 2019 IEEE International Solid-State Circuits Conference --- (ISSCC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 142--144
year: 2019
DOI: https://doi.org/10.1109/ISSCC.2019.8662302
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
keywords: Acceleration; Deep learning; Neural networks; Registers; Throughput; Training
acknowledgement: ack-nhfb
rawauthor: Jinsu Lee and Juhyoung Lee and Donghyeon Han and Jinmook Lee and Gwangtae Park and Hoi-Jun Yoo
rawbooktitle: {2019 IEEE International Solid-State Circuits Conference --- (ISSCC)}
title:
7.7 LNPU: a 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8--FP16

rawtitle:
7.7 {LNPU}: a {25.3TFLOPS/W} Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of {FP8--FP16}

entry:
@InProceedings{Lee:2019:LWS,
  author =       "Jinsu Lee and Juhyoung Lee and Donghyeon Han and
                 Jinmook Lee and Gwangtae Park and Hoi-Jun Yoo",
  booktitle =    "{2019 IEEE International Solid-State Circuits
                 Conference --- (ISSCC)}",
  title =        "7.7 {LNPU}: a {25.3TFLOPS/W} Sparse
                 Deep-Neural-Network Learning Processor with
                 Fine-Grained Mixed Precision of {FP8--FP16}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "142--144",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ISSCC.2019.8662302",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; Deep learning; Neural networks;
                 Registers; Throughput; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2019:ACM
author: Vincent Lefevre and Jean-Michel Muller
title: Accurate Complex Multiplication in Floating-Point Arithmetic
crossref: Takagi:2019:ISC
pages: 23--29
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00013
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre and Jean-Michel Muller
rawtitle: Accurate Complex Multiplication in Floating-Point Arithmetic
abstract:
We deal with accurate complex multiplication in binary floating-point arithmetic, with an emphasis on the case where one of the operands is a ``double-word'' number. We provide an algorithm that returns a complex product with normwise relative error bound close to the best possible one, i.e., the rounding unit u.

keywords:
accurate complex multiplication; Approximation algorithms; ARITH-26; binary floating-point arithmetic; complex product; Digital arithmetic; double-word number; floating point arithmetic; Floating-point arithmetic; Floating-point arithmetic, Complex multiplication, Rounding error analysis; Lips; Parallel processing; Standards; Zirconium

rawabstract:
We deal with accurate complex multiplication in binary floating-point arithmetic, with an emphasis on the case where one of the operands is a ``double-word'' number. We provide an algorithm that returns a complex product with normwise relative error bound close to the best possible one, i.e., the rounding unit u.

entry:
@InProceedings{Lefevre:2019:ACM,
  author =       "Vincent Lef{\`e}vre and Jean-Michel Muller",
  title =        "Accurate Complex Multiplication in Floating-Point
                 Arithmetic",
  crossref =     "Takagi:2019:ISC",
  pages =        "23--29",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00013",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We deal with accurate complex multiplication in binary
                 floating-point arithmetic, with an emphasis on the case
                 where one of the operands is a ``double-word'' number.
                 We provide an algorithm that returns a complex product
                 with normwise relative error bound close to the best
                 possible one, i.e., the rounding unit u.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate complex multiplication; Approximation
                 algorithms; ARITH-26; binary floating-point arithmetic;
                 complex product; Digital arithmetic; double-word
                 number; floating point arithmetic; Floating-point
                 arithmetic; Floating-point arithmetic, Complex
                 multiplication, Rounding error analysis; Lips; Parallel
                 processing; Standards; Zirconium",
}


bibtype: article
filename: fparith.bib
label: Lemire:2019:FRD
author: Daniel Lemire and Owen Kaser and Nathan Kurz
title: Faster remainder by direct computation: Applications to compilers and software libraries
journal: j-SPE
volume: 49
number: 6
pages: 953--970
month: jun
monthnumber: 6
year: 2019
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.2689
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Sat Oct 12 09:43:47 MDT 2019
bibtimestamp: 2019.10.12 09:43:47 MDT
fjournal: Software --- Practice and Experience
keywords: integer division; integer remainder
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 27 February 2019
rawauthor: Daniel Lemire and Owen Kaser and Nathan Kurz
rawtitle: Faster remainder by direct computation: Applications to compilers and software libraries
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib

remark:
Paul Zimmermann reported on the gmp-devel mailing list on Tue, 15 Oct 2019 10:40:48 +0200 that the remainder algorithm in this report was described earlier in unpublished work in cite Bernstein:2004:SRT.

entry:
@Article{Lemire:2019:FRD,
  author =       "Daniel Lemire and Owen Kaser and Nathan Kurz",
  title =        "Faster remainder by direct computation: Applications
                 to compilers and software libraries",
  journal =      j-SPE,
  volume =       "49",
  number =       "6",
  pages =        "953--970",
  month =        jun,
  year =         "2019",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.2689",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Sat Oct 12 09:43:47 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "integer division; integer remainder",
  onlinedate =   "27 February 2019",
  remark =       "Paul Zimmermann reported on the gmp-devel mailing list
                 on Tue, 15 Oct 2019 10:40:48 +0200 that the remainder
                 algorithm in this report was described earlier in
                 unpublished work in \cite{Bernstein:2004:SRT}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Lindstrom:2019:UCR
author: Peter Lindstrom
title: Universal Coding of the Reals Using Bisection
crossref: Gustafson:2019:CPC
pages: 7:1--7:10
year: 2019
DOI: https://doi.org/10.1145/3316279.3316286
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
acknowledgement: ack-nhfb
articleno: 7
rawauthor: Peter Lindstrom
rawtitle: Universal Coding of the Reals Using Bisection
keywords:
wobbling accuracy, floating point, bracketing, binary search, bisection, Universal coding, posits, unbounded search

entry:
@InProceedings{Lindstrom:2019:UCR,
  author =       "Peter Lindstrom",
  title =        "Universal Coding of the Reals Using Bisection",
  crossref =     "Gustafson:2019:CPC",
  pages =        "7:1--7:10",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316286",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  keywords =     "wobbling accuracy, floating point, bracketing, binary
                 search, bisection, Universal coding, posits, unbounded
                 search",
  location =     "Singapore, Singapore",
  numpages =     "10",
}


bibtype: article
filename: fparith.bib
label: Liu:2019:DAA
author: W. Liu and T. Cao and P. Yin and Y. Zhu and C. Wang and E. E. Swartzlander and F. Lombardi
title: Design and Analysis of Approximate Redundant Binary Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 6
pages: 804--819
month: jun
monthnumber: 6
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2890222
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: W. Liu and T. Cao and P. Yin and Y. Zhu and C. Wang and E. E. Swartzlander and F. Lombardi
rawtitle: Design and Analysis of Approximate Redundant Binary Multipliers
keywords:
adders; Adders; approximate arithmetic designs; approximate Booth encoders; approximate circuits; approximate computing; Approximate computing; approximate NB Booth multipliers; approximate product arrays; approximate RB multipliers; approximate redundant binary multiplier design; Compressors; Delays; Error analysis; error analysis; error characteristics; error-resilient applications; error-tolerant applications; exact regular partial product arrays; Hardware; hardware simulation; logic design; low power; low power circuits; modified Booth encoder; multiplying circuits; partial product array; Power demand; RB 4:2 compressors; RB adders; RB compressor; RB compressors; RB-NB converter; RB-normal binary converter; redundant binary (RB) multiplier

entry:
@Article{Liu:2019:DAA,
  author =       "W. Liu and T. Cao and P. Yin and Y. Zhu and C. Wang
                 and E. E. Swartzlander and F. Lombardi",
  title =        "Design and Analysis of Approximate Redundant Binary
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "6",
  pages =        "804--819",
  month =        jun,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2890222",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "adders; Adders; approximate arithmetic designs;
                 approximate Booth encoders; approximate circuits;
                 approximate computing; Approximate computing;
                 approximate NB Booth multipliers; approximate product
                 arrays; approximate RB multipliers; approximate
                 redundant binary multiplier design; Compressors;
                 Delays; Error analysis; error analysis; error
                 characteristics; error-resilient applications;
                 error-tolerant applications; exact regular partial
                 product arrays; Hardware; hardware simulation; logic
                 design; low power; low power circuits; modified Booth
                 encoder; multiplying circuits; partial product array;
                 Power demand; RB 4:2 compressors; RB adders; RB
                 compressor; RB compressors; RB-NB converter; RB-normal
                 binary converter; redundant binary (RB) multiplier",
}


bibtype: article
filename: fparith.bib
label: Lourenco:2019:ESS
author: Christopher Lourenco and Adolfo R. Escobedo and Erick Moreno-Centeno and Timothy A. Davis
journal: j-SIAM-J-MAT-ANA-APPL
volume: 40
number: 2
pages: 609--638
year: 2019
CODEN: SJMAEL
DOI: https://doi.org/10.1137/18M1202499
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
bibdate: Thu Oct 10 08:00:32 MDT 2019
bibtimestamp: 2019.10.10 08:00:32 MDT
fjournal: SIAM Journal on Matrix Analysis and Applications
keywords: exact rational arithmetic; Sparse Left-looking Integer-Preserving (SLIP) LU factorization
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/simax
onlinedate: January 2019
rawauthor: Christopher Lourenco and Adolfo R. Escobedo and Erick Moreno-Centeno and Timothy A. Davis
title:
Exact Solution of Sparse Linear Systems via Left-Looking Roundoff-Error-Free $ L U $ Factorization in Time Proportional to Arithmetic Work

bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/40/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib

rawtitle:
Exact Solution of Sparse Linear Systems via Left-Looking Roundoff-Error-Free {$ L U $} Factorization in Time Proportional to Arithmetic Work

entry:
@Article{Lourenco:2019:ESS,
  author =       "Christopher Lourenco and Adolfo R. Escobedo and Erick
                 Moreno-Centeno and Timothy A. Davis",
  title =        "Exact Solution of Sparse Linear Systems via
                 Left-Looking Roundoff-Error-Free {$ L U $}
                 Factorization in Time Proportional to Arithmetic Work",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "40",
  number =       "2",
  pages =        "609--638",
  month =        "????",
  year =         "2019",
  CODEN =        "SJMAEL",
  DOI =          "https://doi.org/10.1137/18M1202499",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  bibdate =      "Thu Oct 10 08:00:32 MDT 2019",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/40/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
  keywords =     "exact rational arithmetic; Sparse Left-looking
                 Integer-Preserving (SLIP) LU factorization",
  onlinedate =   "January 2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Lu:2019:TDN
author: Jinming Lu and Siyuan Lu and Zhisheng Wang and Chao Fang and Jun Lin and Zhongfeng Wang and Li Du
editor: IEEE
booktitle: 2019 32nd IEEE International System-on-Chip Conference (SOCC)
title: Training Deep Neural Networks Using Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 62--67
year: 2019
DOI: https://doi.org/10.1109/SOCC46988.2019.1570558530
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Jinming Lu and Siyuan Lu and Zhisheng Wang and Chao Fang and Jun Lin and Zhongfeng Wang and Li Du
rawbooktitle: {2019 32nd IEEE International System-on-Chip Conference (SOCC)}
raweditor: {IEEE}
rawtitle: Training Deep Neural Networks Using Posit Number System
entry:
@InProceedings{Lu:2019:TDN,
  author =       "Jinming Lu and Siyuan Lu and Zhisheng Wang and Chao
                 Fang and Jun Lin and Zhongfeng Wang and Li Du",
  editor =       "{IEEE}",
  booktitle =    "{2019 32nd IEEE International System-on-Chip
                 Conference (SOCC)}",
  title =        "Training Deep Neural Networks Using Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "62--67",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SOCC46988.2019.1570558530",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lutz:2019:AFP
author: David Lutz
title: ARM Floating Point 2019: Latency, Area, Power
crossref: Takagi:2019:ISC
pages: 97--98
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00025
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: David Lutz
rawtitle: {ARM} Floating Point 2019: Latency, Area, Power
abstract:
We have had little or no speed increase from process in the past few years, but latency continues to decrease due to algorithmic improvements [1] and a decision to spend more area on CPU datapaths [2]. A binary64 floating-point (FP) add now takes two cycles when done as part of a 2+2-cycle FMA, and even one cycle when done as part of an in-order vector reduction. Smaller and more specialized FP operations (bfloat16) are even faster. Finally, the decision to spend more area on datapath logic took a new twist this year when we applied it to GPUs, cutting dynamic power there by a third.

keywords:
2+2-cycle FMA; adders; Adders; ARITH-26; ARM floating point 2019; bfloat16; binary64 floating-point; Clocks; CPU datapaths; datapath logic; Digital arithmetic; floating point arithmetic; in-order vector reduction; Microarchitecture; Pipelines; random number generation; Security; Standards; vectors

rawabstract:
We have had little or no speed increase from process in the past few years, but latency continues to decrease due to algorithmic improvements [1] and a decision to spend more area on CPU datapaths [2]. A binary64 floating-point (FP) add now takes two cycles when done as part of a 2+2-cycle FMA, and even one cycle when done as part of an in-order vector reduction. Smaller and more specialized FP operations (bfloat16) are even faster. Finally, the decision to spend more area on datapath logic took a new twist this year when we applied it to GPUs, cutting dynamic power there by a third.

entry:
@InProceedings{Lutz:2019:AFP,
  author =       "David Lutz",
  title =        "{ARM} Floating Point 2019: Latency, Area, Power",
  crossref =     "Takagi:2019:ISC",
  pages =        "97--98",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00025",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We have had little or no speed increase from process
                 in the past few years, but latency continues to
                 decrease due to algorithmic improvements [1] and a
                 decision to spend more area on CPU datapaths [2]. A
                 binary64 floating-point (FP) add now takes two cycles
                 when done as part of a 2+2-cycle FMA, and even one
                 cycle when done as part of an in-order vector
                 reduction. Smaller and more specialized FP operations
                 (bfloat16) are even faster. Finally, the decision to
                 spend more area on datapath logic took a new twist this
                 year when we applied it to GPUs, cutting dynamic power
                 there by a third.",
  acknowledgement = ack-nhfb,
  keywords =     "2+2-cycle FMA; adders; Adders; ARITH-26; ARM floating
                 point 2019; bfloat16; binary64 floating-point; Clocks;
                 CPU datapaths; datapath logic; Digital arithmetic;
                 floating point arithmetic; in-order vector reduction;
                 Microarchitecture; Pipelines; random number generation;
                 Security; Standards; vectors",
}


bibtype: misc
filename: fparith.bib
label: Lutz:2019:AMP
author: David Raymond Lutz and Neil Burgess and Christopher Neal Hinds and Andreas Due Engh-Halstvedt
title: Apparatus and method for performing arithmetic operations to accumulate floating-point numbers
pages: 97--98
day: 26
month: feb
monthnumber: 2
year: 2019
bibdate: Thu Oct 17 11:34:51 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 11:34:51 ???
URL: https://patents.google.com/patent/US10216479B2
acknowledgement: ack-nhfb
howpublished: US Patent 10,216,479
rawauthor: David Raymond Lutz and Neil Burgess and Christopher Neal Hinds and Andreas Due Engh-Halstvedt
rawtitle: Apparatus and method for performing arithmetic operations to accumulate floating-point numbers
abstract:
An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.

remark:
Patent filed 6 December 2016, granted to Arm Ltd. on 26 February 2019, expected expiration 2 February 2037 (in 17th year of grant).

rawabstract:
An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.

entry:
@Misc{Lutz:2019:AMP,
  author =       "David Raymond Lutz and Neil Burgess and Christopher
                 Neal Hinds and Andreas Due Engh-Halstvedt",
  title =        "Apparatus and method for performing arithmetic
                 operations to accumulate floating-point numbers",
  howpublished = "US Patent 10,216,479",
  day =          "26",
  month =        feb,
  year =         "2019",
  bibdate =      "Thu Oct 17 11:34:51 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US10216479B2",
  abstract =     "An apparatus and method are provided for performing
                 arithmetic operations to accumulate floating-point
                 numbers. The apparatus comprises execution circuitry to
                 perform arithmetic operations, and decoder circuitry to
                 decode a sequence of instructions. A convert and
                 accumulate instruction is provided, and the decoder
                 circuitry is responsive to decoding the convert and
                 accumulate instruction to generate one or more control
                 signals to control the execution circuitry to convert
                 at least one floating-point operand identified by the
                 convert and accumulate instruction into a corresponding
                 N-bit fixed-point operand having M fraction bits, where
                 M is less than N and M is dependent on a format of the
                 floating-point operand. The execution circuitry
                 accumulates each corresponding N bit fixed-point
                 operand and a P bit fixed-point operand identified by
                 the convert and accumulate instruction in order to
                 generate a P bit fixed-point result value, where P is
                 greater than N and also has M fraction bits.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 6 December 2016, granted to Arm Ltd. on
                 26 February 2019, expected expiration 2 February 2037
                 (in 17th year of grant).",
}


bibtype: inproceedings
filename: fparith.bib
label: Mach:2019:FSB
author: Stefan Mach and Fabian Schuiki and Florian Zaruba and Luca Benini
editor: IEEE
booktitle: 2019 IFIP / IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 95--98
year: 2019
DOI: https://doi.org/10.1109/VLSI-SoC.2019.8920307
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Stefan Mach and Fabian Schuiki and Florian Zaruba and Luca Benini
rawbooktitle: {2019 IFIP\slash IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)}
raweditor: {IEEE}
title:
A 0.80pJ / flop, 1.24Tflop / sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI

rawtitle:
A {0.80pJ\slash flop, 1.24Tflop\slash sW} 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit {RISC-V} Processor in 22nm {FD-SOI}

entry:
@InProceedings{Mach:2019:FSB,
  author =       "Stefan Mach and Fabian Schuiki and Florian Zaruba and
                 Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 IFIP\slash IEEE 27th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "A {0.80pJ\slash flop, 1.24Tflop\slash sW} 8-to-64 bit
                 Transprecision Floating-Point Unit for a 64 bit
                 {RISC-V} Processor in 22nm {FD-SOI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "95--98",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2019.8920307",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Magron:2019:CRE
author: V. Magron and A. Rocca and T. Dang
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 953--966
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2851235
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: V. Magron and A. Rocca and T. Dang
title:
Certified Roundoff Error Bounds Using Bernstein Expansions and Sparse Krivine--Stengle Representations

keywords:
Algebra; Bernstein expansions; Convergence; embedded systems; embedded systems implementation; error analysis; floating point arithmetic; FPBern software package; FPKriSten software package; Krivine-Stengle representations; linear programming; linear programming relaxations; nonlinear programs; Optimization; Polynomial optimization; polynomials; rational functions; rigorous upper bounds; roundoff error bounds; roundoff errors; Roundoff errors; Software algorithms; Tools; Upper bound

rawtitle:
Certified Roundoff Error Bounds Using {Bernstein} Expansions and Sparse {Krivine--Stengle} Representations

entry:
@Article{Magron:2019:CRE,
  author =       "V. Magron and A. Rocca and T. Dang",
  title =        "Certified Roundoff Error Bounds Using {Bernstein}
                 Expansions and Sparse {Krivine--Stengle}
                 Representations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "953--966",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2851235",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Algebra; Bernstein expansions; Convergence; embedded
                 systems; embedded systems implementation; error
                 analysis; floating point arithmetic; FPBern software
                 package; FPKriSten software package; Krivine-Stengle
                 representations; linear programming; linear programming
                 relaxations; nonlinear programs; Optimization;
                 Polynomial optimization; polynomials; rational
                 functions; rigorous upper bounds; roundoff error
                 bounds; roundoff errors; Roundoff errors; Software
                 algorithms; Tools; Upper bound",
}


bibtype: inproceedings
filename: fparith.bib
label: Martins:2019:HHR
author: Paulo Martins and Jeremy Marrez and Jean-Claude Bajard and Leonel Sousa
title: HyPoRes: An Hybrid Representation System for ECC
crossref: Takagi:2019:ISC
pages: 207--214
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00049
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Paulo Martins and Jeremy Marrez and Jean-Claude Bajard and Leonel Sousa
rawtitle: {HyPoRes}: An Hybrid Representation System for {ECC}
abstract:
The Residue Number System (RNS) is a numeral representation enabling for more efficient addition and multiplication implementations. However, due its non-positional nature, modular reductions, required for example by Elliptic Curve (EC) Cryptography (ECC), become costlier. Traditional approaches to RNS modular reduction resort to the Montgomery algorithm, underpinned by large basis extensions. Recently, Hybrid-Positional Residue Number Systems (HPRs) have been proposed, providing a trade-off between the efficiency of RNS and the flexibility of positional number representations. Numbers are represented in a positional representation with the coefficients represented in RNS. By crafting primes of a special form, the complexity of reductions modulo those primes is mitigated, relying on extensions of smaller bases. Due to the need of crafting special primes, this approach is not directly extensible to group operations over currently standardised elliptic curves. In this paper, the Hybrid-Polynomial Residue Number System (HyPoRes) is proposed, enabling for improved modular reductions for any prime. Experimental results show that the modular reduction of HyPoRes, although at most 1.4 times slower than HPR for HPR-crafted primes, is up to 1.4 times faster than a generic RNS approach for primes of ECC standards.

keywords:
ARITH-26; Art; Complexity theory; Dynamic range; ECC standards; Elliptic Curve Cryp-tography; Elliptic curve cryptography; elliptic curve cryptography; Elliptic curves; generic RNS approach; HPR-crafted primes; hybrid representation system; hybrid-polynomial residue number system; hybrid-positional residue number systems; HyPoRes; improved modular reductions; Lattices; Modular Arithmetic; Montgomery algorithm; multiplication implementations; polynomials; positional number representations; public key cryptography; Residue Number System; residue number systems; RNS modular reduction

rawabstract:
The Residue Number System (RNS) is a numeral representation enabling for more efficient addition and multiplication implementations. However, due its non-positional nature, modular reductions, required for example by Elliptic Curve (EC) Cryptography (ECC), become costlier. Traditional approaches to RNS modular reduction resort to the Montgomery algorithm, underpinned by large basis extensions. Recently, Hybrid-Positional Residue Number Systems (HPRs) have been proposed, providing a trade-off between the efficiency of RNS and the flexibility of positional number representations. Numbers are represented in a positional representation with the coefficients represented in RNS. By crafting primes of a special form, the complexity of reductions modulo those primes is mitigated, relying on extensions of smaller bases. Due to the need of crafting special primes, this approach is not directly extensible to group operations over currently standardised elliptic curves. In this paper, the Hybrid-Polynomial Residue Number System (HyPoRes) is proposed, enabling for improved modular reductions for any prime. Experimental results show that the modular reduction of HyPoRes, although at most 1.4 times slower than HPR for HPR-crafted primes, is up to 1.4 times faster than a generic RNS approach for primes of ECC standards.

entry:
@InProceedings{Martins:2019:HHR,
  author =       "Paulo Martins and Jeremy Marrez and Jean-Claude Bajard
                 and Leonel Sousa",
  title =        "{HyPoRes}: An Hybrid Representation System for {ECC}",
  crossref =     "Takagi:2019:ISC",
  pages =        "207--214",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00049",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Residue Number System (RNS) is a numeral
                 representation enabling for more efficient addition and
                 multiplication implementations. However, due its
                 non-positional nature, modular reductions, required for
                 example by Elliptic Curve (EC) Cryptography (ECC),
                 become costlier. Traditional approaches to RNS modular
                 reduction resort to the Montgomery algorithm,
                 underpinned by large basis extensions. Recently,
                 Hybrid-Positional Residue Number Systems (HPRs) have
                 been proposed, providing a trade-off between the
                 efficiency of RNS and the flexibility of positional
                 number representations. Numbers are represented in a
                 positional representation with the coefficients
                 represented in RNS. By crafting primes of a special
                 form, the complexity of reductions modulo those primes
                 is mitigated, relying on extensions of smaller bases.
                 Due to the need of crafting special primes, this
                 approach is not directly extensible to group operations
                 over currently standardised elliptic curves. In this
                 paper, the Hybrid-Polynomial Residue Number System
                 (HyPoRes) is proposed, enabling for improved modular
                 reductions for any prime. Experimental results show
                 that the modular reduction of HyPoRes, although at most
                 1.4 times slower than HPR for HPR-crafted primes, is up
                 to 1.4 times faster than a generic RNS approach for
                 primes of ECC standards.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Art; Complexity theory; Dynamic range; ECC
                 standards; Elliptic Curve Cryp-tography; Elliptic curve
                 cryptography; elliptic curve cryptography; Elliptic
                 curves; generic RNS approach; HPR-crafted primes;
                 hybrid representation system; hybrid-polynomial residue
                 number system; hybrid-positional residue number
                 systems; HyPoRes; improved modular reductions;
                 Lattices; Modular Arithmetic; Montgomery algorithm;
                 multiplication implementations; polynomials; positional
                 number representations; public key cryptography;
                 Residue Number System; residue number systems; RNS
                 modular reduction",
}


bibtype: inproceedings
filename: fparith.bib
label: Matula:2019:PCG
author: David W. Matula and Zizhen Chen
title: Precise and Concise Graphical Representation of the Natural Numbers
crossref: Takagi:2019:ISC
pages: 100--103
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00027
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: David W. Matula and Zizhen Chen
rawtitle: Precise and Concise Graphical Representation of the Natural Numbers
abstract:
A graphical number representation system based on the formal logic foundation of a recursively defined function is presented. The function exposes a one-to-one correspondence between the natural numbers and the set of rooted trees. Secondly, a relation between pairs of natural numbers is shown to partition the integers into disjoint finite sets each visualized as a tree in the forest of all finite trees. This relation encapsulates in visual form the natural structure and distribution of primes in a manner not previously investigated. These representations allow arithmeticians to visually experience natural numbers in a 2D graphical layout. This form is free of cultural choices such as the number of symbols in an alphabet and/or one-dimensional symbol strings. The fundamental nature of these mappings is argued to be accessible to a creative mind independent of formal schooling. This short note includes examples illustrating the simplicity of the constructions.

keywords:
2D graphical layout; ARITH-26; Computer science; disjoint finite sets; finite trees; Forestry; formal logic foundation; graphical number representation system; graphical representation; Labeling; natural numbers; natural structure; number fonts; one-dimensional symbol strings; one-to-one correspondence; prime factorization; prime number function; recursive function; recursive functions; recursively defined function; rooted trees; trees (mathematics); Two dimensional displays; Vegetation; Visualization

rawabstract:
A graphical number representation system based on the formal logic foundation of a recursively defined function is presented. The function exposes a one-to-one correspondence between the natural numbers and the set of rooted trees. Secondly, a relation between pairs of natural numbers is shown to partition the integers into disjoint finite sets each visualized as a tree in the forest of all finite trees. This relation encapsulates in visual form the natural structure and distribution of primes in a manner not previously investigated. These representations allow arithmeticians to visually experience natural numbers in a 2D graphical layout. This form is free of cultural choices such as the number of symbols in an alphabet and/or one-dimensional symbol strings. The fundamental nature of these mappings is argued to be accessible to a creative mind independent of formal schooling. This short note includes examples illustrating the simplicity of the constructions.

entry:
@InProceedings{Matula:2019:PCG,
  author =       "David W. Matula and Zizhen Chen",
  title =        "Precise and Concise Graphical Representation of the
                 Natural Numbers",
  crossref =     "Takagi:2019:ISC",
  pages =        "100--103",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00027",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A graphical number representation system based on the
                 formal logic foundation of a recursively defined
                 function is presented. The function exposes a
                 one-to-one correspondence between the natural numbers
                 and the set of rooted trees. Secondly, a relation
                 between pairs of natural numbers is shown to partition
                 the integers into disjoint finite sets each visualized
                 as a tree in the forest of all finite trees. This
                 relation encapsulates in visual form the natural
                 structure and distribution of primes in a manner not
                 previously investigated. These representations allow
                 arithmeticians to visually experience natural numbers
                 in a 2D graphical layout. This form is free of cultural
                 choices such as the number of symbols in an alphabet
                 and/or one-dimensional symbol strings. The fundamental
                 nature of these mappings is argued to be accessible to
                 a creative mind independent of formal schooling. This
                 short note includes examples illustrating the
                 simplicity of the constructions.",
  acknowledgement = ack-nhfb,
  keywords =     "2D graphical layout; ARITH-26; Computer science;
                 disjoint finite sets; finite trees; Forestry; formal
                 logic foundation; graphical number representation
                 system; graphical representation; Labeling; natural
                 numbers; natural structure; number fonts;
                 one-dimensional symbol strings; one-to-one
                 correspondence; prime factorization; prime number
                 function; recursive function; recursive functions;
                 recursively defined function; rooted trees; trees
                 (mathematics); Two dimensional displays; Vegetation;
                 Visualization",
}


bibtype: article
filename: fparith.bib
label: Maynard:2019:MPA
author: C. M. Maynard and D. N. Walters
journal: j-COMP-PHYS-COMM
volume: 244
pages: 69--75
month: nov
monthnumber: 11
year: 2019
CODEN: CPHCBZ
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Fri Sep 6 11:03:48 MDT 2019
bibtimestamp: 2019.09.06 11:03:48 MDT
URL: https://www.sciencedirect.com/science/article/pii/S0010465519302127
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: C. M. Maynard and D. N. Walters
title:
Mixed-precision arithmetic in the ENDGame dynamical core of the Unified Model, a numerical weather prediction and climate model code

bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Mixed-precision arithmetic in the {ENDGame} dynamical core of the {Unified Model}, a numerical weather prediction and climate model code

entry:
@Article{Maynard:2019:MPA,
  author =       "C. M. Maynard and D. N. Walters",
  title =        "Mixed-precision arithmetic in the {ENDGame} dynamical
                 core of the {Unified Model}, a numerical weather
                 prediction and climate model code",
  journal =      j-COMP-PHYS-COMM,
  volume =       "244",
  number =       "??",
  pages =        "69--75",
  month =        nov,
  year =         "2019",
  CODEN =        "CPHCBZ",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Fri Sep 6 11:03:48 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S0010465519302127",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: article
filename: fparith.bib
label: McCullough:2019:WTS
author: B. D. McCullough and Taha Mokfi and Mahsa Almaeenjad
title: Wilkinson's Tests and SQL Packages
journal: j-SIGMOD
volume: 48
number: 3
pages: 17--22
month: sep
monthnumber: 9
year: 2019
CODEN: SRECD8
DOI: https://doi.org/10.1145/3377391.3377395
ISSN: 0163-5808 (print), 1943-5835 (electronic) OR 01635808 (print), 19435835 (electronic)
ISSNL: 0163-5808 OR 01635808
bibdate: Sat Dec 21 07:26:01 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigmod.bib
bibtimestamp: 2019.12.21 07:26:01 MST
fjournal: SIGMOD Record (ACM Special Interest Group on Management of Data)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J689
rawauthor: B. D. McCullough and Taha Mokfi and Mahsa Almaeenjad
rawtitle: {Wilkinson}'s Tests and {SQL} Packages
abstract:
Wilkinson's Tests are used to benchmark the accuracy of some statistical functions in six SQL packages: Apache Hive, Microsoft Access, Microsoft SQL Server, MySQL, Oracle 11g SQL, and SAP Hana. Using the best choice of data type, we find that different packages use different rounding schemes, two packages use unreliable algorithms to compute the sample variance, one package returns the population standard deviation when the sample standard deviation is called, and one package has an unstable algorithm for computing the correlation coefficient. Using the wrong data type all but guarantees inaccurate results.

remark:
This paper looks at statistical software inside six widely-used SQL databases, and find serious errors in most of them, and poor numerical implementations for standard deviations and other well-understood computational algorithms. See also earlier work recorded in fparith.bib cite McCullough:1998:ARS,McCullough:1999:ARS,McCullough:1999:NRE.

rawabstract:
Wilkinson's Tests are used to benchmark the accuracy of some statistical functions in six SQL packages: Apache Hive, Microsoft Access, Microsoft SQL Server, MySQL, Oracle 11g SQL, and SAP Hana. Using the best choice of data type, we find that different packages use different rounding schemes, two packages use unreliable algorithms to compute the sample variance, one package returns the population standard deviation when the sample standard deviation is called, and one package has an unstable algorithm for computing the correlation coefficient. Using the wrong data type all but guarantees inaccurate results.

entry:
@Article{McCullough:2019:WTS,
  author =       "B. D. McCullough and Taha Mokfi and Mahsa Almaeenjad",
  title =        "{Wilkinson}'s Tests and {SQL} Packages",
  journal =      j-SIGMOD,
  volume =       "48",
  number =       "3",
  pages =        "17--22",
  month =        sep,
  year =         "2019",
  CODEN =        "SRECD8",
  DOI =          "https://doi.org/10.1145/3377391.3377395",
  ISSN =         "0163-5808 (print), 1943-5835 (electronic)",
  ISSN-L =       "0163-5808",
  bibdate =      "Sat Dec 21 07:26:01 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigmod.bib",
  abstract =     "Wilkinson's Tests are used to benchmark the accuracy
                 of some statistical functions in six SQL packages:
                 Apache Hive, Microsoft Access, Microsoft SQL Server,
                 MySQL, Oracle 11g SQL, and SAP Hana. Using the best
                 choice of data type, we find that different packages
                 use different rounding schemes, two packages use
                 unreliable algorithms to compute the sample variance,
                 one package returns the population standard deviation
                 when the sample standard deviation is called, and one
                 package has an unstable algorithm for computing the
                 correlation coefficient. Using the wrong data type all
                 but guarantees inaccurate results.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGMOD Record (ACM Special Interest Group on
                 Management of Data)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J689",
  remark =       "This paper looks at statistical software inside six
                 widely-used SQL databases, and find serious errors in
                 most of them, and poor numerical implementations for
                 standard deviations and other well-understood
                 computational algorithms. See also earlier work
                 recorded in fparith.bib
                 \cite{McCullough:1998:ARS,McCullough:1999:ARS,McCullough:1999:NRE}.",
}


bibtype: inproceedings
filename: fparith.bib
label: McKinstry:2019:DLP
title: Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Inference
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 6--9
year: 2019
DOI: https://doi.org/10.1109/EMC2-NIPS53020.2019.00009
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawtitle: Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Inference
author:
Jeffrey L. McKinstry and Steven K. Esser and Rathinakumar Appuswamy and Deepika Bablani and John V. Arthur and Izzet B. Yildiz and Dharmendra S. Modha

booktitle:
2019 Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing --- NeurIPS Edition (EMC2-NIPS)

keywords:
Benchmark testing; computer vision; Conferences; deep learning; Energy efficiency; fp32; low precision; Machine learning; Quantization (signal); Sensitivity analysis; Training

rawauthor:
Jeffrey L. McKinstry and Steven K. Esser and Rathinakumar Appuswamy and Deepika Bablani and John V. Arthur and Izzet B. Yildiz and Dharmendra S. Modha

rawbooktitle:
{2019 Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing --- NeurIPS Edition (EMC2-NIPS)}

entry:
@InProceedings{McKinstry:2019:DLP,
  author =       "Jeffrey L. McKinstry and Steven K. Esser and
                 Rathinakumar Appuswamy and Deepika Bablani and John V.
                 Arthur and Izzet B. Yildiz and Dharmendra S. Modha",
  booktitle =    "{2019 Fifth Workshop on Energy Efficient Machine
                 Learning and Cognitive Computing --- NeurIPS Edition
                 (EMC2-NIPS)}",
  title =        "Discovering Low-Precision Networks Close to
                 Full-Precision Networks for Efficient Inference",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "6--9",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/EMC2-NIPS53020.2019.00009",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Benchmark testing; computer vision; Conferences; deep
                 learning; Energy efficiency; fp32; low precision;
                 Machine learning; Quantization (signal); Sensitivity
                 analysis; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Melquiond:2019:FVS
author: Guillaume Melquiond and Raphael Rieu-Helft
title: Formal Verification of a State-of-the-Art Integer Square Root
crossref: Takagi:2019:ISC
pages: 183--186
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00041
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Guillaume Melquiond and Raphael Rieu-Helft
rawtitle: Formal Verification of a State-of-the-Art Integer Square Root
abstract:
We present the automatic formal verification of a state-of-the-art algorithm from the GMP library that computes the square root of a 64-bit integer. Although it uses only integer operations, the best way to understand the program is to view it as a fixed-point arithmetic algorithm that implements Newton's method. The C code is short but intricate, involving magic constants and intentional arithmetic overflows. We have verified the algorithm using the Why3 tool and automated solvers such as Gappa.

keywords:
64-bit integer; Approximation algorithms; ARITH-26; automatic formal verification; C code; C language; Convergence; Digital arithmetic; electronic engineering computing; fixed point arithmetic; Fixed-point arithmetic; fixed-point arithmetic algorithm; floating point arithmetic; Floors; Formal verification; GMP library; integer operations; integer square root; intentional arithmetic overflows; Libraries; Newton method; program verification; programming; Tools; Why3 tool

rawabstract:
We present the automatic formal verification of a state-of-the-art algorithm from the GMP library that computes the square root of a 64-bit integer. Although it uses only integer operations, the best way to understand the program is to view it as a fixed-point arithmetic algorithm that implements Newton's method. The C code is short but intricate, involving magic constants and intentional arithmetic overflows. We have verified the algorithm using the Why3 tool and automated solvers such as Gappa.

entry:
@InProceedings{Melquiond:2019:FVS,
  author =       "Guillaume Melquiond and Raphael Rieu-Helft",
  title =        "Formal Verification of a State-of-the-Art Integer
                 Square Root",
  crossref =     "Takagi:2019:ISC",
  pages =        "183--186",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00041",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present the automatic formal verification of a
                 state-of-the-art algorithm from the GMP library that
                 computes the square root of a 64-bit integer. Although
                 it uses only integer operations, the best way to
                 understand the program is to view it as a fixed-point
                 arithmetic algorithm that implements Newton's method.
                 The C code is short but intricate, involving magic
                 constants and intentional arithmetic overflows. We have
                 verified the algorithm using the Why3 tool and
                 automated solvers such as Gappa.",
  acknowledgement = ack-nhfb,
  keywords =     "64-bit integer; Approximation algorithms; ARITH-26;
                 automatic formal verification; C code; C language;
                 Convergence; Digital arithmetic; electronic engineering
                 computing; fixed point arithmetic; Fixed-point
                 arithmetic; fixed-point arithmetic algorithm; floating
                 point arithmetic; Floors; Formal verification; GMP
                 library; integer operations; integer square root;
                 intentional arithmetic overflows; Libraries; Newton
                 method; program verification; programming; Tools; Why3
                 tool",
}


bibtype: phdthesis
filename: fparith.bib
label: Melquiond:2019:NVN
author: Guillaume Melquiond
title: Normal Verification for Numerical Computations, and the Other Way Around
type: Habilitation a Diriger des Recherches
school: Universite Paris Sud, 2
address: Paris, France
pages: x + 163
day: 25
month: jul
monthnumber: 7
year: 2019
bibdate: Fri Sep 22 16:46:42 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:46:42 ???
URL: https://theses.hal.science/tel-02194683/document
acknowledgement: ack-nhfb
rawauthor: Guillaume Melquiond
rawtitle: Normal Verification for Numerical Computations, and the Other Way Around
entry:
@PhdThesis{Melquiond:2019:NVN,
  author =       "Guillaume Melquiond",
  title =        "Normal Verification for Numerical Computations, and
                 the Other Way Around",
  type =         "{Habilitation {\`a} Diriger des Recherches}",
  school =       "Universit{\'e} Paris Sud, 2",
  address =      "Paris, France",
  pages =        "x + 163",
  day =          "25",
  month =        jul,
  year =         "2019",
  bibdate =      "Fri Sep 22 16:46:42 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://theses.hal.science/tel-02194683/document",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Mian:2019:CAE
author: Riaz-ul-haque Mian and Michihiro Shintani and Michiko Inoue
editor: IEEE
booktitle: 2019 32nd IEEE International System-on-Chip Conference (SOCC)
title: Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 412--417
year: 2019
DOI: https://doi.org/10.1109/SOCC46988.2019.1570559752
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Riaz-ul-haque Mian and Michihiro Shintani and Michiko Inoue
rawbooktitle: {2019 32nd IEEE International System-on-Chip Conference (SOCC)}
raweditor: {IEEE}
keywords:
Decimal arithmetic; Decimal multiplication; Evaluation framework; Hardware accelerator; RISC-V; RoCC; Rocket chip

rawtitle:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in {RISC-V} Ecosystem

entry:
@InProceedings{Mian:2019:CAE,
  author =       "Riaz-ul-haque Mian and Michihiro Shintani and Michiko
                 Inoue",
  editor =       "{IEEE}",
  booktitle =    "{2019 32nd IEEE International System-on-Chip
                 Conference (SOCC)}",
  title =        "Cycle-Accurate Evaluation of Software-Hardware
                 Co-Design of Decimal Computation in {RISC-V}
                 Ecosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "412--417",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SOCC46988.2019.1570559752",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Decimal arithmetic; Decimal multiplication; Evaluation
                 framework; Hardware accelerator; RISC-V; RoCC; Rocket
                 chip",
}


bibtype: misc
filename: fparith.bib
label: Moler:2019:CCF
author: Cleve Moler
title: Cleve's Corner: Floating Point Arithmetic Before IEEE 754
pages: 412--417
day: 18
month: jan
monthnumber: 1
year: 2019
bibdate: Sat Jan 19 15:18:17 2019
bibtimestamp: 2019.01.19 15:18:17 ???
URL: https://blogs.mathworks.com/cleve/2019/01/18/floating-point-arithmetic-before-ieee-754/
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawtitle: {Cleve}'s Corner: Floating Point Arithmetic Before {IEEE 754}
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib; https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
In a comment following my post about half-precision arithmetic, ``Raj C'' asked how the parameters for IEEE Standard 754 floating point arithmetic were chosen. I replied that I didn't know but would try to find out. I called emeritus U. C. Berkeley Professor W. (Velvel) Kahan, who was the principle architect of 754. Here is what I learned.

rawabstract:
In a comment following my post about half-precision arithmetic, ``Raj C'' asked how the parameters for IEEE Standard 754 floating point arithmetic were chosen. I replied that I didn't know but would try to find out. I called emeritus U. C. Berkeley Professor W. (Velvel) Kahan, who was the principle architect of 754. Here is what I learned.

entry:
@Misc{Moler:2019:CCF,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: Floating Point Arithmetic Before
                 {IEEE 754}",
  howpublished = "MathWorks Web site.",
  day =          "18",
  month =        jan,
  year =         "2019",
  bibdate =      "Sat Jan 19 15:18:17 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://blogs.mathworks.com/cleve/2019/01/18/floating-point-arithmetic-before-ieee-754/",
  abstract =     "In a comment following my post about half-precision
                 arithmetic, ``Raj C'' asked how the parameters for IEEE
                 Standard 754 floating point arithmetic were chosen. I
                 replied that I didn't know but would try to find out. I
                 called emeritus U. C. Berkeley Professor W. (Velvel)
                 Kahan, who was the principle architect of 754. Here is
                 what I learned.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Moler:2019:CCV
author: Cleve Moler
title: Cleve's Corner: Variable Format Half Precision Floating Point Arithmetic
pages: 412--417
day: 16
month: jan
monthnumber: 1
year: 2019
bibdate: Sat Jan 19 15:14:03 2019
bibtimestamp: 2019.01.19 15:14:03 ???
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawtitle: {Cleve}'s Corner: Variable Format Half Precision Floating Point Arithmetic
URL:
https://blogs.mathworks.com/cleve/2019/01/16/variable-format-half-precision-floating-point-arithmetic/

abstract:
A year and a half ago I wrote a post about ``half precision'' 16-bit floating point arithmetic, Moler on fp16. I followed this with a bug fix, bug in fp16. Both posts were about fp16, defined in IEEE standard 754. This is only one of 15 possible 16-bit formats. In this post I am going to consider all 15.

rawabstract:
A year and a half ago I wrote a post about ``half precision'' 16-bit floating point arithmetic, Moler on fp16. I followed this with a bug fix, bug in fp16. Both posts were about fp16, defined in IEEE standard 754. This is only one of 15 possible 16-bit formats. In this post I am going to consider all 15.

entry:
@Misc{Moler:2019:CCV,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: Variable Format Half Precision
                 Floating Point Arithmetic",
  howpublished = "MathWorks Web site.",
  day =          "16",
  month =        jan,
  year =         "2019",
  bibdate =      "Sat Jan 19 15:14:03 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://blogs.mathworks.com/cleve/2019/01/16/variable-format-half-precision-floating-point-arithmetic/",
  abstract =     "A year and a half ago I wrote a post about ``half
                 precision'' 16-bit floating point arithmetic, Moler on
                 fp16. I followed this with a bug fix, bug in fp16. Both
                 posts were about fp16, defined in IEEE standard 754.
                 This is only one of 15 possible 16-bit formats. In this
                 post I am going to consider all 15.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Mopuri:2019:CRB
author: Suresh Mopuri and Swati Bhardwaj and Amit Acharyya
title: Coordinate Rotation-Based Design Methodology for Square Root and Division Computation
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 66
number: 7
pages: 1227--1231
year: 2019
DOI: https://doi.org/10.1109/TCSII.2018.2878599
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Mon Oct 27 10:32:44 2025
bibtimestamp: 2025.10.27 10:32:44 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Suresh Mopuri and Swati Bhardwaj and Amit Acharyya
rawtitle: Coordinate Rotation-Based Design Methodology for Square Root and Division Computation
keywords:
Circuits and systems; Computer architecture; CORDIC; Covariance matrices; Design methodology; division; Hardware; Matrix decomposition; Monitoring; Square root

entry:
@Article{Mopuri:2019:CRB,
  author =       "Suresh Mopuri and Swati Bhardwaj and Amit Acharyya",
  title =        "Coordinate Rotation-Based Design Methodology for
                 Square Root and Division Computation",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "66",
  number =       "7",
  pages =        "1227--1231",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/TCSII.2018.2878599",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "Circuits and systems; Computer architecture; CORDIC;
                 Covariance matrices; Design methodology; division;
                 Hardware; Matrix decomposition; Monitoring; Square
                 root",
}


bibtype: inproceedings
filename: fparith.bib
label: Moriai:2019:PPD
author: Shiho Moriai
title: Privacy-Preserving Deep Learning via Additively Homomorphic Encryption
crossref: Takagi:2019:ISC
pages: 198--198
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00047
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Shiho Moriai
rawtitle: Privacy-Preserving Deep Learning via Additively Homomorphic Encryption
abstract:
We aim at creating a society where we can resolve various social challenges by incorporating the innovations of the fourth industrial revolution (e.g. IoT, big data, AI, robot, and the sharing economy) into every industry and social life. By doing so the society of the future will be one in which new values and services are created continuously, making people's lives more conformable and sustainable. This is Society 5.0, a super-smart society. Security and privacy are key issues to be addressed to realize Society 5.0. Privacy-preserving data analytics will play an important role. In this talk we show our recent works on privacy-preserving data analytics such as privacy-preserving logistic regression and privacy-preserving deep learning. Finally, we show our ongoing research project under JST CREST AI. In this project we are developing privacy-preserving financial data analytics systems that can detect fraud with high security and accuracy. To validate the systems, we will perform demonstration tests with several financial institutions and solve the problems necessary for their implementation in the real world.

keywords:
additively homomorphic encryption; ARITH-26; Big Data; data analysis; Data analysis; data privacy; Deep learning; Digital arithmetic; Encryption; financial data processing; financial institutions; fourth industrial revolution; fraud; Information and communication technology; IoT; JST CREST AI; neural nets; privacy issues; privacy-preserving deep learning; privacy-preserving financial data analytics systems; privacy-preserving logistic regression; regression analysis; social challenges; social life; social sciences computing; Society 5.0; super-smart society

rawabstract:
We aim at creating a society where we can resolve various social challenges by incorporating the innovations of the fourth industrial revolution (e.g. IoT, big data, AI, robot, and the sharing economy) into every industry and social life. By doing so the society of the future will be one in which new values and services are created continuously, making people's lives more conformable and sustainable. This is Society 5.0, a super-smart society. Security and privacy are key issues to be addressed to realize Society 5.0. Privacy-preserving data analytics will play an important role. In this talk we show our recent works on privacy-preserving data analytics such as privacy-preserving logistic regression and privacy-preserving deep learning. Finally, we show our ongoing research project under JST CREST AI. In this project we are developing privacy-preserving financial data analytics systems that can detect fraud with high security and accuracy. To validate the systems, we will perform demonstration tests with several financial institutions and solve the problems necessary for their implementation in the real world.

entry:
@InProceedings{Moriai:2019:PPD,
  author =       "Shiho Moriai",
  title =        "Privacy-Preserving Deep Learning via Additively
                 Homomorphic Encryption",
  crossref =     "Takagi:2019:ISC",
  pages =        "198--198",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00047",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We aim at creating a society where we can resolve
                 various social challenges by incorporating the
                 innovations of the fourth industrial revolution (e.g.
                 IoT, big data, AI, robot, and the sharing economy) into
                 every industry and social life. By doing so the society
                 of the future will be one in which new values and
                 services are created continuously, making people's
                 lives more conformable and sustainable. This is Society
                 5.0, a super-smart society. Security and privacy are
                 key issues to be addressed to realize Society 5.0.
                 Privacy-preserving data analytics will play an
                 important role. In this talk we show our recent works
                 on privacy-preserving data analytics such as
                 privacy-preserving logistic regression and
                 privacy-preserving deep learning. Finally, we show our
                 ongoing research project under JST CREST AI. In this
                 project we are developing privacy-preserving financial
                 data analytics systems that can detect fraud with high
                 security and accuracy. To validate the systems, we will
                 perform demonstration tests with several financial
                 institutions and solve the problems necessary for their
                 implementation in the real world.",
  acknowledgement = ack-nhfb,
  keywords =     "additively homomorphic encryption; ARITH-26; Big Data;
                 data analysis; Data analysis; data privacy; Deep
                 learning; Digital arithmetic; Encryption; financial
                 data processing; financial institutions; fourth
                 industrial revolution; fraud; Information and
                 communication technology; IoT; JST CREST AI; neural
                 nets; privacy issues; privacy-preserving deep learning;
                 privacy-preserving financial data analytics systems;
                 privacy-preserving logistic regression; regression
                 analysis; social challenges; social life; social
                 sciences computing; Society 5.0; super-smart society",
}


bibtype: article
filename: fparith.bib
label: Moroz:2019:EFP
author: Leonid Moroz and Volodymyr Samotyy
title: Efficient Floating-Point Division for Digital Signal Processing Application [Tips & Tricks]
journal: j-IEEE-SIGNAL-PROCESS-MAG
volume: 36
number: 1
pages: 159--163
month: jan
monthnumber: 1
year: 2019
CODEN: ISPRE6
DOI: https://doi.org/10.1109/msp.2018.2875977
ISSN: 1053-5888 (print), 1558-0792 (electronic) OR 10535888 (print), 15580792 (electronic)
ISSNL: 1053-5888 OR 10535888
bibdate: Thu Apr 10 15:04:29 2025
bibtimestamp: 2025.04.10 15:04:29 ???
fjournal: IEEE Signal Processing Magazine
acknowledgement: ack-nhfb
rawauthor: Leonid Moroz and Volodymyr Samotyy
rawtitle: Efficient Floating-Point Division for Digital Signal Processing Application [Tips \& Tricks]
entry:
@Article{Moroz:2019:EFP,
  author =       "Leonid Moroz and Volodymyr Samotyy",
  title =        "Efficient Floating-Point Division for Digital Signal
                 Processing Application [Tips \& Tricks]",
  journal =      j-IEEE-SIGNAL-PROCESS-MAG,
  volume =       "36",
  number =       "1",
  pages =        "159--163",
  month =        jan,
  year =         "2019",
  CODEN =        "ISPRE6",
  DOI =          "https://doi.org/10.1109/msp.2018.2875977",
  ISSN =         "1053-5888 (print), 1558-0792 (electronic)",
  ISSN-L =       "1053-5888",
  bibdate =      "Thu Apr 10 15:04:29 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Signal Processing Magazine",
}


bibtype: article
filename: fparith.bib
label: Munoz-Coreas:2019:QCD
author: E. Munoz-Coreas and H. Thapliyal
title: Quantum Circuit Design of a $T$-count Optimized Integer Multiplier
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 729--739
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2882774
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Mu{\~n}oz-Coreas and H. Thapliyal
rawtitle: Quantum Circuit Design of a {$T$}-count Optimized Integer Multiplier
keywords:
adders; Adders; Clifford+T gates; conditional adder; fault tolerance; Fault tolerance; fault tolerant implementations; Fault tolerant systems; integer multiplication; logic design; Logic gates; quantum arithmetic; quantum circuit design; quantum circuits; Quantum computing; quantum conditional adder circuit; quantum gates; quantum hardware resources; quantum multiplier design; qubits; Registers; reliable quantum circuits; scalable quantum circuits; T-count optimized quantum circuit; T-count savings; Toffoli gate array

entry:
@Article{Munoz-Coreas:2019:QCD,
  author =       "E. Mu{\~n}oz-Coreas and H. Thapliyal",
  title =        "Quantum Circuit Design of a {$T$}-count Optimized
                 Integer Multiplier",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "729--739",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2882774",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "adders; Adders; Clifford+T gates; conditional adder;
                 fault tolerance; Fault tolerance; fault tolerant
                 implementations; Fault tolerant systems; integer
                 multiplication; logic design; Logic gates; quantum
                 arithmetic; quantum circuit design; quantum circuits;
                 Quantum computing; quantum conditional adder circuit;
                 quantum gates; quantum hardware resources; quantum
                 multiplier design; qubits; Registers; reliable quantum
                 circuits; scalable quantum circuits; T-count optimized
                 quantum circuit; T-count savings; Toffoli gate array",
}


bibtype: article
filename: fparith.bib
label: Nabavinejad:2019:CDP
author: Seyed Morteza Nabavinejad and Hassan Hafez-Kolahi and Sherief Reda
title: Coordinated DVFS and Precision Control for Deep Neural Networks
journal: j-IEEE-COMPUT-ARCHIT-LETT
volume: 18
number: 2
pages: 136--140
year: 2019
DOI: https://doi.org/10.1109/LCA.2019.2942020
ISSN: 1556-6056 (print), 1556-6064 (electronic) OR 15566056 (print), 15566064 (electronic)
ISSNL: 1556-6056 OR 15566056
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
fjournal: IEEE Computer Architecture Letters
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208
rawauthor: Seyed Morteza Nabavinejad and Hassan Hafez-Kolahi and Sherief Reda
rawtitle: Coordinated {DVFS} and Precision Control for Deep Neural Networks
keywords:
accuracy; Deep neural network; Graphics processing units; hardware accelerator; Neural networks; power; Power demand; response time; Runtime; Servers; Time factors; Time-frequency analysis

entry:
@Article{Nabavinejad:2019:CDP,
  author =       "Seyed Morteza Nabavinejad and Hassan Hafez-Kolahi and
                 Sherief Reda",
  title =        "Coordinated {DVFS} and Precision Control for Deep
                 Neural Networks",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "18",
  number =       "2",
  pages =        "136--140",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/LCA.2019.2942020",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Computer Architecture Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
  keywords =     "accuracy; Deep neural network; Graphics processing
                 units; hardware accelerator; Neural networks; power;
                 Power demand; response time; Runtime; Servers; Time
                 factors; Time-frequency analysis",
}


bibtype: article
filename: fparith.bib
label: Nannarelli:2019:TFP
author: A. Nannarelli
title: Tunable Floating-Point Adder
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 10
pages: 1553--1560
month: oct
monthnumber: 10
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2906907
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Sep 12 13:33:25 2019
bibtimestamp: 2019.09.12 13:33:25 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Nannarelli
rawtitle: Tunable Floating-Point Adder
keywords:
Adders; addition; Computer architecture; energy efficiency; Floating-point; Google; Hardware; IEEE rounding; Indexes; Standards; Tuning

remark:
From the abstract: ``TFP is a variable precision format in which a given precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of an algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient.''

entry:
@Article{Nannarelli:2019:TFP,
  author =       "A. Nannarelli",
  title =        "Tunable Floating-Point Adder",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "10",
  pages =        "1553--1560",
  month =        oct,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2906907",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Sep 12 13:33:25 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; addition; Computer architecture; energy
                 efficiency; Floating-point; Google; Hardware; IEEE
                 rounding; Indexes; Standards; Tuning",
  remark =       "From the abstract: ``TFP is a variable precision
                 format in which a given precision can be chosen for a
                 single operation by selecting a specific number of bits
                 for significand and exponent in the floating-point
                 representation. By tuning the precision of an algorithm
                 to the minimum precision achieving an acceptable target
                 error, we can make the computation more power
                 efficient.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Nogami:2019:OWV
author: Wakana Nogami and Tsutomu Ikegami and Shin-ichi O'uchi and Ryousei Takano and Tomohiro Kudoh
booktitle: 2019 International Joint Conference on Neural Networks (IJCNN)
title: Optimizing Weight Value Quantization for CNN Inference
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--8
year: 2019
DOI: https://doi.org/10.1109/IJCNN.2019.8852331
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Wakana Nogami and Tsutomu Ikegami and Shin-ichi O'uchi and Ryousei Takano and Tomohiro Kudoh
rawbooktitle: {2019 International Joint Conference on Neural Networks (IJCNN)}
rawtitle: Optimizing Weight Value Quantization for {CNN} Inference
keywords:
Computational modeling; Convolutional Neural Network; Genetic Algorithm; Genetic algorithms; Genomics; Mathematical model; Neural networks; Optimization; Quantization; Quantization (signal); Simulated Annealing; Training

entry:
@InProceedings{Nogami:2019:OWV,
  author =       "Wakana Nogami and Tsutomu Ikegami and Shin-ichi O'uchi
                 and Ryousei Takano and Tomohiro Kudoh",
  booktitle =    "{2019 International Joint Conference on Neural
                 Networks (IJCNN)}",
  title =        "Optimizing Weight Value Quantization for {CNN}
                 Inference",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/IJCNN.2019.8852331",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Computational modeling; Convolutional Neural Network;
                 Genetic Algorithm; Genetic algorithms; Genomics;
                 Mathematical model; Neural networks; Optimization;
                 Quantization; Quantization (signal); Simulated
                 Annealing; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Nurvitadhi:2019:WCW
title: Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 199--207
year: 2019
DOI: https://doi.org/10.1109/FCCM.2019.00035
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawtitle: Why Compete When You Can Work Together: {FPGA-ASIC} Integration for Persistent {RNNs}
author:
Eriko Nurvitadhi and Dongup Kwon and Ali Jafari and Andrew Boutros and Jaewoong Sim and Phillip Tomson and Huseyin Sumbul and Gregory Chen and Phil Knag and Raghavan Kumar and Ram Krishnamurthy and Sergey Gribok and Bogdan Pasca and Martin Langhammer and Debbie Marr and Aravind Dasu

booktitle:
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

keywords:
chiplet; Computational modeling; Deep learning; Field programmable gate arrays; fpga; Graphics processing units; Hazards; persistent AI; Real-time systems; system in package; System-on-chip; Throughput

rawauthor:
Eriko Nurvitadhi and Dongup Kwon and Ali Jafari and Andrew Boutros and Jaewoong Sim and Phillip Tomson and Huseyin Sumbul and Gregory Chen and Phil Knag and Raghavan Kumar and Ram Krishnamurthy and Sergey Gribok and Bogdan Pasca and Martin Langhammer and Debbie Marr and Aravind Dasu

rawbooktitle:
{2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}

entry:
@InProceedings{Nurvitadhi:2019:WCW,
  author =       "Eriko Nurvitadhi and Dongup Kwon and Ali Jafari and
                 Andrew Boutros and Jaewoong Sim and Phillip Tomson and
                 Huseyin Sumbul and Gregory Chen and Phil Knag and
                 Raghavan Kumar and Ram Krishnamurthy and Sergey Gribok
                 and Bogdan Pasca and Martin Langhammer and Debbie Marr
                 and Aravind Dasu",
  booktitle =    "{2019 IEEE 27th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "Why Compete When You Can Work Together: {FPGA-ASIC}
                 Integration for Persistent {RNNs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "199--207",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/FCCM.2019.00035",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "chiplet; Computational modeling; Deep learning; Field
                 programmable gate arrays; fpga; Graphics processing
                 units; Hazards; persistent AI; Real-time systems;
                 system in package; System-on-chip; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Pandey:2019:UFP
author: Kumar Sambhav Pandey and Dinesh Kumar B and Neeraj Goel and Hitesh Shrimali
title: An Ultra-Fast Parallel Prefix Adder
crossref: Takagi:2019:ISC
pages: 125--134
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00034
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Kumar Sambhav Pandey and Dinesh Kumar B and Neeraj Goel and Hitesh Shrimali
rawtitle: An Ultra-Fast Parallel Prefix Adder
abstract:
Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26% improvement.

keywords:
adder recurrence relations; Adders; adders; architecture level; area-throughput characteristics; ARITH-26; arithmetic units; Computer architecture; Digital arithmetic; digital arithmetic; integrated circuit layout; integrated logic circuits; logic design; Logic gates; Microprocessors; Parallel prefix adders; Terminology; Topology; ultrafast parallel prefix adder

rawabstract:
Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26\% improvement.

entry:
@InProceedings{Pandey:2019:UFP,
  author =       "Kumar Sambhav Pandey and Dinesh Kumar B and Neeraj
                 Goel and Hitesh Shrimali",
  title =        "An Ultra-Fast Parallel Prefix Adder",
  crossref =     "Takagi:2019:ISC",
  pages =        "125--134",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00034",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Parallel Prefix adders are arguably the most commonly
                 used arithmetic units. They have been extensively
                 investigated at architecture level, register transfer
                 level (RTL), gate level, circuit level as well as
                 layout level giving rise to a plethora of mathematical
                 formulations, topologies and implementations. This
                 paper contributes significantly to the understanding of
                 these parallel prefix adders in a couple of ways.
                 Firstly, it attempts to describe various such parallel
                 prefix adders in elegant and consistent formulations.
                 Secondly, a new family of parallel prefix adders is
                 proposed at architecture level. The estimates of the
                 area-throughput characteristics for an instance of this
                 family are also presented. While the speeds achieved by
                 this instance match those achieved by the state of the
                 art adders, their area characteristics exhibit upto
                 26\% improvement.",
  acknowledgement = ack-nhfb,
  keywords =     "adder recurrence relations; Adders; adders;
                 architecture level; area-throughput characteristics;
                 ARITH-26; arithmetic units; Computer architecture;
                 Digital arithmetic; digital arithmetic; integrated
                 circuit layout; integrated logic circuits; logic
                 design; Logic gates; Microprocessors; Parallel prefix
                 adders; Terminology; Topology; ultrafast parallel
                 prefix adder",
}


bibtype: article
filename: fparith.bib
label: Parhi:2019:CAF
author: Keshab K. Parhi and Yin Liu
title: Computing Arithmetic Functions Using Stochastic Logic by Series Expansion
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 7
number: 1
pages: 44--59
month: jan
monthnumber: 1
year: 2019
DOI: https://doi.org/10.1109/TETC.2016.2618750
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Keshab K. Parhi and Yin Liu
rawtitle: Computing Arithmetic Functions Using Stochastic Logic by Series Expansion
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib

abstract:
Stochastic logic implementations of complex arithmetic functions, such as trigonometric, exponential, and sigmoid, are derived based on truncated versions of their Maclaurin series expansions. This paper makes three contributions. First, it is shown that a polynomial can be implemented using multiple levels of NAND gates based on Horner's rule, if the coefficients are alternately positive and negative and their magnitudes are monotonically decreasing. Truncated Maclaurin series expansions of arithmetic functions are used to generate polynomials which satisfy these constraints. The input and output in these functions are represented by unipolar representation. Functions including sine, cosine, tangent hyperbolic, logarithm and exponential can be implemented using this method. Second, for a polynomial that does not satisfy these constraints, it still can be implemented based on Horner's rule if each factor of the polynomial satisfies these constraints. It is shown that functions such as $ sin pi x / pi $, $ e^-a x $, $ tanh a x $ and $ sigmoid (a x^3) $ (for values of $ a > 1$) can be implemented using stochastic logic using factorization in combination with Horner's rule. Third, format conversion is proposed for arithmetic functions with input and output represented in different formats, such as $ cos pi x$ given $ x in [0, 1]$ and $ sigmoid (x)$ given $ x in [ - 1, 1]$. Polynomials are transformed to equivalent forms that naturally exploit format conversions. The proposed stochastic logic circuits outperform the well-known Bernstein polynomial based and finite-state-machine (FSM) based implementations. Furthermore, the hardware complexity and the critical path of the proposed implementations are less than the well-known Bernstein polynomial based and FSM based implementations for most cases

rawabstract:
Stochastic logic implementations of complex arithmetic functions, such as trigonometric, exponential, and sigmoid, are derived based on truncated versions of their Maclaurin series expansions. This paper makes three contributions. First, it is shown that a polynomial can be implemented using multiple levels of NAND gates based on Horner's rule, if the coefficients are alternately positive and negative and their magnitudes are monotonically decreasing. Truncated Maclaurin series expansions of arithmetic functions are used to generate polynomials which satisfy these constraints. The input and output in these functions are represented by unipolar representation. Functions including sine, cosine, tangent hyperbolic, logarithm and exponential can be implemented using this method. Second, for a polynomial that does not satisfy these constraints, it still can be implemented based on Horner's rule if each factor of the polynomial satisfies these constraints. It is shown that functions such as $ \sin \pi x / \pi $, $ e^{-a x} $, $ \tanh a x $ and $ \sigmoid (a x^3) $ (for values of $ a > 1$) can be implemented using stochastic logic using factorization in combination with Horner's rule. Third, format conversion is proposed for arithmetic functions with input and output represented in different formats, such as $ \cos \pi x$ given $ x \in [0, 1]$ and $ \sigmoid (x)$ given $ x \in [ - 1, 1]$. Polynomials are transformed to equivalent forms that naturally exploit format conversions. The proposed stochastic logic circuits outperform the well-known Bernstein polynomial based and finite-state-machine (FSM) based implementations. Furthermore, the hardware complexity and the critical path of the proposed implementations are less than the well-known Bernstein polynomial based and FSM based implementations for most cases

entry:
@Article{Parhi:2019:CAF,
  author =       "Keshab K. Parhi and Yin Liu",
  title =        "Computing Arithmetic Functions Using Stochastic Logic
                 by Series Expansion",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "7",
  number =       "1",
  pages =        "44--59",
  month =        jan # "\slash " # mar,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/TETC.2016.2618750",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "Stochastic logic implementations of complex arithmetic
                 functions, such as trigonometric, exponential, and
                 sigmoid, are derived based on truncated versions of
                 their Maclaurin series expansions. This paper makes
                 three contributions. First, it is shown that a
                 polynomial can be implemented using multiple levels of
                 NAND gates based on Horner's rule, if the coefficients
                 are alternately positive and negative and their
                 magnitudes are monotonically decreasing. Truncated
                 Maclaurin series expansions of arithmetic functions are
                 used to generate polynomials which satisfy these
                 constraints. The input and output in these functions
                 are represented by unipolar representation. Functions
                 including sine, cosine, tangent hyperbolic, logarithm
                 and exponential can be implemented using this method.
                 Second, for a polynomial that does not satisfy these
                 constraints, it still can be implemented based on
                 Horner's rule if each factor of the polynomial
                 satisfies these constraints. It is shown that functions
                 such as $ \sin \pi x / \pi $, $ e^{-a x} $, $ \tanh a x
                 $ and $ \sigmoid (a x^3) $ (for values of $ a > 1$) can
                 be implemented using stochastic logic using
                 factorization in combination with Horner's rule. Third,
                 format conversion is proposed for arithmetic functions
                 with input and output represented in different formats,
                 such as $ \cos \pi x$ given $ x \in [0, 1]$ and $
                 \sigmoid (x)$ given $ x \in [ - 1, 1]$. Polynomials are
                 transformed to equivalent forms that naturally exploit
                 format conversions. The proposed stochastic logic
                 circuits outperform the well-known Bernstein polynomial
                 based and finite-state-machine (FSM) based
                 implementations. Furthermore, the hardware complexity
                 and the critical path of the proposed implementations
                 are less than the well-known Bernstein polynomial based
                 and FSM based implementations for most cases",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Parry:2019:PSO
author: Katherine Parry
title: A Perspective into Squarer Optimization
crossref: Takagi:2019:ISC
pages: 124--124
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00033
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Katherine Parry
rawtitle: A Perspective into Squarer Optimization
abstract:
Artificial Intelligence applications do millions of square calculations, such as within Gradient Descent or Principle Component Analysis (PCA). Any time measured or observed data is analyzed; the error, residual, or a comparison against a norm, it is evaluated using a square operation. Squarers are special purpose multipliers that can be employed when the operands are identical. Most calculations use slower multipliers, even though squarers calculate faster, use less power, and occupy less area. Multiplication is composed of a series of partial products that are accumulated to result in the multiplied product. Multiplier and squarer propagation delay is assessed using the number of partial products, or more their addition. The calculation of partial products can occur in parallel, thus does not significantly tax the propagation delay, but carries from their addition create computational dependencies. A standard 8-bit multiplier requires 56 partial product additions and previous work has reduced a squarer to 22 partial products sums. This paper reviews the previous technology and illustrates further Boolean optimizations that minimize the number of additions to 15 partial products.

keywords:
8-bit multiplier; ARITH-26; Artificial intelligence; artificial intelligence applications; Boolean functions; Boolean optimizations; Digital arithmetic; digital arithmetic; gradient descent; Measurement uncertainty; multiplied product; multiplying circuits; optimisation; Optimization; partial product additions; partial products sums; Principal component analysis; principle component analysis; Propagation delay; special purpose multipliers; square calculations; square operation; squarer optimization; squarer propagation delay; Urban areas

rawabstract:
Artificial Intelligence applications do millions of square calculations, such as within Gradient Descent or Principle Component Analysis (PCA). Any time measured or observed data is analyzed; the error, residual, or a comparison against a norm, it is evaluated using a square operation. Squarers are special purpose multipliers that can be employed when the operands are identical. Most calculations use slower multipliers, even though squarers calculate faster, use less power, and occupy less area. Multiplication is composed of a series of partial products that are accumulated to result in the multiplied product. Multiplier and squarer propagation delay is assessed using the number of partial products, or more their addition. The calculation of partial products can occur in parallel, thus does not significantly tax the propagation delay, but carries from their addition create computational dependencies. A standard 8-bit multiplier requires 56 partial product additions and previous work has reduced a squarer to 22 partial products sums. This paper reviews the previous technology and illustrates further Boolean optimizations that minimize the number of additions to 15 partial products.

entry:
@InProceedings{Parry:2019:PSO,
  author =       "Katherine Parry",
  title =        "A Perspective into Squarer Optimization",
  crossref =     "Takagi:2019:ISC",
  pages =        "124--124",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00033",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Artificial Intelligence applications do millions of
                 square calculations, such as within Gradient Descent or
                 Principle Component Analysis (PCA). Any time measured
                 or observed data is analyzed; the error, residual, or a
                 comparison against a norm, it is evaluated using a
                 square operation. Squarers are special purpose
                 multipliers that can be employed when the operands are
                 identical. Most calculations use slower multipliers,
                 even though squarers calculate faster, use less power,
                 and occupy less area. Multiplication is composed of a
                 series of partial products that are accumulated to
                 result in the multiplied product. Multiplier and
                 squarer propagation delay is assessed using the number
                 of partial products, or more their addition. The
                 calculation of partial products can occur in parallel,
                 thus does not significantly tax the propagation delay,
                 but carries from their addition create computational
                 dependencies. A standard 8-bit multiplier requires 56
                 partial product additions and previous work has reduced
                 a squarer to 22 partial products sums. This paper
                 reviews the previous technology and illustrates further
                 Boolean optimizations that minimize the number of
                 additions to 15 partial products.",
  acknowledgement = ack-nhfb,
  keywords =     "8-bit multiplier; ARITH-26; Artificial intelligence;
                 artificial intelligence applications; Boolean
                 functions; Boolean optimizations; Digital arithmetic;
                 digital arithmetic; gradient descent; Measurement
                 uncertainty; multiplied product; multiplying circuits;
                 optimisation; Optimization; partial product additions;
                 partial products sums; Principal component analysis;
                 principle component analysis; Propagation delay;
                 special purpose multipliers; square calculations;
                 square operation; squarer optimization; squarer
                 propagation delay; Urban areas",
}


bibtype: inproceedings
filename: fparith.bib
label: Pasca:2019:HDP
author: Bogdan Pasca
title: Hybrid Dot-Product Design for FP-Enabled FPGAs
crossref: Takagi:2019:ISC
pages: 194--196
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00045
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Bogdan Pasca
rawtitle: Hybrid Dot-Product Design for {FP}-Enabled {FPGAs}
abstract:
FPGAs are becoming interesting solutions for neural network training acceleration. Efficient implementation of dot-products, as part of matrix-matrix multiply engines, plays a key role towards this. The now de facto standard involves the matrix multiplication on bfloat16 inputs, with all reductions be performed in single-precision arithmetic. We present here a generic hybrid dot-product implementation that: (1) has a user-defined accuracy knob and (2) targets a user-defined logic/DSP ratio. Since our architecture is very specialized to a given target device, we discuss the challenges in generating this architecture automatically.

keywords:
Adders; ARITH-26; arithmetic; Bandwidth; bfloat16; dot product; dot-products; Field programmable gate arrays; field programmable gate arrays; floating point; floating point arithmetic; FP-enabled FPGA; FPGA; generator; hybrid; hybrid dot-product design; hybrid dot-product implementation; Lead; logic design; matrix multiplication; matrix-matrix multiply engines; multiplying circuits; neural nets; neural network training; Neural networks; single precision; single-precision arithmetic; Tools; Training

rawabstract:
FPGAs are becoming interesting solutions for neural network training acceleration. Efficient implementation of dot-products, as part of matrix-matrix multiply engines, plays a key role towards this. The now de facto standard involves the matrix multiplication on bfloat16 inputs, with all reductions be performed in single-precision arithmetic. We present here a generic hybrid dot-product implementation that: (1) has a user-defined accuracy knob and (2) targets a user-defined logic/DSP ratio. Since our architecture is very specialized to a given target device, we discuss the challenges in generating this architecture automatically.

entry:
@InProceedings{Pasca:2019:HDP,
  author =       "Bogdan Pasca",
  title =        "Hybrid Dot-Product Design for {FP}-Enabled {FPGAs}",
  crossref =     "Takagi:2019:ISC",
  pages =        "194--196",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00045",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "FPGAs are becoming interesting solutions for neural
                 network training acceleration. Efficient implementation
                 of dot-products, as part of matrix-matrix multiply
                 engines, plays a key role towards this. The now de
                 facto standard involves the matrix multiplication on
                 bfloat16 inputs, with all reductions be performed in
                 single-precision arithmetic. We present here a generic
                 hybrid dot-product implementation that: (1) has a
                 user-defined accuracy knob and (2) targets a
                 user-defined logic/DSP ratio. Since our architecture is
                 very specialized to a given target device, we discuss
                 the challenges in generating this architecture
                 automatically.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-26; arithmetic; Bandwidth; bfloat16; dot
                 product; dot-products; Field programmable gate arrays;
                 field programmable gate arrays; floating point;
                 floating point arithmetic; FP-enabled FPGA; FPGA;
                 generator; hybrid; hybrid dot-product design; hybrid
                 dot-product implementation; Lead; logic design; matrix
                 multiplication; matrix-matrix multiply engines;
                 multiplying circuits; neural nets; neural network
                 training; Neural networks; single precision;
                 single-precision arithmetic; Tools; Training",
}


bibtype: article
filename: fparith.bib
label: Pranesh:2019:LPF
author: Srikara Pranesh
title: Low Precision Floating-Point Formats: The Wild West of Computer Arithmetic
journal: j-SIAM-NEWS
volume: 52
number: 9
pages: 12--12
month: nov
monthnumber: 11
year: 2019
ISSN: 0036-1437 OR 00361437
bibdate: Mon Nov 04 14:49:07 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.11.04 14:49:07 ???
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: http://www.siam.org/news/
rawauthor: Srikara Pranesh
rawtitle: Low Precision Floating-Point Formats: The {Wild West} of Computer Arithmetic
URL:
https://sinews.siam.org/Details-Page/low-precision-floating-point-formats-the-wild-west-of-computer-arithmetic

entry:
@Article{Pranesh:2019:LPF,
  author =       "Srikara Pranesh",
  title =        "Low Precision Floating-Point Formats: The {Wild West}
                 of Computer Arithmetic",
  journal =      j-SIAM-NEWS,
  volume =       "52",
  number =       "9",
  pages =        "12--12",
  month =        nov,
  year =         "2019",
  DOI =          "",
  ISSN =         "0036-1437",
  bibdate =      "Mon Nov 04 14:49:07 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/low-precision-floating-point-formats-the-wild-west-of-computer-arithmetic",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "http://www.siam.org/news/",
}


bibtype: article
filename: fparith.bib
label: Qi:2019:GGI
author: Meng Qi and Ke Yan and Yuanjie Zheng
journal: j-IEEE-ACCESS
volume: 7
pages: 60868--60876
year: 2019
DOI: https://doi.org/10.1109/ACCESS.2019.2911641
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Meng Qi and Ke Yan and Yuanjie Zheng
title:
GPredicates: GPU Implementation of Robust and Adaptive Floating-Point Predicates for Computational Geometry

keywords:
Arbitrary precision floating-point arithmetic; Computational geometry; computational geometry; geometric robustness; GPGPU; Graphics processing units; incircle test; Instruction sets; Memory management; orientation test; Parallel processing; Three-dimensional displays; Two dimensional displays

rawtitle:
{GPredicates}: {GPU} Implementation of Robust and Adaptive Floating-Point Predicates for Computational Geometry

entry:
@Article{Qi:2019:GGI,
  author =       "Meng Qi and Ke Yan and Yuanjie Zheng",
  title =        "{GPredicates}: {GPU} Implementation of Robust and
                 Adaptive Floating-Point Predicates for Computational
                 Geometry",
  journal =      j-IEEE-ACCESS,
  volume =       "7",
  pages =        "60868--60876",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ACCESS.2019.2911641",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Arbitrary precision floating-point arithmetic;
                 Computational geometry; computational geometry;
                 geometric robustness; GPGPU; Graphics processing units;
                 incircle test; Instruction sets; Memory management;
                 orientation test; Parallel processing;
                 Three-dimensional displays; Two dimensional displays",
}


bibtype: article
filename: fparith.bib
label: Reyhani-Masoleh:2019:NMI
author: A. Reyhani-Masoleh and H. El-Razouk and A. Monfared
title: New Multiplicative Inverse Architectures Using Gaussian Normal Basis
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 991--1006
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2859941
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Reyhani-Masoleh and H. El-Razouk and A. Monfared
rawtitle: New Multiplicative Inverse Architectures Using {Gaussian} Normal Basis
keywords:
application specific integrated circuits; arithmetic operations; binary fields; classic inversion scheme; classic-based addition chains; classical-interleaved architecture; classical-interleaved inverter; CMOS integrated circuits; Computer architecture; cryptography; Digit-level multiplier; digital arithmetic; field inversion; field programmable gate arrays; finite field; FSISM; FSISM processor; fully-serial-in square-multiply processor; Galois fields; Gaussian normal basis; Gaussian processes; hybrid-double multiplication; input registers; inversion architecture; inversion architectures; Inverters; invertors; Itoh-Tsujii algorithm; latency; Logic gates; multiplication cycle; multiplicative inverse architectures; multiplying circuits; NIST; Propagation delay; size 65.0 nm; ternary Itoh-Tsujii algorithm

entry:
@Article{Reyhani-Masoleh:2019:NMI,
  author =       "A. Reyhani-Masoleh and H. El-Razouk and A. Monfared",
  title =        "New Multiplicative Inverse Architectures Using
                 {Gaussian} Normal Basis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "991--1006",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2859941",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "application specific integrated circuits; arithmetic
                 operations; binary fields; classic inversion scheme;
                 classic-based addition chains; classical-interleaved
                 architecture; classical-interleaved inverter; CMOS
                 integrated circuits; Computer architecture;
                 cryptography; Digit-level multiplier; digital
                 arithmetic; field inversion; field programmable gate
                 arrays; finite field; FSISM; FSISM processor;
                 fully-serial-in square-multiply processor; Galois
                 fields; Gaussian normal basis; Gaussian processes;
                 hybrid-double multiplication; input registers;
                 inversion architecture; inversion architectures;
                 Inverters; invertors; Itoh-Tsujii algorithm; latency;
                 Logic gates; multiplication cycle; multiplicative
                 inverse architectures; multiplying circuits; NIST;
                 Propagation delay; size 65.0 nm; ternary Itoh-Tsujii
                 algorithm",
}


bibtype: inproceedings
filename: fparith.bib
label: Rohloff:2019:CAR
author: Kurt Rohloff
crossref: Takagi:2019:ISC
pages: 197--197
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00046
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Kurt Rohloff
title:
Computer Arithmetic Research to Accelerate Privacy-Protecting Encrypted Computing Such as Homomorphic Encryption

abstract:
One of the first major breakthroughs of computer science in the 21st century has been the discovery and practical demonstration of encrypted computing technologies such as Fully Homomorphic Encryption (FHE). Encrypted computing technologies allow sensitive data to be encrypted such that arbitrary programs can be securely run over the encrypted data where the output, when decrypted, is equivalent to the result of running the original algorithm on the unencrypted data. In this talk we focus on the use of and potential for computer arithmetic research to enable more practical encrypted computing, such as to accelerate advanced encryption implementations on custom hardware. These technologies are ground-breaking in their ability for privacy-preserving data science on sensitive data sets with minimal costs in terms of engineering effort, power, compute resources, etc. ldots . We discuss theory, design, algorithmic, hardware, software engineering and systems research that is enabling applications of encrypted computing in regulated data industries, such as in medical and financial domains. We use our work using accelerating the PALISADE open-source homomorphic encryption software library for practical applications in case studies.

keywords:
Acceleration; advanced encryption implementations; ARITH-26; computer arithmetic research; computer science; Computer science; Computers; cryptography; data privacy; Digital arithmetic; encrypted computing technologies; encrypted data; Encryption; fully homomorphic encryption; Hardware; PALISADE open-source homomorphic encryption software library; privacy-preserving data science; privacy-protecting encrypted computing; public domain software; regulated data industries; sensitive data sets; software engineering; software libraries; unencrypted data

rawabstract:
One of the first major breakthroughs of computer science in the 21st century has been the discovery and practical demonstration of encrypted computing technologies such as Fully Homomorphic Encryption (FHE). Encrypted computing technologies allow sensitive data to be encrypted such that arbitrary programs can be securely run over the encrypted data where the output, when decrypted, is equivalent to the result of running the original algorithm on the unencrypted data. In this talk we focus on the use of and potential for computer arithmetic research to enable more practical encrypted computing, such as to accelerate advanced encryption implementations on custom hardware. These technologies are ground-breaking in their ability for privacy-preserving data science on sensitive data sets with minimal costs in terms of engineering effort, power, compute resources, etc. \ldots{}. We discuss theory, design, algorithmic, hardware, software engineering and systems research that is enabling applications of encrypted computing in regulated data industries, such as in medical and financial domains. We use our work using accelerating the PALISADE open-source homomorphic encryption software library for practical applications in case studies.

rawtitle:
Computer Arithmetic Research to Accelerate Privacy-Protecting Encrypted Computing Such as Homomorphic Encryption

entry:
@InProceedings{Rohloff:2019:CAR,
  author =       "Kurt Rohloff",
  title =        "Computer Arithmetic Research to Accelerate
                 Privacy-Protecting Encrypted Computing Such as
                 Homomorphic Encryption",
  crossref =     "Takagi:2019:ISC",
  pages =        "197--197",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00046",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "One of the first major breakthroughs of computer
                 science in the 21st century has been the discovery and
                 practical demonstration of encrypted computing
                 technologies such as Fully Homomorphic Encryption
                 (FHE). Encrypted computing technologies allow sensitive
                 data to be encrypted such that arbitrary programs can
                 be securely run over the encrypted data where the
                 output, when decrypted, is equivalent to the result of
                 running the original algorithm on the unencrypted data.
                 In this talk we focus on the use of and potential for
                 computer arithmetic research to enable more practical
                 encrypted computing, such as to accelerate advanced
                 encryption implementations on custom hardware. These
                 technologies are ground-breaking in their ability for
                 privacy-preserving data science on sensitive data sets
                 with minimal costs in terms of engineering effort,
                 power, compute resources, etc. \ldots{}. We discuss
                 theory, design, algorithmic, hardware, software
                 engineering and systems research that is enabling
                 applications of encrypted computing in regulated data
                 industries, such as in medical and financial domains.
                 We use our work using accelerating the PALISADE
                 open-source homomorphic encryption software library for
                 practical applications in case studies.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; advanced encryption implementations;
                 ARITH-26; computer arithmetic research; computer
                 science; Computer science; Computers; cryptography;
                 data privacy; Digital arithmetic; encrypted computing
                 technologies; encrypted data; Encryption; fully
                 homomorphic encryption; Hardware; PALISADE open-source
                 homomorphic encryption software library;
                 privacy-preserving data science; privacy-protecting
                 encrypted computing; public domain software; regulated
                 data industries; sensitive data sets; software
                 engineering; software libraries; unencrypted data",
}


bibtype: article
filename: fparith.bib
label: Roughan:2019:PSS
author: Matthew Roughan
title: Practically surreal: Surreal arithmetic in Julia
journal: j-SOFTWAREX
volume: 9
pages: 293--298
month: jan
monthnumber: 1
year: 2019
ISSN: 2352-7110 OR 23527110
ISSNL: 2352-7110 OR 23527110
bibdate: Mon Oct 14 09:45:43 MDT 2019
bibtimestamp: 2019.10.14 09:45:43 MDT
URL: http://www.sciencedirect.com/science/article/pii/S2352711018302152
fjournal: SoftwareX
keywords: Conway's surreal numbers
acknowledgement: ack-nhfb
journalURL: https://www.sciencedirect.com/journal/softwarex/issues
rawauthor: Matthew Roughan
rawtitle: Practically surreal: {Surreal} arithmetic in {Julia}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/softwarex.bib

entry:
@Article{Roughan:2019:PSS,
  author =       "Matthew Roughan",
  title =        "Practically surreal: {Surreal} arithmetic in {Julia}",
  journal =      j-SOFTWAREX,
  volume =       "9",
  number =       "??",
  pages =        "293--298",
  month =        jan # "\slash " # jun,
  year =         "2019",
  CODEN =        "????",
  ISSN =         "2352-7110",
  ISSN-L =       "2352-7110",
  bibdate =      "Mon Oct 14 09:45:43 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/softwarex.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S2352711018302152",
  acknowledgement = ack-nhfb,
  fjournal =     "SoftwareX",
  journal-URL =  "https://www.sciencedirect.com/journal/softwarex/issues",
  keywords =     "Conway's surreal numbers",
}


bibtype: inproceedings
filename: fparith.bib
label: Rump:2019:EBC
author: Siegfried M. Rump
title: Error Bounds for Computer Arithmetics
crossref: Takagi:2019:ISC
pages: 1--14
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00011
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Siegfried M. Rump
rawtitle: Error Bounds for Computer Arithmetics
abstract:
This note summarizes recent progress in error bounds for compound operations performed in some computer arithmetic. Given a general set of real numbers together with some operations satisfying the first standard model, we identify three types A, B, and C of weak sufficient assumptions implying new results and sharper error estimates. Those include linearized error estimates in the number of operations, faithfully rounded and reproducible results. All types of assumptions are satisfied for an IEEE-754 p-digit base- floating-point arithmetic.

keywords:
ARITH-26; Compounds; Computational modeling; computer arithmetic; CREST; Digital arithmetic; error analysis; error bounds; floating point arithmetic; IEEE-754 p-digit base- floating-point arithmetic; Japan Science and Technology Agency; Kernel; Standards; Switches; Vegetation

rawabstract:
This note summarizes recent progress in error bounds for compound operations performed in some computer arithmetic. Given a general set of real numbers together with some operations satisfying the first standard model, we identify three types A, B, and C of weak sufficient assumptions implying new results and sharper error estimates. Those include linearized error estimates in the number of operations, faithfully rounded and reproducible results. All types of assumptions are satisfied for an IEEE-754 p-digit base- floating-point arithmetic.

entry:
@InProceedings{Rump:2019:EBC,
  author =       "Siegfried M. Rump",
  title =        "Error Bounds for Computer Arithmetics",
  crossref =     "Takagi:2019:ISC",
  pages =        "1--14",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00011",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This note summarizes recent progress in error bounds
                 for compound operations performed in some computer
                 arithmetic. Given a general set of real numbers
                 together with some operations satisfying the first
                 standard model, we identify three types A, B, and C of
                 weak sufficient assumptions implying new results and
                 sharper error estimates. Those include linearized error
                 estimates in the number of operations, faithfully
                 rounded and reproducible results. All types of
                 assumptions are satisfied for an IEEE-754 p-digit base-
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Compounds; Computational modeling; computer
                 arithmetic; CREST; Digital arithmetic; error analysis;
                 error bounds; floating point arithmetic; IEEE-754
                 p-digit base- floating-point arithmetic; Japan Science
                 and Technology Agency; Kernel; Standards; Switches;
                 Vegetation",
}


bibtype: article
filename: fparith.bib
label: Salamati:2019:MEM
author: Mahmoud Salamati and Rocco Salvia and Eva Darulova and Sadegh Soudjani and Rupak Majumdar
title: Memory-Efficient Mixed-Precision Implementations for Robust Explicit Model Predictive Control
journal: j-TECS
volume: 18
number: 5s
pages: 100:1--100:??
month: oct
monthnumber: 10
year: 2019
DOI: https://doi.org/10.1145/3358223
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Oct 17 18:16:44 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2019.10.17 18:16:44 MDT
URL: https://dl.acm.org/ft_gateway.cfm?id=3358223
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 100
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawauthor: Mahmoud Salamati and Rocco Salvia and Eva Darulova and Sadegh Soudjani and Rupak Majumdar
rawtitle: Memory-Efficient Mixed-Precision Implementations for Robust Explicit Model Predictive Control
abstract:
We propose an optimization for space-efficient implementations of explicit model-predictive controllers (MPC) for robust control of linear time-invariant (LTI) systems on embedded platforms. We obtain an explicit-form robust model-predictive controller as a solution to a multi-parametric linear programming problem. The structure of the controller is a polyhedral decomposition of the control domain, with an affine map for each domain. While explicit MPC is suited for embedded devices with low computational power, the memory requirements for such controllers can be high. We provide an optimization algorithm for a mixed-precision implementation of the controller, where the deviation of the implemented controller from the original one is within the robustness margin of the robust control problem. The core of the mixed-precision optimization is an iterative static analysis that co-designs a robust controller and a low-bitwidth approximation that is statically guaranteed to always be within the robustness margin of the original controller. We have implemented our algorithm and show on a set of benchmarks that our optimization can reduce space requirements by up to 20.9% and on average by 12.6% compared to a minimal uniform precision implementation of the original controller.

rawabstract:
We propose an optimization for space-efficient implementations of explicit model-predictive controllers (MPC) for robust control of linear time-invariant (LTI) systems on embedded platforms. We obtain an explicit-form robust model-predictive controller as a solution to a multi-parametric linear programming problem. The structure of the controller is a polyhedral decomposition of the control domain, with an affine map for each domain. While explicit MPC is suited for embedded devices with low computational power, the memory requirements for such controllers can be high. We provide an optimization algorithm for a mixed-precision implementation of the controller, where the deviation of the implemented controller from the original one is within the robustness margin of the robust control problem. The core of the mixed-precision optimization is an iterative static analysis that co-designs a robust controller and a low-bitwidth approximation that is statically guaranteed to always be within the robustness margin of the original controller. We have implemented our algorithm and show on a set of benchmarks that our optimization can reduce space requirements by up to 20.9\% and on average by 12.6\% compared to a minimal uniform precision implementation of the original controller.

entry:
@Article{Salamati:2019:MEM,
  author =       "Mahmoud Salamati and Rocco Salvia and Eva Darulova and
                 Sadegh Soudjani and Rupak Majumdar",
  title =        "Memory-Efficient Mixed-Precision Implementations for
                 Robust Explicit Model Predictive Control",
  journal =      j-TECS,
  volume =       "18",
  number =       "5s",
  pages =        "100:1--100:??",
  month =        oct,
  year =         "2019",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3358223",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Oct 17 18:16:44 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/ft_gateway.cfm?id=3358223",
  abstract =     "We propose an optimization for space-efficient
                 implementations of explicit model-predictive
                 controllers (MPC) for robust control of linear
                 time-invariant (LTI) systems on embedded platforms. We
                 obtain an explicit-form robust model-predictive
                 controller as a solution to a multi-parametric linear
                 programming problem. The structure of the controller is
                 a polyhedral decomposition of the control domain, with
                 an affine map for each domain. While explicit MPC is
                 suited for embedded devices with low computational
                 power, the memory requirements for such controllers can
                 be high. We provide an optimization algorithm for a
                 mixed-precision implementation of the controller, where
                 the deviation of the implemented controller from the
                 original one is within the robustness margin of the
                 robust control problem. The core of the mixed-precision
                 optimization is an iterative static analysis that
                 co-designs a robust controller and a low-bitwidth
                 approximation that is statically guaranteed to always
                 be within the robustness margin of the original
                 controller. We have implemented our algorithm and show
                 on a set of benchmarks that our optimization can reduce
                 space requirements by up to 20.9\% and on average by
                 12.6\% compared to a minimal uniform precision
                 implementation of the original controller.",
  acknowledgement = ack-nhfb,
  articleno =    "100",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: inproceedings
filename: fparith.bib
label: Sarkar:2019:RAP
author: Souradip Sarkar and Purushotham Murugappa Velayuthan and Manil Dev Gomony
editor: IEEE
booktitle: 2019 22nd Euromicro Conference on Digital System Design (DSD)
title: A Reconfigurable Architecture for Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 82--87
year: 2019
DOI: https://doi.org/10.1109/DSD.2019.00022
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Souradip Sarkar and Purushotham Murugappa Velayuthan and Manil Dev Gomony
rawbooktitle: {2019 22nd Euromicro Conference on Digital System Design (DSD)}
raweditor: {IEEE}
rawtitle: A Reconfigurable Architecture for Posit Arithmetic
entry:
@InProceedings{Sarkar:2019:RAP,
  author =       "Souradip Sarkar and Purushotham Murugappa Velayuthan
                 and Manil Dev Gomony",
  editor =       "{IEEE}",
  booktitle =    "{2019 22nd Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "A Reconfigurable Architecture for Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "82--87",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/DSD.2019.00022",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Seo:2019:HTM
author: Jihee Seo and Dae Hyun Kim
title: High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding
crossref: Takagi:2019:ISC
pages: 143--150
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00036
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Jihee Seo and Dae Hyun Kim
rawtitle: High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding
abstract:
In this paper, we propose a pipelined multiplier architecture that can resolve data dependencies. The proposed architecture generates partial results in the pipeline stages of the multiplier and forwards the partial results back to the pipeline stages through so-called fast-forwarding paths, thereby enabling an execution of dependent multiplications with a minimum delay penalty. We apply the architecture to a normal binary multiplier (NBBE-2) and two redundant binary multipliers (RBBE-4 and CRBBE-4) and compare the execution time, clock period, area, and power consumption of the multipliers. The simulation results show that the proposed architecture achieves up to 30% execution time reduction.

keywords:
ARITH-26; Clocks; Computer architecture; data dependencies; Delays; dependent multiplications; digital arithmetic; execution time reduction; Fast Forwarding; fast-forwarding paths; high-throughput multiplier architectures; intra-unit fast forwarding; minimum delay penalty; Multiplexing; Multiplication; Multiplier; multiplying circuits; normal binary multiplier; pipeline processing; Pipeline processing; pipeline stages; pipelined multiplier architecture; Pipelines; redundant binary multipliers; Throughput

rawabstract:
In this paper, we propose a pipelined multiplier architecture that can resolve data dependencies. The proposed architecture generates partial results in the pipeline stages of the multiplier and forwards the partial results back to the pipeline stages through so-called fast-forwarding paths, thereby enabling an execution of dependent multiplications with a minimum delay penalty. We apply the architecture to a normal binary multiplier (NBBE-2) and two redundant binary multipliers (RBBE-4 and CRBBE-4) and compare the execution time, clock period, area, and power consumption of the multipliers. The simulation results show that the proposed architecture achieves up to 30\% execution time reduction.

entry:
@InProceedings{Seo:2019:HTM,
  author =       "Jihee Seo and Dae Hyun Kim",
  title =        "High-Throughput Multiplier Architectures Enabled by
                 Intra-Unit Fast Forwarding",
  crossref =     "Takagi:2019:ISC",
  pages =        "143--150",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00036",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we propose a pipelined multiplier
                 architecture that can resolve data dependencies. The
                 proposed architecture generates partial results in the
                 pipeline stages of the multiplier and forwards the
                 partial results back to the pipeline stages through
                 so-called fast-forwarding paths, thereby enabling an
                 execution of dependent multiplications with a minimum
                 delay penalty. We apply the architecture to a normal
                 binary multiplier (NBBE-2) and two redundant binary
                 multipliers (RBBE-4 and CRBBE-4) and compare the
                 execution time, clock period, area, and power
                 consumption of the multipliers. The simulation results
                 show that the proposed architecture achieves up to 30\%
                 execution time reduction.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Clocks; Computer architecture; data
                 dependencies; Delays; dependent multiplications;
                 digital arithmetic; execution time reduction; Fast
                 Forwarding; fast-forwarding paths; high-throughput
                 multiplier architectures; intra-unit fast forwarding;
                 minimum delay penalty; Multiplexing; Multiplication;
                 Multiplier; multiplying circuits; normal binary
                 multiplier; pipeline processing; Pipeline processing;
                 pipeline stages; pipelined multiplier architecture;
                 Pipelines; redundant binary multipliers; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Serre:2019:DBM
author: Francois Serre and Markus Puschel
title: DSL-Based Modular IP Core Generators: Example FFT and Related Structures
crossref: Takagi:2019:ISC
pages: 190--191
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00043
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Fran{\c{c}}ois Serre and Markus P{\"u}schel
rawtitle: {DSL}-Based Modular {IP} Core Generators: Example {FFT} and Related Structures
abstract:
We present a hardware generator for signal processing algorithms that consist of a network of small processing elements, including the fast Fourier transform and sorting networks. The generator is implemented in Scala and uses a principled design that leverages modern language features to generate an entire design space of hardware implementations. Examples include the use of embedded domain-specific languages and staging to represent and optimize the designs at different levels of abstraction, and the use of Scala's type system to efficiently encode different degrees of hardware reuse and arithmetic formats.

keywords:
ARITH-26; arithmetic formats; Design automation; design space; digital arithmetic; Domain specific language; DSL; DSL-based modular IP core generators; electronic engineering computing; embedded domain-specific languages; embedded systems; fast Fourier transform; fast Fourier transforms; FFT; Generators; Hardware; hardware generator; Hardware generator; hardware implementations; hardware reuse; microprocessor chips; object-oriented programming; Optimization; processing elements; Random access memory; Scala type system; signal processing; signal processing algorithms; Sorting; sorting; sorting networks; specification languages; Staging; Streaming hardware

rawabstract:
We present a hardware generator for signal processing algorithms that consist of a network of small processing elements, including the fast Fourier transform and sorting networks. The generator is implemented in Scala and uses a principled design that leverages modern language features to generate an entire design space of hardware implementations. Examples include the use of embedded domain-specific languages and staging to represent and optimize the designs at different levels of abstraction, and the use of Scala's type system to efficiently encode different degrees of hardware reuse and arithmetic formats.

entry:
@InProceedings{Serre:2019:DBM,
  author =       "Fran{\c{c}}ois Serre and Markus P{\"u}schel",
  title =        "{DSL}-Based Modular {IP} Core Generators: Example
                 {FFT} and Related Structures",
  crossref =     "Takagi:2019:ISC",
  pages =        "190--191",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00043",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a hardware generator for signal processing
                 algorithms that consist of a network of small
                 processing elements, including the fast Fourier
                 transform and sorting networks. The generator is
                 implemented in Scala and uses a principled design that
                 leverages modern language features to generate an
                 entire design space of hardware implementations.
                 Examples include the use of embedded domain-specific
                 languages and staging to represent and optimize the
                 designs at different levels of abstraction, and the use
                 of Scala's type system to efficiently encode different
                 degrees of hardware reuse and arithmetic formats.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic formats; Design automation;
                 design space; digital arithmetic; Domain specific
                 language; DSL; DSL-based modular IP core generators;
                 electronic engineering computing; embedded
                 domain-specific languages; embedded systems; fast
                 Fourier transform; fast Fourier transforms; FFT;
                 Generators; Hardware; hardware generator; Hardware
                 generator; hardware implementations; hardware reuse;
                 microprocessor chips; object-oriented programming;
                 Optimization; processing elements; Random access
                 memory; Scala type system; signal processing; signal
                 processing algorithms; Sorting; sorting; sorting
                 networks; specification languages; Staging; Streaming
                 hardware",
}


bibtype: article
filename: fparith.bib
label: Sherman:2019:SRS
author: Benjamin Sherman and Jesse Michel and Michael Carbin
title: Sound and robust solid modeling via exact real arithmetic and continuity
journal: j-PACMPL
volume: 3
number: ICFP
pages: 99:1--99:29
month: jul
monthnumber: 7
year: 2019
DOI: https://doi.org/10.1145/3341703
ISSN: 2475-1421 OR 24751421
bibdate: Fri Aug 7 19:22:28 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2020.08.07 19:22:28 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3341703
fjournal: Proceedings of the ACM on Programming Languages
acknowledgement: ack-nhfb
articleno: 99
journalURL: https://pacmpl.acm.org/
rawauthor: Benjamin Sherman and Jesse Michel and Michael Carbin
rawtitle: Sound and robust solid modeling via exact real arithmetic and continuity
abstract:
Algorithms for solid modeling, i.e., Computer-Aided Design (CAD) and computer graphics, are often specified on real numbers and then implemented with finite-precision arithmetic, such as floating-point. The result is that these implementations do not soundly compute the results that are expected from their specifications.par We present a new library, StoneWorks, that provides sound and robust solid modeling primitives. We implement StoneWorks in MarshallB, a pure functional programming language for exact real arithmetic in which types denote topological spaces and functions denote continuous maps, ensuring that all programs are sound and robust. We developed MarshallB as an extension of the Marshall language.par We also define a new shape representation, compact representation (K-rep), that enables constructions such as Minkowski sum and analyses such as Hausdorff distance that are not possible with traditional representations. K-rep is a nondeterminism monad for describing all the points in a shape.par With our library, language, and representation together, we show that short StoneWorks programs can specify and execute sound and robust solid modeling algorithms and tasks.

rawabstract:
Algorithms for solid modeling, i.e., Computer-Aided Design (CAD) and computer graphics, are often specified on real numbers and then implemented with finite-precision arithmetic, such as floating-point. The result is that these implementations do not soundly compute the results that are expected from their specifications.\par We present a new library, StoneWorks, that provides sound and robust solid modeling primitives. We implement StoneWorks in MarshallB, a pure functional programming language for exact real arithmetic in which types denote topological spaces and functions denote continuous maps, ensuring that all programs are sound and robust. We developed MarshallB as an extension of the Marshall language.\par We also define a new shape representation, compact representation (K-rep), that enables constructions such as Minkowski sum and analyses such as Hausdorff distance that are not possible with traditional representations. K-rep is a nondeterminism monad for describing all the points in a shape.\par With our library, language, and representation together, we show that short StoneWorks programs can specify and execute sound and robust solid modeling algorithms and tasks.

entry:
@Article{Sherman:2019:SRS,
  author =       "Benjamin Sherman and Jesse Michel and Michael Carbin",
  title =        "Sound and robust solid modeling via exact real
                 arithmetic and continuity",
  journal =      j-PACMPL,
  volume =       "3",
  number =       "ICFP",
  pages =        "99:1--99:29",
  month =        jul,
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3341703",
  ISSN =         "2475-1421",
  bibdate =      "Fri Aug 7 19:22:28 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3341703",
  abstract =     "Algorithms for solid modeling, i.e., Computer-Aided
                 Design (CAD) and computer graphics, are often specified
                 on real numbers and then implemented with
                 finite-precision arithmetic, such as floating-point.
                 The result is that these implementations do not soundly
                 compute the results that are expected from their
                 specifications.\par

                 We present a new library, StoneWorks, that provides
                 sound and robust solid modeling primitives. We
                 implement StoneWorks in MarshallB, a pure functional
                 programming language for exact real arithmetic in which
                 types denote topological spaces and functions denote
                 continuous maps, ensuring that all programs are sound
                 and robust. We developed MarshallB as an extension of
                 the Marshall language.\par

                 We also define a new shape representation, compact
                 representation (K-rep), that enables constructions such
                 as Minkowski sum and analyses such as Hausdorff
                 distance that are not possible with traditional
                 representations. K-rep is a nondeterminism monad for
                 describing all the points in a shape.\par

                 With our library, language, and representation
                 together, we show that short StoneWorks programs can
                 specify and execute sound and robust solid modeling
                 algorithms and tasks.",
  acknowledgement = ack-nhfb,
  articleno =    "99",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
}


bibtype: misc
filename: fparith.bib
label: Silver:2019:CCN
author: Mike Silver and Kalimah Redd Knight
title: Cutting Corners on Numbers
pages: 99:1--99:29
day: 24
month: sep
monthnumber: 9
year: 2019
bibdate: Wed Sep 25 10:47:09 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.25 10:47:09 ???
note: See cite Boghosian:2019:NPS.
URL: https://now.tufts.edu/articles/cutting-corners-numbers-computation
acknowledgement: ack-nhfb
howpublished: TuftsNow Web site.
rawauthor: Mike Silver and Kalimah Redd Knight
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Cutting Corners on Numbers
abstract:
Tufts mathematicians find the way we represent numbers in computers can lead to large computational errors, especially for modeling dynamical systems.

rawabstract:
Tufts mathematicians find the way we represent numbers in computers can lead to large computational errors, especially for modeling dynamical systems.

entry:
@Misc{Silver:2019:CCN,
  author =       "Mike Silver and Kalimah Redd Knight",
  title =        "Cutting Corners on Numbers",
  howpublished = "TuftsNow Web site.",
  day =          "24",
  month =        sep,
  year =         "2019",
  bibdate =      "Wed Sep 25 10:47:09 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://now.tufts.edu/articles/cutting-corners-numbers-computation",
  abstract =     "Tufts mathematicians find the way we represent numbers
                 in computers can lead to large computational errors,
                 especially for modeling dynamical systems.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Singh:2019:LPP
booktitle: Embedded Computer Systems: Architectures, Modeling, and Simulation
title: Low Precision Processing for High Order Stencil Computations
publisher: pub-SV
address: pub-SV:adr
pages: 403--415
year: 2019
DOI: https://doi.org/10.1007/978-3-030-27562-4_29
ISBN: 3-030-27562-0 OR 3030275620
ISBN13: 978-3-030-27562-4 OR 9783030275624
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawbooktitle: Embedded Computer Systems: Architectures, Modeling, and Simulation
rawtitle: Low Precision Processing for High Order Stencil Computations
author:
Gagandeep Singh and Dionysios Diamantopoulos and Sander Stuijk and Christoph Hagleitner and Henk Corporaal

rawauthor:
Gagandeep Singh and Dionysios Diamantopoulos and Sander Stuijk and Christoph Hagleitner and Henk Corporaal

entry:
@InProceedings{Singh:2019:LPP,
  author =       "Gagandeep Singh and Dionysios Diamantopoulos and
                 Sander Stuijk and Christoph Hagleitner and Henk
                 Corporaal",
  booktitle =    "Embedded Computer Systems: Architectures, Modeling,
                 and Simulation",
  title =        "Low Precision Processing for High Order Stencil
                 Computations",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "403--415",
  year =         "2019",
  DOI =          "https://doi.org/10.1007/978-3-030-27562-4_29",
  ISBN =         "3-030-27562-0",
  ISBN-13 =      "978-3-030-27562-4",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Solovyev:2019:REF
title: Rigorous Estimation of Floating-Point Round-Off Errors with Symbolic Taylor Expansions
journal: j-TOPLAS
volume: 41
number: 1
pages: 2:1--2:??
month: mar
monthnumber: 3
year: 2019
CODEN: ATPSDT
DOI: https://doi.org/10.1145/3230733
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Mon Mar 4 08:35:09 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toplas.bib
bibtimestamp: 2019.03.04 08:35:09 MST
URL: https://dl.acm.org/ft_gateway.cfm?id=3230733
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
articleno: 2
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawtitle: Rigorous Estimation of Floating-Point Round-Off Errors with Symbolic {Taylor} Expansions
author:
Alexey Solovyev and Marek S. Baranowski and Ian Briggs and Charles Jacobsen and Zvonimir Rakamaric and Ganesh Gopalakrishnan

abstract:
Rigorous estimation of maximum floating-point round-off errors is an important capability central to many formal verification tools. Unfortunately, available techniques for this task often provide very pessimistic overestimates, causing unnecessary verification failure. We have developed a new approach called Symbolic Taylor Expansions that avoids these problems, and implemented a new tool called FPTaylor embodying this approach. Key to our approach is the use of rigorous global optimization, instead of the more familiar interval arithmetic, affine arithmetic, and/or SMT solvers. FPTaylor emits per-instance analysis certificates in the form of HOL Light proofs that can be machine checked. In this article, we present the basic ideas behind Symbolic Taylor Expansions in detail. We also survey as well as thoroughly evaluate six tool families, namely, Gappa (two tool options studied), Fluctuat, PRECiSA, Real2Float, Rosa, and FPTaylor (two tool options studied) on 24 examples, running on the same machine, and taking care to find the best options for running each of these tools. This study demonstrates that FPTaylor estimates round-off errors within much tighter bounds compared to other tools on a significant number of case studies. We also release FPTaylor along with our benchmarks, thus contributing to future studies and tool development in this area.

rawabstract:
Rigorous estimation of maximum floating-point round-off errors is an important capability central to many formal verification tools. Unfortunately, available techniques for this task often provide very pessimistic overestimates, causing unnecessary verification failure. We have developed a new approach called Symbolic Taylor Expansions that avoids these problems, and implemented a new tool called FPTaylor embodying this approach. Key to our approach is the use of rigorous global optimization, instead of the more familiar interval arithmetic, affine arithmetic, and/or SMT solvers. FPTaylor emits per-instance analysis certificates in the form of HOL Light proofs that can be machine checked. In this article, we present the basic ideas behind Symbolic Taylor Expansions in detail. We also survey as well as thoroughly evaluate six tool families, namely, Gappa (two tool options studied), Fluctuat, PRECiSA, Real2Float, Rosa, and FPTaylor (two tool options studied) on 24 examples, running on the same machine, and taking care to find the best options for running each of these tools. This study demonstrates that FPTaylor estimates round-off errors within much tighter bounds compared to other tools on a significant number of case studies. We also release FPTaylor along with our benchmarks, thus contributing to future studies and tool development in this area.

rawauthor:
Alexey Solovyev and Marek S. Baranowski and Ian Briggs and Charles Jacobsen and Zvonimir Rakamari{\'c} and Ganesh Gopalakrishnan

entry:
@Article{Solovyev:2019:REF,
  author =       "Alexey Solovyev and Marek S. Baranowski and Ian Briggs
                 and Charles Jacobsen and Zvonimir Rakamari{\'c} and
                 Ganesh Gopalakrishnan",
  title =        "Rigorous Estimation of Floating-Point Round-Off Errors
                 with Symbolic {Taylor} Expansions",
  journal =      j-TOPLAS,
  volume =       "41",
  number =       "1",
  pages =        "2:1--2:??",
  month =        mar,
  year =         "2019",
  CODEN =        "ATPSDT",
  DOI =          "https://doi.org/10.1145/3230733",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Mon Mar 4 08:35:09 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toplas.bib",
  URL =          "https://dl.acm.org/ft_gateway.cfm?id=3230733",
  abstract =     "Rigorous estimation of maximum floating-point
                 round-off errors is an important capability central to
                 many formal verification tools. Unfortunately,
                 available techniques for this task often provide very
                 pessimistic overestimates, causing unnecessary
                 verification failure. We have developed a new approach
                 called Symbolic Taylor Expansions that avoids these
                 problems, and implemented a new tool called FPTaylor
                 embodying this approach. Key to our approach is the use
                 of rigorous global optimization, instead of the more
                 familiar interval arithmetic, affine arithmetic, and/or
                 SMT solvers. FPTaylor emits per-instance analysis
                 certificates in the form of HOL Light proofs that can
                 be machine checked. In this article, we present the
                 basic ideas behind Symbolic Taylor Expansions in
                 detail. We also survey as well as thoroughly evaluate
                 six tool families, namely, Gappa (two tool options
                 studied), Fluctuat, PRECiSA, Real2Float, Rosa, and
                 FPTaylor (two tool options studied) on 24 examples,
                 running on the same machine, and taking care to find
                 the best options for running each of these tools. This
                 study demonstrates that FPTaylor estimates round-off
                 errors within much tighter bounds compared to other
                 tools on a significant number of case studies. We also
                 release FPTaylor along with our benchmarks, thus
                 contributing to future studies and tool development in
                 this area.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
}


bibtype: misc
filename: fparith.bib
label: Stephens:2019:BPN
author: Nigel Stephens
title: BFloat16 processing for Neural Networks on Armv8-A
pages: 2:1--2:??
day: 29
month: aug
monthnumber: 8
year: 2019
bibdate: Mon Sep 23 07:25:21 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.23 07:25:21 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Nigel Stephens
rawtitle: {BFloat16} processing for Neural Networks on {Armv8-A}
URL:
https://community.arm.com/developer/ip-products/processors/b/ml-ip-blog/posts/bfloat16-processing-for-neural-networks-on-armv8_2d00_a

remark:
From the article: ``The next revision of the Armv8-A architecture will introduce Neon and SVE vector instructions designed to accelerate certain computations using the BFloat16 (BF16) floating-point number format. BF16 has recently emerged as a format tailored specifically to high-performance processing of Neural Networks (NNs). BF16 is a truncated form of the IEEE 754 [ieee754-2008] single-precision representation (IEEE-FP32), which has only 7 fraction bits, instead of 23.'' IEEE FP16 has 1-bit sign, 5-bit exponent, and 10-bit significand. BF16 has 1-bit sign, 8-bit exponent, and 7-bit significand. [This disagrees with cite Verheyde:2019:BDD, which says 5-bit exponent, and 10-bit significand.] The article also says that two instructions, BFDOT and BFMMLA have only one rounding mode: Round to Odd, one type of NaN, and flush-to-zero on underflow.

entry:
@Misc{Stephens:2019:BPN,
  author =       "Nigel Stephens",
  title =        "{BFloat16} processing for Neural Networks on
                 {Armv8-A}",
  howpublished = "Web site.",
  day =          "29",
  month =        aug,
  year =         "2019",
  bibdate =      "Mon Sep 23 07:25:21 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://community.arm.com/developer/ip-products/processors/b/ml-ip-blog/posts/bfloat16-processing-for-neural-networks-on-armv8_2d00_a",
  acknowledgement = ack-nhfb,
  remark =       "From the article: ``The next revision of the Armv8-A
                 architecture will introduce Neon and SVE vector
                 instructions designed to accelerate certain
                 computations using the BFloat16 (BF16) floating-point
                 number format. BF16 has recently emerged as a format
                 tailored specifically to high-performance processing of
                 Neural Networks (NNs). BF16 is a truncated form of the
                 IEEE 754 [ieee754-2008] single-precision representation
                 (IEEE-FP32), which has only 7 fraction bits, instead of
                 23.'' IEEE FP16 has 1-bit sign, 5-bit exponent, and
                 10-bit significand. BF16 has 1-bit sign, 8-bit
                 exponent, and 7-bit significand. [This disagrees with
                 \cite{Verheyde:2019:BDD}, which says 5-bit exponent,
                 and 10-bit significand.] The article also says that two
                 instructions, BFDOT and BFMMLA have only one rounding
                 mode: Round to Odd, one type of NaN, and flush-to-zero
                 on underflow.",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:AI
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Author Index
crossref: Takagi:2019:ISC
pages: 219--220
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00051
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents an index of the authors whose articles are published in the conference proceedings record.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents an index of the authors whose articles are published in the conference proceedings record.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Author Index
entry:
@InProceedings{Takagi:2019:AI,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Author Index",
  crossref =     "Takagi:2019:ISC",
  pages =        "219--220",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00051",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents an index of the authors whose articles are
                 published in the conference proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:CN
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: [Copyright notice]
crossref: Takagi:2019:ISC
pages: 4--4
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00003
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents the copyright information for the conference. May include reprint permission information.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents the copyright information for the conference. May include reprint permission information.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: [{Copyright} notice]
entry:
@InProceedings{Takagi:2019:CN,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "[{Copyright} notice]",
  crossref =     "Takagi:2019:ISC",
  pages =        "4--4",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00003",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the copyright information for the conference.
                 May include reprint permission information.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:CO
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Conference Organization
crossref: Takagi:2019:ISC
pages: 11--11
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00006
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Conference Organization
entry:
@InProceedings{Takagi:2019:CO,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Conference Organization",
  crossref =     "Takagi:2019:ISC",
  pages =        "11--11",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00006",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:F
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Foreword
crossref: Takagi:2019:ISC
pages: 10--10
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00005
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Foreword
abstract:
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.

entry:
@InProceedings{Takagi:2019:F,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Foreword",
  crossref =     "Takagi:2019:ISC",
  pages =        "10--10",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00005",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the introductory welcome message from the
                 conference proceedings. May include the conference
                 officers' congratulations to all involved with the
                 conference event and publication of the proceedings
                 record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:PC
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Program Committee
crossref: Takagi:2019:ISC
pages: 12--12
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00007
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Program Committee
entry:
@InProceedings{Takagi:2019:PC,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Program Committee",
  crossref =     "Takagi:2019:ISC",
  pages =        "12--12",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00007",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:Sa
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Sponsors
crossref: Takagi:2019:ISC
pages: 14--14
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00009
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Sponsors
entry:
@InProceedings{Takagi:2019:Sa,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Sponsors",
  crossref =     "Takagi:2019:ISC",
  pages =        "14--14",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00009",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference organizers greatly appreciate the
                 support of the various corporate sponsors listed.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:Sb
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Supporters
crossref: Takagi:2019:ISC
pages: 15--15
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00010
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Supporters
entry:
@InProceedings{Takagi:2019:Sb,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Supporters",
  crossref =     "Takagi:2019:ISC",
  pages =        "15--15",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00010",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference organizers greatly appreciate the
                 support of the various corporate sponsors listed.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:SC
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Steering Committee
crossref: Takagi:2019:ISC
pages: 13--13
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00008
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Steering Committee
entry:
@InProceedings{Takagi:2019:SC,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Steering Committee",
  crossref =     "Takagi:2019:ISC",
  pages =        "13--13",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00008",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:TC
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Table of contents
crossref: Takagi:2019:ISC
pages: 5--9
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00004
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents the table of contents/splash page of the proceedings record.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents the table of contents/splash page of the proceedings record.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Table of contents
entry:
@InProceedings{Takagi:2019:TC,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Table of contents",
  crossref =     "Takagi:2019:ISC",
  pages =        "5--9",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00004",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the table of contents/splash page of the
                 proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:TPI
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: [Title page iii]
crossref: Takagi:2019:ISC
pages: 3--3
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00002
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents the title page of the proceedings record.
keywords: ARITH 2019; ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents the title page of the proceedings record.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: [{Title} page iii]
entry:
@InProceedings{Takagi:2019:TPI,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "[{Title} page iii]",
  crossref =     "Takagi:2019:ISC",
  pages =        "3--3",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00002",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2019; ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Thibault:2019:OWL
author: Hilaire Thibault and Hacene Ouzia and Benoit Lopez
title: Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers
crossref: Takagi:2019:ISC
pages: 175--182
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00040
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Hilaire Thibault and Hacene Ouzia and Benoit Lopez
rawtitle: Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers
abstract:
This article presents a word-length optimization problem under accuracy constraints for the hardware implementation of linear signal processing systems with fixed-point arithmetic. For State-Space systems (describing a linear filter or a controller), a complete error analysis is exhibited, where the final output error bound depends on the word-lengths and the fixed-point formats chosen for each variable. The Most Significant Bit of each one can be determined in order to guarantee that no overflow occurs. Thus, it is possible to obtain a hardware implementation minimizing resource use. This leads to a convex nonlinear integer optimization problem where the resources to minimize and the accuracy constraints depend on the internal word-lengths. This problem can then be solved with appropriate heuristics. Finally, a global approach is proposed and illustrated by some examples.

keywords:
ARITH-26; convex nonlinear integer optimization problem; convex programming; error analysis; filters; fixed point arithmetic; fixed-point arithmetic; Hardware; hardware implementation; integer programming; linear filter; linear signal processing systems; nonlinear programming; optimal word-length allocation; Optimization; Quantization (signal); Roundoff errors; signal processing; Signal processing algorithms; state-space methods; state-space systems; word length optimization; word-length optimization problem; worst case MSB

rawabstract:
This article presents a word-length optimization problem under accuracy constraints for the hardware implementation of linear signal processing systems with fixed-point arithmetic. For State-Space systems (describing a linear filter or a controller), a complete error analysis is exhibited, where the final output error bound depends on the word-lengths and the fixed-point formats chosen for each variable. The Most Significant Bit of each one can be determined in order to guarantee that no overflow occurs. Thus, it is possible to obtain a hardware implementation minimizing resource use. This leads to a convex nonlinear integer optimization problem where the resources to minimize and the accuracy constraints depend on the internal word-lengths. This problem can then be solved with appropriate heuristics. Finally, a global approach is proposed and illustrated by some examples.

entry:
@InProceedings{Thibault:2019:OWL,
  author =       "Hilaire Thibault and Hacene Ouzia and Benoit Lopez",
  title =        "Optimal Word-Length Allocation for the Fixed-Point
                 Implementation of Linear Filters and Controllers",
  crossref =     "Takagi:2019:ISC",
  pages =        "175--182",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00040",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This article presents a word-length optimization
                 problem under accuracy constraints for the hardware
                 implementation of linear signal processing systems with
                 fixed-point arithmetic. For State-Space systems
                 (describing a linear filter or a controller), a
                 complete error analysis is exhibited, where the final
                 output error bound depends on the word-lengths and the
                 fixed-point formats chosen for each variable. The Most
                 Significant Bit of each one can be determined in order
                 to guarantee that no overflow occurs. Thus, it is
                 possible to obtain a hardware implementation minimizing
                 resource use. This leads to a convex nonlinear integer
                 optimization problem where the resources to minimize
                 and the accuracy constraints depend on the internal
                 word-lengths. This problem can then be solved with
                 appropriate heuristics. Finally, a global approach is
                 proposed and illustrated by some examples.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; convex nonlinear integer optimization
                 problem; convex programming; error analysis; filters;
                 fixed point arithmetic; fixed-point arithmetic;
                 Hardware; hardware implementation; integer programming;
                 linear filter; linear signal processing systems;
                 nonlinear programming; optimal word-length allocation;
                 Optimization; Quantization (signal); Roundoff errors;
                 signal processing; Signal processing algorithms;
                 state-space methods; state-space systems; word length
                 optimization; word-length optimization problem; worst
                 case MSB",
}


bibtype: inproceedings
filename: fparith.bib
label: Thomas:2019:CTG
author: David B. Thomas
title: Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools
crossref: Takagi:2019:ISC
pages: 192--193
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00044
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: David B. Thomas
rawtitle: Compile-Time Generation of Custom-Precision Floating-Point {IP} using {HLS} Tools
abstract:
High-Level Synthesis (HLS) tools usually treat floating-point operators as black-box IP cores, and then schedule them as primitives when synthesising code to circuits. This approach relies on a library of IP blocks for chosen floating-point formats, which are pre-characterised to determine latency and area properties needed at compilation time. Two weaknesses of this approach are that it limits the number of floating-point formats - typically to half, single, and double - and that it requires conservative per-cycle scheduling of operators. Modern HLS tools have sophisticated intra-cycle scheduling of integer primitives, as well as C++ front-ends that can execute substantial algorithms at compile-time. This has enabled the creation of platform-independent C++ floating-point libraries which generate custom-precision operators at compile-time, while providing similar or better results as vendor-supplied IP blocks. However, certain problems and questions related to compilation performance and verification remain, so it is not yet clear how widely applicable this technique is.

keywords:
ARITH-26; black-box IP cores; C++; C++ languages; chosen floating-point formats; compilation performance; compilation time; Compile time IP; compile-time generation; custom-precision floating-point IP; custom-precision operators; field programmable gate arrays; Field programmable gate arrays; Floating point; floating point arithmetic; floating-point libraries; floating-point operators; FPGA; High Level Synthesis; high level synthesis; High-Level Synthesis tools; HLS; intra-cycle scheduling; IP networks; Libraries; Meta programming; modern HLS tools; Pipelines; Schedules; Templates; Tools; vendor-supplied IP blocks

rawabstract:
High-Level Synthesis (HLS) tools usually treat floating-point operators as black-box IP cores, and then schedule them as primitives when synthesising code to circuits. This approach relies on a library of IP blocks for chosen floating-point formats, which are pre-characterised to determine latency and area properties needed at compilation time. Two weaknesses of this approach are that it limits the number of floating-point formats - typically to half, single, and double - and that it requires conservative per-cycle scheduling of operators. Modern HLS tools have sophisticated intra-cycle scheduling of integer primitives, as well as C++ front-ends that can execute substantial algorithms at compile-time. This has enabled the creation of platform-independent C++ floating-point libraries which generate custom-precision operators at compile-time, while providing similar or better results as vendor-supplied IP blocks. However, certain problems and questions related to compilation performance and verification remain, so it is not yet clear how widely applicable this technique is.

entry:
@InProceedings{Thomas:2019:CTG,
  author =       "David B. Thomas",
  title =        "Compile-Time Generation of Custom-Precision
                 Floating-Point {IP} using {HLS} Tools",
  crossref =     "Takagi:2019:ISC",
  pages =        "192--193",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00044",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "High-Level Synthesis (HLS) tools usually treat
                 floating-point operators as black-box IP cores, and
                 then schedule them as primitives when synthesising code
                 to circuits. This approach relies on a library of IP
                 blocks for chosen floating-point formats, which are
                 pre-characterised to determine latency and area
                 properties needed at compilation time. Two weaknesses
                 of this approach are that it limits the number of
                 floating-point formats - typically to half, single, and
                 double - and that it requires conservative per-cycle
                 scheduling of operators. Modern HLS tools have
                 sophisticated intra-cycle scheduling of integer
                 primitives, as well as C++ front-ends that can execute
                 substantial algorithms at compile-time. This has
                 enabled the creation of platform-independent C++
                 floating-point libraries which generate
                 custom-precision operators at compile-time, while
                 providing similar or better results as vendor-supplied
                 IP blocks. However, certain problems and questions
                 related to compilation performance and verification
                 remain, so it is not yet clear how widely applicable
                 this technique is.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; black-box IP cores; C++; C++ languages;
                 chosen floating-point formats; compilation performance;
                 compilation time; Compile time IP; compile-time
                 generation; custom-precision floating-point IP;
                 custom-precision operators; field programmable gate
                 arrays; Field programmable gate arrays; Floating point;
                 floating point arithmetic; floating-point libraries;
                 floating-point operators; FPGA; High Level Synthesis;
                 high level synthesis; High-Level Synthesis tools; HLS;
                 intra-cycle scheduling; IP networks; Libraries; Meta
                 programming; modern HLS tools; Pipelines; Schedules;
                 Templates; Tools; vendor-supplied IP blocks",
}


bibtype: article
filename: fparith.bib
label: Tiwari:2019:PPE
author: Sugandha Tiwari and Neel Gala and Chester Rebeiro and V. Kamakoti
title: PERI: A Posit Enabled RISC-V Core
journal: arXiv.org
pages: 1--14
month: nov
monthnumber: 11
year: 2019
bibdate: Thu Apr 09 15:06:39 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.04.09 15:06:39 ???
URL: https://arxiv.org/pdf/1908.01466.pdf
keywords: floating-point; IEEE-754; Posit; processor; RISC-V
acknowledgement: ack-nhfb
rawauthor: Sugandha Tiwari and Neel Gala and Chester Rebeiro and V. Kamakoti
rawtitle: {PERI}: A Posit Enabled {RISC-V} Core
abstract:
Owing to the failure of Dennard's scaling the last decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE 754-2008. Posit promises more accuracy, higher dynamic range and fewer unused states along with simpler hardware designs as compared to IEEE 754- 2008. RISC-V, on the other hand, provides a commercial-grade open-source ISA. It is not only elegant and simple but also highly extensible and customizable, thereby facilitating novel micro-architectural research and exploration. In this paper, we bring these two technologies together and propose the first Posit Enabled RISC-V core. The paper provides insights on how the current 'F' extension and the custom op-code space of RISCV can be leveraged/modified to support Posit arithmetic. We also present implementation details of a parameterized and feature-complete Posit FPU which is integrated with the RISC-V compliant SHAKTI C-class core either as an execution unit or as an accelerator. To fully leverage the potential of Posit, we further enhance our Posit FPU, with minimal overheads, to support two different exponent sizes (with posit-size being 32-bits). This allows applications to switch from high-accuracy computation mode to a mode with higher dynamic-range at run-time. In the absence of viable software tool-chain to enable porting of applications in the Posit domain, we present a workaround on how certain applications can be modified minimally to exploit the existing RISC-V tool-chain. We also provide examples of applications which can perform better with Posit as compared to IEEE 754-2008. The proposed Posit FPU consumes 3507 slice LUTs and 1294 slice registers on an Artix-7-100T Xilinx FPGA while capable of operating at 100 MHz.

rawabstract:
Owing to the failure of Dennard's scaling the last decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE 754-2008. Posit promises more accuracy, higher dynamic range and fewer unused states along with simpler hardware designs as compared to IEEE 754- 2008. RISC-V, on the other hand, provides a commercial-grade open-source ISA. It is not only elegant and simple but also highly extensible and customizable, thereby facilitating novel micro-architectural research and exploration. In this paper, we bring these two technologies together and propose the first Posit Enabled RISC-V core. The paper provides insights on how the current 'F' extension and the custom op-code space of RISCV can be leveraged/modified to support Posit arithmetic. We also present implementation details of a parameterized and feature-complete Posit FPU which is integrated with the RISC-V compliant SHAKTI C-class core either as an execution unit or as an accelerator. To fully leverage the potential of Posit, we further enhance our Posit FPU, with minimal overheads, to support two different exponent sizes (with posit-size being 32-bits). This allows applications to switch from high-accuracy computation mode to a mode with higher dynamic-range at run-time. In the absence of viable software tool-chain to enable porting of applications in the Posit domain, we present a workaround on how certain applications can be modified minimally to exploit the existing RISC-V tool-chain. We also provide examples of applications which can perform better with Posit as compared to IEEE 754-2008. The proposed Posit FPU consumes 3507 slice LUTs and 1294 slice registers on an Artix-7-100T Xilinx FPGA while capable of operating at 100 MHz.

entry:
@Article{Tiwari:2019:PPE,
  author =       "Sugandha Tiwari and Neel Gala and Chester Rebeiro and
                 V. Kamakoti",
  title =        "{PERI}: A Posit Enabled {RISC-V} Core",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--14",
  month =        nov,
  year =         "2019",
  bibdate =      "Thu Apr 09 15:06:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/pdf/1908.01466.pdf",
  abstract =     "Owing to the failure of Dennard's scaling the last
                 decade has seen a steep growth of prominent new
                 paradigms leveraging opportunities in computer
                 architecture. Two technologies of interest are Posit
                 and RISC-V. Posit was introduced in mid-2017 as a
                 viable alternative to IEEE 754-2008. Posit promises
                 more accuracy, higher dynamic range and fewer unused
                 states along with simpler hardware designs as compared
                 to IEEE 754- 2008. RISC-V, on the other hand, provides
                 a commercial-grade open-source ISA. It is not only
                 elegant and simple but also highly extensible and
                 customizable, thereby facilitating novel
                 micro-architectural research and exploration. In this
                 paper, we bring these two technologies together and
                 propose the first Posit Enabled RISC-V core. The paper
                 provides insights on how the current 'F' extension and
                 the custom op-code space of RISCV can be
                 leveraged/modified to support Posit arithmetic. We also
                 present implementation details of a parameterized and
                 feature-complete Posit FPU which is integrated with the
                 RISC-V compliant SHAKTI C-class core either as an
                 execution unit or as an accelerator. To fully leverage
                 the potential of Posit, we further enhance our Posit
                 FPU, with minimal overheads, to support two different
                 exponent sizes (with posit-size being 32-bits). This
                 allows applications to switch from high-accuracy
                 computation mode to a mode with higher dynamic-range at
                 run-time. In the absence of viable software tool-chain
                 to enable porting of applications in the Posit domain,
                 we present a workaround on how certain applications can
                 be modified minimally to exploit the existing RISC-V
                 tool-chain. We also provide examples of applications
                 which can perform better with Posit as compared to IEEE
                 754-2008. The proposed Posit FPU consumes 3507 slice
                 LUTs and 1294 slice registers on an Artix-7-100T Xilinx
                 FPGA while capable of operating at 100 MHz.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point; IEEE-754; Posit; processor; RISC-V",
}


bibtype: inproceedings
filename: fparith.bib
label: Uguen:2019:EHC
author: Yohann Uguen and Luc Forget and Florent de Dinechin
editor: IEEE
booktitle: 2019 29th International Conference on Field Programmable Logic and Applications (FPL)
title: Evaluating the Hardware Cost of the Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 106--113
year: 2019
DOI: https://doi.org/10.1109/FPL.2019.00026
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Yohann Uguen and Luc Forget and Florent de Dinechin
rawbooktitle: {2019 29th International Conference on Field Programmable Logic and Applications (FPL)}
raweditor: {IEEE}
rawtitle: Evaluating the Hardware Cost of the Posit Number System
entry:
@InProceedings{Uguen:2019:EHC,
  author =       "Yohann Uguen and Luc Forget and Florent de Dinechin",
  editor =       "{IEEE}",
  booktitle =    "{2019 29th International Conference on Field
                 Programmable Logic and Applications (FPL)}",
  title =        "Evaluating the Hardware Cost of the Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "106--113",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/FPL.2019.00026",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: vanDam:2019:APA
author: Laurens van Dam and Johan Peltenburg and Zaid Al-Ars and H. Peter Hofstee
title: An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM
crossref: Gustafson:2019:CPC
pages: 5:1--5:10
year: 2019
DOI: https://doi.org/10.1145/3316279.3316284
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
keywords: pair-HMM, BLAS, decimal accuracy, arithmetic, unum-III, accelerator, posit, unum, FPGA
acknowledgement: ack-nhfb
articleno: 5
rawauthor: Laurens van Dam and Johan Peltenburg and Zaid Al-Ars and H. Peter Hofstee
rawtitle: An Accelerator for Posit Arithmetic Targeting Posit Level 1 {BLAS} Routines and {Pair-HMM}
entry:
@InProceedings{vanDam:2019:APA,
  author =       "Laurens van Dam and Johan Peltenburg and Zaid Al-Ars
                 and H. Peter Hofstee",
  title =        "An Accelerator for Posit Arithmetic Targeting Posit
                 Level 1 {BLAS} Routines and {Pair-HMM}",
  crossref =     "Gustafson:2019:CPC",
  pages =        "5:1--5:10",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316284",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  keywords =     "pair-HMM, BLAS, decimal accuracy, arithmetic,
                 unum-III, accelerator, posit, unum, FPGA",
  location =     "Singapore, Singapore",
  numpages =     "10",
}


bibtype: article
filename: fparith.bib
label: vanWyk:2019:RVT
author: Leonard van Wyk
title: Rounding versus truncation estimates in difference calculations
journal: j-MATH-GAZ
volume: 103
number: 557
pages: 285--292
month: jul
monthnumber: 7
year: 2019
CODEN: MAGAAS
DOI: https://doi.org/10.1017/mag.2019.60
ISSN: 0025-5572 (print), 2056-6328 (electronic) OR 00255572 (print), 20566328 (electronic)
ISSNL: 0025-5572 OR 00255572
bibdate: Mon Jul 22 08:44:42 MDT 2019
bibtimestamp: 2019.07.22 08:44:42 MDT
fjournal: The Mathematical Gazette
acknowledgement: ack-nhfb
ajournal: Math. Gaz.
onlinedate: 06 June 2019
rawauthor: Leonard van Wyk
rawtitle: Rounding versus truncation estimates in difference calculations
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathgaz2010.bib

URL:
https://www.cambridge.org/core/journals/mathematical-gazette/article/rounding-versus-truncation-estimates-in-difference-calculations/57BD92568C03F0FCDE63BBBDB5E6FF6D

abstract:
Two common methods of approximating difference problems are by rounding or truncating the minuend and the subtrahend before calculating the difference. Since rounding generally gives a better approximation of a number than truncation, one might expect that rounding also generally gives a better approximation in difference problems. We show that intuition to be false.

journalURL:
http://journals.cambridge.org/action/displayIssue?jid=MAG; http://www.m-a.org.uk/jsp/index.jsp?lnk=620

rawabstract:
Two common methods of approximating difference problems are by rounding or truncating the minuend and the subtrahend before calculating the difference. Since rounding generally gives a better approximation of a number than truncation, one might expect that rounding also generally gives a better approximation in difference problems. We show that intuition to be false.

entry:
@Article{vanWyk:2019:RVT,
  author =       "Leonard van Wyk",
  title =        "Rounding versus truncation estimates in difference
                 calculations",
  journal =      j-MATH-GAZ,
  volume =       "103",
  number =       "557",
  pages =        "285--292",
  month =        jul,
  year =         "2019",
  CODEN =        "MAGAAS",
  DOI =          "https://doi.org/10.1017/mag.2019.60",
  ISSN =         "0025-5572 (print), 2056-6328 (electronic)",
  ISSN-L =       "0025-5572",
  bibdate =      "Mon Jul 22 08:44:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathgaz2010.bib",
  URL =          "https://www.cambridge.org/core/journals/mathematical-gazette/article/rounding-versus-truncation-estimates-in-difference-calculations/57BD92568C03F0FCDE63BBBDB5E6FF6D",
  abstract =     "Two common methods of approximating difference
                 problems are by rounding or truncating the minuend and
                 the subtrahend before calculating the difference. Since
                 rounding generally gives a better approximation of a
                 number than truncation, one might expect that rounding
                 also generally gives a better approximation in
                 difference problems. We show that intuition to be
                 false.",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Gaz.",
  fjournal =     "The Mathematical Gazette",
  journal-URL =  "http://journals.cambridge.org/action/displayIssue?jid=MAG;
                 http://www.m-a.org.uk/jsp/index.jsp?lnk=620",
  onlinedate =   "06 June 2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2019:NPT
author: Alvaro Vazquez and Elisardo Antelo
title: New $3$D Projection Transformation for Point Clouds
crossref: Takagi:2019:ISC
pages: 77--83
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00020
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Alvaro V{\'a}zquez and Elisardo Antelo
rawtitle: New {$3$D} Projection Transformation for Point Clouds
abstract:
3D Computer Graphics based on clouds of points is an alternative of interest for high quality rendering of complex scenes. For high quality graphics, the computational requirements are significantly higher than in the case of conventional front-end vertex processing. One of the key computations in the graphics pipeline is the projection transformation. Conventional computation of the point-based projection using current vertex processors might not be the best option for scalable, high quality 3D graphics based on point clouds. In this work we propose a new scalable method that takes advantage of the special characteristics of the point rendering model. The number of reciprocal/division computations for perspective correction is reduced, using instead more effective multiply-accumulate operations. This is done by performing a linear approximation of the reciprocal at the cost of introducing an error in the pixel value. There is a trade-off in the error introduced and the exactness of the computation (linear approximation instead of reciprocal).

keywords:
3D computer graphics; 3D projection transformation; ARITH-26; Cameras; complex geometry; computational geometry; graphics processor; high quality 3D graphics; Linear approximation; Point based rendering; point clouds; point rendering model; point-based projection; projection transform; Rendering (computer graphics); rendering (computer graphics); rendering quality; Three-dimensional displays; Upper bound; vertex processing; VLSI graphis hardware; Zirconium

rawabstract:
3D Computer Graphics based on clouds of points is an alternative of interest for high quality rendering of complex scenes. For high quality graphics, the computational requirements are significantly higher than in the case of conventional front-end vertex processing. One of the key computations in the graphics pipeline is the projection transformation. Conventional computation of the point-based projection using current vertex processors might not be the best option for scalable, high quality 3D graphics based on point clouds. In this work we propose a new scalable method that takes advantage of the special characteristics of the point rendering model. The number of reciprocal/division computations for perspective correction is reduced, using instead more effective multiply-accumulate operations. This is done by performing a linear approximation of the reciprocal at the cost of introducing an error in the pixel value. There is a trade-off in the error introduced and the exactness of the computation (linear approximation instead of reciprocal).

entry:
@InProceedings{Vazquez:2019:NPT,
  author =       "Alvaro V{\'a}zquez and Elisardo Antelo",
  title =        "New {$3$D} Projection Transformation for Point
                 Clouds",
  crossref =     "Takagi:2019:ISC",
  pages =        "77--83",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00020",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "3D Computer Graphics based on clouds of points is an
                 alternative of interest for high quality rendering of
                 complex scenes. For high quality graphics, the
                 computational requirements are significantly higher
                 than in the case of conventional front-end vertex
                 processing. One of the key computations in the graphics
                 pipeline is the projection transformation. Conventional
                 computation of the point-based projection using current
                 vertex processors might not be the best option for
                 scalable, high quality 3D graphics based on point
                 clouds. In this work we propose a new scalable method
                 that takes advantage of the special characteristics of
                 the point rendering model. The number of
                 reciprocal/division computations for perspective
                 correction is reduced, using instead more effective
                 multiply-accumulate operations. This is done by
                 performing a linear approximation of the reciprocal at
                 the cost of introducing an error in the pixel value.
                 There is a trade-off in the error introduced and the
                 exactness of the computation (linear approximation
                 instead of reciprocal).",
  acknowledgement = ack-nhfb,
  keywords =     "3D computer graphics; 3D projection transformation;
                 ARITH-26; Cameras; complex geometry; computational
                 geometry; graphics processor; high quality 3D graphics;
                 Linear approximation; Point based rendering; point
                 clouds; point rendering model; point-based projection;
                 projection transform; Rendering (computer graphics);
                 rendering (computer graphics); rendering quality;
                 Three-dimensional displays; Upper bound; vertex
                 processing; VLSI graphis hardware; Zirconium",
}


bibtype: article
filename: fparith.bib
label: Venkatachalam:2019:DAA
author: S. Venkatachalam and E. Adams and H. J. Lee and S. Ko
title: Design and Analysis of Area and Power Efficient Approximate Booth Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1697--1703
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2926275
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Venkatachalam and E. Adams and H. J. Lee and S. Ko
rawtitle: Design and Analysis of Area and Power Efficient Approximate {Booth} Multipliers
keywords:
Adders; Approximate Booth arithmetic; Complexity theory; Computational modeling; Digital signal processing; Encoding; Generators; inexact computing; Integrated circuit modeling; radix-4 partial product generators

entry:
@Article{Venkatachalam:2019:DAA,
  author =       "S. Venkatachalam and E. Adams and H. J. Lee and S.
                 Ko",
  title =        "Design and Analysis of Area and Power Efficient
                 Approximate {Booth} Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1697--1703",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2926275",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; Approximate Booth arithmetic; Complexity
                 theory; Computational modeling; Digital signal
                 processing; Encoding; Generators; inexact computing;
                 Integrated circuit modeling; radix-4 partial product
                 generators",
}


bibtype: misc
filename: fparith.bib
label: Verheyde:2019:BDD
author: Arne Verheyde
title: BFloat16 Deep Dive: ARM Brings BF16 Deep Learning Data Format to ARMv8-A
pages: 1697--1703
day: 21
month: sep
monthnumber: 9
year: 2019
bibdate: Mon Sep 23 07:15:36 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.23 07:15:36 ???
URL: https://www.tomshardware.com/news/bfloat16-deep-dive-arm-bf16-support-armv8-a,40305.html
acknowledgement: ack-nhfb
howpublished: Tom's Hardware Web site.
rawauthor: Arne Verheyde
rawtitle: {BFloat16} Deep Dive: {ARM} Brings {BF16} Deep Learning Data Format to {ARMv8-A}
abstract:
RM will be adding BFloat16 support in the next revision of the ARMv8-A architecture under its Project Trillium ML platform. It marks a new major milestone in the widespread adoption of the young data format that is taking the deep learning community by storm. In this article, we'll dive into the origins and benefits of the format.

remark:
The BFloat16 format has 1-bit sign, 5-bit exponent, and 10-bit significand. From the article: ``ldots hardware area (number of transistors) scales roughly with the square of the mantissa width. So having just three fewer mantissa bits (7 instead of 10) means that a bfloat16 multiplier takes up about half the area of a conventional FP16 unit. Compared to an FP32 multiplier, its size is eight times smaller, with an equivalent reduction in power consumption as well. Or conversely, within the same silicon area more useful hardware can be put to achieve higher performance. ldots Bfloat16 is called Brain Floating Point Format in full (or BF16 in short), as it is named after the Google Brain research group where it was conceived. As Jeff Dean, Senior Fellow of Google AI, explained in a series of Twitter posts, Google started using the format since the early days of TensorFlow. More specifically, it was supported in hardware since the second version of its Tensor Processing Units (TPUs), the TPU v2 in 2017. ldots Intel showed that an integer multiplier costs less than half the area of a floating point multiplier of the same number of bits. Though less relevant, the difference is even larger for addition: while an integer adder scales linearly with the number of bits, a floating point adder scales quadratically, ldots ''

rawabstract:
RM will be adding BFloat16 support in the next revision of the ARMv8-A architecture under its Project Trillium ML platform. It marks a new major milestone in the widespread adoption of the young data format that is taking the deep learning community by storm. In this article, we'll dive into the origins and benefits of the format.

entry:
@Misc{Verheyde:2019:BDD,
  author =       "Arne Verheyde",
  title =        "{BFloat16} Deep Dive: {ARM} Brings {BF16} Deep
                 Learning Data Format to {ARMv8-A}",
  howpublished = "Tom's Hardware Web site.",
  day =          "21",
  month =        sep,
  year =         "2019",
  bibdate =      "Mon Sep 23 07:15:36 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.tomshardware.com/news/bfloat16-deep-dive-arm-bf16-support-armv8-a,40305.html",
  abstract =     "RM will be adding BFloat16 support in the next
                 revision of the ARMv8-A architecture under its Project
                 Trillium ML platform. It marks a new major milestone in
                 the widespread adoption of the young data format that
                 is taking the deep learning community by storm. In this
                 article, we'll dive into the origins and benefits of
                 the format.",
  acknowledgement = ack-nhfb,
  remark =       "The BFloat16 format has 1-bit sign, 5-bit exponent,
                 and 10-bit significand. From the article: ``\ldots{}
                 hardware area (number of transistors) scales roughly
                 with the square of the mantissa width. So having just
                 three fewer mantissa bits (7 instead of 10) means that
                 a bfloat16 multiplier takes up about half the area of a
                 conventional FP16 unit. Compared to an FP32 multiplier,
                 its size is eight times smaller, with an equivalent
                 reduction in power consumption as well. Or conversely,
                 within the same silicon area more useful hardware can
                 be put to achieve higher performance. \ldots{} Bfloat16
                 is called Brain Floating Point Format in full (or BF16
                 in short), as it is named after the Google Brain
                 research group where it was conceived. As Jeff Dean,
                 Senior Fellow of Google AI, explained in a series of
                 Twitter posts, Google started using the format since
                 the early days of TensorFlow. More specifically, it was
                 supported in hardware since the second version of its
                 Tensor Processing Units (TPUs), the TPU v2 in 2017.
                 \ldots{} Intel showed that an integer multiplier costs
                 less than half the area of a floating point multiplier
                 of the same number of bits. Though less relevant, the
                 difference is even larger for addition: while an
                 integer adder scales linearly with the number of bits,
                 a floating point adder scales quadratically,
                 \ldots{}''",
}


bibtype: inproceedings
filename: fparith.bib
label: Villa:2019:NDB
author: Oreste Villa and Mark Stephenson and David Nellans and Stephen W. Keckler
editor: IEEE / ACM
title: Nvbit: A dynamic binary instrumentation framework for NVIDIA GPUs
publisher: pub-ACM
address: pub-ACM:adr
pages: 372--383
year: 2019
ISBN: 1-4503-6938-3 OR 1450369383
ISBN13: 978-1-4503-6938-1 OR 9781450369381
LCCN: QA76.6 .A568
bibdate: Mon Sep 11 07:23:59 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:23:59 ???
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1145/3352460
bookpages: 1104
rawauthor: Oreste Villa and Mark Stephenson and David Nellans and Stephen W. Keckler
raweditor: {IEEE\slash ACM}
rawtitle: {Nvbit}: A dynamic binary instrumentation framework for {NVIDIA GPUs}
booktitle:
MICRO '52: Proceedings of the 52nd Annual IEEE / ACM International Symposium on Microarchitecture, Columbus OH, USA, October 12--16, 2019

rawbooktitle:
{MICRO '52: Proceedings of the 52nd Annual IEEE\slash ACM International Symposium on Microarchitecture, Columbus OH, USA, October 12--16, 2019}

entry:
@InProceedings{Villa:2019:NDB,
  author =       "Oreste Villa and Mark Stephenson and David Nellans and
                 Stephen W. Keckler",
  editor =       "{IEEE\slash ACM}",
  booktitle =    "{MICRO '52: Proceedings of the 52nd Annual IEEE\slash
                 ACM International Symposium on Microarchitecture,
                 Columbus OH, USA, October 12--16, 2019}",
  title =        "{Nvbit}: A dynamic binary instrumentation framework
                 for {NVIDIA GPUs}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  bookpages =    "1104",
  pages =        "372--383",
  year =         "2019",
  ISBN =         "1-4503-6938-3",
  ISBN-13 =      "978-1-4503-6938-1",
  LCCN =         "QA76.6 .A568",
  bibdate =      "Mon Sep 11 07:23:59 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1145/3352460",
}


bibtype: inproceedings
filename: fparith.bib
label: Villalba-Moreno:2019:RSU
author: Julio Villalba-Moreno and Javier Hormigo and Francisco Jaime
title: Reproducible Summation Under HUB Format
crossref: Takagi:2019:ISC
pages: 38--45
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00015
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Francisco Jaime
rawtitle: Reproducible Summation Under {HUB} Format
abstract:
Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any carry propagation and saving time and area. In this paper we study the reproducible summation of HUB numbers by using a error-free vector transformation technique, providing both a specific architecture and the usage of combined HUB/Standard floating point adders to achieve a reproducible result.

keywords:
adders; Adders; ARITH-26; carry propagation; Computer architecture; Computer science; Delays; Digital arithmetic; end users; error-free vector transformation technique; floating point arithmetic; Half-Unit-Biased; HUB (Half-Unit-Biased) floating-point format; HUB format; HUB numbers; point adders; point reproducibility; representation format; reproducible summation; Reproducible summation, HUB format; Standards; Terminology

rawabstract:
Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any carry propagation and saving time and area. In this paper we study the reproducible summation of HUB numbers by using a error-free vector transformation technique, providing both a specific architecture and the usage of combined HUB/Standard floating point adders to achieve a reproducible result.

entry:
@InProceedings{Villalba-Moreno:2019:RSU,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Francisco
                 Jaime",
  title =        "Reproducible Summation Under {HUB} Format",
  crossref =     "Takagi:2019:ISC",
  pages =        "38--45",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00015",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point reproducibility is a property claimed
                 by programmers and end users. Half-Unit-Biased (HUB) is
                 a new representation format in which the round to
                 nearest is carried out by truncation, preventing any
                 carry propagation and saving time and area. In this
                 paper we study the reproducible summation of HUB
                 numbers by using a error-free vector transformation
                 technique, providing both a specific architecture and
                 the usage of combined HUB/Standard floating point
                 adders to achieve a reproducible result.",
  acknowledgement = ack-nhfb,
  keywords =     "adders; Adders; ARITH-26; carry propagation; Computer
                 architecture; Computer science; Delays; Digital
                 arithmetic; end users; error-free vector transformation
                 technique; floating point arithmetic; Half-Unit-Biased;
                 HUB (Half-Unit-Biased) floating-point format; HUB
                 format; HUB numbers; point adders; point
                 reproducibility; representation format; reproducible
                 summation; Reproducible summation, HUB format;
                 Standards; Terminology",
}


bibtype: inproceedings
filename: fparith.bib
label: Volkova:2019:SAI
author: Anastasia Volkova and Jean-Michel Muller
title: Semi-Automatic Implementation of the Complementary Error Function
crossref: Takagi:2019:ISC
pages: 167--174
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00039
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Anastasia Volkova and Jean-Michel Muller
rawtitle: Semi-Automatic Implementation of the Complementary Error Function
abstract:
The normal and complementary error functions are ubiquitous special functions for any mathematical library. They have a wide range of applications. Practical applications call for customized implementations that have strict accuracy requirements. Accurate numerical implementation of these functions is, however, non-trivial. In particular, the complementary error function erfc for large positive arguments heavily suffers from cancellation, which is largely due to its asymptotic behavior. We provide a semi-automatic code generator for the erfc function which is parameterized by the user-given bound on the relative error. Our solution exploits the asymptotic expression of erfc and leverages the automatic code generator Metalibm that provides accurate polynomial approximations. A fine-grained a priori error analysis provides a libm developer with the required accuracy for each step of the evaluation. In critical parts, we exploit double-word arithmetic to achieve implementations that are fast, yet accurate up to 50 bits, even for large input arguments. We demonstrate that for high required accuracies the automatically generated code has performance comparable to that of the standard libm and for lower ones our code demonstrated roughly 25% speedup.

keywords:
a priori error analysis; ARITH-26; asymptotic behavior; asymptotic expression; complementary error functions; Digital arithmetic; Error analysis; error analysis; error function; floating-point arithmetic; Generators; Libraries; Lips; mathematical library; Metalibm; normal error functions; polynomial approximation; polynomial approximations; program compilers; semi-automated code generation; semiautomatic code generator; semiautomatic implementation; Standards; Tools; ubiquitous special functions

rawabstract:
The normal and complementary error functions are ubiquitous special functions for any mathematical library. They have a wide range of applications. Practical applications call for customized implementations that have strict accuracy requirements. Accurate numerical implementation of these functions is, however, non-trivial. In particular, the complementary error function erfc for large positive arguments heavily suffers from cancellation, which is largely due to its asymptotic behavior. We provide a semi-automatic code generator for the erfc function which is parameterized by the user-given bound on the relative error. Our solution exploits the asymptotic expression of erfc and leverages the automatic code generator Metalibm that provides accurate polynomial approximations. A fine-grained a priori error analysis provides a libm developer with the required accuracy for each step of the evaluation. In critical parts, we exploit double-word arithmetic to achieve implementations that are fast, yet accurate up to 50 bits, even for large input arguments. We demonstrate that for high required accuracies the automatically generated code has performance comparable to that of the standard libm and for lower ones our code demonstrated roughly 25\% speedup.

entry:
@InProceedings{Volkova:2019:SAI,
  author =       "Anastasia Volkova and Jean-Michel Muller",
  title =        "Semi-Automatic Implementation of the Complementary
                 Error Function",
  crossref =     "Takagi:2019:ISC",
  pages =        "167--174",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00039",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The normal and complementary error functions are
                 ubiquitous special functions for any mathematical
                 library. They have a wide range of applications.
                 Practical applications call for customized
                 implementations that have strict accuracy requirements.
                 Accurate numerical implementation of these functions
                 is, however, non-trivial. In particular, the
                 complementary error function erfc for large positive
                 arguments heavily suffers from cancellation, which is
                 largely due to its asymptotic behavior. We provide a
                 semi-automatic code generator for the erfc function
                 which is parameterized by the user-given bound on the
                 relative error. Our solution exploits the asymptotic
                 expression of erfc and leverages the automatic code
                 generator Metalibm that provides accurate polynomial
                 approximations. A fine-grained a priori error analysis
                 provides a libm developer with the required accuracy
                 for each step of the evaluation. In critical parts, we
                 exploit double-word arithmetic to achieve
                 implementations that are fast, yet accurate up to 50
                 bits, even for large input arguments. We demonstrate
                 that for high required accuracies the automatically
                 generated code has performance comparable to that of
                 the standard libm and for lower ones our code
                 demonstrated roughly 25\% speedup.",
  acknowledgement = ack-nhfb,
  keywords =     "a priori error analysis; ARITH-26; asymptotic
                 behavior; asymptotic expression; complementary error
                 functions; Digital arithmetic; Error analysis; error
                 analysis; error function; floating-point arithmetic;
                 Generators; Libraries; Lips; mathematical library;
                 Metalibm; normal error functions; polynomial
                 approximation; polynomial approximations; program
                 compilers; semi-automated code generation;
                 semiautomatic code generator; semiautomatic
                 implementation; Standards; Tools; ubiquitous special
                 functions",
}


bibtype: article
filename: fparith.bib
label: Walczyk:2019:MFI
author: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cieslinski
title: A Modification of the Fast Inverse Square Root Algorithm
journal: Computation
volume: 7
number: 3
pages: 41
month: aug
monthnumber: 8
year: 2019
DOI: https://doi.org/10.3390/computation7030041
ISSN: 2079-3197 OR 20793197
ISSNL: 2079-3197 OR 20793197
bibdate: Thu Apr 10 15:20:23 2025
bibtimestamp: 2025.04.10 15:20:23 ???
acknowledgement: ack-nhfb
rawauthor: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cie{\'s}li{\'n}ski
rawtitle: A Modification of the Fast Inverse Square Root Algorithm
entry:
@Article{Walczyk:2019:MFI,
  author =       "Cezary J. Walczyk and Leonid V. Moroz and Jan L.
                 Cie{\'s}li{\'n}ski",
  title =        "A Modification of the Fast Inverse Square Root
                 Algorithm",
  journal =      "Computation",
  volume =       "7",
  number =       "3",
  pages =        "41",
  month =        aug,
  year =         "2019",
  DOI =          "https://doi.org/10.3390/computation7030041",
  ISSN =         "2079-3197",
  ISSN-L =       "2079-3197",
  bibdate =      "Thu Apr 10 15:20:23 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Walther:2019:VNR
author: Christoph Walther
title: Verified Newton--Raphson Iteration for Multiplicative Inverses Modulo Powers of Any Base
journal: j-TOMS
volume: 45
number: 1
pages: 9:1--9:7
month: mar
monthnumber: 3
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3301317
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon May 6 18:23:42 MDT 2019
bibtimestamp: 2019.05.06 18:23:42 MDT
note: See cite Dumas:2014:NRI.
URL: https://dl.acm.org/citation.cfm?id=3301317
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 9
journalURL: https://dl.acm.org/loi/toms
rawauthor: Christoph Walther
rawnote: See \cite{Dumas:2014:NRI}.
rawtitle: Verified {Newton--Raphson} Iteration for Multiplicative Inverses Modulo Powers of Any Base
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We identify two faults in a published algorithm for fast computation of multiplicative inverses modulo prime powers. We patch the algorithm and present machine-assisted proofs of correctness of the repair. Our formal proofs also reveal that being prime is an unnecessary demand for the power base, thus attributing a wider scope of applications to the repaired algorithm.

rawabstract:
We identify two faults in a published algorithm for fast computation of multiplicative inverses modulo prime powers. We patch the algorithm and present machine-assisted proofs of correctness of the repair. Our formal proofs also reveal that being prime is an unnecessary demand for the power base, thus attributing a wider scope of applications to the repaired algorithm.

entry:
@Article{Walther:2019:VNR,
  author =       "Christoph Walther",
  title =        "Verified {Newton--Raphson} Iteration for
                 Multiplicative Inverses Modulo Powers of Any Base",
  journal =      j-TOMS,
  volume =       "45",
  number =       "1",
  pages =        "9:1--9:7",
  month =        mar,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3301317",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon May 6 18:23:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "See \cite{Dumas:2014:NRI}.",
  URL =          "https://dl.acm.org/citation.cfm?id=3301317",
  abstract =     "We identify two faults in a published algorithm for
                 fast computation of multiplicative inverses modulo
                 prime powers. We patch the algorithm and present
                 machine-assisted proofs of correctness of the repair.
                 Our formal proofs also reveal that being prime is an
                 unnecessary demand for the power base, thus attributing
                 a wider scope of applications to the repaired
                 algorithm.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: misc
filename: fparith.bib
label: Wang:2019:BSH
author: Shibo Wang and Pankaj Kanwar
title: BFloat16: The secret to high performance on Cloud TPUs
pages: 9:1--9:7
day: 23
month: aug
monthnumber: 8
year: 2019
bibdate: Fri Apr 03 09:12:39 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.04.03 09:12:39 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Shibo Wang and Pankaj Kanwar
rawtitle: {BFloat16}: The secret to high performance on Cloud {TPUs}
URL:
https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus

entry:
@Misc{Wang:2019:BSH,
  author =       "Shibo Wang and Pankaj Kanwar",
  title =        "{BFloat16}: The secret to high performance on Cloud
                 {TPUs}",
  howpublished = "Web site",
  day =          "23",
  month =        aug,
  year =         "2019",
  bibdate =      "Fri Apr 03 09:12:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Wang:2019:PAA
author: Shouxiang Wang and Kai Wang and Lei Wu and Chengshan Wang
journal: j-TOMS
volume: 45
number: 1
pages: 6:1--6:29
month: mar
monthnumber: 3
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3274659
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon May 6 18:23:42 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2019.05.06 18:23:42 MDT
URL: https://dl.acm.org/citation.cfm?id=3274659
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 6
journalURL: https://dl.acm.org/loi/toms
rawauthor: Shouxiang Wang and Kai Wang and Lei Wu and Chengshan Wang
title:
Polar Affine Arithmetic: Optimal Affine Approximation and Operation Development for Computation in Polar Form Under Uncertainty

abstract:
Uncertainties practically arise from numerous factors, such as ambiguous information, inaccurate model, and environment disturbance. Interval arithmetic has emerged to solve problems with uncertain parameters, especially in the computational process where only the upper and lower bounds of parameters can be ascertained. In rectangular coordinate systems, the basic interval operations and improved interval algorithms have been developed in the numerical analysis. However, in polar coordinate systems, interval arithmetic still suffers from issues of complex computation and overestimation. This article defines a polar affine variable and develops a polar affine arithmetic (PAA) that extends affine arithmetic to the polar coordinate systems, which performs better in many aspects than the corresponding polar interval arithmetic (PIA). Basic arithmetic operations are developed based on the complex affine arithmetic. The Chebyshev approximation theory and the min-range approximation theory are used to identify the best affine approximation. PAA can accurately keep track of the interdependency among multiple variables throughout the calculation procedure, which prominently reduces the solution conservativeness. Numerical examples implemented in MATLAB programs show that, compared with benchmark results from the Monte Carlo method, the proposed PAA ensures completeness of the exact solution and presents a more compact solution region than PIA when dependency exists in the calculation process. Meanwhile, a comparison of affine arithmetic in polar and rectangular coordinates is presented. An application of PAA in circuit analysis is quantitatively presented and potential applications in other research fields involving complex variables in polar form will be gradually developed.

rawabstract:
Uncertainties practically arise from numerous factors, such as ambiguous information, inaccurate model, and environment disturbance. Interval arithmetic has emerged to solve problems with uncertain parameters, especially in the computational process where only the upper and lower bounds of parameters can be ascertained. In rectangular coordinate systems, the basic interval operations and improved interval algorithms have been developed in the numerical analysis. However, in polar coordinate systems, interval arithmetic still suffers from issues of complex computation and overestimation. This article defines a polar affine variable and develops a polar affine arithmetic (PAA) that extends affine arithmetic to the polar coordinate systems, which performs better in many aspects than the corresponding polar interval arithmetic (PIA). Basic arithmetic operations are developed based on the complex affine arithmetic. The Chebyshev approximation theory and the min-range approximation theory are used to identify the best affine approximation. PAA can accurately keep track of the interdependency among multiple variables throughout the calculation procedure, which prominently reduces the solution conservativeness. Numerical examples implemented in MATLAB programs show that, compared with benchmark results from the Monte Carlo method, the proposed PAA ensures completeness of the exact solution and presents a more compact solution region than PIA when dependency exists in the calculation process. Meanwhile, a comparison of affine arithmetic in polar and rectangular coordinates is presented. An application of PAA in circuit analysis is quantitatively presented and potential applications in other research fields involving complex variables in polar form will be gradually developed.

rawtitle:
Polar Affine Arithmetic: Optimal Affine Approximation and Operation Development for Computation in Polar Form Under Uncertainty

entry:
@Article{Wang:2019:PAA,
  author =       "Shouxiang Wang and Kai Wang and Lei Wu and Chengshan
                 Wang",
  title =        "Polar Affine Arithmetic: Optimal Affine Approximation
                 and Operation Development for Computation in Polar Form
                 Under Uncertainty",
  journal =      j-TOMS,
  volume =       "45",
  number =       "1",
  pages =        "6:1--6:29",
  month =        mar,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3274659",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon May 6 18:23:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3274659",
  abstract =     "Uncertainties practically arise from numerous factors,
                 such as ambiguous information, inaccurate model, and
                 environment disturbance. Interval arithmetic has
                 emerged to solve problems with uncertain parameters,
                 especially in the computational process where only the
                 upper and lower bounds of parameters can be
                 ascertained. In rectangular coordinate systems, the
                 basic interval operations and improved interval
                 algorithms have been developed in the numerical
                 analysis. However, in polar coordinate systems,
                 interval arithmetic still suffers from issues of
                 complex computation and overestimation. This article
                 defines a polar affine variable and develops a polar
                 affine arithmetic (PAA) that extends affine arithmetic
                 to the polar coordinate systems, which performs better
                 in many aspects than the corresponding polar interval
                 arithmetic (PIA). Basic arithmetic operations are
                 developed based on the complex affine arithmetic. The
                 Chebyshev approximation theory and the min-range
                 approximation theory are used to identify the best
                 affine approximation. PAA can accurately keep track of
                 the interdependency among multiple variables throughout
                 the calculation procedure, which prominently reduces
                 the solution conservativeness. Numerical examples
                 implemented in MATLAB programs show that, compared with
                 benchmark results from the Monte Carlo method, the
                 proposed PAA ensures completeness of the exact solution
                 and presents a more compact solution region than PIA
                 when dependency exists in the calculation process.
                 Meanwhile, a comparison of affine arithmetic in polar
                 and rectangular coordinates is presented. An
                 application of PAA in circuit analysis is
                 quantitatively presented and potential applications in
                 other research fields involving complex variables in
                 polar form will be gradually developed.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Ye:2019:NCA
author: T. Ye and Y. Wei and W. Meier
title: A New Cube Attack on MORUS by Using Division Property
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 12
pages: 1731--1740
month: dec
monthnumber: 12
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2929137
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Nov 7 11:20:24 2019
bibtimestamp: 2019.11.07 11:20:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. Ye and Y. Wei and W. Meier
rawtitle: A New Cube Attack on {MORUS} by Using Division Property
keywords:
Authenticated encryption algorithm; Boolean functions; cube attack; division property; Encryption; mixed integer linear programming; MORUS; Software algorithms; Time complexity; time complexity

entry:
@Article{Ye:2019:NCA,
  author =       "T. Ye and Y. Wei and W. Meier",
  title =        "A New Cube Attack on {MORUS} by Using Division
                 Property",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "12",
  pages =        "1731--1740",
  month =        dec,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2929137",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Nov 7 11:20:24 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Authenticated encryption algorithm; Boolean functions;
                 cube attack; division property; Encryption; mixed
                 integer linear programming; MORUS; Software algorithms;
                 Time complexity; time complexity",
}


bibtype: article
filename: fparith.bib
label: Zhang:2019:EMP
author: H. Zhang and D. Chen and S. Ko
title: Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 1035--1048
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2895031
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Zhang and D. Chen and S. Ko
rawtitle: Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support
keywords:
Adders; Clocks; Computer architecture; Deep learning; double-precision operations; efficiency 10.6 percent; efficiency 6.5 percent; floating point arithmetic; floating-point arithmetics; floating-point operations; FMA architecture; Fused multiply-add; half-precision FMA operations; Hardware; logic design; mixed-precision arithmetics; mixed-precision dot-product operations; mixed-precision FMA operations; mixed-precision operations; mixed-precision support; multiple-precision arithmetics; multiple-precision floating-point; multiple-precision FMA design; multiple-precision FMA unit; multiplying circuits; normal FMA operations; parallel half-precision operations; Pipelines; quadruple-precision operation; single-precision operations; Standards

entry:
@Article{Zhang:2019:EMP,
  author =       "H. Zhang and D. Chen and S. Ko",
  title =        "Efficient Multiple-Precision Floating-Point Fused
                 Multiply-Add with Mixed-Precision Support",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "1035--1048",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2895031",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; Clocks; Computer architecture; Deep learning;
                 double-precision operations; efficiency 10.6 percent;
                 efficiency 6.5 percent; floating point arithmetic;
                 floating-point arithmetics; floating-point operations;
                 FMA architecture; Fused multiply-add; half-precision
                 FMA operations; Hardware; logic design; mixed-precision
                 arithmetics; mixed-precision dot-product operations;
                 mixed-precision FMA operations; mixed-precision
                 operations; mixed-precision support; multiple-precision
                 arithmetics; multiple-precision floating-point;
                 multiple-precision FMA design; multiple-precision FMA
                 unit; multiplying circuits; normal FMA operations;
                 parallel half-precision operations; Pipelines;
                 quadruple-precision operation; single-precision
                 operations; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhang:2019:EPM
author: Hao Zhang and Jiongrui He and Seok-Bum Ko
editor: IEEE
booktitle: 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
month: may
monthnumber: 5
year: 2019
DOI: https://doi.org/10.1109/iscas.2019.8702349
bibdate: Thu Dec 14 18:03:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 18:03:31 ???
acknowledgement: ack-nhfb
rawauthor: Hao Zhang and Jiongrui He and Seok-Bum Ko
rawbooktitle: {2019 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: IEEE
rawtitle: Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications
entry:
@InProceedings{Zhang:2019:EPM,
  author =       "Hao Zhang and Jiongrui He and Seok-Bum Ko",
  editor =       "IEEE",
  booktitle =    "{2019 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Efficient Posit Multiply-Accumulate Unit Generator for
                 Deep Learning Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  month =        may,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/iscas.2019.8702349",
  bibdate =      "Thu Dec 14 18:03:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Zhu:2019:DPS
author: Weibin Zhu and Shengjin Ye and Yao Huang and Zi Xue
title: Design of a precise subdivision system for gratings using a modified CORDIC algorithm
journal: IET Circuits, Devices & Systems
volume: 13
number: 8
pages: 1284--1291
year: 2019
DOI: https://doi.org/10.1049/iet-cds.2019.0150
bibdate: Wed Oct 29 15:08:31 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.29 15:08:31 ???
URL: https://onlinelibrary.wiley.com/doi/abs/10.1049/iet-cds.2019.0150
acknowledgement: ack-nhfb
rawauthor: Weibin Zhu and Shengjin Ye and Yao Huang and Zi Xue
rawtitle: Design of a precise subdivision system for gratings using a modified {CORDIC} algorithm
keywords:
amplitude deviation; angle-measurement accuracy; angle-measuring device; angular measurement; arccosine functions; circular grating; digital arithmetic; digital subdivision; direct current offset deviation; double-rotation iteration; dynamic response; error compensation; field programmable gate arrays; field-programmable gate array chip; function generator; function generators; grating lines; grating Moircge signal; ideal subdivision effect; light interferometers; measurement error; measurement errors; MicroE system; modified CORDIC algorithm; Moire signals; nonlinear subdivision; precise subdivision system design; robust linearisation method; rotation digital computer algorithm; sinusoidal signal; stable signals

entry:
@Article{Zhu:2019:DPS,
  author =       "Weibin Zhu and Shengjin Ye and Yao Huang and Zi Xue",
  title =        "Design of a precise subdivision system for gratings
                 using a modified {CORDIC} algorithm",
  journal =      "IET Circuits, Devices \& Systems",
  volume =       "13",
  number =       "8",
  pages =        "1284--1291",
  year =         "2019",
  DOI =          "https://doi.org/10.1049/iet-cds.2019.0150",
  bibdate =      "Wed Oct 29 15:08:31 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://onlinelibrary.wiley.com/doi/abs/10.1049/iet-cds.2019.0150",
  acknowledgement = ack-nhfb,
  eprint =       "https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0150",
  keywords =     "amplitude deviation; angle-measurement accuracy;
                 angle-measuring device; angular measurement; arccosine
                 functions; circular grating; digital arithmetic;
                 digital subdivision; direct current offset deviation;
                 double-rotation iteration; dynamic response; error
                 compensation; field programmable gate arrays;
                 field-programmable gate array chip; function generator;
                 function generators; grating lines; grating Moircg{\'e}
                 signal; ideal subdivision effect; light
                 interferometers; measurement error; measurement errors;
                 MicroE system; modified CORDIC algorithm; Moir{\'e}
                 signals; nonlinear subdivision; precise subdivision
                 system design; robust linearisation method; rotation
                 digital computer algorithm; sinusoidal signal; stable
                 signals",
}


bibtype: inproceedings
filename: fparith.bib
label: Zorn:2019:SPD
author: Bill Zorn and Dan Grossman and Zach Tatlock
title: Sinking Point: Dynamic Precision Tracking for Floating-Point
crossref: Gustafson:2019:CPC
pages: 4:1--4:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316283
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
keywords: Floating point, numerical analysis
acknowledgement: ack-nhfb
articleno: 4
rawauthor: Bill Zorn and Dan Grossman and Zach Tatlock
rawtitle: Sinking Point: Dynamic Precision Tracking for Floating-Point
entry:
@InProceedings{Zorn:2019:SPD,
  author =       "Bill Zorn and Dan Grossman and Zach Tatlock",
  title =        "Sinking Point: Dynamic Precision Tracking for
                 Floating-Point",
  crossref =     "Gustafson:2019:CPC",
  pages =        "4:1--4:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316283",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  keywords =     "Floating point, numerical analysis",
  location =     "Singapore, Singapore",
  numpages =     "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Abdelfattah:2020:IBF
author: Ahmad Abdelfattah and Stan Tomov and Jack Dongarra
crossref: Krzhizhanovskaya:2020:CSI
pages: 237--250
year: 2020
DOI: https://doi.org/10.1007/978-3-030-50417-5_18
bibdate: Thu Jun 25 08:49:09 2020
bibtimestamp: 2020.06.25 08:49:09 ???
acknowledgement: ack-nhfb
rawauthor: Ahmad Abdelfattah and Stan Tomov and Jack Dongarra
title:
Investigating the Benefit of FP16-Enabled Mixed-Precision Solvers for Symmetric Positive Definite Matrices Using GPUs

rawtitle:
Investigating the Benefit of {FP16}-Enabled Mixed-Precision Solvers for Symmetric Positive Definite Matrices Using {GPUs}

entry:
@InProceedings{Abdelfattah:2020:IBF,
  author =       "Ahmad Abdelfattah and Stan Tomov and Jack Dongarra",
  title =        "Investigating the Benefit of {FP16}-Enabled
                 Mixed-Precision Solvers for Symmetric Positive Definite
                 Matrices Using {GPUs}",
  crossref =     "Krzhizhanovskaya:2020:CSI",
  pages =        "237--250",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-50417-5_18",
  bibdate =      "Thu Jun 25 08:49:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Abdelfattah:2020:MMB
author: Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra
title: Matrix multiplication on batches of small matrices in half and half-complex precisions
journal: j-J-PAR-DIST-COMP
volume: 145
pages: 188--201
month: nov
monthnumber: 11
year: 2020
CODEN: JPDCER
DOI: https://doi.org/10.1016/j.jpdc.2020.07.001
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Wed May 26 16:11:03 MDT 2021
bibtimestamp: 2021.05.26 16:11:03 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0743731520303300
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra
rawtitle: Matrix multiplication on batches of small matrices in half and half-complex precisions
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib

entry:
@Article{Abdelfattah:2020:MMB,
  author =       "Ahmad Abdelfattah and Stanimire Tomov and Jack
                 Dongarra",
  title =        "Matrix multiplication on batches of small matrices in
                 half and half-complex precisions",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "145",
  number =       "??",
  pages =        "188--201",
  month =        nov,
  year =         "2020",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1016/j.jpdc.2020.07.001",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Wed May 26 16:11:03 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731520303300",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: article
filename: fparith.bib
label: Adams:2020:ARD
author: E. Adams and S. Venkatachalam and S. Ko
title: Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 4
pages: 468--474
month: apr
monthnumber: 4
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2953751
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Mar 12 16:58:27 2020
bibtimestamp: 2020.03.12 16:58:27 ???
fjournal: IEEE Transactions on Computers
keywords: Approximate computing; error analysis; image processing applications; low-power; restoring division
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Adams and S. Venkatachalam and S. Ko
rawtitle: Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

entry:
@Article{Adams:2020:ARD,
  author =       "E. Adams and S. Venkatachalam and S. Ko",
  title =        "Approximate Restoring Dividers Using Inexact Cells and
                 Estimation From Partial Remainders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "4",
  pages =        "468--474",
  month =        apr,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2953751",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Mar 12 16:58:27 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Approximate computing; error analysis; image
                 processing applications; low-power; restoring
                 division",
}


bibtype: inproceedings
filename: fparith.bib
label: Agrawal:2020:FAH
author: Rashmi Agrawal and Lake Bu and Michel A. Kinsy
title: Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 206--206
year: 2020
DOI: https://doi.org/10.1109/FCCM48280.2020.00037
bibdate: Fri Sep 22 08:05:37 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 08:05:37 ???
acknowledgement: ack-nhfb
rawauthor: Rashmi Agrawal and Lake Bu and Michel A. Kinsy
rawtitle: Fast Arithmetic Hardware Library For {RLWE-Based} Homomorphic Encryption
booktitle:
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

rawbooktitle:
{2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}

entry:
@InProceedings{Agrawal:2020:FAH,
  author =       "Rashmi Agrawal and Lake Bu and Michel A. Kinsy",
  booktitle =    "{2020 IEEE 28th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "Fast Arithmetic Hardware Library For {RLWE-Based}
                 Homomorphic Encryption",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "206--206",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FCCM48280.2020.00037",
  bibdate =      "Fri Sep 22 08:05:37 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ahrens:2020:AER
author: Peter Ahrens and James Demmel and Hong Diep Nguyen
title: Algorithms for Efficient Reproducible Floating Point Summation
journal: j-TOMS
volume: 46
number: 3
pages: 22:1--22:49
month: sep
monthnumber: 9
year: 2020
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3389360
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Sep 26 07:28:19 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2020.09.26 07:28:19 MDT
URL: https://dl.acm.org/doi/10.1145/3389360
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
articleno: 22
journalURL: https://dl.acm.org/loi/toms
rawauthor: Peter Ahrens and James Demmel and Hong Diep Nguyen
rawtitle: Algorithms for Efficient Reproducible Floating Point Summation
abstract:
We define ``reproducibility'' as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a ``reproducible accumulator'' data structure (the ``binned number'') and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing $n$ words with a 6-word reproducible accumulator requires approximately $ 9 n$ floating point operations (arithmetic, comparison, and absolute value) and approximately $ 3 n$ bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 229 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs

rawabstract:
We define ``reproducibility'' as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a ``reproducible accumulator'' data structure (the ``binned number'') and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing $n$ words with a 6-word reproducible accumulator requires approximately $ 9 n$ floating point operations (arithmetic, comparison, and absolute value) and approximately $ 3 n$ bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 229 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs

entry:
@Article{Ahrens:2020:AER,
  author =       "Peter Ahrens and James Demmel and Hong Diep Nguyen",
  title =        "Algorithms for Efficient Reproducible Floating Point
                 Summation",
  journal =      j-TOMS,
  volume =       "46",
  number =       "3",
  pages =        "22:1--22:49",
  month =        sep,
  year =         "2020",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3389360",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Sep 26 07:28:19 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3389360",
  abstract =     "We define ``reproducibility'' as getting bitwise
                 identical results from multiple runs of the same
                 program, perhaps with different hardware resources or
                 other changes that should not affect the answer. Many
                 users depend on reproducibility for debugging or
                 correctness. However, dynamic scheduling of parallel
                 computing resources, combined with nonassociative
                 floating point addition, makes reproducibility
                 challenging even for summation, or operations like the
                 BLAS. We describe a ``reproducible accumulator'' data
                 structure (the ``binned number'') and associated
                 algorithms to reproducibly sum binary floating point
                 numbers, independent of summation order. We use a
                 subset of the IEEE Floating Point Standard 754-2008 and
                 bitwise operations on the standard representations in
                 memory. Our approach requires only one read-only pass
                 over the data, and one reduction in parallel, using a
                 6-word reproducible accumulator (more words can be used
                 for higher accuracy), enabling standard tiling
                 optimization techniques. Summing $n$ words with a
                 6-word reproducible accumulator requires approximately
                 $ 9 n$ floating point operations (arithmetic,
                 comparison, and absolute value) and approximately $ 3
                 n$ bitwise operations. The final error bound with a
                 6-word reproducible accumulator and our default
                 settings can be up to 229 times smaller than the error
                 bound for conventional (recursive) summation on
                 ill-conditioned double-precision inputs",
  acknowledgement = ack-nhfb,
  articleno =    "22",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ACa
author: Anonymous
title: ARITH 2020 Committees
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00006
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Anonymous
rawtitle: {ARITH 2020} Committees
entry:
@InProceedings{Anonymous:2020:ACa,
  author =       "Anonymous",
  title =        "{ARITH 2020} Committees",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00006",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ACb
author: Anonymous
title: ARITH 2020 Committees
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00007
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Anonymous
rawtitle: {ARITH 2020} Committees
entry:
@InProceedings{Anonymous:2020:ACb,
  author =       "Anonymous",
  title =        "{ARITH 2020} Committees",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00007",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ACN
author: Anonymous
title: [ARITH 2020 Copyright notice]
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00003
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the copyright information for the conference. May include reprint permission information.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Presents the copyright information for the conference. May include reprint permission information.
rawauthor: Anonymous
rawtitle: [{ARITH 2020} Copyright notice]
entry:
@InProceedings{Anonymous:2020:ACN,
  author =       "Anonymous",
  title =        "[{ARITH 2020} Copyright notice]",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00003",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the copyright information for the conference.
                 May include reprint permission information.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:AI
author: Anonymous
title: ARITH 2020 Index
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00030
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents an index of the authors whose articles are published in the conference proceedings record.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Presents an index of the authors whose articles are published in the conference proceedings record.
rawauthor: Anonymous
rawtitle: {ARITH 2020} Index
entry:
@InProceedings{Anonymous:2020:AI,
  author =       "Anonymous",
  title =        "{ARITH 2020} Index",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00030",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents an index of the authors whose articles are
                 published in the conference proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ALR
author: Anonymous
title: ARITH 2020 List Reviewer Page
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00008
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: The conference offers a note of thanks and lists its reviewers.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: The conference offers a note of thanks and lists its reviewers.
rawauthor: Anonymous
rawtitle: {ARITH 2020} List Reviewer Page
entry:
@InProceedings{Anonymous:2020:ALR,
  author =       "Anonymous",
  title =        "{ARITH 2020} List Reviewer Page",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00008",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference offers a note of thanks and lists its
                 reviewers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2020:RVE
author: Anonymous
title: RISC-V embedded variant RV32E now fully supported by SEGGER's Floating-Point library
pages: i--i
day: 21
month: sep
monthnumber: 9
year: 2020
bibdate: Thu Jan 28 18:02:53 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.01.28 18:02:53 ???
URL: https://www.design-reuse.com/news/48672/segger-s-floating-point-library-risc-v-rv32e.html
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: {RISC-V} embedded variant {RV32E} now fully supported by {SEGGER}'s Floating-Point library
remark:
The story reports a significant code size reduction, and speedup, over the GNU floating-point library.

entry:
@Misc{Anonymous:2020:RVE,
  author =       "Anonymous",
  title =        "{RISC-V} embedded variant {RV32E} now fully supported
                 by {SEGGER}'s Floating-Point library",
  howpublished = "Web site",
  day =          "21",
  month =        sep,
  year =         "2020",
  bibdate =      "Thu Jan 28 18:02:53 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.design-reuse.com/news/48672/segger-s-floating-point-library-risc-v-rv32e.html",
  acknowledgement = ack-nhfb,
  remark =       "The story reports a significant code size reduction,
                 and speedup, over the GNU floating-point library.",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:SA
author: Anonymous
title: Sponsors ARITH 2020
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00009
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
rawauthor: Anonymous
rawtitle: Sponsors {ARITH 2020}
entry:
@InProceedings{Anonymous:2020:SA,
  author =       "Anonymous",
  title =        "Sponsors {ARITH 2020}",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00009",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference organizers greatly appreciate the
                 support of the various corporate sponsors listed.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:TC
author: Anonymous
title: Table of Contents
crossref: Cornea:2020:ISC
pages: i--iii
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00004
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the table of contents/splash page of the proceedings record.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Presents the table of contents/splash page of the proceedings record.
rawauthor: Anonymous
rawtitle: Table of Contents
entry:
@InProceedings{Anonymous:2020:TC,
  author =       "Anonymous",
  title =        "Table of Contents",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--iii",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00004",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the table of contents/splash page of the
                 proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:TPa
author: Anonymous
title: [Title page]
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00001
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the title page of the proceedings record.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Presents the title page of the proceedings record.
rawauthor: Anonymous
rawtitle: [{Title} page]
entry:
@InProceedings{Anonymous:2020:TPa,
  author =       "Anonymous",
  title =        "[{Title} page]",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00001",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:TPb
author: Anonymous
title: [Title page]
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00002
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the title page of the proceedings record.
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawabstract: Presents the title page of the proceedings record.
rawauthor: Anonymous
rawtitle: [{Title} page]
entry:
@InProceedings{Anonymous:2020:TPb,
  author =       "Anonymous",
  title =        "[{Title} page]",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00002",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: article
filename: fparith.bib
label: Arnold:2020:IRL
author: M. G. Arnold and V. Paliouras and I. Kouretas
title: Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 12
pages: 1719--1732
month: dec
monthnumber: 12
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2930514
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Nov 24 09:42:22 2020
bibtimestamp: 2020.11.24 09:42:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. G. Arnold and V. Paliouras and I. Kouretas
rawtitle: Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

entry:
@Article{Arnold:2020:IRL,
  author =       "M. G. Arnold and V. Paliouras and I. Kouretas",
  title =        "Implementing the Residue Logarithmic Number System
                 Using Interpolation and Cotransformation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "12",
  pages =        "1719--1732",
  month =        dec,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2930514",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Nov 24 09:42:22 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2020:AFV
author: Jean-Claude Bajard and Julien Eynard and Paulo Martins and Leonel Sousa and Vincent Zucca
title: An asymptotically faster version of FV supported on HPR
crossref: Cornea:2020:ISC
pages: 80--87
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00020
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Jean-Claude Bajard and Julien Eynard and Paulo Martins and Leonel Sousa and Vincent Zucca
rawtitle: An asymptotically faster version of {FV} supported on {HPR}
abstract:
State-of-the-art implementations of homomorphic encryption exploit the Fan and Vercauteren (FV) scheme and the Residue Number System (RNS). While the RNS breaks down large integer arithmetic into smaller independent channels, its non-positional nature makes operations such as division and rounding hard to implement, and makes the representation of small values inefficient. In this work, we propose the application of the Hybrid Position-Residues Number System representation to the FV scheme. This is a positional representation of large radix where the digits are represented in RNS. It inherits the benefits from RNS and allows to accelerate the critical division and rounding operations while also making the representation of smaller values more compact. This directly benefits the decryption and the homomorphic multiplication procedures, reducing their asymptotic complexity, in dimension n, from O(n2 log n) to O(n log n) and from O(n3 log n) to O(n3), respectively and has resulted in noticeable speedups when experimentally compared to related art RNS implementations.

keywords:
Acceleration; ARITH 2020; ARITH-27; Art; Complexity theory; Encryption; Fan-Vercauteren scheme; Fans; Homomorphic Encryption; Indexes; Residue Number System

rawabstract:
State-of-the-art implementations of homomorphic encryption exploit the Fan and Vercauteren (FV) scheme and the Residue Number System (RNS). While the RNS breaks down large integer arithmetic into smaller independent channels, its non-positional nature makes operations such as division and rounding hard to implement, and makes the representation of small values inefficient. In this work, we propose the application of the Hybrid Position-Residues Number System representation to the FV scheme. This is a positional representation of large radix where the digits are represented in RNS. It inherits the benefits from RNS and allows to accelerate the critical division and rounding operations while also making the representation of smaller values more compact. This directly benefits the decryption and the homomorphic multiplication procedures, reducing their asymptotic complexity, in dimension n, from O(n2 log n) to O(n log n) and from O(n3 log n) to O(n3), respectively and has resulted in noticeable speedups when experimentally compared to related art RNS implementations.

entry:
@InProceedings{Bajard:2020:AFV,
  author =       "Jean-Claude Bajard and Julien Eynard and Paulo Martins
                 and Leonel Sousa and Vincent Zucca",
  title =        "An asymptotically faster version of {FV} supported on
                 {HPR}",
  crossref =     "Cornea:2020:ISC",
  pages =        "80--87",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00020",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "State-of-the-art implementations of homomorphic
                 encryption exploit the Fan and Vercauteren (FV) scheme
                 and the Residue Number System (RNS). While the RNS
                 breaks down large integer arithmetic into smaller
                 independent channels, its non-positional nature makes
                 operations such as division and rounding hard to
                 implement, and makes the representation of small values
                 inefficient. In this work, we propose the application
                 of the Hybrid Position-Residues Number System
                 representation to the FV scheme. This is a positional
                 representation of large radix where the digits are
                 represented in RNS. It inherits the benefits from RNS
                 and allows to accelerate the critical division and
                 rounding operations while also making the
                 representation of smaller values more compact. This
                 directly benefits the decryption and the homomorphic
                 multiplication procedures, reducing their asymptotic
                 complexity, in dimension n, from O(n2 log n) to O(n log
                 n) and from O(n3 log n) to O(n3), respectively and has
                 resulted in noticeable speedups when experimentally
                 compared to related art RNS implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; ARITH 2020; ARITH-27; Art; Complexity
                 theory; Encryption; Fan-Vercauteren scheme; Fans;
                 Homomorphic Encryption; Indexes; Residue Number
                 System",
}


bibtype: inproceedings
filename: fparith.bib
label: Barthel:2020:ASA
author: Moritz Barthel and Jochen Rust and Steffen Paul
booktitle: 2020 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Application-Specific Analysis of Different SORN Datatypes for Unum Type-2-Based Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2020
DOI: https://doi.org/10.1109/ISCAS45731.2020.9181182
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Moritz B{\"a}rthel and Jochen Rust and Steffen Paul
rawbooktitle: {2020 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: Application-Specific Analysis of Different {SORN} Datatypes for Unum Type-2-Based Arithmetic
entry:
@InProceedings{Barthel:2020:ASA,
  author =       "Moritz B{\"a}rthel and Jochen Rust and Steffen Paul",
  booktitle =    "{2020 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Application-Specific Analysis of Different {SORN}
                 Datatypes for Unum Type-2-Based Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9181182",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2020:CRF
author: Sylvie Boldo and Diane Gallois-Wong and Thibault Hilaire
title: A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algorithm
crossref: Cornea:2020:ISC
pages: 9--16
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00011
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Diane Gallois-Wong and Thibault Hilaire
rawtitle: A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algorithm
abstract:
Dot products (also called sums of products) are ubiquitous in matrix computations, for instance in signal processing. We are especially interested in digital filters, where they are the core operation. We therefore focus on fixed-point arithmetic, used in embedded systems for time and energy efficiency. Common dot product algorithms ensure faithful rounding. For the sake of accuracy and reproducibility, we want to ensure correct rounding. This article describes an algorithm that computes a correctly-rounded sum of products from inputs whose format is known in advance. This algorithm relies on odd rounding (that is easily implemented in hardware) and comes with a careful proof and some cost analysis.

keywords:
ARITH 2020; ARITH-27; Correct Rounding; Dot Product; Embedded systems; Fixed-point arithmetic; Fixed-Point Arithmetic; floating-point arithmetic; Hardware; Odd Rounding; Runtime; Signal processing; Signal processing algorithms; Sorting; Sum-of-Products

rawabstract:
Dot products (also called sums of products) are ubiquitous in matrix computations, for instance in signal processing. We are especially interested in digital filters, where they are the core operation. We therefore focus on fixed-point arithmetic, used in embedded systems for time and energy efficiency. Common dot product algorithms ensure faithful rounding. For the sake of accuracy and reproducibility, we want to ensure correct rounding. This article describes an algorithm that computes a correctly-rounded sum of products from inputs whose format is known in advance. This algorithm relies on odd rounding (that is easily implemented in hardware) and comes with a careful proof and some cost analysis.

entry:
@InProceedings{Boldo:2020:CRF,
  author =       "Sylvie Boldo and Diane Gallois-Wong and Thibault
                 Hilaire",
  title =        "A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product
                 Algorithm",
  crossref =     "Cornea:2020:ISC",
  pages =        "9--16",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00011",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Dot products (also called sums of products) are
                 ubiquitous in matrix computations, for instance in
                 signal processing. We are especially interested in
                 digital filters, where they are the core operation. We
                 therefore focus on fixed-point arithmetic, used in
                 embedded systems for time and energy efficiency. Common
                 dot product algorithms ensure faithful rounding. For
                 the sake of accuracy and reproducibility, we want to
                 ensure correct rounding. This article describes an
                 algorithm that computes a correctly-rounded sum of
                 products from inputs whose format is known in advance.
                 This algorithm relies on odd rounding (that is easily
                 implemented in hardware) and comes with a careful proof
                 and some cost analysis.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Correct Rounding; Dot Product;
                 Embedded systems; Fixed-point arithmetic; Fixed-Point
                 Arithmetic; floating-point arithmetic; Hardware; Odd
                 Rounding; Runtime; Signal processing; Signal processing
                 algorithms; Sorting; Sum-of-Products",
}


bibtype: inproceedings
filename: fparith.bib
label: Bottcher:2020:HDL
author: Andreas Bottcher and Keanu Kullmann and Martin Kumm
title: Heuristics for the Design of Large Multipliers for FPGAs
crossref: Cornea:2020:ISC
pages: 17--24
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00012
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Andreas B{\"o}ttcher and Keanu Kullmann and Martin Kumm
rawtitle: Heuristics for the Design of Large Multipliers for {FPGAs}
abstract:
The following topics are dealt with: floating point arithmetic; cryptography; field programmable gate arrays; computational complexity; embedded systems; public key cryptography; optimisation; probability; fixed point arithmetic; and digital signal processing chips.

keywords:
ARITH 2020; ARITH-27; Complexity theory; computer arithmetic; Digital arithmetic; Field programmable gate arrays; heuristics; Integer linear programming; Karatsuba multiplier; large multiplier; Optimization; post quantum cryptography; Shape; Table lookup; tiling

rawabstract:
The following topics are dealt with: floating point arithmetic; cryptography; field programmable gate arrays; computational complexity; embedded systems; public key cryptography; optimisation; probability; fixed point arithmetic; and digital signal processing chips.

entry:
@InProceedings{Bottcher:2020:HDL,
  author =       "Andreas B{\"o}ttcher and Keanu Kullmann and Martin
                 Kumm",
  title =        "Heuristics for the Design of Large Multipliers for
                 {FPGAs}",
  crossref =     "Cornea:2020:ISC",
  pages =        "17--24",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00012",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The following topics are dealt with: floating point
                 arithmetic; cryptography; field programmable gate
                 arrays; computational complexity; embedded systems;
                 public key cryptography; optimisation; probability;
                 fixed point arithmetic; and digital signal processing
                 chips.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Complexity theory; computer
                 arithmetic; Digital arithmetic; Field programmable gate
                 arrays; heuristics; Integer linear programming;
                 Karatsuba multiplier; large multiplier; Optimization;
                 post quantum cryptography; Shape; Table lookup;
                 tiling",
}


bibtype: article
filename: fparith.bib
label: Boyvalenkov:2020:CMS
title: Classification of Moduli Sets for Residue Number System With Special Diagonal Functions
journal: j-IEEE-ACCESS
volume: 8
pages: 156104--156116
year: 2020
DOI: https://doi.org/10.1109/ACCESS.2020.3019452
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:08:36 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:08:36 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawtitle: Classification of Moduli Sets for Residue Number System With Special Diagonal Functions
author:
Peter Boyvalenkov and Nikolay I. Chervyakov and Pavel Lyakhov and Nataliya Semyonova and Anton Nazarov and Maria Valueva and Georgi Boyvalenkov and Danil Bogaevskiy and Dmitrii Kaplun

keywords:
average bit-width; Current measurement; diagonal function; FPGA; Hardware; hardware implementation; Heuristic algorithms; non-modular operations; Object recognition; Parallel processing; quadruples; Residue number system; RNS balance; triples

rawauthor:
Peter Boyvalenkov and Nikolay I. Chervyakov and Pavel Lyakhov and Nataliya Semyonova and Anton Nazarov and Maria Valueva and Georgi Boyvalenkov and Danil Bogaevskiy and Dmitrii Kaplun

entry:
@Article{Boyvalenkov:2020:CMS,
  author =       "Peter Boyvalenkov and Nikolay I. Chervyakov and Pavel
                 Lyakhov and Nataliya Semyonova and Anton Nazarov and
                 Maria Valueva and Georgi Boyvalenkov and Danil
                 Bogaevskiy and Dmitrii Kaplun",
  title =        "Classification of Moduli Sets for Residue Number
                 System With Special Diagonal Functions",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  pages =        "156104--156116",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.3019452",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:08:36 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "average bit-width; Current measurement; diagonal
                 function; FPGA; Hardware; hardware implementation;
                 Heuristic algorithms; non-modular operations; Object
                 recognition; Parallel processing; quadruples; Residue
                 number system; RNS balance; triples",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2020:EAS
author: Nicolas Brisebarre and Mioara Joldes and Jean-Michel Muller and Ana-Maria Nanes and Joris Picot
title: Error Analysis of Some Operations Involved in the Cooley--Tukey Fast Fourier Transform
journal: j-TOMS
volume: 46
number: 2
pages: 11:1--11:27
month: jun
monthnumber: 6
year: 2020
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3368619
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Jun 12 07:37:53 MDT 2020
bibtimestamp: 2020.06.12 07:37:53 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3368619
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 11
journalURL: https://dl.acm.org/loi/toms
rawauthor: Nicolas Brisebarre and Mioara Joldes and Jean-Michel Muller and Ana-Maria Nanes and Joris Picot
rawtitle: Error Analysis of Some Operations Involved in the {Cooley--Tukey Fast Fourier Transform}
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/t/tukey-john-w.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We are interested in obtaining error bounds for the classical Cooley--Tukey fast Fourier transform algorithm in floating-point arithmetic, for the 2-norm as well as for the infinity norm. For that purpose, we also give some results on the relative error of the complex multiplication by a root of unity, and on the largest value that can take the real or imaginary part of one term of the fast Fourier transform of a vector $x$, assuming that all terms of $x$ have real and imaginary parts less than some value $b$.

rawabstract:
We are interested in obtaining error bounds for the classical Cooley--Tukey fast Fourier transform algorithm in floating-point arithmetic, for the 2-norm as well as for the infinity norm. For that purpose, we also give some results on the relative error of the complex multiplication by a root of unity, and on the largest value that can take the real or imaginary part of one term of the fast Fourier transform of a vector $x$, assuming that all terms of $x$ have real and imaginary parts less than some value $b$.

entry:
@Article{Brisebarre:2020:EAS,
  author =       "Nicolas Brisebarre and Mioara Joldes and Jean-Michel
                 Muller and Ana-Maria Nanes and Joris Picot",
  title =        "Error Analysis of Some Operations Involved in the
                 {Cooley--Tukey Fast Fourier Transform}",
  journal =      j-TOMS,
  volume =       "46",
  number =       "2",
  pages =        "11:1--11:27",
  month =        jun,
  year =         "2020",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3368619",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Jun 12 07:37:53 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/t/tukey-john-w.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3368619",
  abstract =     "We are interested in obtaining error bounds for the
                 classical Cooley--Tukey fast Fourier transform
                 algorithm in floating-point arithmetic, for the 2-norm
                 as well as for the infinity norm. For that purpose, we
                 also give some results on the relative error of the
                 complex multiplication by a root of unity, and on the
                 largest value that can take the real or imaginary part
                 of one term of the fast Fourier transform of a vector
                 $x$, assuming that all terms of $x$ have real and
                 imaginary parts less than some value $b$.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Bruguera:2020:LLF
author: J. D. Bruguera
title: Low Latency Floating-Point Division and Square Root Unit
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 2
pages: 274--287
month: feb
monthnumber: 2
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2947899
ISSN: 2326-3814 OR 23263814
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jan 22 06:44:09 2020
bibtimestamp: 2020.01.22 06:44:09 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. D. Bruguera
rawtitle: Low Latency Floating-Point Division and Square Root Unit
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

keywords:
Computer architecture; Convergence; Digit-recurrence algorithms; Estimation; floating-point division, and square root; Iterative methods; Organizations; Registers; Timing

entry:
@Article{Bruguera:2020:LLF,
  author =       "J. D. Bruguera",
  title =        "Low Latency Floating-Point Division and Square Root
                 Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "2",
  pages =        "274--287",
  month =        feb,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2947899",
  ISSN =         "2326-3814",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jan 22 06:44:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Computer architecture; Convergence; Digit-recurrence
                 algorithms; Estimation; floating-point division, and
                 square root; Iterative methods; Organizations;
                 Registers; Timing",
}


bibtype: inproceedings
filename: fparith.bib
label: Brunie:2020:TFP
author: Hugo Brunie and Costin Iancu and Khaled Z. Ibrahim and Philip Brisk and Brandon Cook
title: Tuning floating-point precision using dynamic program information and temporal locality
crossref: IEEE:2020:SPI
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--14
year: 2020
bibdate: Mon Sep 11 08:19:28 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 08:19:28 ???
acknowledgement: ack-nhfb
articleno: 50
rawauthor: Hugo Brunie and Costin Iancu and Khaled Z. Ibrahim and Philip Brisk and Brandon Cook
rawtitle: Tuning floating-point precision using dynamic program information and temporal locality
abstract:
We present a methodology for precision tuning of full applications. These techniques must select a search space composed of either variables or instructions and provide a scalable search strategy. In full application settings one cannot assume compiler support for practical reasons. Thus, an additional important challenge is enabling code refactoring. We argue for an instruction-based search space and we show: (1) how to exploit dynamic program information based on call stacks; and (2) how to exploit the iterative nature of scientific codes, combined with temporal locality. We applied the methodology to tune the implementation of scientific codes written in a combination of Python, CUDA, C++ and Fortran, tuning calls to math exp library functions. The iterative search refinement always reduces the search complexity and the number of steps to solution. Dynamic program information increases search efficacy. Using this approach, we obtain application runtime performance improvements up to 27%.

rawabstract:
We present a methodology for precision tuning of full applications. These techniques must select a search space composed of either variables or instructions and provide a scalable search strategy. In full application settings one cannot assume compiler support for practical reasons. Thus, an additional important challenge is enabling code refactoring. We argue for an instruction-based search space and we show: (1) how to exploit dynamic program information based on call stacks; and (2) how to exploit the iterative nature of scientific codes, combined with temporal locality. We applied the methodology to tune the implementation of scientific codes written in a combination of Python, CUDA, C++ and Fortran, tuning calls to math exp library functions. The iterative search refinement always reduces the search complexity and the number of steps to solution. Dynamic program information increases search efficacy. Using this approach, we obtain application runtime performance improvements up to 27\%.

entry:
@InProceedings{Brunie:2020:TFP,
  author =       "Hugo Brunie and Costin Iancu and Khaled Z. Ibrahim and
                 Philip Brisk and Brandon Cook",
  title =        "Tuning floating-point precision using dynamic program
                 information and temporal locality",
  crossref =     "IEEE:2020:SPI",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--14",
  year =         "2020",
  bibdate =      "Mon Sep 11 08:19:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a methodology for precision tuning of full
                 applications. These techniques must select a search
                 space composed of either variables or instructions and
                 provide a scalable search strategy. In full application
                 settings one cannot assume compiler support for
                 practical reasons. Thus, an additional important
                 challenge is enabling code refactoring. We argue for an
                 instruction-based search space and we show: (1) how to
                 exploit dynamic program information based on call
                 stacks; and (2) how to exploit the iterative nature of
                 scientific codes, combined with temporal locality. We
                 applied the methodology to tune the implementation of
                 scientific codes written in a combination of Python,
                 CUDA, C++ and Fortran, tuning calls to math exp library
                 functions. The iterative search refinement always
                 reduces the search complexity and the number of steps
                 to solution. Dynamic program information increases
                 search efficacy. Using this approach, we obtain
                 application runtime performance improvements up to
                 27\%.",
  acknowledgement = ack-nhfb,
  articleno =    "50",
}


bibtype: inproceedings
filename: fparith.bib
label: Buoncristiani:2020:ENS
author: Nicholas Buoncristiani and Sanjana Shah and David Donofrio and John Shalf
editor: IEEE
booktitle: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
title: Evaluating the Numerical Stability of Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 612--621
year: 2020
DOI: https://doi.org/10.1109/IPDPS47924.2020.00069
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Nicholas Buoncristiani and Sanjana Shah and David Donofrio and John Shalf
rawbooktitle: {2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}
raweditor: {IEEE}
rawtitle: Evaluating the Numerical Stability of Posit Arithmetic
entry:
@InProceedings{Buoncristiani:2020:ENS,
  author =       "Nicholas Buoncristiani and Sanjana Shah and David
                 Donofrio and John Shalf",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Parallel and Distributed
                 Processing Symposium (IPDPS)}",
  title =        "Evaluating the Numerical Stability of Posit
                 Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "612--621",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/IPDPS47924.2020.00069",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Calligo:2020:PNU
author: Calligo Technologies
title: Posit Numeric Unit (PNU-IP)
pages: 612--621
year: 2020
bibdate: Sat Dec 16 15:24:16 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 15:24:16 ???
URL: https://calligotech.com/posit-numeric-unit-pnu-ip
keywords: posit arithmetic
acknowledgement: ack-nhfb
howpublished: Web software.
rawauthor: {Calligo Technologies}
rawtitle: Posit Numeric Unit ({PNU-IP})
entry:
@Misc{Calligo:2020:PNU,
  author =       "{Calligo Technologies}",
  title =        "Posit Numeric Unit ({PNU-IP})",
  howpublished = "Web software.",
  year =         "2020",
  bibdate =      "Sat Dec 16 15:24:16 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://calligotech.com/posit-numeric-unit-pnu-ip",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Cavalcante:2020:AGS
author: Matheus Cavalcante and Fabian Schuiki and Florian Zaruba and Michael Schaffner and Luca Benini
journal: j-IEEE-TRANS-VLSI-SYST
volume: 28
number: 2
pages: 530--543
year: 2020
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2019.2950087
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Matheus Cavalcante and Fabian Schuiki and Florian Zaruba and Michael Schaffner and Luca Benini
title:
Ara: a 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI

rawtitle:
{Ara}: a {1-GHz+} Scalable and Energy-Efficient {RISC-V} Vector Processor With Multiprecision Floating-Point Support in 22-nm {FD-SOI}

entry:
@Article{Cavalcante:2020:AGS,
  author =       "Matheus Cavalcante and Fabian Schuiki and Florian
                 Zaruba and Michael Schaffner and Luca Benini",
  title =        "{Ara}: a {1-GHz+} Scalable and Energy-Efficient
                 {RISC-V} Vector Processor With Multiprecision
                 Floating-Point Support in 22-nm {FD-SOI}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "28",
  number =       "2",
  pages =        "530--543",
  year =         "2020",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2019.2950087",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: article
filename: fparith.bib
label: Cherubin:2020:TRP
author: Stefano Cherubin and Giovanni Agosta
title: Tools for Reduced Precision Computation: a Survey
journal: j-COMP-SURV
volume: 53
number: 2
pages: 33:1--33:35
month: jul
monthnumber: 7
year: 2020
CODEN: CMSVAN
DOI: https://doi.org/10.1145/3381039
ISSN: 0360-0300 (print), 1557-7341 (electronic) OR 03600300 (print), 15577341 (electronic)
ISSNL: 0360-0300 OR 03600300
bibdate: Wed Jul 8 17:24:43 MDT 2020
bibtimestamp: 2020.07.08 17:24:43 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3381039
fjournal: ACM Computing Surveys
acknowledgement: ack-nhfb
articleno: 33
journalURL: https://dl.acm.org/loi/csur
rawauthor: Stefano Cherubin and Giovanni Agosta
rawtitle: Tools for Reduced Precision Computation: a Survey
bibsource:
https://www.math.utah.edu/pub/tex/bib/compsurv.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The use of reduced precision to improve performance metrics such as computation latency and power consumption is a common practice in the embedded systems field. This practice is emerging as a new trend in High Performance Computing (HPC), especially when new error-tolerant applications are considered. However, standard compiler frameworks do not support automated precision customization, and manual tuning and code transformation is the approach usually adopted in most domains. In recent years, research have been studying ways to improve the automation of this process. This article surveys this body of work, identifying the critical steps of this process, the most advanced tools available, and the open challenges in this research area. We conclude that, while several mature tools exist, there is still a gap to close, especially for tools based on static analysis rather than profiling, as well as for integration within mainstream, industry-strength compiler frameworks.

rawabstract:
The use of reduced precision to improve performance metrics such as computation latency and power consumption is a common practice in the embedded systems field. This practice is emerging as a new trend in High Performance Computing (HPC), especially when new error-tolerant applications are considered. However, standard compiler frameworks do not support automated precision customization, and manual tuning and code transformation is the approach usually adopted in most domains. In recent years, research have been studying ways to improve the automation of this process. This article surveys this body of work, identifying the critical steps of this process, the most advanced tools available, and the open challenges in this research area. We conclude that, while several mature tools exist, there is still a gap to close, especially for tools based on static analysis rather than profiling, as well as for integration within mainstream, industry-strength compiler frameworks.

entry:
@Article{Cherubin:2020:TRP,
  author =       "Stefano Cherubin and Giovanni Agosta",
  title =        "Tools for Reduced Precision Computation: a Survey",
  journal =      j-COMP-SURV,
  volume =       "53",
  number =       "2",
  pages =        "33:1--33:35",
  month =        jul,
  year =         "2020",
  CODEN =        "CMSVAN",
  DOI =          "https://doi.org/10.1145/3381039",
  ISSN =         "0360-0300 (print), 1557-7341 (electronic)",
  ISSN-L =       "0360-0300",
  bibdate =      "Wed Jul 8 17:24:43 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compsurv.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3381039",
  abstract =     "The use of reduced precision to improve performance
                 metrics such as computation latency and power
                 consumption is a common practice in the embedded
                 systems field. This practice is emerging as a new trend
                 in High Performance Computing (HPC), especially when
                 new error-tolerant applications are considered.
                 However, standard compiler frameworks do not support
                 automated precision customization, and manual tuning
                 and code transformation is the approach usually adopted
                 in most domains. In recent years, research have been
                 studying ways to improve the automation of this
                 process. This article surveys this body of work,
                 identifying the critical steps of this process, the
                 most advanced tools available, and the open challenges
                 in this research area. We conclude that, while several
                 mature tools exist, there is still a gap to close,
                 especially for tools based on static analysis rather
                 than profiling, as well as for integration within
                 mainstream, industry-strength compiler frameworks.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Computing Surveys",
  journal-URL =  "https://dl.acm.org/loi/csur",
}


bibtype: inproceedings
filename: fparith.bib
label: Chien:2020:PNA
author: Steven W. D. Chien and Ivy B. Peng and Stefano Markidis
title: Posit NPB: Assessing the Precision Improvement in HPC Scientific Applications
crossref: Wyrzykowski:2020:PPA
pages: 301--310
year: 2020
DOI: https://doi.org/10.1007/978-3-030-43229-4_26
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Steven W. D. Chien and Ivy B. Peng and Stefano Markidis
rawtitle: Posit {NPB}: Assessing the Precision Improvement in {HPC} Scientific Applications
entry:
@InProceedings{Chien:2020:PNA,
  author =       "Steven W. D. Chien and Ivy B. Peng and Stefano
                 Markidis",
  title =        "Posit {NPB}: Assessing the Precision Improvement in
                 {HPC} Scientific Applications",
  crossref =     "Wyrzykowski:2020:PPA",
  pages =        "301--310",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-43229-4_26",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Chowdhary:2020:DDN
author: Sangeeta Chowdhary and Jay P. Lim and Santosh Nagarakatte
title: Debugging and detecting numerical errors in computation with posits
publisher: pub-ACM
address: pub-ACM:adr
pages: 731--746
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1145/3385412.3386004
bibdate: Sat Dec 9 08:43:53 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.09 08:43:53 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Sangeeta Chowdhary and Jay P. Lim and Santosh Nagarakatte
rawtitle: Debugging and detecting numerical errors in computation with posits
booktitle:
PLDI 2020: Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation

rawbooktitle:
{PLDI 2020: Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation}

entry:
@InProceedings{Chowdhary:2020:DDN,
  author =       "Sangeeta Chowdhary and Jay P. Lim and Santosh
                 Nagarakatte",
  booktitle =    "{PLDI 2020: Proceedings of the 41st ACM SIGPLAN
                 Conference on Programming Language Design and
                 Implementation}",
  title =        "Debugging and detecting numerical errors in
                 computation with posits",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "731--746",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1145/3385412.3386004",
  bibdate =      "Sat Dec 9 08:43:53 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cococcioni:2020:FAH
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
booktitle: Applications in Electronics Pervading Industry, Environment and Society
publisher: pub-SV
address: pub-SV:adr
pages: 213--221
year: 2020
DOI: https://doi.org/10.1007/978-3-030-37277-4_25
ISBN: 3-030-37277-4 OR 3030372774
ISBN13: 978-3-030-37277-4 OR 9783030372774
ISSN: 1876-1119 OR 18761119
ISSNL: 1876-1100 OR 18761100
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawbooktitle: Applications in Electronics Pervading Industry, Environment and Society
title:
A Fast Approximation of the Hyperbolic Tangent When Using Posit Numbers and Its Application to Deep Neural Networks

rawtitle:
A Fast Approximation of the Hyperbolic Tangent When Using Posit Numbers and Its Application to Deep Neural Networks

entry:
@InProceedings{Cococcioni:2020:FAH,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  booktitle =    "Applications in Electronics Pervading Industry,
                 Environment and Society",
  title =        "A Fast Approximation of the Hyperbolic Tangent When
                 Using Posit Numbers and Its Application to Deep Neural
                 Networks",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "213--221",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-37277-4_25",
  ISBN =         "3-030-37277-4",
  ISBN-13 =      "978-3-030-37277-4",
  ISSN =         "1876-1119",
  ISSN-L =       "1876-1100",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Cococcioni:2020:FDN
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
title: Fast deep neural networks for image processing using posits and ARM scalable vector extension
journal: Journal of Real-Time Image Processing
volume: 17
number: 3
pages: 759--771
month: may
monthnumber: 5
year: 2020
DOI: https://doi.org/10.1007/s11554-020-00984-x
ISSN: 1861-8219 OR 18618219
ISSNL: 1861-8200 OR 18618200
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawtitle: Fast deep neural networks for image processing using posits and {ARM} scalable vector extension
entry:
@Article{Cococcioni:2020:FDN,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  title =        "Fast deep neural networks for image processing using
                 posits and {ARM} scalable vector extension",
  journal =      "Journal of Real-Time Image Processing",
  volume =       "17",
  number =       "3",
  pages =        "759--771",
  month =        may,
  year =         "2020",
  DOI =          "https://doi.org/10.1007/s11554-020-00984-x",
  ISSN =         "1861-8219",
  ISSN-L =       "1861-8200",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cococcioni:2020:NPB
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
editor: IEEE
booktitle: 2020 IEEE International Conference on Smart Computing (SMARTCOMP)
title: A Novel Posit-based Fast Approximation of ELU Activation Function for Deep Neural Networks
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 244--246
year: 2020
DOI: https://doi.org/10.1109/SMARTCOMP50058.2020.00053
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawbooktitle: {2020 IEEE International Conference on Smart Computing (SMARTCOMP)}
raweditor: {IEEE}
rawtitle: A Novel Posit-based Fast Approximation of {ELU} Activation Function for Deep Neural Networks
entry:
@InProceedings{Cococcioni:2020:NPB,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Conference on Smart Computing
                 (SMARTCOMP)}",
  title =        "A Novel Posit-based Fast Approximation of {ELU}
                 Activation Function for Deep Neural Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "244--246",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/SMARTCOMP50058.2020.00053",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2020:FA
author: Marius Cornea and Weiqiang Liu and Arnaud Tisserand
title: Foreword ARITH 2020
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00005
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
keywords: ARITH 2020; ARITH-27
acknowledgement: ack-nhfb
rawauthor: Marius Cornea and Weiqiang Liu and Arnaud Tisserand
rawtitle: Foreword {ARITH 2020}
abstract:
The 27th IEEE Symposium on Computer Arithmetic, ARITH-2020, was initially planned to be held in Portland, Oregon, USA on Jun 7-10, 2020. Due to the COVID-19 crisis all around the world in 2020, the face-to-face meeting has been canceled. The paper selection process was completed, and the accepted papers have been included in the ARITH-2020 proceedings. For ARITH-2020, 73 anonymous submissions have been submitted at the beginning of February. Following the peer-review practice of this symposium, each paper was blind-reviewed by at least three, and up to five, Program Committee members, and a final decision was made by the committee in mid-April. 40 PC members and some external reviewers were involved in this process. The technical program of ARITH- 2020 includes 16 regular papers (8 pages) and 4 short papers (4 pages).

rawabstract:
The 27th IEEE Symposium on Computer Arithmetic, ARITH-2020, was initially planned to be held in Portland, Oregon, USA on Jun 7-10, 2020. Due to the COVID-19 crisis all around the world in 2020, the face-to-face meeting has been canceled. The paper selection process was completed, and the accepted papers have been included in the ARITH-2020 proceedings. For ARITH-2020, 73 anonymous submissions have been submitted at the beginning of February. Following the peer-review practice of this symposium, each paper was blind-reviewed by at least three, and up to five, Program Committee members, and a final decision was made by the committee in mid-April. 40 PC members and some external reviewers were involved in this process. The technical program of ARITH- 2020 includes 16 regular papers (8 pages) and 4 short papers (4 pages).

entry:
@InProceedings{Cornea:2020:FA,
  author =       "Marius Cornea and Weiqiang Liu and Arnaud Tisserand",
  title =        "Foreword {ARITH 2020}",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00005",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The 27th IEEE Symposium on Computer Arithmetic,
                 ARITH-2020, was initially planned to be held in
                 Portland, Oregon, USA on Jun 7-10, 2020. Due to the
                 COVID-19 crisis all around the world in 2020, the
                 face-to-face meeting has been canceled. The paper
                 selection process was completed, and the accepted
                 papers have been included in the ARITH-2020
                 proceedings. For ARITH-2020, 73 anonymous submissions
                 have been submitted at the beginning of February.
                 Following the peer-review practice of this symposium,
                 each paper was blind-reviewed by at least three, and up
                 to five, Program Committee members, and a final
                 decision was made by the committee in mid-April. 40 PC
                 members and some external reviewers were involved in
                 this process. The technical program of ARITH- 2020
                 includes 16 regular papers (8 pages) and 4 short papers
                 (4 pages).",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27",
}


bibtype: inproceedings
filename: fparith.bib
label: Coward:2020:ADS
author: Samuel Coward and Theo Drane and Yoav Harel
title: Automatic Design Space Exploration for an Error Tolerant Application
crossref: Cornea:2020:ISC
pages: 117--120
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00025
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Samuel Coward and Theo Drane and Yoav Harel
rawtitle: Automatic Design Space Exploration for an Error Tolerant Application
abstract:
Creating optimized hardware for error tolerant applications presents significant challenges as well as opportunities. Many algorithms in computer graphics & vision are error tolerant, as their application level correctness ultimately rests on human perception. This error tolerance can be exploited in reducing hardware implementation cost. The challenge is how to explore the space of application level correct designs to determine the optimized hardware architecture. This paper puts forward an approach to automatically explore the space which maximally exploits the acceptable error to minimize hardware cost for a particular graphics algorithm --- Level-Of-Detail. Results, so far, have shown a 26% hardware area improvement.

keywords:
accuracy hardware tradeoffs; approximate computing; ARITH 2020; ARITH-27; computer graphics; Computer graphics; Delays; design automation; floating-point; Hardware; Logic gates; Minimization; multiple-precision; numerical analysis; power-efficient; Space exploration

rawabstract:
Creating optimized hardware for error tolerant applications presents significant challenges as well as opportunities. Many algorithms in computer graphics & vision are error tolerant, as their application level correctness ultimately rests on human perception. This error tolerance can be exploited in reducing hardware implementation cost. The challenge is how to explore the space of application level correct designs to determine the optimized hardware architecture. This paper puts forward an approach to automatically explore the space which maximally exploits the acceptable error to minimize hardware cost for a particular graphics algorithm --- Level-Of-Detail. Results, so far, have shown a 26\% hardware area improvement.

entry:
@InProceedings{Coward:2020:ADS,
  author =       "Samuel Coward and Theo Drane and Yoav Harel",
  title =        "Automatic Design Space Exploration for an Error
                 Tolerant Application",
  crossref =     "Cornea:2020:ISC",
  pages =        "117--120",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00025",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Creating optimized hardware for error tolerant
                 applications presents significant challenges as well as
                 opportunities. Many algorithms in computer graphics &
                 vision are error tolerant, as their application level
                 correctness ultimately rests on human perception. This
                 error tolerance can be exploited in reducing hardware
                 implementation cost. The challenge is how to explore
                 the space of application level correct designs to
                 determine the optimized hardware architecture. This
                 paper puts forward an approach to automatically explore
                 the space which maximally exploits the acceptable error
                 to minimize hardware cost for a particular graphics
                 algorithm --- Level-Of-Detail. Results, so far, have
                 shown a 26\% hardware area improvement.",
  acknowledgement = ack-nhfb,
  keywords =     "accuracy hardware tradeoffs; approximate computing;
                 ARITH 2020; ARITH-27; computer graphics; Computer
                 graphics; Delays; design automation; floating-point;
                 Hardware; Logic gates; Minimization;
                 multiple-precision; numerical analysis;
                 power-efficient; Space exploration",
}


bibtype: inproceedings
filename: fparith.bib
label: Das:2020:SYR
author: Arnab Das and Ian Briggs and Ganesh Gopalakrishnan and Sriram Krishnamoorthy and Pavel Panchekha
title: Scalable yet Rigorous Floating-Point Error Analysis
crossref: IEEE:2020:SPI
pages: 1--14
year: 2020
bibdate: Mon Sep 11 06:40:11 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 06:40:11 ???
acknowledgement: ack-nhfb
articleno: 51
rawauthor: Arnab Das and Ian Briggs and Ganesh Gopalakrishnan and Sriram Krishnamoorthy and Pavel Panchekha
rawtitle: Scalable yet Rigorous Floating-Point Error Analysis
abstract:
Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification, and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators --- barely enough for HPC. In this work, we offer an approach embedded in a new tool called Satire that scales error analysis by four orders of magnitude compared to today's best-of-class tools. We explain how three key ideas underlying Satire helps it attain such scale: path strength reduction, bound optimization, and abstraction. Satire provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication, and PDE stencils.

rawabstract:
Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification, and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators --- barely enough for HPC. In this work, we offer an approach embedded in a new tool called Satire that scales error analysis by four orders of magnitude compared to today's best-of-class tools. We explain how three key ideas underlying Satire helps it attain such scale: path strength reduction, bound optimization, and abstraction. Satire provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication, and PDE stencils.

entry:
@InProceedings{Das:2020:SYR,
  author =       "Arnab Das and Ian Briggs and Ganesh Gopalakrishnan and
                 Sriram Krishnamoorthy and Pavel Panchekha",
  title =        "Scalable yet Rigorous Floating-Point Error Analysis",
  crossref =     "IEEE:2020:SPI",
  pages =        "1--14",
  year =         "2020",
  bibdate =      "Mon Sep 11 06:40:11 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Automated techniques for rigorous floating-point
                 round-off error analysis are a prerequisite to placing
                 important activities in HPC such as precision
                 allocation, verification, and code optimization on a
                 formal footing. Yet existing techniques cannot provide
                 tight bounds for expressions beyond a few dozen
                 operators --- barely enough for HPC. In this work, we
                 offer an approach embedded in a new tool called Satire
                 that scales error analysis by four orders of magnitude
                 compared to today's best-of-class tools. We explain how
                 three key ideas underlying Satire helps it attain such
                 scale: path strength reduction, bound optimization, and
                 abstraction. Satire provides tight bounds and rigorous
                 guarantees on significantly larger expressions with
                 well over a hundred thousand operators, covering
                 important examples including FFT, matrix
                 multiplication, and PDE stencils.",
  acknowledgement = ack-nhfb,
  articleno =    "51",
}


bibtype: article
filename: fparith.bib
label: deCamargo:2020:REA
author: Andre Pierro de Camargo
journal: j-NUMER-ALGORITHMS
volume: 85
number: 2
pages: 591--606
month: oct
monthnumber: 10
year: 2020
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-019-00828-1
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Thu Sep 10 11:29:47 MDT 2020
bibtimestamp: 2020.09.10 11:29:47 MDT
URL: http://link.springer.com/article/10.1007/s11075-019-00828-1
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Andr{\'e} Pierro de Camargo
title:
Rounding error analysis of divided differences schemes: Newton's divided differences; Neville's algorithm; Richardson extrapolation; Romberg quadrature; etc.

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib

rawtitle:
Rounding error analysis of divided differences schemes: {Newton}'s divided differences; {Neville}'s algorithm; {Richardson} extrapolation; {Romberg} quadrature; etc.

entry:
@Article{deCamargo:2020:REA,
  author =       "Andr{\'e} Pierro de Camargo",
  title =        "Rounding error analysis of divided differences
                 schemes: {Newton}'s divided differences; {Neville}'s
                 algorithm; {Richardson} extrapolation; {Romberg}
                 quadrature; etc.",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "85",
  number =       "2",
  pages =        "591--606",
  month =        oct,
  year =         "2020",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-019-00828-1",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Thu Sep 10 11:29:47 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib",
  URL =          "http://link.springer.com/article/10.1007/s11075-019-00828-1",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
}


bibtype: inproceedings
filename: fparith.bib
label: Defour:2020:CPM
author: David Defour and Pablo de Oliveira Castro and Matei Istoan and Eric Petit
title: Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization
crossref: Cornea:2020:ISC
pages: 121--124
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00026
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: David Defour and Pablo de Oliveira Castro and Matei I{\c{s}}toan and Eric Petit
rawtitle: Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization
abstract:
The typical processors used for scientific computing have fixed-width data-paths. This implies that mathematical libraries were specifically developed to target each of these fixed precisions (binary16, binary32, binary64). However, to address the increasing energy consumption and throughput requirements of scientific applications, library and hardware designers are moving beyond this one-size-fits-all approach. In this article we propose to study the effects and benefits of using user-defined floating-point formats and target accuracies in calculations involving mathematical functions. Our tool collects input-data profiles and iteratively explores lower precisions for each call-site of a mathematical function in user applications. This profiling data will be a valuable asset for specializing and fine-tuning mathematical function implementations for a given application. We demonstrate the tool's capabilities on SGP4, a satellite tracking application. The profile data shows the potential for specialization and provides insight into answering where it is useful to provide variable-precision designs for elementary function evaluation.

keywords:
ARITH 2020; ARITH-27; custom-precision; floating-point; Hardware; HPC; libm; Libraries; Mathematical model; Optimization; optimization; Satellites; specialization; Standards; Tools

rawabstract:
The typical processors used for scientific computing have fixed-width data-paths. This implies that mathematical libraries were specifically developed to target each of these fixed precisions (binary16, binary32, binary64). However, to address the increasing energy consumption and throughput requirements of scientific applications, library and hardware designers are moving beyond this one-size-fits-all approach. In this article we propose to study the effects and benefits of using user-defined floating-point formats and target accuracies in calculations involving mathematical functions. Our tool collects input-data profiles and iteratively explores lower precisions for each call-site of a mathematical function in user applications. This profiling data will be a valuable asset for specializing and fine-tuning mathematical function implementations for a given application. We demonstrate the tool's capabilities on SGP4, a satellite tracking application. The profile data shows the potential for specialization and provides insight into answering where it is useful to provide variable-precision designs for elementary function evaluation.

entry:
@InProceedings{Defour:2020:CPM,
  author =       "David Defour and Pablo de Oliveira Castro and Matei
                 I{\c{s}}toan and Eric Petit",
  title =        "Custom-Precision Mathematical Library Explorations for
                 Code Profiling and Optimization",
  crossref =     "Cornea:2020:ISC",
  pages =        "121--124",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00026",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The typical processors used for scientific computing
                 have fixed-width data-paths. This implies that
                 mathematical libraries were specifically developed to
                 target each of these fixed precisions (binary16,
                 binary32, binary64). However, to address the increasing
                 energy consumption and throughput requirements of
                 scientific applications, library and hardware designers
                 are moving beyond this one-size-fits-all approach. In
                 this article we propose to study the effects and
                 benefits of using user-defined floating-point formats
                 and target accuracies in calculations involving
                 mathematical functions. Our tool collects input-data
                 profiles and iteratively explores lower precisions for
                 each call-site of a mathematical function in user
                 applications. This profiling data will be a valuable
                 asset for specializing and fine-tuning mathematical
                 function implementations for a given application. We
                 demonstrate the tool's capabilities on SGP4, a
                 satellite tracking application. The profile data shows
                 the potential for specialization and provides insight
                 into answering where it is useful to provide
                 variable-precision designs for elementary function
                 evaluation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; custom-precision;
                 floating-point; Hardware; HPC; libm; Libraries;
                 Mathematical model; Optimization; optimization;
                 Satellites; specialization; Standards; Tools",
}


