# bibtab

bibtype: article
filename: fparith.bib
label: Hung:1994:ASD
author: C. Y. Hung and B. Parhami
title: An approximate sign detection method for residue numbers and its application to RNS division
journal: j-COMPUT-MATH-APPL
volume: 27
number: 4
pages: 23--35
month: feb
monthnumber: 2
year: 1994
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 19:11:19 MST 2017
bibtimestamp: 2017.03.01 19:11:19 MST
URL: http://www.sciencedirect.com/science/article/pii/0898122194900523
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: C. Y. Hung and B. Parhami
rawtitle: An approximate sign detection method for residue numbers and its application to {RNS} division
entry:
@Article{Hung:1994:ASD,
  author =       "C. Y. Hung and B. Parhami",
  title =        "An approximate sign detection method for residue
                 numbers and its application to {RNS} division",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "27",
  number =       "4",
  pages =        "23--35",
  month =        feb,
  year =         "1994",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 19:11:19 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl1990.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0898122194900523",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Hung:1994:FRD
author: Ching Yu Hung and Behrooz Parhami
title: Fast RNS division algorithms for fixed divisors with application to RSA encryption
journal: j-INFO-PROC-LETT
volume: 51
number: 4
pages: 163--169
day: 24
month: aug
monthnumber: 8
year: 1994
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
MRclass: 94A60
MRnumber: 1 294 308
bibdate: Fri Oct 25 18:39:09 2002
bibtimestamp: 2002.10.25 18:39:09 ???
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
affiliation: Univ of California
affiliationaddress: Santa Barbara, CA, USA
corpsource: Department of Electr. and Comput. Eng., California University, Santa Barbara, CA, USA
journalURL: http://www.sciencedirect.com/science/journal/00200190
journalabr: Inf Process Lett
treatment: A Application; T Theoretical or Mathematical
rawauthor: Ching Yu Hung and Behrooz Parhami
rawtitle: Fast {RNS} division algorithms for fixed divisors with application to {RSA} encryption
bibsource:
Compendex database; http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc.bib; MathSciNet database

keywords:
Algorithms; Chinese remainder theorem; Chinese remainder theorem decoding and table lookup; Computational complexity; computational complexity; Computational complexity; Computational methods; Computer software; Cryptography; cryptography; Cryptography; Decoding; Digital arithmetic; digital arithmetic; Digital arithmetic; Division; divisor reciprocal; Exponentiation; fast RNS division algorithms; fixed divisors; Fixed divisors; Function evaluation; mathematics computing; Modular multiplication; multiplication; Numbering systems; on-line speed; ordinary integer division; Parallel processing systems; preprocessing; Residue number system; Residue processors; RSA encryption; Sign detection; Table lookup; Time complexity; time complexity; Time complexity

entry:
@Article{Hung:1994:FRD,
  author =       "Ching Yu Hung and Behrooz Parhami",
  title =        "Fast {RNS} division algorithms for fixed divisors with
                 application to {RSA} encryption",
  journal =      j-INFO-PROC-LETT,
  volume =       "51",
  number =       "4",
  pages =        "163--169",
  day =          "24",
  month =        aug,
  year =         "1994",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  MRclass =      "94A60",
  MRnumber =     "1 294 308",
  bibdate =      "Fri Oct 25 18:39:09 2002",
  bibsource =    "Compendex database;
                 http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc.bib;
                 MathSciNet database",
  acknowledgement = ack-nhfb,
  affiliation =  "Univ of California",
  affiliationaddress = "Santa Barbara, CA, USA",
  classification = "722.4; 723.1; 723.2; 921.6; C4240 (Programming and
                 algorithm theory)C6130S (Data security); C7310
                 (Mathematics)",
  corpsource =   "Department of Electr. and Comput. Eng., California
                 University, Santa Barbara, CA, USA",
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
  journalabr =   "Inf Process Lett",
  keywords =     "Algorithms; Chinese remainder theorem; Chinese
                 remainder theorem decoding and table lookup;
                 Computational complexity; computational complexity;
                 Computational complexity; Computational methods;
                 Computer software; Cryptography; cryptography;
                 Cryptography; Decoding; Digital arithmetic; digital
                 arithmetic; Digital arithmetic; Division; divisor
                 reciprocal; Exponentiation; fast RNS division
                 algorithms; fixed divisors; Fixed divisors; Function
                 evaluation; mathematics computing; Modular
                 multiplication; multiplication; Numbering systems;
                 on-line speed; ordinary integer division; Parallel
                 processing systems; preprocessing; Residue number
                 system; Residue processors; RSA encryption; Sign
                 detection; Table lookup; Time complexity; time
                 complexity; Time complexity",
  treatment =    "A Application; T Theoretical or Mathematical",
}


bibtype: book
filename: fparith.bib
label: IBM:1994:IRS
editor: Steve White and John Reysa
title: IBM RISC System / 6000 Technology: Volume II
publisher: pub-IBM
address: pub-IBM:adr
pages: 163--169
year: 1994
bibdate: Fri Mar 18 10:25:19 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.03.18 10:25:19 ???
acknowledgement: ack-nhfb
raweditor: Steve White and John Reysa
rawtitle: {IBM RISC} System\slash 6000 Technology: Volume {II}
note:
A partial draft is available via anonymous ftp to path |ibminet.awdpa.ibm.com| in the PostScript file path |/pub/rs6kpapers/techbook.ps|.

rawnote:
A partial draft is available via anonymous ftp to \path|ibminet.awdpa.ibm.com| in the PostScript file \path|/pub/rs6kpapers/techbook.ps|.

entry:
@Book{IBM:1994:IRS,
  editor =       "Steve White and John Reysa",
  title =        "{IBM RISC} System\slash 6000 Technology: Volume {II}",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  year =         "1994",
  bibdate =      "Fri Mar 18 10:25:19 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "A partial draft is available via anonymous ftp to
                 \path|ibminet.awdpa.ibm.com| in the PostScript file
                 \path|/pub/rs6kpapers/techbook.ps|.",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: IBM:1994:OA
author: IBM Corporation
title: The PowerPC Architecture: a Specification for a New Family of RISC Processors
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
edition: Second
pages: xxxi + 518
year: 1994
ISBN: 1-55860-316-6 OR 1558603166
ISBN13: 978-1-55860-316-5 OR 9781558603165
LCCN: QA76.8.P67 P68 1994
bibdate: Wed Jul 6 14:15:23 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.07.06 14:15:23 ???
acknowledgement: ack-nhfb
rawauthor: {IBM Corporation}
rawtitle: The {PowerPC} Architecture: a Specification for a New Family of {RISC} Processors
entry:
@Book{IBM:1994:OA,
  author =       "{IBM Corporation}",
  title =        "The {PowerPC} Architecture: a Specification for a New
                 Family of {RISC} Processors",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxxi + 518",
  year =         "1994",
  ISBN =         "1-55860-316-6",
  ISBN-13 =      "978-1-55860-316-5",
  LCCN =         "QA76.8.P67 P68 1994",
  bibdate =      "Wed Jul 6 14:15:23 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "US\$49.95",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ienne:1994:BSM
author: P. Ienne and M. A. Viredaz
title: Bit-serial multipliers and squarers
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 12
pages: 1445--1450
month: dec
monthnumber: 12
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.338107
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:59 MDT 2011
bibtimestamp: 2011.07.07 07:13:59 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=338107
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Ienne and M. A. Viredaz
rawtitle: Bit-serial multipliers and squarers
entry:
@Article{Ienne:1994:BSM,
  author =       "P. Ienne and M. A. Viredaz",
  title =        "Bit-serial multipliers and squarers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "12",
  pages =        "1445--1450",
  month =        dec,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.338107",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:59 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=338107",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Ignatowski:1994:CNA
author: R. Ignatowski and E. E. Swartzlander
journal: Conference record
pages: 152--??
year: 1994
ISSN: 1058-6393 OR 10586393
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: R. Ignatowski and E. E. Swartzlander
title:
Creating New Algorithms and Modifying Old Algorithms to Use the Variable Precision Floating Point Simulator

rawtitle:
Creating New Algorithms and Modifying Old Algorithms to Use the Variable Precision Floating Point Simulator

entry:
@Article{Ignatowski:1994:CNA,
  author =       "R. Ignatowski and E. E. Swartzlander",
  title =        "Creating New Algorithms and Modifying Old Algorithms
                 to Use the Variable Precision Floating Point
                 Simulator",
  journal =      "Conference record",
  pages =        "152--??",
  year =         "1994",
  ISSN =         "1058-6393",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Isaacson:1994:ANM
author: Eugene Isaacson and Herbert Bishop Keller
title: Analysis of numerical methods
publisher: pub-DOVER
address: pub-DOVER:adr
pages: xv + 541
year: 1994
ISBN: 0-486-68029-0 (paperback) OR 0486680290 (paperback)
ISBN13: 978-0-486-68029-3 (paperback) OR 9780486680293 (paperback)
LCCN: QA297 .I8 1994
bibdate: Fri Aug 20 09:37:14 MDT 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2010.08.20 09:37:14 MDT
URL: http://www.loc.gov/catdir/description/dover031/94007740.html
remark: Originally published in cite Isaacson:1966:ANM. Contains new preface.
subject: Numerical analysis
acknowledgement: ack-nhfb
rawauthor: Eugene Isaacson and Herbert Bishop Keller
rawtitle: Analysis of numerical methods
entry:
@Book{Isaacson:1994:ANM,
  author =       "Eugene Isaacson and Herbert Bishop Keller",
  title =        "Analysis of numerical methods",
  publisher =    pub-DOVER,
  address =      pub-DOVER:adr,
  pages =        "xv + 541",
  year =         "1994",
  ISBN =         "0-486-68029-0 (paperback)",
  ISBN-13 =      "978-0-486-68029-3 (paperback)",
  LCCN =         "QA297 .I8 1994",
  bibdate =      "Fri Aug 20 09:37:14 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  URL =          "http://www.loc.gov/catdir/description/dover031/94007740.html",
  acknowledgement = ack-nhfb,
  remark =       "Originally published in \cite{Isaacson:1966:ANM}.
                 Contains new preface.",
  subject =      "Numerical analysis",
}


bibtype: book
filename: fparith.bib
label: ISO:1994:IIIa
author: ISO
publisher: pub-ISO
address: pub-ISO:adr
pages: viii + 92
day: 15
month: dec
monthnumber: 12
year: 1994
bibdate: Sun Mar 15 11:09:44 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.03.15 11:09:44 ???
acknowledgement: ack-nhfb
rawauthor: {ISO}
title:
ISO / IEC 10967-1 (1994-12): Information technology --- Language independent arithmetic --- Part 1: Integer and floating point arithmetic

URL:
http://standards.iso.org/ittf/PubliclyAvailableStandards/c018939_ISO_IEC_10967-1_1994(E).zip; http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019729; http://www.iso.ch/cate/d18939.html

rawtitle:
{ISO\slash IEC 10967-1 (1994-12)}: {Information} technology --- {Language} independent arithmetic --- {Part 1}: {Integer} and floating point arithmetic

entry:
@Book{ISO:1994:IIIa,
  author =       "{ISO}",
  title =        "{ISO\slash IEC 10967-1 (1994-12)}: {Information}
                 technology --- {Language} independent arithmetic ---
                 {Part 1}: {Integer} and floating point arithmetic",
  publisher =    pub-ISO,
  address =      pub-ISO:adr,
  pages =        "viii + 92",
  day =          "15",
  month =        dec,
  year =         "1994",
  bibdate =      "Sun Mar 15 11:09:44 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "CHF 176, US\$136.00",
  URL =          "http://standards.iso.org/ittf/PubliclyAvailableStandards/c018939_ISO_IEC_10967-1_1994(E).zip;
                 http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019729;
                 http://www.iso.ch/cate/d18939.html",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Jackson:1994:PCE
author: K. R. Jackson and N. S. Nedialkov
title: Precision Control and Exception Handling in Scientific Computing
type: Technical Report
institution: Department of Computer Science, University of Toronto
address: Toronto, ON, Canada
pages: 8
year: 1994
bibdate: Tue May 22 15:45:43 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.05.22 15:45:43 ???
acknowledgement: ack-nhfb
rawauthor: K. R. Jackson and N. S. Nedialkov
rawtitle: Precision Control and Exception Handling in Scientific Computing
URL:
http://www.cs.toronto.edu/NA/reports.html#prec.except; http://www.cs.toronto.edu/pub/reports/na/prec.except.ps.Z

abstract:
This paper describes convenient language facilities for precision control and exception handling. Nedialkov has developed a variable-precision and exception handling library, SciLib, implemented as a numerical class library in C++. A new scalar data type, em real, is introduced, consisting of variable-precision floating-point numbers. Arithmetic, relational, and input and output operators of the language are overloaded for reals, so that mathematical expressions can be written without explicit function calls. Precision of computations can be changed during program execution. The exception handling mechanism treats only numerical exceptions and does not distinguish between different types of exceptions.par The proposed precision control and exception handling facilities are illustrated by sample SciLib programs.

rawabstract:
This paper describes convenient language facilities for precision control and exception handling. Nedialkov has developed a variable-precision and exception handling library, SciLib, implemented as a numerical class library in C++. A new scalar data type, {\em real}, is introduced, consisting of variable-precision floating-point numbers. Arithmetic, relational, and input and output operators of the language are overloaded for reals, so that mathematical expressions can be written without explicit function calls. Precision of computations can be changed during program execution. The exception handling mechanism treats only numerical exceptions and does not distinguish between different types of exceptions.\par The proposed precision control and exception handling facilities are illustrated by sample SciLib programs.

entry:
@TechReport{Jackson:1994:PCE,
  author =       "K. R. Jackson and N. S. Nedialkov",
  title =        "Precision Control and Exception Handling in Scientific
                 Computing",
  type =         "Technical Report",
  institution =  "Department of Computer Science, University of
                 Toronto",
  address =      "Toronto, ON, Canada",
  pages =        "8",
  year =         "1994",
  bibdate =      "Tue May 22 15:45:43 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.toronto.edu/NA/reports.html#prec.except;
                 http://www.cs.toronto.edu/pub/reports/na/prec.except.ps.Z",
  abstract =     "This paper describes convenient language facilities
                 for precision control and exception handling. Nedialkov
                 has developed a variable-precision and exception
                 handling library, SciLib, implemented as a numerical
                 class library in C++. A new scalar data type, {\em
                 real}, is introduced, consisting of variable-precision
                 floating-point numbers. Arithmetic, relational, and
                 input and output operators of the language are
                 overloaded for reals, so that mathematical expressions
                 can be written without explicit function calls.
                 Precision of computations can be changed during program
                 execution. The exception handling mechanism treats only
                 numerical exceptions and does not distinguish between
                 different types of exceptions.\par

                 The proposed precision control and exception handling
                 facilities are illustrated by sample SciLib programs.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jain:1994:SRR
author: V. K. Jain and Lei Lin
title: Square-root, reciprocal, sine / cosine, arctangent cell for signal and image processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II/521--II/524
year: 1994
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: V. K. Jain and Lei Lin
rawtitle: Square-root, reciprocal, sine\slash cosine, arctangent cell for signal and image processing
booktitle:
IEEE International Conference on Acoustics, Speech, and Signal Processing: ICASSP-94, 19--22 April 1994

rawbooktitle:
{IEEE} International Conference on Acoustics, Speech, and Signal Processing: {ICASSP-94, 19--22} April 1994

entry:
@InProceedings{Jain:1994:SRR,
  author =       "V. K. Jain and Lei Lin",
  booktitle =    "{IEEE} International Conference on Acoustics, Speech,
                 and Signal Processing: {ICASSP-94, 19--22} April 1994",
  title =        "Square-root, reciprocal, sine\slash cosine, arctangent
                 cell for signal and image processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II/521--II/524",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper discusses an efficient interpolation method
                 for nonlinear function generation. Based on this, a 24
                 bit VLSI cell, capable of computing the (1) square
                 root, (2) reciprocal, (3) sine/cosine, and (4)
                 arctangent functions, is presented for \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Jaromczyk:1994:CCH
author: Jerzy W. Jaromczyk and G. W. Wasilkowski
title: Computing convex hull in a floating point arithmetic
journal: j-COMP-GEOM
volume: 4
number: 5
pages: 283--292
year: 1994
ISSN: 0925-7721 (print), 1879-081X (electronic) OR 09257721 (print), 1879081X (electronic)
ISSNL: 0925-7721 OR 09257721
MRclass: 68U05
MRnumber: 95j:68159
bibdate: Fri Dec 8 08:24:07 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:07 ???
fjournal: Computational Geometry. Theory and Applications
acknowledgement: ack-nhfb
rawauthor: Jerzy W. Jaromczyk and G. W. Wasilkowski
rawtitle: Computing convex hull in a floating point arithmetic
entry:
@Article{Jaromczyk:1994:CCH,
  author =       "Jerzy W. Jaromczyk and G. W. Wasilkowski",
  title =        "Computing convex hull in a floating point arithmetic",
  journal =      j-COMP-GEOM,
  volume =       "4",
  number =       "5",
  pages =        "283--292",
  year =         "1994",
  ISSN =         "0925-7721 (print), 1879-081X (electronic)",
  ISSN-L =       "0925-7721",
  MRclass =      "68U05",
  MRnumber =     "95j:68159",
  bibdate =      "Fri Dec 8 08:24:07 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computational Geometry. Theory and Applications",
}


bibtype: article
filename: fparith.bib
label: Johnstone:1994:DAN
author: Paul Johnstone and Frederick E. Petry
title: Design and analysis of non-binary radix floating point representations
journal: j-COMPUT-ELECTR-ENG
volume: 20
number: 1
pages: 39--50
month: jan
monthnumber: 1
year: 1994
CODEN: CPEEBQ
ISSN: 0045-7906 (print), 1879-0755 (electronic) OR 00457906 (print), 18790755 (electronic)
ISSNL: 0045-7906 OR 00457906
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Computers and Electrical Engineering
acknowledgement: ack-nhfb
affiliation: Dow Jones Telerate, New Orleans, LA, USA
thesaurus: Digital arithmetic; Roundoff errors
rawauthor: Paul Johnstone and Frederick E. Petry
rawtitle: Design and analysis of non-binary radix floating point representations
abstract:
The authors examine the feasibility of higher radix floating point representations and in particular decimal based representations. Traditional analyses of such representations have assumed the format of a floating point datum to be roughly identical to that of traditional binary floating point encodings such as the IEEE P754 task group standard representations. We relax this restriction and propose a method of encoding higher radix floating point data with range, precision and storage requirements comparable to those exhibited by traditional binary representations. Results from W. M. McKeeman's (1967) maximum and average relative representational error (MRRE and ARRE) analyses, R. P. Brent's (1973) RMS error evaluation, D. W. Matula's (1970) ratio of significance space and gap functions, and W. S. Brown and P. L. Richman's (1969) exponent range estimates are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed and the behavior of such a system is contrasted with that of a comparable binary system.

keywords:
ARRE; Average relative representational error; Decimal alternative; Decimal based representations; decimal floating-point arithmetic; Exponent range estimates; Floating point datum; Gap functions; Higher radix floating point representations; MRRE; Non-binary radix floating point representations; RMS error evaluation; Significance space ratio; Storage requirements

rawabstract:
The authors examine the feasibility of higher radix floating point representations and in particular decimal based representations. Traditional analyses of such representations have assumed the format of a floating point datum to be roughly identical to that of traditional binary floating point encodings such as the IEEE P754 task group standard representations. We relax this restriction and propose a method of encoding higher radix floating point data with range, precision and storage requirements comparable to those exhibited by traditional binary representations. Results from W. M. McKeeman's (1967) maximum and average relative representational error (MRRE and ARRE) analyses, R. P. Brent's (1973) RMS error evaluation, D. W. Matula's (1970) ratio of significance space and gap functions, and W. S. Brown and P. L. Richman's (1969) exponent range estimates are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed and the behavior of such a system is contrasted with that of a comparable binary system.

entry:
@Article{Johnstone:1994:DAN,
  author =       "Paul Johnstone and Frederick E. Petry",
  title =        "Design and analysis of non-binary radix floating point
                 representations",
  journal =      j-COMPUT-ELECTR-ENG,
  volume =       "20",
  number =       "1",
  pages =        "39--50",
  month =        jan,
  year =         "1994",
  CODEN =        "CPEEBQ",
  ISSN =         "0045-7906 (print), 1879-0755 (electronic)",
  ISSN-L =       "0045-7906",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors examine the feasibility of higher radix
                 floating point representations and in particular
                 decimal based representations. Traditional analyses of
                 such representations have assumed the format of a
                 floating point datum to be roughly identical to that of
                 traditional binary floating point encodings such as the
                 IEEE P754 task group standard representations. We relax
                 this restriction and propose a method of encoding
                 higher radix floating point data with range, precision
                 and storage requirements comparable to those exhibited
                 by traditional binary representations. Results from W.
                 M. McKeeman's (1967) maximum and average relative
                 representational error (MRRE and ARRE) analyses, R. P.
                 Brent's (1973) RMS error evaluation, D. W. Matula's
                 (1970) ratio of significance space and gap functions,
                 and W. S. Brown and P. L. Richman's (1969) exponent
                 range estimates are extended to accommodate the
                 proposed representation. A decimal alternative to
                 traditional binary representations is proposed and the
                 behavior of such a system is contrasted with that of a
                 comparable binary system.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dow Jones Telerate, New Orleans, LA, USA",
  classification = "B1265 (Digital electronics); C5230 (Digital
                 arithmetic methods)",
  fjournal =     "Computers and Electrical Engineering",
  keywords =     "ARRE; Average relative representational error; Decimal
                 alternative; Decimal based representations; decimal
                 floating-point arithmetic; Exponent range estimates;
                 Floating point datum; Gap functions; Higher radix
                 floating point representations; MRRE; Non-binary radix
                 floating point representations; RMS error evaluation;
                 Significance space ratio; Storage requirements",
  thesaurus =    "Digital arithmetic; Roundoff errors",
}


bibtype: article
filename: fparith.bib
label: Kabuo:1994:ARS
title: Accurate Rounding Scheme for the Newton--Raphson Method Using Redundant Binary Representation
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 1
pages: 43--51
month: jan
monthnumber: 1
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.250608
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:53 MDT 2011
bibtimestamp: 2011.07.07 07:13:53 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250608
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nj
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Accurate Rounding Scheme for the {Newton--Raphson} Method Using Redundant Binary Representation
author:
H. Kabuo and T. Taniguchi and A. Miyoshi and H. Yamashita and M. Urano and H. Edamatsu and S. Kuninobu

rawauthor:
H. Kabuo and T. Taniguchi and A. Miyoshi and H. Yamashita and M. Urano and H. Edamatsu and S. Kuninobu

entry:
@Article{Kabuo:1994:ARS,
  author =       "H. Kabuo and T. Taniguchi and A. Miyoshi and H.
                 Yamashita and M. Urano and H. Edamatsu and S.
                 Kuninobu",
  title =        "Accurate Rounding Scheme for the {Newton--Raphson}
                 Method Using Redundant Binary Representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "1",
  pages =        "43--51",
  month =        jan,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.250608",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:53 MDT 2011",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250608",
  acknowledgement = ack-nj # "\slash " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "Proposes a new algorithm of estimation and
                 compensation of the error effect for rounding in the
                 case of implementation of division and square root
                 using the Newton--Raphson method. The authors analyze
                 the error of the hardware system to confirm the
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kalliojarvi:1994:RCW
author: K. Kalliojarvi and J. Astola
title: Required coefficient word length in floating-point and logarithmic digital filters
journal: j-IEEE-SIGNAL-PROCESS-LETT
volume: 1
number: 3
pages: 52--54
month: mar
monthnumber: 3
year: 1994
CODEN: ISPLEM
ISSN: 1070-9908 (print), 1558-2361 (electronic) OR 10709908 (print), 15582361 (electronic)
ISSNL: 1070-9908 OR 10709908
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Signal Processing Letters
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97
rawauthor: K. Kalliojarvi and J. Astola
rawtitle: Required coefficient word length in floating-point and logarithmic digital filters
entry:
@Article{Kalliojarvi:1994:RCW,
  author =       "K. Kalliojarvi and J. Astola",
  title =        "Required coefficient word length in floating-point and
                 logarithmic digital filters",
  journal =      j-IEEE-SIGNAL-PROCESS-LETT,
  volume =       "1",
  number =       "3",
  pages =        "52--54",
  month =        mar,
  year =         "1994",
  CODEN =        "ISPLEM",
  ISSN =         "1070-9908 (print), 1558-2361 (electronic)",
  ISSN-L =       "1070-9908",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Signal Processing Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97",
  summary =      "The effects of coefficient quantization to the
                 response of a digital filter are studied. Easy-to-use
                 expressions for the required coefficient word length,
                 with which the filter response deviations are within
                 specified bounds, are derived for filters \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Kambi:1994:EAD
author: Shivaprakash Jayadev Kambi
title: Error analysis of digital filters realized with floating-point arithmetic
type: Thesis (M.S.)
school: Mississippi State University. Department of Electrical and Computer Engineering
address: Mississippi State, MS 39762, USA
pages: viii + 82
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Shivaprakash Jayadev Kambi
rawtitle: Error analysis of digital filters realized with floating-point arithmetic
keywords:
Digital filters (Mathematics); Electric filters, Digital.; Floating-point arithmetic.; Mississippi State University --- Thesis --- (1994)

entry:
@MastersThesis{Kambi:1994:EAD,
  author =       "Shivaprakash Jayadev Kambi",
  title =        "Error analysis of digital filters realized with
                 floating-point arithmetic",
  type =         "Thesis ({M.S.})",
  school =       "Mississippi State University. Department of Electrical
                 and Computer Engineering",
  address =      "Mississippi State, MS 39762, USA",
  pages =        "viii + 82",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics); Electric filters,
                 Digital.; Floating-point arithmetic.; Mississippi State
                 University --- Thesis --- (1994)",
}


bibtype: inproceedings
filename: fparith.bib
label: Kanellakis:1994:FPR
author: A. Kanellakis and P. Agathoklis
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS '94, 2 June 1994
title: Floating-point roundoff noise analysis of $2$-D state-space digital filters
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 601--604
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: A. Kanellakis and P. Agathoklis
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS '94}, 2 June 1994
rawtitle: Floating-point roundoff noise analysis of {$2$-D} state-space digital filters
entry:
@InProceedings{Kanellakis:1994:FPR,
  author =       "A. Kanellakis and P. Agathoklis",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS '94}, 2 June 1994",
  title =        "Floating-point roundoff noise analysis of {$2$-D}
                 state-space digital filters",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "601--604",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "In this paper the analysis of roundoff noise in
                 floating point state-space realizations of $2$-D
                 digital filters is considered. The variance of the
                 roundoff noise at the output of a $2$-D digital filter
                 is derived. It is shown that this variance is
                 \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Karp:1994:FPA
author: Alan H. Karp and Peter Markstein and Dennis Brzezinski
pages: 601--604
day: 23
month: aug
monthnumber: 8
year: 1994
bibdate: Thu Oct 17 10:20:52 2019
bibtimestamp: 2019.10.17 10:20:52 ???
URL: http://patft.uspto.gov/netahtml/PTO/search-bool.html; https://patents.google.com/patent/US5341321A
acknowledgement: ack-nhfb
howpublished: US Patent 5,341,321
rawauthor: Alan H. Karp and Peter Markstein and Dennis Brzezinski
title:
Floating point arithmetic unit using modified Newton--Raphson technique for division and square root

note:
Patent filed 5 May 1993, granted to Hewlett-Packard Company on 23 August 1994. Patent expired 5-May-2013. See criticism in cite Zimmermann:2005:XXX.

abstract:
A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton--Raphson method. The modified form of the Newton--Raphson method is used in place of the final iteration of the conventional Newton--Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

rawabstract:
A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton--Raphson method. The modified form of the Newton--Raphson method is used in place of the final iteration of the conventional Newton--Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

rawnote:
Patent filed 5 May 1993, granted to Hewlett-Packard Company on 23 August 1994. Patent expired 5-May-2013. See criticism in \cite{Zimmermann:2005:XXX}.

rawtitle:
Floating point arithmetic unit using modified {Newton--Raphson} technique for division and square root

entry:
@Misc{Karp:1994:FPA,
  author =       "Alan H. Karp and Peter Markstein and Dennis
                 Brzezinski",
  title =        "Floating point arithmetic unit using modified
                 {Newton--Raphson} technique for division and square
                 root",
  howpublished = "US Patent 5,341,321",
  day =          "23",
  month =        aug,
  year =         "1994",
  bibdate =      "Thu Oct 17 10:20:52 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Patent filed 5 May 1993, granted to Hewlett-Packard
                 Company on 23 August 1994. Patent expired 5-May-2013.
                 See criticism in \cite{Zimmermann:2005:XXX}.",
  URL =          "http://patft.uspto.gov/netahtml/PTO/search-bool.html;
                 https://patents.google.com/patent/US5341321A",
  abstract =     "A floating point processing system which uses a
                 multiplier unit and an adder unit to perform floating
                 point division and square root operations using both a
                 conventional and a modified form of the Newton--Raphson
                 method. The modified form of the Newton--Raphson method
                 is used in place of the final iteration of the
                 conventional Newton--Raphson so as to compute high
                 precision approximated results with a substantial
                 improvement in speed. The invention computes
                 approximated results faster and simplifies hardware
                 requirements because no multiplications of numbers of
                 the precision of the result are required.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Katti:1994:CDC
author: R. Katti
title: Comments on ``Decomposition of Complex Multipliers Using Polynomial Encoding''
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 3
pages: 381--383
month: mar
monthnumber: 3
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.272441
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:54 MDT 2011
bibtimestamp: 2011.07.07 07:13:54 MDT
note: See cite Skavantzos:1992:DCM.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272441
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Katti
rawnote: See \cite{Skavantzos:1992:DCM}.
rawtitle: Comments on {``Decomposition of Complex Multipliers Using Polynomial Encoding''}
entry:
@Article{Katti:1994:CDC,
  author =       "R. Katti",
  title =        "Comments on {``Decomposition of Complex Multipliers
                 Using Polynomial Encoding''}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "3",
  pages =        "381--383",
  month =        mar,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.272441",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:54 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  note =         "See \cite{Skavantzos:1992:DCM}.",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272441",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kawahito:1994:HSA
author: S. Kawahito and M. Ishida and T. Nakamura and M. Kameyama and T. Higuchi
title: High-speed area-efficient multiplier design using multiple-valued current-mode circuits
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 1
pages: 34--42
month: jan
monthnumber: 1
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.250607
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:53 MDT 2011
bibtimestamp: 2011.07.07 07:13:53 MDT
note: See comments cite Parhami:1996:CHS.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250607
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Kawahito and M. Ishida and T. Nakamura and M. Kameyama and T. Higuchi
rawnote: See comments \cite{Parhami:1996:CHS}.
rawtitle: High-speed area-efficient multiplier design using multiple-valued current-mode circuits
entry:
@Article{Kawahito:1994:HSA,
  author =       "S. Kawahito and M. Ishida and T. Nakamura and M.
                 Kameyama and T. Higuchi",
  title =        "High-speed area-efficient multiplier design using
                 multiple-valued current-mode circuits",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "1",
  pages =        "34--42",
  month =        jan,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.250607",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:53 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  note =         "See comments \cite{Parhami:1996:CHS}.",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=250607",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kim:1994:FPF
author: Seehyun Kim and Wonyong Sung
title: A Floating-Point to Fixed-Point Assembly Program Translator for the TMS 320C25
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 41
number: 11
pages: 730--739
month: nov
monthnumber: 11
year: 1994
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.331543
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: Seehyun Kim and Wonyong Sung
rawtitle: A Floating-Point to Fixed-Point Assembly Program Translator for the {TMS} {320C25}
entry:
@Article{Kim:1994:FPF,
  author =       "Seehyun Kim and Wonyong Sung",
  title =        "A Floating-Point to Fixed-Point Assembly Program
                 Translator for the {TMS} {320C25}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "41",
  number =       "11",
  pages =        "730--739",
  month =        nov,
  year =         "1994",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.331543",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "A floating-point digital signal processor-like
                 programming environment is developed for the Texas
                 Instruments TMS 320C25, a fixed-point digital signal
                 professor. Programmers first develop an assembly
                 program using a hypothetical floating-point instrument
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kobbelt:1994:FDP
author: L. Kobbelt
title: A Fast Dot-Product Algorithm with Minimal Rounding Errors
journal: j-COMPUTING
volume: 52
number: 4
pages: 355--369
year: 1994
CODEN: CMPTA2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 68Q20 (68Q25)
MRnumber: 1 287 970
bibdate: Tue Oct 12 16:33:42 MDT 1999
bibtimestamp: 1999.10.12 16:33:42 MDT
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-nhfb
affiliation: Inst. fur Betriebs-und Dialogsyst., Karlsruhe University, Germany
journalURL: http://link.springer.com/journal/607
journalabr: Comput Vienna New York
rawauthor: L. Kobbelt
rawtitle: A Fast Dot-Product Algorithm with Minimal Rounding Errors
bibsource:
Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database; OCLC Contents1st database

abstract:
Presents a new algorithm which computes dot-products of arbitrary length with minimal rounding errors, independent of the number of addends. The algorithm has an O(n) time and O(1) memory complexity, and does not need extensions of the arithmetic kernel, i.e., the usual floating-point operations. A slight modification yields an algorithm which computes the dot-product in machine precision. Due to its simplicity, the algorithm can easily be implemented in hardware.

keywords:
Addends; Algorithms; Arbitrary length; Arithmetic kernel; Computational complexity; Computer arithmetic; Computer hardware; Digital arithmetic; Dot product computation; Errors; Exact computer arithmetic; Fast dot-product algorithm; Floating-point operations; Hardware implementation; Machine precision; Matrix algebra; Matrix multiplications; Memory complexity; Minimal rounding errors; Numerical algorithms; Numerical methods; Stability; Summation; Time complexity

thesaurus:
Computational complexity; Digital arithmetic; Matrix algebra; Numerical analysis; Roundoff errors; Vectors

rawabstract:
Presents a new algorithm which computes dot-products of arbitrary length with minimal rounding errors, independent of the number of addends. The algorithm has an O(n) time and O(1) memory complexity, and does not need extensions of the arithmetic kernel, i.e., the usual floating-point operations. A slight modification yields an algorithm which computes the dot-product in machine precision. Due to its simplicity, the algorithm can easily be implemented in hardware.

entry:
@Article{Kobbelt:1994:FDP,
  author =       "L. Kobbelt",
  title =        "A Fast Dot-Product Algorithm with Minimal Rounding
                 Errors",
  journal =      j-COMPUTING,
  volume =       "52",
  number =       "4",
  pages =        "355--369",
  year =         "1994",
  CODEN =        "CMPTA2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "68Q20 (68Q25)",
  MRnumber =     "1 287 970",
  bibdate =      "Tue Oct 12 16:33:42 MDT 1999",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database; OCLC Contents1st database",
  abstract =     "Presents a new algorithm which computes dot-products
                 of arbitrary length with minimal rounding errors,
                 independent of the number of addends. The algorithm has
                 an O(n) time and O(1) memory complexity, and does not
                 need extensions of the arithmetic kernel, i.e., the
                 usual floating-point operations. A slight modification
                 yields an algorithm which computes the dot-product in
                 machine precision. Due to its simplicity, the algorithm
                 can easily be implemented in hardware.",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst. f{\"u}r Betriebs-und Dialogsyst., Karlsruhe
                 University, Germany",
  classification = "721.1; 722.4; 921.1; 921.6; C4140 (Linear algebra);
                 C4240 (Programming and algorithm theory); C5230
                 (Digital arithmetic methods)",
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  journalabr =   "Comput Vienna New York",
  keywords =     "Addends; Algorithms; Arbitrary length; Arithmetic
                 kernel; Computational complexity; Computer arithmetic;
                 Computer hardware; Digital arithmetic; Dot product
                 computation; Errors; Exact computer arithmetic; Fast
                 dot-product algorithm; Floating-point operations;
                 Hardware implementation; Machine precision; Matrix
                 algebra; Matrix multiplications; Memory complexity;
                 Minimal rounding errors; Numerical algorithms;
                 Numerical methods; Stability; Summation; Time
                 complexity",
  pubcountry =   "Austria",
  thesaurus =    "Computational complexity; Digital arithmetic; Matrix
                 algebra; Numerical analysis; Roundoff errors; Vectors",
}


bibtype: article
filename: fparith.bib
label: Kornerup:1994:SLA
author: P. Kornerup
title: A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 892--898
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295851
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295851
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Kornerup
rawtitle: A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
entry:
@Article{Kornerup:1994:SLA,
  author =       "P. Kornerup",
  title =        "A Systolic, Linear-Array Multiplier for a Class of
                 Right-Shift Algorithms",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "892--898",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295851",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295851",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Krandick:1994:EMF
author: W. Krandick and J. R. Johnson
title: Efficient multiprecision floating point multiplication with exact rounding
crossref: Calmet:1994:RWC
pages: 207--??
year: 1994
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Res. Inst. for Symbolic Comput., Johannes Kepler University, Linz, Austria
thesaurus: Digital arithmetic; Mathematics computing
rawauthor: W. Krandick and J. R. Johnson
rawtitle: Efficient multiprecision floating point multiplication with exact rounding
abstract:
An algorithm is described for multiplying multiprecision floating point numbers. The returned result is equal to the floating point number obtained by rounding the exact product. Software implementations of multiprecision floating point multiplication can reduce the computing time by a factor of two if they do not compute the low order digits of the product of the two mantissas. However, these algorithms do not necessarily provide exactly rounded results. The algorithm described in this paper is guaranteed to produce exactly rounded results and typically obtains the same savings. The method can be modified to take advantage of Karatsuba's algorithm for fast integer multiplication.

keywords:
Exact rounding; Fast integer multiplication; Karatsuba's algorithm; Multiprecision floating point multiplication; Software implementations

rawabstract:
An algorithm is described for multiplying multiprecision floating point numbers. The returned result is equal to the floating point number obtained by rounding the exact product. Software implementations of multiprecision floating point multiplication can reduce the computing time by a factor of two if they do not compute the low order digits of the product of the two mantissas. However, these algorithms do not necessarily provide exactly rounded results. The algorithm described in this paper is guaranteed to produce exactly rounded results and typically obtains the same savings. The method can be modified to take advantage of Karatsuba's algorithm for fast integer multiplication.

entry:
@InProceedings{Krandick:1994:EMF,
  author =       "W. Krandick and J. R. Johnson",
  title =        "Efficient multiprecision floating point multiplication
                 with exact rounding",
  crossref =     "Calmet:1994:RWC",
  pages =        "207--??",
  year =         "1994",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An algorithm is described for multiplying
                 multiprecision floating point numbers. The returned
                 result is equal to the floating point number obtained
                 by rounding the exact product. Software implementations
                 of multiprecision floating point multiplication can
                 reduce the computing time by a factor of two if they do
                 not compute the low order digits of the product of the
                 two mantissas. However, these algorithms do not
                 necessarily provide exactly rounded results. The
                 algorithm described in this paper is guaranteed to
                 produce exactly rounded results and typically obtains
                 the same savings. The method can be modified to take
                 advantage of Karatsuba's algorithm for fast integer
                 multiplication.",
  acknowledgement = ack-nhfb,
  affiliation =  "Res. Inst. for Symbolic Comput., Johannes Kepler
                 University, Linz, Austria",
  classification = "C5230 (Digital arithmetic methods); C7310
                 (Mathematics computing)",
  keywords =     "Exact rounding; Fast integer multiplication;
                 Karatsuba's algorithm; Multiprecision floating point
                 multiplication; Software implementations",
  thesaurus =    "Digital arithmetic; Mathematics computing",
}


bibtype: article
filename: fparith.bib
label: Laakso:1994:BFP
author: T. I. Laakso and L. B. Jackson
title: Bounds for Floating-Point Roundoff Noise
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 41
number: 6
pages: 424--426
month: jun
monthnumber: 6
year: 1994
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.300204
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: T. I. Laakso and L. B. Jackson
rawtitle: Bounds for Floating-Point Roundoff Noise
entry:
@Article{Laakso:1994:BFP,
  author =       "T. I. Laakso and L. B. Jackson",
  title =        "Bounds for Floating-Point Roundoff Noise",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "41",
  number =       "6",
  pages =        "424--426",
  month =        jun,
  year =         "1994",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.300204",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "The dummy multiplier model and the conventional
                 estimates for roundoff noise variance in floating-point
                 implementations are compared. Common upper and lower
                 bounds for the noise estimates are derived and
                 experimental results are presented. Although \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Laakso:1994:ELC
author: T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 41
number: 4
pages: 308--313
month: apr
monthnumber: 4
year: 1994
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.285707
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo
title:
Elimination of limit cycles in floating-point implementations of direct-form recursive digital filters

rawtitle:
Elimination of limit cycles in floating-point implementations of direct-form recursive digital filters

entry:
@Article{Laakso:1994:ELC,
  author =       "T. Laakso and B. Zeng and I. Hartimo and Y. Neuvo",
  title =        "Elimination of limit cycles in floating-point
                 implementations of direct-form recursive digital
                 filters",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "41",
  number =       "4",
  pages =        "308--313",
  month =        apr,
  year =         "1994",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.285707",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "This paper focuses on the limit cycle analysis of
                 floating-point implementations of direct form recursive
                 digital filters. A sufficient criterion for the absence
                 of zero-input limit cycles is derived for a direct-form
                 implementation with a single \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ledoux:1994:TOW
author: C. Ledoux and J. F. Grandin
title: Two original weight pruning methods based on statistical tests and rounding techniques
journal: Vision, Image and Signal Processing, IEE Proceedings-
volume: 141
number: 4
pages: 230--237
month: aug
monthnumber: 8
year: 1994
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
acknowledgement: ack-nhfb
rawauthor: C. Ledoux and J. F. Grandin
rawtitle: Two original weight pruning methods based on statistical tests and rounding techniques
entry:
@Article{Ledoux:1994:TOW,
  author =       "C. Ledoux and J. F. Grandin",
  title =        "Two original weight pruning methods based on
                 statistical tests and rounding techniques",
  journal =      "Vision, Image and Signal Processing, IEE
                 Proceedings-",
  volume =       "141",
  number =       "4",
  pages =        "230--237",
  month =        aug,
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors focus on the use of neural networks to
                 approximate continuous decision functions. In this
                 context, the parameters to be estimated are the
                 synaptic weights of the network. The number of such
                 parameters and the quantity of data \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Lewis:1994:IMF
author: D. M. Lewis
title: Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 974--982
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295859
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:57 MDT 2011
bibtimestamp: 2011.07.07 07:13:57 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295859
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Toronto University, Ont., Canada
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. M. Lewis
rawtitle: Interleaved Memory Function Interpolators with Application to an Accurate {LNS} Arithmetic Unit
abstract:
This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units.

keywords:
32 Bit; 91 Kbit; Accuracy requirements; Accurate logarithmic number system (LNS) arithmetic unit; Floating point; Interleaved memory function interpolators; Polynomial interpolation; ROM; Round to nearest; Storage requirements

thesaurus:
Approximation theory; Digital arithmetic; Error analysis; Interpolation; Polynomials; Read-only storage

rawabstract:
This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units.

entry:
@Article{Lewis:1994:IMF,
  author =       "D. M. Lewis",
  title =        "Interleaved Memory Function Interpolators with
                 Application to an Accurate {LNS} Arithmetic Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "974--982",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295859",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=295859",
  abstract =     "This paper describes a new method for polynomial
                 interpolation in hardware, with advantages demonstrated
                 by its application to an accurate logarithmic number
                 system (LNS) arithmetic unit. The use of an interleaved
                 memory reduces storage requirements by allowing each
                 stored function value to be used in interpolation
                 across several segments. This strategy can be shown to
                 always use fewer words of memory than an optimized
                 polynomial with stored polynomial coefficients.
                 Interleaved memory function interpolators are then
                 applied to the specific goal of an accurate logarithmic
                 number system arithmetic unit. Many accuracy
                 requirements for the LNS arithmetic unit are possible.
                 Although a round to nearest would be desirable, it
                 cannot be easily achieved. The goal suggested is to
                 insure that the worst case LNS relative error is
                 smaller than the worst case floating point (FP)
                 relative error. Using the interleaved memory
                 interpolator, the detailed design of an LNS arithmetic
                 unit is performed using a second order polynomial
                 interpolator including approximately 91K bits of ROM.
                 This arithmetic unit has better accuracy and less
                 complexity than previous LNS units.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Toronto
                 University, Ont., Canada",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C4110 (Error analysis in numerical methods); C4130
                 (Interpolation and function approximation); C5230
                 (Digital arithmetic methods); C5320G (Semiconductor
                 storage)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "32 Bit; 91 Kbit; Accuracy requirements; Accurate
                 logarithmic number system (LNS) arithmetic unit;
                 Floating point; Interleaved memory function
                 interpolators; Polynomial interpolation; ROM; Round to
                 nearest; Storage requirements",
  numericalindex = "Word length 3.2E+01 bit; Storage capacity 9.3E+04
                 bit",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  summary =      "This paper describes a new method for polynomial
                 interpolation in hardware, with advantages demonstrated
                 by its application to an accurate logarithmic number
                 system (LNS) arithmetic unit. The use of an interleaved
                 memory reduces storage requirements \ldots{}",
  thesaurus =    "Approximation theory; Digital arithmetic; Error
                 analysis; Interpolation; Polynomials; Read-only
                 storage",
}


bibtype: article
filename: fparith.bib
label: Lo:1994:RFP
author: Jien-Chung Lo
title: Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 4
pages: 400--412
month: apr
monthnumber: 4
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.278479
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:55 MDT 2011
bibtimestamp: 2011.07.07 07:13:55 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=278479
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., Rhode Island University, Kingston, RI, USA
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Error correction codes; Redundancy
rawauthor: Jien-Chung Lo
rawtitle: Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
abstract:
Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers.

keywords:
Berger check prediction; Berger encoded; Computer arithmetic; Concurrent error detection; Error-coded operands; Floating-point arithmetic; Hardware redundancy; High-density VLSI; Low-cost residue codes; Redundancy ratios; Reliable floating-point multiplication; Residue encoded; Soft-errors; Standard IEEE floating-point numbers

rawabstract:
Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8\% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40\% of hardware redundancy for single precision numbers and about 16\% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45\% for single precision numbers and about 36\% for double precision numbers.

entry:
@Article{Lo:1994:RFP,
  author =       "Jien-Chung Lo",
  title =        "Reliable Floating-Point Arithmetic Algorithms for
                 Error-Coded Operands",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "4",
  pages =        "400--412",
  month =        apr,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.278479",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=278479",
  abstract =     "Reliable floating-point arithmetic is vital for
                 dependable computing systems. It is also important for
                 future high-density VLSI realizations that are
                 vulnerable to soft-errors. However, the direct checking
                 of floating-point arithmetic is still an open problem.
                 The author presents a set of reliable floating-point
                 arithmetic algorithms for low-cost residue encoded and
                 Berger encoded operands, respectively. Closed form
                 equations are derived for floating-point addition,
                 subtraction, multiplication, and division. Given the
                 standard IEEE floating-point numbers, the proposed
                 reliable floating-point multiplication algorithms for
                 low-cost residue encoded operands are extremely
                 low-cost: it requires less than 8\% of hardware
                 redundancy in all cases. For reliable floating-point
                 addition and subtraction, the author finds the hardware
                 redundancy ratios of applying low-cost residue code is
                 about the same as that of applying Berger code: less
                 than 40\% of hardware redundancy for single precision
                 numbers and about 16\% for double precision numbers.
                 For reliable floating-point division, Berger encoded
                 operands yields hardware cost-effectiveness: about 45\%
                 for single precision numbers and about 36\% for double
                 precision numbers.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng., Rhode Island University,
                 Kingston, RI, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Berger check prediction; Berger encoded; Computer
                 arithmetic; Concurrent error detection; Error-coded
                 operands; Floating-point arithmetic; Hardware
                 redundancy; High-density VLSI; Low-cost residue codes;
                 Redundancy ratios; Reliable floating-point
                 multiplication; Residue encoded; Soft-errors; Standard
                 IEEE floating-point numbers",
  summary =      "Reliable floating-point arithmetic is vital for
                 dependable computing systems. It is also important for
                 future high-density VLSI realizations that are
                 vulnerable to soft-errors. However, the direct checking
                 of floating-point arithmetic is still an open
                 \ldots{}",
  thesaurus =    "Digital arithmetic; Error correction codes;
                 Redundancy",
}


bibtype: book
filename: fparith.bib
label: May:1994:PAS
editor: Cathy May and Ed Silha and Rick Simpson and Hank Warren
title: The PowerPC Architecture: a Specification for a New Family of RISC Processors
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
edition: Second
pages: xxxi + 518
year: 1994
ISBN: 1-55860-316-6 OR 1558603166
ISBN13: 978-1-55860-316-5 OR 9781558603165
LCCN: QA76.8.P67 P68 1994
bibdate: Sat Feb 24 10:55:16 2001
bibtimestamp: 2001.02.24 10:55:16 ???
acknowledgement: ack-nhfb
raweditor: Cathy May and Ed Silha and Rick Simpson and Hank Warren
rawtitle: The {PowerPC} Architecture: a Specification for a New Family of {RISC} Processors
TOC:
Book III. PowerPC Operating Environment Architecture 2. Branch Processor 3. Fixed-Point Processor 4. Storage Control 5. Interrupts 6. Timer Facilities 7. Synchronization Requirements for Special Registers and for Lookaside Buffers Appendix A. Optional Facilities and Instructions Appendix B. Assembler Extended Mnemonics Appendix C. Cross-Reference for Changed POWER Mnemonics Appendix D. New Instructions Appendix E. Implementation-Specific SPRs Appendix F. Interpretation of the DSISR as Set by an Alignment Interrupt Appendix G. PowerPC Operating Environment Instruction Set

rawTOC:
Book III. PowerPC Operating Environment Architecture \\ 2. Branch Processor \\ 3. Fixed-Point Processor \\ 4. Storage Control \\ 5. Interrupts \\ 6. Timer Facilities \\ 7. Synchronization Requirements for Special Registers and for Lookaside Buffers \\ Appendix A. Optional Facilities and Instructions \\ Appendix B. Assembler Extended Mnemonics \\ Appendix C. Cross-Reference for Changed POWER Mnemonics \\ Appendix D. New Instructions \\ Appendix E. Implementation-Specific SPRs \\ Appendix F. Interpretation of the DSISR as Set by an Alignment Interrupt \\ Appendix G. PowerPC Operating Environment Instruction Set

entry:
@Book{May:1994:PAS,
  editor =       "Cathy May and Ed Silha and Rick Simpson and Hank
                 Warren",
  title =        "The {PowerPC} Architecture: a Specification for a New
                 Family of {RISC} Processors",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxxi + 518",
  year =         "1994",
  ISBN =         "1-55860-316-6",
  ISBN-13 =      "978-1-55860-316-5",
  LCCN =         "QA76.8.P67 P68 1994",
  bibdate =      "Sat Feb 24 10:55:16 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$49.95",
  acknowledgement = ack-nhfb,
  oldlabel =     "IBM:1994:PAS",
  tableofcontents = "Book III. PowerPC Operating Environment
                 Architecture \\
                 2. Branch Processor \\
                 3. Fixed-Point Processor \\
                 4. Storage Control \\
                 5. Interrupts \\
                 6. Timer Facilities \\
                 7. Synchronization Requirements for Special Registers
                 and for Lookaside Buffers \\
                 Appendix A. Optional Facilities and Instructions \\
                 Appendix B. Assembler Extended Mnemonics \\
                 Appendix C. Cross-Reference for Changed POWER Mnemonics
                 \\
                 Appendix D. New Instructions \\
                 Appendix E. Implementation-Specific SPRs \\
                 Appendix F. Interpretation of the DSISR as Set by an
                 Alignment Interrupt \\
                 Appendix G. PowerPC Operating Environment Instruction
                 Set",
}


bibtype: article
filename: fparith.bib
label: McGrath:1994:OMC
author: Gary McGrath
title: Optimizing MC68882 Code
journal: j-DDJ
volume: 19
number: 6
pages: 58, 60, 62, 64, 66, 98--99
month: jun
monthnumber: 6
year: 1994
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 03 09:15:49 1996
bibtimestamp: 1996.09.03 09:15:49 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
affiliation: Stanford Linear Accel. Center, Stanford University, CA, USA
rawauthor: Gary McGrath
rawtitle: Optimizing {MC68882} Code
abstract:
The MC68882 floating-point coprocessor adds 46 instructions to the MC68020/030 32-bit microprocessor, substantially increasing the speed of floating-point calculations. Gary examines these instructions and finds certain combinations to be faster than others.

keywords:
32 Bit; 80 Bit; 80-Bit extended precision; ANSI-IEEE 754-1985 binary floating-point arithmetic standard; FPCP; MC68020 microprocessor; MC68030 microprocessor; MC68882 floating-point coprocessor; Optimizing MC68882 code; Parallel operation; Pipeline architecture

thesaurus:
Digital arithmetic; Microprocessor chips; Parallel processing; Pipeline processing; Satellite computers

rawabstract:
The MC68882 floating-point coprocessor adds 46 instructions to the MC68020/030 32-bit microprocessor, substantially increasing the speed of floating-point calculations. Gary examines these instructions and finds certain combinations to be faster than others.

entry:
@Article{McGrath:1994:OMC,
  author =       "Gary McGrath",
  title =        "Optimizing {MC68882} Code",
  journal =      j-DDJ,
  volume =       "19",
  number =       "6",
  pages =        "58, 60, 62, 64, 66, 98--99",
  month =        jun,
  year =         "1994",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 03 09:15:49 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "The MC68882 floating-point coprocessor adds 46
                 instructions to the MC68020/030 32-bit microprocessor,
                 substantially increasing the speed of floating-point
                 calculations. Gary examines these instructions and
                 finds certain combinations to be faster than others.",
  acknowledgement = ack-nhfb,
  affiliation =  "Stanford Linear Accel. Center, Stanford University,
                 CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel architecture);
                 C5230 (Digital arithmetic methods)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "32 Bit; 80 Bit; 80-Bit extended precision; ANSI-IEEE
                 754-1985 binary floating-point arithmetic standard;
                 FPCP; MC68020 microprocessor; MC68030 microprocessor;
                 MC68882 floating-point coprocessor; Optimizing MC68882
                 code; Parallel operation; Pipeline architecture",
  thesaurus =    "Digital arithmetic; Microprocessor chips; Parallel
                 processing; Pipeline processing; Satellite computers",
}


bibtype: article
filename: fparith.bib
label: Meek:1994:PLT
author: Brian L. Meek
title: Programming languages: towards greater commonality
journal: j-SIGPLAN
volume: 29
number: 4
pages: 49--57
month: apr
monthnumber: 4
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:49 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:16:49 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
corpsource: Comput. Centre, King's Coll., London, UK
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: G General Review
rawauthor: Brian L. Meek
rawtitle: Programming languages: towards greater commonality
keywords:
cross-language standardisation; JTC1; language independent arithmetic; language independent calling; language independent datatypes; language independent procedure calling; language independent standards; language standardisation; OSI; programming; programming guidelines; programming languages; programming languages commonality; programming languages differences; remote procedure calling; remote procedure calls; SC22; standardisation; standards; subcommittee; working group

entry:
@Article{Meek:1994:PLT,
  author =       "Brian L. Meek",
  title =        "Programming languages: towards greater commonality",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "4",
  pages =        "49--57",
  month =        apr,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:49 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C6110 (Systems analysis and programming); C6140
                 (Programming languages)",
  corpsource =   "Comput. Centre, King's Coll., London, UK",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "cross-language standardisation; JTC1; language
                 independent arithmetic; language independent calling;
                 language independent datatypes; language independent
                 procedure calling; language independent standards;
                 language standardisation; OSI; programming; programming
                 guidelines; programming languages; programming
                 languages commonality; programming languages
                 differences; remote procedure calling; remote procedure
                 calls; SC22; standardisation; standards; subcommittee;
                 working group",
  treatment =    "G General Review",
}


bibtype: inproceedings
filename: fparith.bib
label: Mehlhorn:1994:IGA
author: Kurt Mehlhorn and Stefan Naher
title: The Implementation of Geometric Algorithms
crossref: Pehrson:1994:IPP
volume: 1
pages: 223--231
year: 1994
bibdate: Tue Nov 13 21:47:31 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.13 21:47:31 ???
acknowledgement: ack-nhfb
rawauthor: Kurt Mehlhorn and Stefan Naher
rawtitle: The Implementation of Geometric Algorithms
entry:
@InProceedings{Mehlhorn:1994:IGA,
  author =       "Kurt Mehlhorn and Stefan Naher",
  title =        "The Implementation of Geometric Algorithms",
  crossref =     "Pehrson:1994:IPP",
  volume =       "1",
  pages =        "223--231",
  year =         "1994",
  bibdate =      "Tue Nov 13 21:47:31 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Montgomery:1994:SRP
author: Peter L. Montgomery
title: Square roots of products of algebraic numbers
crossref: Gautschi:1994:MCH
pages: 567--571
year: 1994
bibdate: Thu Oct 25 14:53:00 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.25 14:53:00 ???
acknowledgement: ack-nhfb
rawauthor: Peter L. Montgomery
rawtitle: Square roots of products of algebraic numbers
entry:
@InProceedings{Montgomery:1994:SRP,
  author =       "Peter L. Montgomery",
  title =        "Square roots of products of algebraic numbers",
  crossref =     "Gautschi:1994:MCH",
  pages =        "567--571",
  year =         "1994",
  bibdate =      "Thu Oct 25 14:53:00 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Montuschi:1994:DUN
author: P. Montuschi and L. Ciminiera and A. Giustina
title: Division unit with Newton--Raphson approximation and digit-by-digit refinement of the quotient
journal: j-IEE-PROC-COMPUT-DIGIT-TECH
volume: 141
number: 6
pages: 317--324
month: nov
monthnumber: 11
year: 1994
CODEN: ICDTEA
ISSN: 1350-2387 (print), 1359-7027 (electronic) OR 13502387 (print), 13597027 (electronic)
ISSNL: 1350-2387 OR 13502387
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: IEE Proceedings. Computers and Digital Techniques
acknowledgement: ack-nhfb
affiliation: Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
thesaurus: Dividing circuits; Floating point arithmetic; Newton--Raphson method
rawauthor: P. Montuschi and L. Ciminiera and A. Giustina
rawtitle: Division unit with {Newton--Raphson} approximation and digit-by-digit refinement of the quotient
abstract:
The advantages of the convergence with the square of the Newton--Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, together with one example of possible implementation. In particular, the proposed implementation achieves a speedup varying from 20% to about 30% in comparison with a previous architecture by Fandrianto, with a relatively small additional hardware cost if a multiplier is already available on the arithmetic unit.

keywords:
Convergence; Digit-by-digit refinement; Fast division; Floating point standard; Newton--Raphson approximation

rawabstract:
The advantages of the convergence with the square of the Newton--Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, together with one example of possible implementation. In particular, the proposed implementation achieves a speedup varying from 20\% to about 30\% in comparison with a previous architecture by Fandrianto, with a relatively small additional hardware cost if a multiplier is already available on the arithmetic unit.

entry:
@Article{Montuschi:1994:DUN,
  author =       "P. Montuschi and L. Ciminiera and A. Giustina",
  title =        "Division unit with {Newton--Raphson} approximation and
                 digit-by-digit refinement of the quotient",
  journal =      j-IEE-PROC-COMPUT-DIGIT-TECH,
  volume =       "141",
  number =       "6",
  pages =        "317--324",
  month =        nov,
  year =         "1994",
  CODEN =        "ICDTEA",
  ISSN =         "1350-2387 (print), 1359-7027 (electronic)",
  ISSN-L =       "1350-2387",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The advantages of the convergence with the square of
                 the Newton--Raphson method are combined with the
                 precision characteristics of digit-by-digit algorithms
                 to obtain units for fast division that satisfy the IEEE
                 754 floating point standard requirements. A general
                 design methodology that leads to a class of alternative
                 architectures providing interesting performances for
                 division is presented, together with one example of
                 possible implementation. In particular, the proposed
                 implementation achieves a speedup varying from 20\% to
                 about 30\% in comparison with a previous architecture
                 by Fandrianto, with a relatively small additional
                 hardware cost if a multiplier is already available on
                 the arithmetic unit.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dipartimento di Autom. e Inf., Politecnico di Torino,
                 Italy",
  classification = "C4130 (Interpolation and function approximation);
                 C5120 (Logic and switching circuits); C5230 (Digital
                 arithmetic methods)",
  fjournal =     "IEE Proceedings. Computers and Digital Techniques",
  keywords =     "Convergence; Digit-by-digit refinement; Fast division;
                 Floating point standard; Newton--Raphson
                 approximation",
  pubcountry =   "UK",
  thesaurus =    "Dividing circuits; Floating point arithmetic;
                 Newton--Raphson method",
}


bibtype: article
filename: fparith.bib
label: Montuschi:1994:RDO
author: P. Montuschi and L. Ciminiera
title: Radix-8 division with over-redundant digit set
journal: j-J-VLSI-SIGNAL-PROC
volume: 7
number: 3
pages: 259--270
month: may
monthnumber: 5
year: 1994
CODEN: JVSPED
DOI: https://doi.org/10.1007/BF02409402
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
affiliation: Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
thesaurus: Digital arithmetic; Dividing circuits
rawauthor: P. Montuschi and L. Ciminiera
rawtitle: Radix-8 division with over-redundant digit set
abstract:
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obtain simple digit selection rules. We show that the proposed enlarged set of values for the quotient digit does not lead to increases both in the complexity and the delay of the adder required to update the remainder, with respect to similar solutions, since the values allowed for the quotient digit have been selected carefully. The digit selection process is subdivided into two concurrent steps, each one making reference to a secondary digit set and the resulting implementation can be cheaper and faster than other units which do not use over-redundant digit sets. A performance analysis estimates a speed improvement from 25% to 35% with respect to a radix-8 architecture by Fandrianto (1987, 1989), and from 21% to 30% with respect to a radix-4 architecture with prescaling, presented by Ercegovac and Lang (1990). As required from the IEEE 754 floating point standard, the proposed algorithm features the correct remainder of the division.

keywords:
Algorithm; Delay; Digit selection rules; IEEE 754 floating point standard; Over-redundant digit set; Performance analysis; Quotient; Radix-8 divider; Radix-8 division; Remainder; Speed improvement

rawabstract:
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obtain simple digit selection rules. We show that the proposed enlarged set of values for the quotient digit does not lead to increases both in the complexity and the delay of the adder required to update the remainder, with respect to similar solutions, since the values allowed for the quotient digit have been selected carefully. The digit selection process is subdivided into two concurrent steps, each one making reference to a secondary digit set and the resulting implementation can be cheaper and faster than other units which do not use over-redundant digit sets. A performance analysis estimates a speed improvement from 25\% to 35\% with respect to a radix-8 architecture by Fandrianto (1987, 1989), and from 21\% to 30\% with respect to a radix-4 architecture with prescaling, presented by Ercegovac and Lang (1990). As required from the IEEE 754 floating point standard, the proposed algorithm features the correct remainder of the division.

entry:
@Article{Montuschi:1994:RDO,
  author =       "P. Montuschi and L. Ciminiera",
  title =        "Radix-8 division with over-redundant digit set",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "7",
  number =       "3",
  pages =        "259--270",
  month =        may,
  year =         "1994",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/BF02409402",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a radix-8 divider that uses an
                 over-redundant digit set for the quotient in order to
                 obtain simple digit selection rules. We show that the
                 proposed enlarged set of values for the quotient digit
                 does not lead to increases both in the complexity and
                 the delay of the adder required to update the
                 remainder, with respect to similar solutions, since the
                 values allowed for the quotient digit have been
                 selected carefully. The digit selection process is
                 subdivided into two concurrent steps, each one making
                 reference to a secondary digit set and the resulting
                 implementation can be cheaper and faster than other
                 units which do not use over-redundant digit sets. A
                 performance analysis estimates a speed improvement from
                 25\% to 35\% with respect to a radix-8 architecture by
                 Fandrianto (1987, 1989), and from 21\% to 30\% with
                 respect to a radix-4 architecture with prescaling,
                 presented by Ercegovac and Lang (1990). As required
                 from the IEEE 754 floating point standard, the proposed
                 algorithm features the correct remainder of the
                 division.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dipartimento di Autom. e Inf., Politecnico di Torino,
                 Italy",
  classification = "B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5230 (Digital arithmetic methods)",
  fjournal =     "Journal of VLSI Signal Processing",
  keywords =     "Algorithm; Delay; Digit selection rules; IEEE 754
                 floating point standard; Over-redundant digit set;
                 Performance analysis; Quotient; Radix-8 divider;
                 Radix-8 division; Remainder; Speed improvement",
  pubcountry =   "Netherlands",
  thesaurus =    "Digital arithmetic; Dividing circuits",
}


bibtype: article
filename: fparith.bib
label: Montuschi:1994:RDS
author: P. Montuschi and L. Ciminiera
title: Over-redundant digit sets and the design of digit-by-digit division units
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 3
pages: 269--277
month: mar
monthnumber: 3
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.272428
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:54 MDT 2011
bibtimestamp: 2011.07.07 07:13:54 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272428
fjournal: IEEE Transactions on Computers
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Montuschi and L. Ciminiera
rawtitle: Over-redundant digit sets and the design of digit-by-digit division units
entry:
@Article{Montuschi:1994:RDS,
  author =       "P. Montuschi and L. Ciminiera",
  title =        "Over-redundant digit sets and the design of
                 digit-by-digit division units",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "3",
  pages =        "269--277",
  month =        mar,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.272428",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:54 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272428",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Muller:1994:SCF
author: Jean-Michel Muller
title: Some characterizations of functions computable in on-line arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 6
pages: 752--755
month: jun
monthnumber: 6
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.286308
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:56 MDT 2011
bibtimestamp: 2011.07.07 07:13:56 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=286308
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jean-Michel Muller
rawtitle: Some characterizations of functions computable in on-line arithmetic
entry:
@Article{Muller:1994:SCF,
  author =       "Jean-Michel Muller",
  title =        "Some characterizations of functions computable in
                 on-line arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "6",
  pages =        "752--755",
  month =        jun,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.286308",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:56 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=286308",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Murofushi:1994:RBR
author: Makoto Murofushi and Hideko Nagasaka
title: The relationship between the round-off errors and Moller's algorithm in the extrapolation method
journal: j-ANN-NUM-MATH
volume: 1
number: 1--4
pages: 451--458
year: 1994
ISSN: 1021-2655 OR 10212655
ISSNL: 1021-2655 OR 10212655
MRclass: 65L05 (65L70)
MRnumber: 1340673
MRreviewer: Haydar Ak{\c{c}}a
bibdate: Sat Feb 08 09:16:09 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:16:09 ???
note: Scientific computation and differential equations (Auckland, 1993).
fjournal: Annals of Numerical Mathematics
acknowledgement: ack-nhfb
ajournal: Ann. Numer. Math.
rawauthor: Makoto Murofushi and Hideko Nagasaka
rawnote: Scientific computation and differential equations (Auckland, 1993).
rawtitle:
The relationship between the round-off errors and {M{\o}ller}'s algorithm in the extrapolation method

entry:
@Article{Murofushi:1994:RBR,
  author =       "Makoto Murofushi and Hideko Nagasaka",
  title =        "The relationship between the round-off errors and
                 {M{\o}ller}'s algorithm in the extrapolation method",
  journal =      j-ANN-NUM-MATH,
  volume =       "1",
  number =       "1--4",
  pages =        "451--458",
  year =         "1994",
  ISSN =         "1021-2655",
  ISSN-L =       "1021-2655",
  MRclass =      "65L05 (65L70)",
  MRnumber =     "1340673",
  MRreviewer =   "Haydar Ak{\c{c}}a",
  bibdate =      "Sat Feb 08 09:16:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Scientific computation and differential equations
                 (Auckland, 1993).",
  acknowledgement = ack-nhfb,
  ajournal =     "Ann. Numer. Math.",
  fjournal =     "Annals of Numerical Mathematics",
}


bibtype: inproceedings
filename: fparith.bib
label: Nakamura:1994:EPV
author: H. Nakamura and H. Imori and Y. Yamashita and K. Nakazawa and T. Boku and H. Li and I. Nakata
title: Evaluation of pseudo vector processor based on slide-windowed registers
crossref: Mudge:1994:PTS
pages: 368--377
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: Inst. of Inf. Sci. and Electron., Tsukuba University, Ibaraki, Japan
thesaurus: FORTRAN; Performance evaluation; Vector processor systems
rawauthor: H. Nakamura and H. Imori and Y. Yamashita and K. Nakazawa and T. Boku and H. Li and I. Nakata
rawtitle: Evaluation of pseudo vector processor based on slide-windowed registers
abstract:
We present a new scalar processor for high-speed vector processing and its evaluation. The proposed processor can hide long main memory access latency by introducing slide-windowed floating-point registers with data preloading feature and pipelined memory. Owing to the slide-window structure, the proposed processor can utilize more floating-point registers in keeping upward compatibility with existing scalar architecture. We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed processor drastically reduces the penalty of main memory access compared with an ordinary scalar processor. For example, the proposed processor with 96 registers hides memory access latency of 70 CPU cycles when the throughput of main memory is 8 byte/cycle. From these results, it is concluded that the proposed architecture is very suitable for high-speed vector processing.

keywords:
Data preloading feature; Floating-point registers; High-speed vector processing; Livermore Fortran Kernels; Performance; Pipelined memory; Pseudo vector processor; Scalar processor; Slide-windowed registers

rawabstract:
We present a new scalar processor for high-speed vector processing and its evaluation. The proposed processor can hide long main memory access latency by introducing slide-windowed floating-point registers with data preloading feature and pipelined memory. Owing to the slide-window structure, the proposed processor can utilize more floating-point registers in keeping upward compatibility with existing scalar architecture. We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed processor drastically reduces the penalty of main memory access compared with an ordinary scalar processor. For example, the proposed processor with 96 registers hides memory access latency of 70 CPU cycles when the throughput of main memory is 8 byte/cycle. From these results, it is concluded that the proposed architecture is very suitable for high-speed vector processing.

entry:
@InProceedings{Nakamura:1994:EPV,
  author =       "H. Nakamura and H. Imori and Y. Yamashita and K.
                 Nakazawa and T. Boku and H. Li and I. Nakata",
  title =        "Evaluation of pseudo vector processor based on
                 slide-windowed registers",
  crossref =     "Mudge:1994:PTS",
  pages =        "368--377",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a new scalar processor for high-speed
                 vector processing and its evaluation. The proposed
                 processor can hide long main memory access latency by
                 introducing slide-windowed floating-point registers
                 with data preloading feature and pipelined memory.
                 Owing to the slide-window structure, the proposed
                 processor can utilize more floating-point registers in
                 keeping upward compatibility with existing scalar
                 architecture. We have evaluated its performance on
                 Livermore Fortran Kernels. The evaluation results show
                 that the proposed processor drastically reduces the
                 penalty of main memory access compared with an ordinary
                 scalar processor. For example, the proposed processor
                 with 96 registers hides memory access latency of 70 CPU
                 cycles when the throughput of main memory is 8
                 byte/cycle. From these results, it is concluded that
                 the proposed architecture is very suitable for
                 high-speed vector processing.",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst. of Inf. Sci. and Electron., Tsukuba University,
                 Ibaraki, Japan",
  classification = "C5220P (Parallel architecture); C5440
                 (Multiprocessor systems and techniques); C5470
                 (Performance evaluation and testing)",
  keywords =     "Data preloading feature; Floating-point registers;
                 High-speed vector processing; Livermore Fortran
                 Kernels; Performance; Pipelined memory; Pseudo vector
                 processor; Scalar processor; Slide-windowed registers",
  thesaurus =    "FORTRAN; Performance evaluation; Vector processor
                 systems",
}


bibtype: article
filename: fparith.bib
label: Narayanaswami:1994:AE
author: Chandrasekhar Narayanaswami and William Luken
title: Approximating $ x^n $ efficiently
journal: j-INFO-PROC-LETT
volume: 50
number: 4
pages: 205--210
day: 25
month: may
monthnumber: 5
year: 1994
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
MRclass: 65D20 (41-04 65B99)
MRnumber: 95b:65031
bibdate: Wed Nov 11 12:16:26 MST 1998
bibtimestamp: 1998.11.11 12:16:26 MST
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
affiliation: IBM Advanced Workstations and Systems Div
affiliationaddress: Austin, TX, USA
corpsource: IBM Adv. Workstations and Syst. Div., Austin, TX, USA
journalURL: http://www.sciencedirect.com/science/journal/00200190
journalabr: Inf Process Lett
treatment: T Theoretical or Mathematical
rawauthor: Chandrasekhar Narayanaswami and William Luken
rawtitle: Approximating $ x^n $ efficiently
bibsource:
Compendex database; http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
$x^n$ approximation; approximation theory; Approximation theory; Color computer graphics; Computational complexity; Computational methods; computer graphics; elementary functions; floating-point arithmetic; Function evaluation; graphics modeling; Image quality; Light intensity computation; look-up tables; performance requirements; Polynomial evaluation; Polynomials; polynomials; power function; scientific applications; Semiconducting silicon; Table lookup

entry:
@Article{Narayanaswami:1994:AE,
  author =       "Chandrasekhar Narayanaswami and William Luken",
  title =        "Approximating $ x^n $ efficiently",
  journal =      j-INFO-PROC-LETT,
  volume =       "50",
  number =       "4",
  pages =        "205--210",
  day =          "25",
  month =        may,
  year =         "1994",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  MRclass =      "65D20 (41-04 65B99)",
  MRnumber =     "95b:65031",
  bibdate =      "Wed Nov 11 12:16:26 MST 1998",
  bibsource =    "Compendex database;
                 http://www.elsevier.com:80/inca/publications/store/5/0/5/6/1/2/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Advanced Workstations and Systems Div",
  affiliationaddress = "Austin, TX, USA",
  classification = "721.1; 723.2; 723.5; 741.2; 921.1; 921.6; B0290F
                 (Interpolation and function approximation); C4130
                 (Interpolation and function approximation); C6130B
                 (Graphics techniques)",
  corpsource =   "IBM Adv. Workstations and Syst. Div., Austin, TX,
                 USA",
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
  journalabr =   "Inf Process Lett",
  keywords =     "$x^n$ approximation; approximation theory;
                 Approximation theory; Color computer graphics;
                 Computational complexity; Computational methods;
                 computer graphics; elementary functions; floating-point
                 arithmetic; Function evaluation; graphics modeling;
                 Image quality; Light intensity computation; look-up
                 tables; performance requirements; Polynomial
                 evaluation; Polynomials; polynomials; power function;
                 scientific applications; Semiconducting silicon; Table
                 lookup",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Nedialkov:1994:PCE
author: Nedialko (Ned) Stoyanov Nedialkov
title: Precision Control and Exception Handling in Scientific Computing
type: M.Sc. Thesis
school: Department of Computer Science, University of Toronto
address: Toronto, ON, Canada
pages: 51
year: 1994
bibdate: Tue May 22 15:44:16 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.05.22 15:44:16 ???
acknowledgement: ack-nhfb
rawauthor: Nedialko (Ned) Stoyanov Nedialkov
rawtitle: Precision Control and Exception Handling in Scientific Computing
URL:
http://www.cs.toronto.edu/NA/reports.html#ned-94-msc; http://www.cs.toronto.edu/pub/reports/na/ned-94-msc.ps.Z

entry:
@MastersThesis{Nedialkov:1994:PCE,
  author =       "Nedialko (Ned) Stoyanov Nedialkov",
  title =        "Precision Control and Exception Handling in Scientific
                 Computing",
  type =         "{M.Sc.} Thesis",
  school =       "Department of Computer Science, University of
                 Toronto",
  address =      "Toronto, ON, Canada",
  pages =        "51",
  year =         "1994",
  bibdate =      "Tue May 22 15:44:16 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.toronto.edu/NA/reports.html#ned-94-msc;
                 http://www.cs.toronto.edu/pub/reports/na/ned-94-msc.ps.Z",
  acknowledgement = ack-nhfb,
}


bibtype: mastersthesis
filename: fparith.bib
label: Niescier:1994:DIC
author: Richard J. Niescier
title: Design of an IEEE compliant 32-bit floating point multiplier / accumulator
type: Thesis (M.S.)
school: Lehigh University
address: Bethlehem, PA, USA
pages: vii + 94
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.; Microprocessors.
acknowledgement: ack-nhfb
rawauthor: Richard J. Niescier
rawtitle: Design of an {IEEE} compliant 32-bit floating point multiplier\slash accumulator
entry:
@MastersThesis{Niescier:1994:DIC,
  author =       "Richard J. Niescier",
  title =        "Design of an {IEEE} compliant 32-bit floating point
                 multiplier\slash accumulator",
  type =         "Thesis ({M.S.})",
  school =       "Lehigh University",
  address =      "Bethlehem, PA, USA",
  pages =        "vii + 94",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.; Microprocessors.",
}


bibtype: mastersthesis
filename: fparith.bib
label: Novak:1994:AFP
author: Joseph Herschel Novak
title: An asynchronous floating point unit
type: Thesis (M.S.)
school: Department of Computer Science, University of Utah
address: Salt Lake City, UT, USA
pages: xi + 151
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Asynchronous circuits.; Computers --- Circuits.; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Joseph Herschel Novak
rawtitle: An asynchronous floating point unit
entry:
@MastersThesis{Novak:1994:AFP,
  author =       "Joseph Herschel Novak",
  title =        "An asynchronous floating point unit",
  type =         "Thesis ({M.S.})",
  school =       "Department of Computer Science, University of Utah",
  address =      "Salt Lake City, UT, USA",
  pages =        "xi + 151",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Asynchronous circuits.; Computers --- Circuits.;
                 Floating-point arithmetic.",
}


bibtype: techreport
filename: fparith.bib
label: Oberman:1994:DIH
author: S. Oberman and N. Quach and M. Flynn
title: The design and implementation of a high-performance floating-point divider
type: Technical Report
number: CSL-TR-94-599
institution: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: xi + 151
month: jan
monthnumber: 1
year: 1994
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
acknowledgement: ack-sfo
rawauthor: S. Oberman and N. Quach and M. Flynn
rawtitle: The design and implementation of a high-performance floating-point divider
entry:
@TechReport{Oberman:1994:DIH,
  author =       "S. Oberman and N. Quach and M. Flynn",
  title =        "The design and implementation of a high-performance
                 floating-point divider",
  type =         "Technical Report",
  number =       "CSL-TR-94-599",
  institution =  "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  month =        jan,
  year =         "1994",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:1994:IPDa
author: S. Oh and D. Garcia
title: Implementation of a parallel DFE using residue number system
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: III/237--III/240
year: 1994
DOI: https://doi.org/10.1109/ICASSP.1994.390024
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: S. Oh and D. Garcia
rawtitle: Implementation of a parallel {DFE} using residue number system
booktitle:
IEEE International Conference on Acoustics, Speech, and Signal Processing. ICASSP-94, 19--22 April 1994

rawbooktitle:
{IEEE} International Conference on Acoustics, Speech, and Signal Processing. {ICASSP-94, 19--22} April 1994

entry:
@InProceedings{Oh:1994:IPDa,
  author =       "S. Oh and D. Garcia",
  booktitle =    "{IEEE} International Conference on Acoustics, Speech,
                 and Signal Processing. {ICASSP-94, 19--22} April 1994",
  title =        "Implementation of a parallel {DFE} using residue
                 number system",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "III/237--III/240",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1994.390024",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A parallel decision feedback equalizer (DFE)
                 implementation using residue number system (RNS) is
                 considered When the DFE implementation for a system
                 requires a wide input data width and high sampling
                 rates, RNS provides a speed advantage over \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Oh:1994:IPDb
author: S. Oh and D. Garcia
title: Implementation of a parallel DFE using residue number system
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: III/237--III/240
year: 1994
DOI: https://doi.org/10.1109/ICASSP.1994.390024
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: S. Oh and D. Garcia
rawtitle: Implementation of a parallel {DFE} using residue number system
booktitle:
IEEE International Conference on Acoustics, Speech, and Signal Processing. ICASSP-94, 19--22 April 1994

rawbooktitle:
{IEEE} International Conference on Acoustics, Speech, and Signal Processing. {ICASSP-94, 19--22} April 1994

entry:
@InProceedings{Oh:1994:IPDb,
  author =       "S. Oh and D. Garcia",
  booktitle =    "{IEEE} International Conference on Acoustics, Speech,
                 and Signal Processing. {ICASSP-94, 19--22} April 1994",
  title =        "Implementation of a parallel {DFE} using residue
                 number system",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "III/237--III/240",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1994.390024",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A parallel decision feedback equalizer (DFE)
                 implementation using residue number system (RNS) is
                 considered When the DFE implementation for a system
                 requires a wide input data width and high sampling
                 rates, RNS provides a speed advantage over \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Ohta:1994:INP
author: S. Ohta and E. Goto and Weng Fai Wong and N. Yoshida
title: Improvement and new proposal on fast evaluation of elementary functions
journal: j-TRANS-INFO-PROCESSING-SOC-JAPAN
volume: 35
number: 5
pages: 926--933
month: may
monthnumber: 5
year: 1994
CODEN: JSGRD5
ISSN: 0387-5806 OR 03875806
ISSNL: 0387-5806 OR 03875806
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Transactions of the Information Processing Society of Japan
language: Japanese
acknowledgement: ack-nhfb
affiliation: RIKEN, Inst. of Phys. and Chem. Res., Saitama, Japan
thesaurus: Digital arithmetic; Function evaluation; Random number generation; Table lookup
rawauthor: S. Ohta and E. Goto and Weng Fai Wong and N. Yoshida
rawtitle: Improvement and new proposal on fast evaluation of elementary functions
abstract:
Wong, Gore, and Yoshida (ibid., vol. 34, no. 7, pp. 1570-1579, 1993) introduced fast methods for numerical evaluation of elementary functions based on table lookup. They are called ATA (add/table-lookup/add) and ATA-M (add/table-lookup/add and multiply) methods for single- and double-precision calculations respectively. In this paper, an improvement to these methods that shrinks the size of the table by a factor of about 3/16 is presented. Another method called the `split parallel multiplication method', which is characterized by simpler table lookup than ATA-M and by split and parallel use of double-precision floating point circuitry, is also introduced, These new methods fit on to integrated circuits of a size comparable with commercially available floating-point accelerators. Methods for accelerating double-precision division, generating uniform pseudo-random numbers in double-precision, and accelerating the multiplication of single-precision complex numbers using the same circuitry are proposed.

keywords:
Add/table-lookup/add method; Add/table-lookup/add/multiply method; ATA method; ATA-M method; Double-precision calculations; Double-precision division; Double-precision floating point circuitry; Elementary functions evaluation; Floating-point accelerators; Integrated circuits; Numerical evaluation; Single-precision calculations; Single-precision complex number multiplication; Split parallel multiplication method; Table size; Uniform pseudo-random number generation

rawabstract:
Wong, Gore, and Yoshida (ibid., vol. 34, no. 7, pp. 1570-1579, 1993) introduced fast methods for numerical evaluation of elementary functions based on table lookup. They are called ATA (add/table-lookup/add) and ATA-M (add/table-lookup/add and multiply) methods for single- and double-precision calculations respectively. In this paper, an improvement to these methods that shrinks the size of the table by a factor of about 3/16 is presented. Another method called the `split parallel multiplication method', which is characterized by simpler table lookup than ATA-M and by split and parallel use of double-precision floating point circuitry, is also introduced, These new methods fit on to integrated circuits of a size comparable with commercially available floating-point accelerators. Methods for accelerating double-precision division, generating uniform pseudo-random numbers in double-precision, and accelerating the multiplication of single-precision complex numbers using the same circuitry are proposed.

entry:
@Article{Ohta:1994:INP,
  author =       "S. Ohta and E. Goto and Weng Fai Wong and N. Yoshida",
  title =        "Improvement and new proposal on fast evaluation of
                 elementary functions",
  journal =      j-TRANS-INFO-PROCESSING-SOC-JAPAN,
  volume =       "35",
  number =       "5",
  pages =        "926--933",
  month =        may,
  year =         "1994",
  CODEN =        "JSGRD5",
  ISSN =         "0387-5806",
  ISSN-L =       "0387-5806",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Wong, Gore, and Yoshida (ibid., vol. 34, no. 7, pp.
                 1570-1579, 1993) introduced fast methods for numerical
                 evaluation of elementary functions based on table
                 lookup. They are called ATA (add/table-lookup/add) and
                 ATA-M (add/table-lookup/add and multiply) methods for
                 single- and double-precision calculations respectively.
                 In this paper, an improvement to these methods that
                 shrinks the size of the table by a factor of about 3/16
                 is presented. Another method called the `split parallel
                 multiplication method', which is characterized by
                 simpler table lookup than ATA-M and by split and
                 parallel use of double-precision floating point
                 circuitry, is also introduced, These new methods fit on
                 to integrated circuits of a size comparable with
                 commercially available floating-point accelerators.
                 Methods for accelerating double-precision division,
                 generating uniform pseudo-random numbers in
                 double-precision, and accelerating the multiplication
                 of single-precision complex numbers using the same
                 circuitry are proposed.",
  acknowledgement = ack-nhfb,
  affiliation =  "RIKEN, Inst. of Phys. and Chem. Res., Saitama, Japan",
  classification = "C4120 (Functional analysis); C5230 (Digital
                 arithmetic methods); C6130 (Data handling techniques)",
  fjournal =     "Transactions of the Information Processing Society of
                 Japan",
  keywords =     "Add/table-lookup/add method;
                 Add/table-lookup/add/multiply method; ATA method; ATA-M
                 method; Double-precision calculations; Double-precision
                 division; Double-precision floating point circuitry;
                 Elementary functions evaluation; Floating-point
                 accelerators; Integrated circuits; Numerical
                 evaluation; Single-precision calculations;
                 Single-precision complex number multiplication; Split
                 parallel multiplication method; Table size; Uniform
                 pseudo-random number generation",
  language =     "Japanese",
  pubcountry =   "Japan",
  thesaurus =    "Digital arithmetic; Function evaluation; Random number
                 generation; Table lookup",
}


bibtype: book
filename: fparith.bib
label: Omondi:1994:CAS
author: Amos R. Omondi
title: Computer Arithmetic Systems: Algorithms, Architecture, and Implementation
publisher: pub-PH
address: pub-PH:adr
pages: xvi + 520
year: 1994
ISBN: 0-13-334301-4 OR 0133343014
ISBN13: 978-0-13-334301-4 OR 9780133343014
LCCN: QA76.9.C62 O46 1994
bibdate: Sat Dec 09 11:57:03 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib
bibtimestamp: 1995.12.09 11:57:03 ???
acknowledgement: ack-nhfb
rawauthor: Amos R. Omondi
rawtitle: Computer Arithmetic Systems: Algorithms, Architecture, and Implementation
TOC:
Preface Preliminary notes Fixed-point number systems / 3 Fixed-point addition and subtraction / 13 Fixed-point multiplication / 119 Fixed-point division / 192 Floating-point number systems and arithmetic / 293 Basic floating-point operations: implementation / 345 Elementary functions / 371 Unconventional number systems and arithmetic / 439 Bibliography / 469 Appendix A: Pipelining / 489 Appendix B: Design of shifters / 505 Index / 514

rawTOC:
Preface \\ Preliminary notes \\ Fixed-point number systems / 3 \\ Fixed-point addition and subtraction / 13 \\ Fixed-point multiplication / 119 \\ Fixed-point division / 192 \\ Floating-point number systems and arithmetic / 293 \\ Basic floating-point operations: implementation / 345 \\ Elementary functions / 371 \\ Unconventional number systems and arithmetic / 439 \\ Bibliography / 469 \\ Appendix A: Pipelining / 489 \\ Appendix B: Design of shifters / 505 \\ Index / 514

entry:
@Book{Omondi:1994:CAS,
  author =       "Amos R. Omondi",
  title =        "Computer Arithmetic Systems: Algorithms, Architecture,
                 and Implementation",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xvi + 520",
  year =         "1994",
  ISBN =         "0-13-334301-4",
  ISBN-13 =      "978-0-13-334301-4",
  LCCN =         "QA76.9.C62 O46 1994",
  bibdate =      "Sat Dec 09 11:57:03 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  price =        "US\$40.00",
  acknowledgement = ack-nhfb,
  tableofcontents = "Preface \\
                 Preliminary notes \\
                 Fixed-point number systems / 3 \\
                 Fixed-point addition and subtraction / 13 \\
                 Fixed-point multiplication / 119 \\
                 Fixed-point division / 192 \\
                 Floating-point number systems and arithmetic / 293 \\
                 Basic floating-point operations: implementation / 345
                 \\
                 Elementary functions / 371 \\
                 Unconventional number systems and arithmetic / 439 \\
                 Bibliography / 469 \\
                 Appendix A: Pipelining / 489 \\
                 Appendix B: Design of shifters / 505 \\
                 Index / 514",
}


bibtype: article
filename: fparith.bib
label: Ooyama:1994:CSC
author: M. Ooyama and H. Hamada
journal: j-TRANS-INFO-PROCESSING-SOC-JAPAN
volume: 35
number: 8
pages: 1642--1651
month: aug
monthnumber: 8
year: 1994
CODEN: JSGRD5
ISSN: 0387-5806 OR 03875806
ISSNL: 0387-5806 OR 03875806
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: Transactions of the Information Processing Society of Japan
language: Japanese
acknowledgement: ack-nhfb
affiliation: Central Res. Lab., Hitachi Ltd., Tokyo, Japan
thesaurus: Combinatorial circuits; Digital arithmetic; Parallel processing; Pipeline processing
rawauthor: M. Ooyama and H. Hamada
title:
A circuit to separate and to connect the exponent part and the mantissa part for URR floating point arithmetic and its application to a URR processor

abstract:
To overcome overflows and underflows in computation, several new floating-point arithmetics have been proposed. But in these new arithmetics, a boundary between the exponent part and the mantissa part moves according to the exponent value and data formats are usually more complicated. So, fast separation and connection of the exponent and the mantissa is a key technology to achieve fast computation of these new arithmetics. In this paper, a circuit scheme to separate and connect the exponent and the mantissa for URR floating-point arithmetic based on double exponential cut is presented. To separate the exponent from the mantissa, this circuit scheme firstly detects the boundary and the position is encoded to a short code. Then barrel shifters, logical operation circuits, and bit pattern generators controlled by the code separate the exponent and the mantissa from URR. To form URR from the exponent and the mantissa, a number of bits of the exponent is counted and encoded to a short code. The boundary can be settled by this code, and using the same circuits controlled by the code, the exponent part and the mantissa part are generated and combined into URR. To achieve fast execution, these processes are executed by the combination logic circuits in bit parallel manner and meet to pipelined architectures. We applied this circuit scheme to an experimental 64 bits URR processor and verified its realization. Its performance was also evaluated. (11 Refs.)

keywords:
64 Bit; Barrel shifters; Bit parallel processing; Bit pattern generators; Combination logic circuits; Double exponential cut; Exponent part; Logical operation circuits; Mantissa part; Pipelined architectures; URR floating point arithmetic; URR processor

rawabstract:
To overcome overflows and underflows in computation, several new floating-point arithmetics have been proposed. But in these new arithmetics, a boundary between the exponent part and the mantissa part moves according to the exponent value and data formats are usually more complicated. So, fast separation and connection of the exponent and the mantissa is a key technology to achieve fast computation of these new arithmetics. In this paper, a circuit scheme to separate and connect the exponent and the mantissa for URR floating-point arithmetic based on double exponential cut is presented. To separate the exponent from the mantissa, this circuit scheme firstly detects the boundary and the position is encoded to a short code. Then barrel shifters, logical operation circuits, and bit pattern generators controlled by the code separate the exponent and the mantissa from URR. To form URR from the exponent and the mantissa, a number of bits of the exponent is counted and encoded to a short code. The boundary can be settled by this code, and using the same circuits controlled by the code, the exponent part and the mantissa part are generated and combined into URR. To achieve fast execution, these processes are executed by the combination logic circuits in bit parallel manner and meet to pipelined architectures. We applied this circuit scheme to an experimental 64 bits URR processor and verified its realization. Its performance was also evaluated. (11 Refs.)

rawtitle:
A circuit to separate and to connect the exponent part and the mantissa part for {URR} floating point arithmetic and its application to a {URR} processor

entry:
@Article{Ooyama:1994:CSC,
  author =       "M. Ooyama and H. Hamada",
  title =        "A circuit to separate and to connect the exponent part
                 and the mantissa part for {URR} floating point
                 arithmetic and its application to a {URR} processor",
  journal =      j-TRANS-INFO-PROCESSING-SOC-JAPAN,
  volume =       "35",
  number =       "8",
  pages =        "1642--1651",
  month =        aug,
  year =         "1994",
  CODEN =        "JSGRD5",
  ISSN =         "0387-5806",
  ISSN-L =       "0387-5806",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "To overcome overflows and underflows in computation,
                 several new floating-point arithmetics have been
                 proposed. But in these new arithmetics, a boundary
                 between the exponent part and the mantissa part moves
                 according to the exponent value and data formats are
                 usually more complicated. So, fast separation and
                 connection of the exponent and the mantissa is a key
                 technology to achieve fast computation of these new
                 arithmetics. In this paper, a circuit scheme to
                 separate and connect the exponent and the mantissa for
                 URR floating-point arithmetic based on double
                 exponential cut is presented. To separate the exponent
                 from the mantissa, this circuit scheme firstly detects
                 the boundary and the position is encoded to a short
                 code. Then barrel shifters, logical operation circuits,
                 and bit pattern generators controlled by the code
                 separate the exponent and the mantissa from URR. To
                 form URR from the exponent and the mantissa, a number
                 of bits of the exponent is counted and encoded to a
                 short code. The boundary can be settled by this code,
                 and using the same circuits controlled by the code, the
                 exponent part and the mantissa part are generated and
                 combined into URR. To achieve fast execution, these
                 processes are executed by the combination logic
                 circuits in bit parallel manner and meet to pipelined
                 architectures. We applied this circuit scheme to an
                 experimental 64 bits URR processor and verified its
                 realization. Its performance was also evaluated. (11
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Central Res. Lab., Hitachi Ltd., Tokyo, Japan",
  classification = "B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5220P (Parallel architecture); C5230
                 (Digital arithmetic methods)",
  fjournal =     "Transactions of the Information Processing Society of
                 Japan",
  keywords =     "64 Bit; Barrel shifters; Bit parallel processing; Bit
                 pattern generators; Combination logic circuits; Double
                 exponential cut; Exponent part; Logical operation
                 circuits; Mantissa part; Pipelined architectures; URR
                 floating point arithmetic; URR processor",
  language =     "Japanese",
  numericalindex = "Word length 6.4E+01 bit",
  pubcountry =   "Japan",
  thesaurus =    "Combinatorial circuits; Digital arithmetic; Parallel
                 processing; Pipeline processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:1994:SDMa
author: V. Paliouras and T. Stouraitis
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Systematic design of multi-modulus / multi-function Residue Number System processors
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 79--82
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.409201
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Systematic design of multi-modulus\slash multi-function {Residue Number System} processors
entry:
@InProceedings{Paliouras:1994:SDMa,
  author =       "V. Paliouras and T. Stouraitis",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Systematic design of multi-modulus\slash
                 multi-function {Residue Number System} processors",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "79--82",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.409201",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A methodology for the design of novel Residue Number
                 System (RNS) processors is presented. It results in
                 ROM-less processors, which perform basic residue
                 arithmetic algorithms in more than one moduli channel,
                 either serially or concurrently. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:1994:SDMb
author: V. Paliouras and T. Stouraitis
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Systematic design of multi-modulus / multi-function Residue Number System processors
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 79--82
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.409201
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and T. Stouraitis
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Systematic design of multi-modulus\slash multi-function {Residue Number System} processors
entry:
@InProceedings{Paliouras:1994:SDMb,
  author =       "V. Paliouras and T. Stouraitis",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Systematic design of multi-modulus\slash
                 multi-function {Residue Number System} processors",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "79--82",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.409201",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A methodology for the design of novel Residue Number
                 System (RNS) processors is presented. It results in
                 ROM-less processors, which perform basic residue
                 arithmetic algorithms in more than one moduli channel,
                 either serially or concurrently. \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parhami:1994:OTLa
author: B. Parhami and C. Y. Hung
booktitle: Workshop on VLSI Signal Processing, VII, 1994
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 470--481
year: 1994
DOI: https://doi.org/10.1109/VLSISP.1994.574771
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: B. Parhami and C. Y. Hung
rawbooktitle: Workshop on {VLSI} Signal Processing, {VII, 1994}
title:
Optimal table lookup schemes for VLSI implementation of input / output conversions and other residue number operations

rawtitle:
Optimal table lookup schemes for {VLSI} implementation of input\slash output conversions and other residue number operations

entry:
@InProceedings{Parhami:1994:OTLa,
  author =       "B. Parhami and C. Y. Hung",
  booktitle =    "Workshop on {VLSI} Signal Processing, {VII, 1994}",
  title =        "Optimal table lookup schemes for {VLSI} implementation
                 of input\slash output conversions and other residue
                 number operations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "470--481",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VLSISP.1994.574771",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue number representation has become a viable
                 alternative for fast, area-efficient VLSI realization
                 of high-performance signal processing hardware. Wider
                 applicability and improved cost/performance of
                 residue-based VLSI implementations of signal \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parhami:1994:OTLb
author: B. Parhami and C. Y. Hung
booktitle: Workshop on VLSI Signal Processing, VII, 1994
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 470--481
year: 1994
DOI: https://doi.org/10.1109/VLSISP.1994.574771
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: B. Parhami and C. Y. Hung
rawbooktitle: Workshop on {VLSI} Signal Processing, {VII, 1994}
title:
Optimal table lookup schemes for VLSI implementation of input / output conversions and other residue number operations

rawtitle:
Optimal table lookup schemes for {VLSI} implementation of input\slash output conversions and other residue number operations

entry:
@InProceedings{Parhami:1994:OTLb,
  author =       "B. Parhami and C. Y. Hung",
  booktitle =    "Workshop on {VLSI} Signal Processing, {VII, 1994}",
  title =        "Optimal table lookup schemes for {VLSI} implementation
                 of input\slash output conversions and other residue
                 number operations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "470--481",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VLSISP.1994.574771",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Residue number representation has become a viable
                 alternative for fast, area-efficient VLSI realization
                 of high-performance signal processing hardware. Wider
                 applicability and improved cost/performance of
                 residue-based VLSI implementations of signal \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parker:1994:FTLa
author: M. G. Parker and M. Benaissa
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Fault-tolerant linear convolution using residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 441--444
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.408997
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. G. Parker and M. Benaissa
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Fault-tolerant linear convolution using residue number systems
entry:
@InProceedings{Parker:1994:FTLa,
  author =       "M. G. Parker and M. Benaissa",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Fault-tolerant linear convolution using residue number
                 systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "441--444",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.408997",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper proposes a fault-tolerant linear
                 convolution architecture using Residue Number Systems
                 (RNS) and Polynomial Residue Number Systems (PRNS). The
                 RNS and PRNS are both given error-detection capability
                 by the addition of redundant residue \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Parker:1994:FTLb
author: M. G. Parker and M. Benaissa
booktitle: IEEE International Symposium on Circuits and Systems, ISCAS '94, 2 June 1994
title: Fault-tolerant linear convolution using residue number systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 441--444
year: 1994
DOI: https://doi.org/10.1109/ISCAS.1994.408997
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. G. Parker and M. Benaissa
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, {ISCAS '94}, 2 June 1994
rawtitle: Fault-tolerant linear convolution using residue number systems
entry:
@InProceedings{Parker:1994:FTLb,
  author =       "M. G. Parker and M. Benaissa",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, {ISCAS '94}, 2 June 1994",
  title =        "Fault-tolerant linear convolution using residue number
                 systems",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "441--444",
  year =         "1994",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1994.408997",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper proposes a fault-tolerant linear
                 convolution architecture using Residue Number Systems
                 (RNS) and Polynomial Residue Number Systems (PRNS). The
                 RNS and PRNS are both given error-detection capability
                 by the addition of redundant residue \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Patankar:1994:SHA
author: Rashmi Arun Patankar
title: Software and hardware approaches to data compression of IEEE 64-bit floating point data
type: Thesis (M.S.)
school: Iowa State University
address: Ames, IA, USA
pages: 55
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Rashmi Arun Patankar
rawtitle: Software and hardware approaches to data compression of {IEEE} 64-bit floating point data
entry:
@MastersThesis{Patankar:1994:SHA,
  author =       "Rashmi Arun Patankar",
  title =        "Software and hardware approaches to data compression
                 of {IEEE} 64-bit floating point data",
  type =         "Thesis ({M.S.})",
  school =       "Iowa State University",
  address =      "Ames, IA, USA",
  pages =        "55",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Phatak:1994:HSD
author: D. S. Phatak and I. Koren
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 880--891
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295850
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. S. Phatak and I. Koren
title:
Hybrid Signed-Digit Number Systems: a Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains

rawtitle:
Hybrid Signed-Digit Number Systems: a Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains

entry:
@Article{Phatak:1994:HSD,
  author =       "D. S. Phatak and I. Koren",
  title =        "Hybrid Signed-Digit Number Systems: a Unified
                 Framework for Redundant Number Representations With
                 Bounded Carry Propagation Chains",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "880--891",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295850",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Popova:1994:EIA
author: Evgenija D. Popova
title: Extended interval arithmetic in IEEE floating-point environment
journal: j-INTERVAL-COMP
volume: 4
pages: 100--129
year: 1994
ISSN: 0135-4868 OR 01354868
MRclass: 65-04 (65G10)
MRnumber: 1 332 078
bibdate: Fri Dec 8 08:24:14 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:14 ???
fjournal: Interval Computations = Interval'nye vychisleniia
acknowledgement: ack-nhfb
rawauthor: Evgenija D. Popova
rawtitle: Extended interval arithmetic in {IEEE} floating-point environment
entry:
@Article{Popova:1994:EIA,
  author =       "Evgenija D. Popova",
  title =        "Extended interval arithmetic in {IEEE} floating-point
                 environment",
  journal =      j-INTERVAL-COMP,
  volume =       "4",
  pages =        "100--129",
  year =         "1994",
  ISSN =         "0135-4868",
  MRclass =      "65-04 (65G10)",
  MRnumber =     "1 332 078",
  bibdate =      "Fri Dec 8 08:24:14 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Interval Computations = Interval'nye vychisleniia",
  xxnote =       "SCAN-93 (Vienna, 1993)",
}


bibtype: article
filename: fparith.bib
label: Prince:1994:TFM
author: Timothy Prince
title: tt float-Precision Math Library
journal: j-CUJ
volume: 12
number: 6
pages: 45--??
month: jun
monthnumber: 6
year: 1994
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: Timothy Prince
rawtitle: {{\tt float}}-Precision Math Library
entry:
@Article{Prince:1994:TFM,
  author =       "Timothy Prince",
  title =        "{{\tt float}}-Precision Math Library",
  journal =      j-CUJ,
  volume =       "12",
  number =       "6",
  pages =        "45--??",
  month =        jun,
  year =         "1994",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: article
filename: fparith.bib
label: Pritchard:1994:RAR
author: A. J. Pritchard and S. J. Sangwine and R. E. N. Horne
title: Rational arithmetic representation of colour image pixels
journal: j-ELECT-LETTERS
volume: 30
number: 18
pages: 1474--1475
month: sep
monthnumber: 9
year: 1994
CODEN: ELLEAK
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Fri Nov 30 07:42:41 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.30 07:42:41 ???
fjournal: Electronics Letters
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: A. J. Pritchard and S. J. Sangwine and R. E. N. Horne
rawtitle: Rational arithmetic representation of colour image pixels
entry:
@Article{Pritchard:1994:RAR,
  author =       "A. J. Pritchard and S. J. Sangwine and R. E. N.
                 Horne",
  title =        "Rational arithmetic representation of colour image
                 pixels",
  journal =      j-ELECT-LETTERS,
  volume =       "30",
  number =       "18",
  pages =        "1474--1475",
  month =        sep,
  year =         "1994",
  CODEN =        "ELLEAK",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Fri Nov 30 07:42:41 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
}


bibtype: inproceedings
filename: fparith.bib
label: Rajski:1994:DRP
author: J. Rajski and J. Tyszer
title: Design of random pattern testable floating point adders
crossref: IEEE:1994:PTA
pages: 227--232
year: 1994
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., McGill University, Montreal, Que., Canada
rawauthor: J. Rajski and J. Tyszer
rawtitle: Design of random pattern testable floating point adders
abstract:
The paper presents a floating point adder with enhanced testability and test response compaction capabilities. It is shown that the testability of the conventional adders can be improved by changing the functionality of some of their internal modules in the testing mode. It is also demonstrated that the floating point units can perform an efficient test response compaction in a built-in self test environment. (7 Refs.)

keywords:
built-in self test environment; enhanced testability; floating point accumulator; floating point units; floating-point testing; functionality; internal modules; random pattern testable floating point adders; rotate shifter; simulation experiments; test response compaction; testability

thesaurus:
adders; built-in self test; design for testability; digital simulation; floating point arithmetic; logic design; modules; shift registers

rawabstract:
The paper presents a floating point adder with enhanced testability and test response compaction capabilities. It is shown that the testability of the conventional adders can be improved by changing the functionality of some of their internal modules in the testing mode. It is also demonstrated that the floating point units can perform an efficient test response compaction in a built-in self test environment. (7 Refs.)

entry:
@InProceedings{Rajski:1994:DRP,
  author =       "J. Rajski and J. Tyszer",
  title =        "Design of random pattern testable floating point
                 adders",
  crossref =     "IEEE:1994:PTA",
  pages =        "227--232",
  year =         "1994",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper presents a floating point adder with
                 enhanced testability and test response compaction
                 capabilities. It is shown that the testability of the
                 conventional adders can be improved by changing the
                 functionality of some of their internal modules in the
                 testing mode. It is also demonstrated that the floating
                 point units can perform an efficient test response
                 compaction in a built-in self test environment. (7
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng., McGill University,
                 Montreal, Que., Canada",
  classification = "B0170E (Production facilities and engineering);
                 B1265B (Logic circuits); B7210B (Automatic test and
                 measurement systems); C5120 (Logic and switching
                 circuits); C5210 (Logic design methods); C5230 (Digital
                 arithmetic methods); C7410D (Electronic engineering
                 computing)",
  keywords =     "built-in self test environment; enhanced testability;
                 floating point accumulator; floating point units;
                 floating-point testing; functionality; internal
                 modules; random pattern testable floating point adders;
                 rotate shifter; simulation experiments; test response
                 compaction; testability",
  thesaurus =    "adders; built-in self test; design for testability;
                 digital simulation; floating point arithmetic; logic
                 design; modules; shift registers",
}


bibtype: mastersthesis
filename: fparith.bib
label: Robe:1994:SME
author: Edward D. Robe
type: Thesis (M.S.)
school: Ohio University
address: Athens, OH, USA
pages: v + 130
month: jun
monthnumber: 6
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital control systems.; Emulators (Computer programs); Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Edward D. Robe
title:
SIMULINK modules that emulate digital controllers realized with fixed-point or floating-point arithmetic

rawtitle:
{SIMULINK} modules that emulate digital controllers realized with fixed-point or floating-point arithmetic

entry:
@MastersThesis{Robe:1994:SME,
  author =       "Edward D. Robe",
  title =        "{SIMULINK} modules that emulate digital controllers
                 realized with fixed-point or floating-point
                 arithmetic",
  type =         "Thesis ({M.S.})",
  school =       "Ohio University",
  address =      "Athens, OH, USA",
  pages =        "v + 130",
  month =        jun,
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital control systems.; Emulators (Computer
                 programs); Floating-point arithmetic.",
}


bibtype: techreport
filename: fparith.bib
label: Rothberg:1994:ILD
author: Edward Rothberg and Robert Schreiber
title: Improved load distribution in parallel sparse Cholesky factorization
address: Moffett Field, CA, USA
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Edward Rothberg and Robert Schreiber
rawtitle: Improved load distribution in parallel sparse {Cholesky} factorization
institution:
Research Institute for Advanced Computer Science, NASA Ames Research Center; National Technical Information Service, distributor

series:
[NASA contractor report]; NASA CR-196380 RIACS technical report; 94.13 RIACS technical report; TR 94.13.

keywords:
Cholesky factorization.; Computer systems performance.; Floating point arithmetic.; Heuristic methods.; Parallel processing (Computers).

remark:
Distributed to depository libraries in microfiche. Shipping list no.: 94-0871-M. Microfiche. [Washington, D.C.: National Aeronautics and Space Administration, 1994] 1 microfiche.

entry:
@TechReport{Rothberg:1994:ILD,
  author =       "Edward Rothberg and Robert Schreiber",
  title =        "Improved load distribution in parallel sparse
                 {Cholesky} factorization",
  institution =  "Research Institute for Advanced Computer Science, NASA
                 Ames Research Center; National Technical Information
                 Service, distributor",
  address =      "Moffett Field, CA, USA",
  pages =        "????",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "[NASA contractor report]; NASA CR-196380 RIACS
                 technical report; 94.13 RIACS technical report; TR
                 94.13.",
  acknowledgement = ack-nhfb,
  govtdocnumber = "NAS 1.26:196380 0830-H-14 (MF)",
  keywords =     "Cholesky factorization.; Computer systems
                 performance.; Floating point arithmetic.; Heuristic
                 methods.; Parallel processing (Computers).",
  remark =       "Distributed to depository libraries in microfiche.
                 Shipping list no.: 94-0871-M. Microfiche. [Washington,
                 D.C.: National Aeronautics and Space Administration,
                 1994] 1 microfiche.",
}


bibtype: article
filename: fparith.bib
label: Schaefer:1994:POU
author: Mark J. Schaefer
title: Precise optimization using range arithmetic
journal: j-J-COMPUT-APPL-MATH
volume: 53
number: 3
pages: 341--351
day: 30
month: aug
monthnumber: 8
year: 1994
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 12:24:32 MST 2017
bibtimestamp: 2017.02.25 12:24:32 MST
URL: http://www.sciencedirect.com/science/article/pii/0377042794900620
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Mark J. Schaefer
rawtitle: Precise optimization using range arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib

entry:
@Article{Schaefer:1994:POU,
  author =       "Mark J. Schaefer",
  title =        "Precise optimization using range arithmetic",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "53",
  number =       "3",
  pages =        "341--351",
  day =          "30",
  month =        aug,
  year =         "1994",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 12:24:32 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0377042794900620",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: mastersthesis
filename: fparith.bib
label: Schaffer:1994:FPM
author: Jonathan T. Schaffer
title: A floating point multiplier for a superscalar microprocessor
type: Thesis (M.S.)
school: North Carolina State University
address: Raleigh, NC, USA
pages: viii + 104
year: 1994
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Jonathan T. Schaffer
rawtitle: A floating point multiplier for a superscalar microprocessor
entry:
@MastersThesis{Schaffer:1994:FPM,
  author =       "Jonathan T. Schaffer",
  title =        "A floating point multiplier for a superscalar
                 microprocessor",
  type =         "Thesis ({M.S.})",
  school =       "North Carolina State University",
  address =      "Raleigh, NC, USA",
  pages =        "viii + 104",
  year =         "1994",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Schorn:1994:DGC
author: Peter Schorn
title: Degeneracy in geometric computation and the perturbation approach
journal: j-COMP-J
volume: 37
number: 1
pages: 35--42
year: 1994
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Jul 21 09:54:00 MDT 1999
bibtimestamp: 1999.07.21 09:54:00 MDT
URL: http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.body.html#AbstractSchorn
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Inst. fur Theor. Inf., ETH, Zurich, Switzerland
classcodes: C4260 (Computational geometry); C4240 (Programming and algorithm theory)
corpsource: Inst. fur Theor. Inf., ETH, Zurich, Switzerland
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Algorithm theory; Computational geometry; Perturbation theory
treatment: T Theoretical or Mathematical
rawauthor: Peter Schorn
rawtitle: Degeneracy in geometric computation and the perturbation approach
bibsource:
http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
algorithm construction; Algorithm construction; algorithm theory; algorithm-dependent; Algorithm-dependent degeneracies; approach; computational geometry; degeneracies; Euclidean constructions; floating; Floating point arithmetic; geometric computation; Geometric computation; input-output; Input-output specifications; integer arithmetic; Integer arithmetic; lexicographic; Lexicographic ordering; ordering; perturbation; Perturbation approach; point arithmetic; problem-dependent degeneracies; Problem-dependent degeneracies; provably correct results; Provably correct results; specifications; theory; winding number; Winding number

entry:
@Article{Schorn:1994:DGC,
  author =       "Peter Schorn",
  title =        "Degeneracy in geometric computation and the
                 perturbation approach",
  journal =      j-COMP-J,
  volume =       "37",
  number =       "1",
  pages =        "35--42",
  month =        "????",
  year =         "1994",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Jul 21 09:54:00 MDT 1999",
  bibsource =    "http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/Volume_37/Issue_01/Vol37_01.body.html#AbstractSchorn",
  acknowledgement = ack-nhfb,
  affiliation =  "Inst. fur Theor. Inf., ETH, Zurich, Switzerland",
  author-1-adr = "Institut f{\"u}r Theoretische Informatik, ETH, CH-8092
                 Zurich, Switzerland",
  classcodes =   "C4260 (Computational geometry); C4240 (Programming and
                 algorithm theory)",
  classification = "C4240 (Programming and algorithm theory); C4260
                 (Computational geometry)",
  corpsource =   "Inst. fur Theor. Inf., ETH, Zurich, Switzerland",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "algorithm construction; Algorithm construction;
                 algorithm theory; algorithm-dependent;
                 Algorithm-dependent degeneracies; approach;
                 computational geometry; degeneracies; Euclidean
                 constructions; floating; Floating point arithmetic;
                 geometric computation; Geometric computation;
                 input-output; Input-output specifications; integer
                 arithmetic; Integer arithmetic; lexicographic;
                 Lexicographic ordering; ordering; perturbation;
                 Perturbation approach; point arithmetic;
                 problem-dependent degeneracies; Problem-dependent
                 degeneracies; provably correct results; Provably
                 correct results; specifications; theory; winding
                 number; Winding number",
  thesaurus =    "Algorithm theory; Computational geometry; Perturbation
                 theory",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: mastersthesis
filename: fparith.bib
label: Schoss:1994:ISF
author: H. Schoss
type: Diplomarbeit
school: Institut fur angewandte Mathematik, Universitat Karlsruhe
address: Karlsruhe, Germany
month: mar
monthnumber: 3
year: 1994
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
acknowledgement: ack-nj
rawauthor: H. Schoss
title:
Intervall Standardfunktionen fur das binare IEEE Zahlenformat toenglish Interval Standard Functions for the Binary IEEE Number Format endtoenglish 

rawtitle:
{Intervall Standardfunktionen f{\"u}r das bin{\"a}re IEEE Zahlenformat} \toenglish {Interval Standard Functions for the Binary IEEE Number Format} \endtoenglish

entry:
@MastersThesis{Schoss:1994:ISF,
  author =       "H. Schoss",
  title =        "{Intervall Standardfunktionen f{\"u}r das bin{\"a}re
                 IEEE Zahlenformat} \toenglish {Interval Standard
                 Functions for the Binary IEEE Number Format}
                 \endtoenglish",
  type =         "{Diplomarbeit}",
  school =       "Institut f{\"u}r angewandte Mathematik,
                 Universit{\"a}t Karlsruhe",
  address =      "Karlsruhe, Germany",
  pages =        "??",
  month =        mar,
  year =         "1994",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Schulte:1994:HDE
author: M. J. Schulte and E. E. Swartzlander, Jr.
title: Hardware Designs for Exactly Rounded Elementary Functions
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 964--973
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295858
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Texas University, Austin, TX, USA
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. J. Schulte and E. E. {Swartzlander, Jr.}
rawtitle: Hardware Designs for Exactly Rounded Elementary Functions
abstract:
This paper presents hardware designs that produce exactly rounded results for the functions of reciprocal, square-root, 2/sup x/, and log/sub 2/(x). These designs use polynomial approximation in which the terms in the approximation are generated in parallel, and then summed by using a multi-operand adder. To reduce the number of terms in the approximation, the input interval is partitioned into subintervals of equal size, and different coefficients are used for each subinterval. The coefficients used in the approximation are initially determined based on the Chebyshev series approximation. They are then adjusted to obtain exactly rounded results for all inputs. Hardware designs are presented, and delay and area comparisons are made based on the degree of the approximating polynomial and the accuracy of the final result. For single-precision floating point numbers, a design that produces exactly rounded results for all four functions has an estimated delay of 80 ns and a total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS technology. Allowing the results to have a maximum error of one unit in the last place reduces the computational delay by 5% to 30% and the area requirements by 33% to 77%.

keywords:
1 Micron; 1.0-Micron CMOS technology; Argument reduction; Chebyshev series approximation; Chip area; Computational delay; Computer arithmetic; Exact rounding; Exactly rounded elementary functions; Hardware designs; Multi-operand adder; Parallel multiplier; Polynomial approximation; Reciprocal; Single-precision floating point numbers; Special-purpose hardware; Square-root

thesaurus:
Approximation theory; Chebyshev approximation; CMOS integrated circuits; Digital arithmetic; Multiplying circuits; Polynomials; Summing circuits

rawabstract:
This paper presents hardware designs that produce exactly rounded results for the functions of reciprocal, square-root, 2/sup x/, and log/sub 2/(x). These designs use polynomial approximation in which the terms in the approximation are generated in parallel, and then summed by using a multi-operand adder. To reduce the number of terms in the approximation, the input interval is partitioned into subintervals of equal size, and different coefficients are used for each subinterval. The coefficients used in the approximation are initially determined based on the Chebyshev series approximation. They are then adjusted to obtain exactly rounded results for all inputs. Hardware designs are presented, and delay and area comparisons are made based on the degree of the approximating polynomial and the accuracy of the final result. For single-precision floating point numbers, a design that produces exactly rounded results for all four functions has an estimated delay of 80 ns and a total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS technology. Allowing the results to have a maximum error of one unit in the last place reduces the computational delay by 5\% to 30\% and the area requirements by 33\% to 77\%.

entry:
@Article{Schulte:1994:HDE,
  author =       "M. J. Schulte and E. E. {Swartzlander, Jr.}",
  title =        "Hardware Designs for Exactly Rounded Elementary
                 Functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "964--973",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295858",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  abstract =     "This paper presents hardware designs that produce
                 exactly rounded results for the functions of
                 reciprocal, square-root, 2/sup x/, and log/sub 2/(x).
                 These designs use polynomial approximation in which the
                 terms in the approximation are generated in parallel,
                 and then summed by using a multi-operand adder. To
                 reduce the number of terms in the approximation, the
                 input interval is partitioned into subintervals of
                 equal size, and different coefficients are used for
                 each subinterval. The coefficients used in the
                 approximation are initially determined based on the
                 Chebyshev series approximation. They are then adjusted
                 to obtain exactly rounded results for all inputs.
                 Hardware designs are presented, and delay and area
                 comparisons are made based on the degree of the
                 approximating polynomial and the accuracy of the final
                 result. For single-precision floating point numbers, a
                 design that produces exactly rounded results for all
                 four functions has an estimated delay of 80 ns and a
                 total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS
                 technology. Allowing the results to have a maximum
                 error of one unit in the last place reduces the
                 computational delay by 5\% to 30\% and the area
                 requirements by 33\% to 77\%.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Department of Electr. and Comput. Eng., Texas
                 University, Austin, TX, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "B0290F (Interpolation and function approximation);
                 B1265B (Logic circuits); B2570D (CMOS integrated
                 circuits); C4130 (Interpolation and function
                 approximation); C5120 (Logic and switching circuits);
                 C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "1 Micron; 1.0-Micron CMOS technology; Argument
                 reduction; Chebyshev series approximation; Chip area;
                 Computational delay; Computer arithmetic; Exact
                 rounding; Exactly rounded elementary functions;
                 Hardware designs; Multi-operand adder; Parallel
                 multiplier; Polynomial approximation; Reciprocal;
                 Single-precision floating point numbers;
                 Special-purpose hardware; Square-root",
  numericalindex = "Size 1.0E-06 m",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
  thesaurus =    "Approximation theory; Chebyshev approximation; CMOS
                 integrated circuits; Digital arithmetic; Multiplying
                 circuits; Polynomials; Summing circuits",
  xxtitle =      "Hardware Design for Exactly Rounded Elementary
                 Functions",
}


bibtype: article
filename: fparith.bib
label: Schulte:1994:OIA
author: M. J. Schulte and J. Omar and E. E. Swartzlander, Jr.
title: Optimal initial approximations for the Newton--Raphson division algorithm
journal: j-COMPUTING
volume: 53
number: 3--4
pages: 233--242
month: sep
monthnumber: 9
year: 1994
CODEN: CMPTA2
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 65D99
MRnumber: 1 308 764
bibdate: Thu Apr 2 08:38:35 1998
bibtimestamp: 1998.04.02 08:38:35 ???
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-sfo
journalURL: http://link.springer.com/journal/607
rawauthor: M. J. Schulte and J. Omar and E. E. {Swartzlander, Jr.}
rawtitle: Optimal initial approximations for the {Newton--Raphson} division algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database; OCLC Contents1st database

note:
International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (Vienna, 1993).

rawnote:
International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (Vienna, 1993).

entry:
@Article{Schulte:1994:OIA,
  author =       "M. J. Schulte and J. Omar and E. E. {Swartzlander,
                 Jr.}",
  title =        "Optimal initial approximations for the
                 {Newton--Raphson} division algorithm",
  journal =      j-COMPUTING,
  volume =       "53",
  number =       "3--4",
  pages =        "233--242",
  month =        sep,
  year =         "1994",
  CODEN =        "CMPTA2",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "65D99",
  MRnumber =     "1 308 764",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database; OCLC Contents1st database",
  note =         "International Symposium on Scientific Computing,
                 Computer Arithmetic and Validated Numerics (Vienna,
                 1993).",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:1994:VIA
author: M. J. Schulte and E. E. Swartzlander, Jr.
title: A variable-precision interval arithmetic processor
crossref: Cappello:1994:PIC
pages: 248--258
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Texas University, Austin, TX, USA
thesaurus: Digital arithmetic; Error analysis; Microprocessor chips; Parallel architectures
rawauthor: M. J. Schulte and E. E. {Swartzlander, Jr.}
rawtitle: A variable-precision interval arithmetic processor
abstract:
This paper presents a special-purpose processor which implements variable-precision, interval arithmetic. Variable-precision arithmetic allows the precision of the computation to be specified, based on the problem to be solved and the required accuracy of the computation. Interval arithmetic produces two values for each result, such that the true result is guaranteed to be between the two values. The distance between the two values gives an upper bound on the error. Direct hardware support for variable-precision, interval arithmetic greatly improves the accuracy of the computation, and is much faster than existing software methods for controlling numerical error. Area and delay estimates indicate that the processor can be implemented on a single chip with a cycle time which is comparable to existing IEEE double-precision floating point processors. For computationally intensive problems, an application-specific array of variable-precision, interval arithmetic processors can execute in parallel to provide high-performance and numerically reliable results.

keywords:
Application-specific array; Hardware support; IEEE double-precision floating point processors; Numerical error; Parallel arithmetic; Special-purpose processor; Variable-precision interval arithmetic processor

rawabstract:
This paper presents a special-purpose processor which implements variable-precision, interval arithmetic. Variable-precision arithmetic allows the precision of the computation to be specified, based on the problem to be solved and the required accuracy of the computation. Interval arithmetic produces two values for each result, such that the true result is guaranteed to be between the two values. The distance between the two values gives an upper bound on the error. Direct hardware support for variable-precision, interval arithmetic greatly improves the accuracy of the computation, and is much faster than existing software methods for controlling numerical error. Area and delay estimates indicate that the processor can be implemented on a single chip with a cycle time which is comparable to existing IEEE double-precision floating point processors. For computationally intensive problems, an application-specific array of variable-precision, interval arithmetic processors can execute in parallel to provide high-performance and numerically reliable results.

entry:
@InProceedings{Schulte:1994:VIA,
  author =       "M. J. Schulte and E. E. {Swartzlander, Jr.}",
  title =        "A variable-precision interval arithmetic processor",
  crossref =     "Cappello:1994:PIC",
  pages =        "248--258",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a special-purpose processor which
                 implements variable-precision, interval arithmetic.
                 Variable-precision arithmetic allows the precision of
                 the computation to be specified, based on the problem
                 to be solved and the required accuracy of the
                 computation. Interval arithmetic produces two values
                 for each result, such that the true result is
                 guaranteed to be between the two values. The distance
                 between the two values gives an upper bound on the
                 error. Direct hardware support for variable-precision,
                 interval arithmetic greatly improves the accuracy of
                 the computation, and is much faster than existing
                 software methods for controlling numerical error. Area
                 and delay estimates indicate that the processor can be
                 implemented on a single chip with a cycle time which is
                 comparable to existing IEEE double-precision floating
                 point processors. For computationally intensive
                 problems, an application-specific array of
                 variable-precision, interval arithmetic processors can
                 execute in parallel to provide high-performance and
                 numerically reliable results.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Texas
                 University, Austin, TX, USA",
  classification = "B0290B (Error analysis in numerical methods); B1265F
                 (Microprocessors and microcomputers); C4110 (Error
                 analysis in numerical methods); C5130 (Microprocessor
                 chips); C5220P (Parallel architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "Application-specific array; Hardware support; IEEE
                 double-precision floating point processors; Numerical
                 error; Parallel arithmetic; Special-purpose processor;
                 Variable-precision interval arithmetic processor",
  thesaurus =    "Digital arithmetic; Error analysis; Microprocessor
                 chips; Parallel architectures",
}


bibtype: article
filename: fparith.bib
label: Schwandt:1994:IAD
author: Hartmut Schwandt
journal: j-J-COMPUT-APPL-MATH
volume: 50
number: 1--3
pages: 509--521
day: 20
month: may
monthnumber: 5
year: 1994
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:02:23 MST 2017
bibtimestamp: 2017.02.25 13:02:23 MST
URL: http://www.sciencedirect.com/science/article/pii/0377042794903247
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Hartmut Schwandt
title:
An interval arithmetic domain decomposition method for a class of elliptic PDEs on nonrectangular domains

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib

rawtitle:
An interval arithmetic domain decomposition method for a class of elliptic {PDEs} on nonrectangular domains

entry:
@Article{Schwandt:1994:IAD,
  author =       "Hartmut Schwandt",
  title =        "An interval arithmetic domain decomposition method for
                 a class of elliptic {PDEs} on nonrectangular domains",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "50",
  number =       "1--3",
  pages =        "509--521",
  day =          "20",
  month =        may,
  year =         "1994",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:02:23 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1990.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0377042794903247",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: techreport
filename: fparith.bib
label: Sharangpani:1994:SAF
author: H. P. Sharangpani and M. L. Barton
title: Statistical analysis of floating point flaw in the Pentium processor
institution: pub-INTEL
address: pub-INTEL:adr
pages: 509--521
month: nov
monthnumber: 11
year: 1994
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
keywords: Intel Pentium divide flaw; Thomas R. Nicely
acknowledgement: ack-sfo
rawauthor: H. P. Sharangpani and M. L. Barton
rawtitle: Statistical analysis of floating point flaw in the {Pentium} processor
URL:
http://home1.gte.net/deleyd/pentbug/white11.ps; http://www.intel.com/procs/support/pentium/fdiv/white11.ps

abstract:
A subtle flaw in the hardware divide unit of the PentiumTM Processor was discovered by Intel. Subsequently, a characterization of its impact to the end-user application base was conducted. The flaw is rare and data-dependent, and causes a reduction in precision of the divide instruction and certain other operations in certain cases.par The significance of the flaw depends upon (a) the rate of use of specific FP instructions in the PentiumTM CPU, (b) the data fed to them, (c) the way in which the results of these instructions are propagated into further computation in the application; and (d) the way in which the final results of the application are interpreted.par The thorough and detailed characterization of the flaw and the subsequent investigations of its impact on applications through elaborate surveys, analyses and empirical observation lead us to the overall conclusion that the flaw is of no concern to the vast majority of users of Pentium processor based systems. A few users of applications in the scientific/engineering and financial engineering fields who require unusual precision and invoke millions of divides per day may need to employ either an updated Pentium processor without the flaw or a software workaround.

remark:
This Intel white paper was controversial, and its minimization of the problem was refuted by others: see cite Edelman:1997:MPD.

rawabstract:
A subtle flaw in the hardware divide unit of the PentiumTM Processor was discovered by Intel. Subsequently, a characterization of its impact to the end-user application base was conducted. The flaw is rare and data-dependent, and causes a reduction in precision of the divide instruction and certain other operations in certain cases.\par The significance of the flaw depends upon (a) the rate of use of specific FP instructions in the PentiumTM CPU, (b) the data fed to them, (c) the way in which the results of these instructions are propagated into further computation in the application; and (d) the way in which the final results of the application are interpreted.\par The thorough and detailed characterization of the flaw and the subsequent investigations of its impact on applications through elaborate surveys, analyses and empirical observation lead us to the overall conclusion that the flaw is of no concern to the vast majority of users of Pentium processor based systems. A few users of applications in the scientific/engineering and financial engineering fields who require unusual precision and invoke millions of divides per day may need to employ either an updated Pentium processor without the flaw or a software workaround.

entry:
@TechReport{Sharangpani:1994:SAF,
  author =       "H. P. Sharangpani and M. L. Barton",
  title =        "Statistical analysis of floating point flaw in the
                 {Pentium} processor",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  month =        nov,
  year =         "1994",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home1.gte.net/deleyd/pentbug/white11.ps;
                 http://www.intel.com/procs/support/pentium/fdiv/white11.ps",
  abstract =     "A subtle flaw in the hardware divide unit of the
                 PentiumTM Processor was discovered by Intel.
                 Subsequently, a characterization of its impact to the
                 end-user application base was conducted. The flaw is
                 rare and data-dependent, and causes a reduction in
                 precision of the divide instruction and certain other
                 operations in certain cases.\par

                 The significance of the flaw depends upon (a) the rate
                 of use of specific FP instructions in the PentiumTM
                 CPU, (b) the data fed to them, (c) the way in which the
                 results of these instructions are propagated into
                 further computation in the application; and (d) the way
                 in which the final results of the application are
                 interpreted.\par

                 The thorough and detailed characterization of the flaw
                 and the subsequent investigations of its impact on
                 applications through elaborate surveys, analyses and
                 empirical observation lead us to the overall conclusion
                 that the flaw is of no concern to the vast majority of
                 users of Pentium processor based systems. A few users
                 of applications in the scientific/engineering and
                 financial engineering fields who require unusual
                 precision and invoke millions of divides per day may
                 need to employ either an updated Pentium processor
                 without the flaw or a software workaround.",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "Intel Pentium divide flaw; Thomas R. Nicely",
  remark =       "This Intel white paper was controversial, and its
                 minimization of the problem was refuted by others: see
                 \cite{Edelman:1997:MPD}.",
}


bibtype: article
filename: fparith.bib
label: Shippy:1994:PFD
author: D. J. Shippy and T. W. Griffith
title: POWER2 fixed-point, data cache, and storage control units
journal: j-IBM-JRD
volume: 38
number: 5
pages: 503--524
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Tue Mar 25 14:26:59 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.03.25 14:26:59 MST
URL: http://www.almaden.ibm.com/journal/rd38-5.html#three
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
corpsource: IBM Corp., Austin, TX, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
treatment: P Practical
rawauthor: D. J. Shippy and T. W. Griffith
rawtitle: {POWER2} fixed-point, data cache, and storage control units
abstract:
The POWER2* fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an improved I/O DMA mechanism to support multiple-streaming Micro Channels.*

keywords:
address translation; Address translation; cache; cache storage; data buses; Data buses; data cache; Data cache; dual fixed-point; Dual fixed-point execution units; execution units; external interrupt; External interrupt mechanism; floating-; Floating-point; mechanism; memory interface; Memory interface; microprocessor chips; multiple-streaming micro channels; Multiple-streaming micro channels; multiported data; Multiported data cache; performance evaluation; point; POWER2; reduced instruction set computing; storage control units; Storage control units; storage management; superscalar RISC processor; Superscalar RISC processor; synchronisation; synchronization; Synchronization; system buses

classcodes:
B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5470 (Performance evaluation and testing); C5610S (System buses); C5320G (Semiconductor storage)

thesaurus:
Cache storage; Microprocessor chips; Performance evaluation; Reduced instruction set computing; Storage management; Synchronisation; System buses

rawabstract:
The POWER2* fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an improved I/O DMA mechanism to support multiple-streaming Micro Channels.*

entry:
@Article{Shippy:1994:PFD,
  author =       "D. J. Shippy and T. W. Griffith",
  title =        "{POWER2} fixed-point, data cache, and storage control
                 units",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "503--524",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#three",
  abstract =     "The POWER2* fixed-point, data cache, and storage
                 control units provide a tightly integrated subunit for
                 a second-generation high-performance superscalar RISC
                 processor. These functional units provide dual
                 fixed-point execution units and a large multiported
                 data cache, as well as high-performance interfaces to
                 memory, I/O, and the other execution units in the
                 processor. These units provide the following features:
                 dual fixed-point execution units, improved
                 fixed-point/floating-point synchronization, new
                 floating-point load and store quadword instructions,
                 improved address translation, improved fixed-point
                 multiply/divide, large multiported D-cache, increased
                 bandwidth into and out of the caches through wider data
                 buses, an improved external interrupt mechanism, and an
                 improved I/O DMA mechanism to support
                 multiple-streaming Micro Channels.*",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5470 (Performance evaluation
                 and testing); C5610S (System buses); C5320G
                 (Semiconductor storage)",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5320G (Semiconductor storage);
                 C5470 (Performance evaluation and testing); C5610S
                 (System buses)",
  corpsource =   "IBM Corp., Austin, TX, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "address translation; Address translation; cache; cache
                 storage; data buses; Data buses; data cache; Data
                 cache; dual fixed-point; Dual fixed-point execution
                 units; execution units; external interrupt; External
                 interrupt mechanism; floating-; Floating-point;
                 mechanism; memory interface; Memory interface;
                 microprocessor chips; multiple-streaming micro
                 channels; Multiple-streaming micro channels;
                 multiported data; Multiported data cache; performance
                 evaluation; point; POWER2; reduced instruction set
                 computing; storage control units; Storage control
                 units; storage management; superscalar RISC processor;
                 Superscalar RISC processor; synchronisation;
                 synchronization; Synchronization; system buses",
  thesaurus =    "Cache storage; Microprocessor chips; Performance
                 evaluation; Reduced instruction set computing; Storage
                 management; Synchronisation; System buses",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Smith:1994:PAT
author: James E. Smith and Shlomo Weiss
title: PowerPC 601 and Alpha 21064: a Tale of Two RISCs
journal: j-COMPUTER
volume: 27
number: 6
pages: 46--58
month: jun
monthnumber: 6
year: 1994
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Mon Feb 3 07:28:57 MST 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.02.03 07:28:57 MST
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Cray Res. Inc., Chippewa Falls, WI, USA
affiliationaddress: Chippewa Falls, WI, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
journalabr: Computer
thesaurus: Instruction sets; Pipeline processing; Reduced instruction set computing
rawauthor: James E. Smith and Shlomo Weiss
rawtitle: {PowerPC 601} and {Alpha 21064}: a Tale of Two {RISCs}
abstract:
Both PowerPC and Alpha are RISC architectures, but they have little in common beyond that. The design philosophy of one emphasizes powerful instructions, the other simplicity.

keywords:
Access memory; Alpha 21064; Buffering; Cache memory; Computer software; Data storage equipment; Digital arithmetic; Digital Equipment Corporation; Floating point instructions; High performance; IBM/Motorola/Apple; Implementation philosophies; Instruction sets; Load/store architecture; Microprocessor chips; Out of order dispatch; Parallel processing systems; Performance; Philosophical aspects; Pipeline processing systems; Pipelined implementations; PowerPC 601; Processing order; Program compilers; Program debugging; Reduced instruction set computing; RISC implementations; RISC microprocessors; Streamlined implementation structure; Superscalar implementations; User interfaces; Very fast clock; Virtual storage

rawabstract:
Both PowerPC and Alpha are RISC architectures, but they have little in common beyond that. The design philosophy of one emphasizes powerful instructions, the other simplicity.

entry:
@Article{Smith:1994:PAT,
  author =       "James E. Smith and Shlomo Weiss",
  title =        "{PowerPC 601} and {Alpha 21064}: a Tale of Two
                 {RISCs}",
  journal =      j-COMPUTER,
  volume =       "27",
  number =       "6",
  pages =        "46--58",
  month =        jun,
  year =         "1994",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Mon Feb 3 07:28:57 MST 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Both PowerPC and Alpha are RISC architectures, but
                 they have little in common beyond that. The design
                 philosophy of one emphasizes powerful instructions, the
                 other simplicity.",
  acknowledgement = ack-nhfb,
  affiliation =  "Cray Res. Inc., Chippewa Falls, WI, USA",
  affiliationaddress = "Chippewa Falls, WI, USA",
  classification = "721.3; 722.1; 722.4; 723.1; C5220P (Parallel
                 architecture); C5440 (Multiprocessor systems and
                 techniques); C6140B (Machine-oriented languages)",
  conferenceyear = "1994",
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  journalabr =   "Computer",
  keywords =     "Access memory; Alpha 21064; Buffering; Cache memory;
                 Computer software; Data storage equipment; Digital
                 arithmetic; Digital Equipment Corporation; Floating
                 point instructions; High performance;
                 IBM/Motorola/Apple; Implementation philosophies;
                 Instruction sets; Load/store architecture;
                 Microprocessor chips; Out of order dispatch; Parallel
                 processing systems; Performance; Philosophical aspects;
                 Pipeline processing systems; Pipelined implementations;
                 PowerPC 601; Processing order; Program compilers;
                 Program debugging; Reduced instruction set computing;
                 RISC implementations; RISC microprocessors; Streamlined
                 implementation structure; Superscalar implementations;
                 User interfaces; Very fast clock; Virtual storage",
  publisherinfo = "IEEE Service Center",
  thesaurus =    "Instruction sets; Pipeline processing; Reduced
                 instruction set computing",
}


bibtype: article
filename: fparith.bib
label: Smith:1994:SFT
author: William Smith
title: A Short Floating-Point Type in C++
journal: j-CUJ
volume: 12
number: 1
pages: 23--??
month: jan
monthnumber: 1
year: 1994
ISSN: 0898-9788 OR 08989788
bibdate: Fri Aug 30 16:52:23 MDT 1996
bibsource: http://www.cuj.com/cbklist.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.30 16:52:23 MDT
fjournal: C Users Journal
acknowledgement: ack-nhfb
rawauthor: William Smith
rawtitle: A Short Floating-Point Type in {C++}
entry:
@Article{Smith:1994:SFT,
  author =       "William Smith",
  title =        "A Short Floating-Point Type in {C++}",
  journal =      j-CUJ,
  volume =       "12",
  number =       "1",
  pages =        "23--??",
  month =        jan,
  year =         "1994",
  ISSN =         "0898-9788",
  bibdate =      "Fri Aug 30 16:52:23 MDT 1996",
  bibsource =    "http://www.cuj.com/cbklist.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "C Users Journal",
}


bibtype: techreport
filename: fparith.bib
label: Solhaug:1994:FDK
author: Fredrik Solhaug
title: Flyttalls A/D-konverter = Floating Point A/D Converter
type: Hovedoppgave
institution: Institutt for teleteknikk, NTH
address: Trondheim, Norway
pages: 23--??
year: 1994
bibdate: Thu May 09 08:14:17 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.09 08:14:17 ???
acknowledgement: ack-nhfb
rawauthor: Fredrik Solhaug
rawtitle: Flyttalls {A/D}-konverter = Floating Point {A/D} Converter
entry:
@TechReport{Solhaug:1994:FDK,
  author =       "Fredrik Solhaug",
  title =        "Flyttalls {A/D}-konverter = Floating Point {A/D}
                 Converter",
  type =         "Hovedoppgave",
  institution =  "Institutt for teleteknikk, NTH",
  address =      "Trondheim, Norway",
  year =         "1994",
  bibdate =      "Thu May 09 08:14:17 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Srivastava:1994:ASB
author: A. Srivastava and A. Eustace
title: ATOM: a system for building customized program analysis tools
journal: j-SIGPLAN
volume: 29
number: 6
pages: 196--205
month: jun
monthnumber: 6
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
note: ACM SIGPLAN '94 Conference on Programming Language Design and Implementation (PLDI).
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-sfo
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: A. Srivastava and A. Eustace
rawnote: ACM SIGPLAN '94 Conference on Programming Language Design and Implementation (PLDI).
rawtitle: {ATOM}: a system for building customized program analysis tools
entry:
@Article{Srivastava:1994:ASB,
  author =       "A. Srivastava and A. Eustace",
  title =        "{ATOM}: a system for building customized program
                 analysis tools",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "6",
  pages =        "196--205",
  month =        jun,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "ACM SIGPLAN '94 Conference on Programming Language
                 Design and Implementation (PLDI).",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: article
filename: fparith.bib
label: Stockman:1994:OMM
author: Harlan W. Stockman
title: Optimizing Matrix Math On The Pentium
journal: j-DDJ
volume: 19
number: 5
pages: 52, 54, 56, 60, 62, 66
month: may
monthnumber: 5
year: 1994
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Tue Sep 03 09:15:49 1996
bibtimestamp: 1996.09.03 09:15:49 ???
fjournal: Dr. Dobb's Journal of Software Tools
acknowledgement: ack-nhfb
affiliation: Department of Geochem., Sandia Nat. Labs., Albuquerque, NM, USA
rawauthor: Harlan W. Stockman
rawtitle: Optimizing Matrix Math On The {Pentium}
abstract:
The Pentium processor is more than just a fast 486. Its pipeline and floating-point and integer operations require that you pay more attention to the flow of data on the off the FPU. Harlan presents and measures methods for speeding up Pentium matrix-math operations.

keywords:
1 MByte; 100 MHz; 256 KByte; 33 MHz; 486DX; 60 MHz; 64 Bit; 64 KByte; 8 Bit; 8-Byte boundaries; Code optimization; Data alignment; Floating-point unit; Gateway 486/33C; Gateway P5-60; Global register allocation; IRIX 4.0.5H; LINPACK routines; Loop unrolling; Matrix multiplication; Matrix operations optimization; MIPS R4000; Pentium microprocessor chip; Pentium-optimized compilers; Performance gains; SGI Elan; Simultaneous linear equations; Symantec C++ 6.0 for DOS; UNIX cc version 3.1; Write-through L2 cache

thesaurus:
Assembly language listings; Digital arithmetic; Mathematics computing; Matrix algebra; Microprocessor chips; Optimisation

rawabstract:
The Pentium processor is more than just a fast 486. Its pipeline and floating-point and integer operations require that you pay more attention to the flow of data on the off the FPU. Harlan presents and measures methods for speeding up Pentium matrix-math operations.

entry:
@Article{Stockman:1994:OMM,
  author =       "Harlan W. Stockman",
  title =        "Optimizing Matrix Math On The {Pentium}",
  journal =      j-DDJ,
  volume =       "19",
  number =       "5",
  pages =        "52, 54, 56, 60, 62, 66",
  month =        may,
  year =         "1994",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Tue Sep 03 09:15:49 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover database",
  abstract =     "The Pentium processor is more than just a fast 486.
                 Its pipeline and floating-point and integer operations
                 require that you pay more attention to the flow of data
                 on the off the FPU. Harlan presents and measures
                 methods for speeding up Pentium matrix-math
                 operations.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Geochem., Sandia Nat. Labs.,
                 Albuquerque, NM, USA",
  classification = "C1180 (Optimisation techniques); C4140 (Linear
                 algebra); C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods); C7310 (Mathematics)",
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "1 MByte; 100 MHz; 256 KByte; 33 MHz; 486DX; 60 MHz; 64
                 Bit; 64 KByte; 8 Bit; 8-Byte boundaries; Code
                 optimization; Data alignment; Floating-point unit;
                 Gateway 486/33C; Gateway P5-60; Global register
                 allocation; IRIX 4.0.5H; LINPACK routines; Loop
                 unrolling; Matrix multiplication; Matrix operations
                 optimization; MIPS R4000; Pentium microprocessor chip;
                 Pentium-optimized compilers; Performance gains; SGI
                 Elan; Simultaneous linear equations; Symantec C++ 6.0
                 for DOS; UNIX cc version 3.1; Write-through L2 cache",
  thesaurus =    "Assembly language listings; Digital arithmetic;
                 Mathematics computing; Matrix algebra; Microprocessor
                 chips; Optimisation",
}


bibtype: article
filename: fparith.bib
label: Thompson:1994:PSN
author: Tom Thompson and Bob Ryan
journal: j-BYTE
volume: 19
number: 11
pages: 113--??
month: nov
monthnumber: 11
year: 1994
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Tue Jan 2 10:01:41 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.01.02 10:01:41 MST
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
rawauthor: Tom Thompson and Bob Ryan
title:
PowerPC 620 Soars: The newest member of the PowerPC family targets the workstation market with fast throughput and speedy floating-point performance

rawtitle:
{PowerPC} 620 Soars: The newest member of the {PowerPC} family targets the workstation market with fast throughput and speedy floating-point performance

entry:
@Article{Thompson:1994:PSN,
  author =       "Tom Thompson and Bob Ryan",
  title =        "{PowerPC} 620 Soars: The newest member of the
                 {PowerPC} family targets the workstation market with
                 fast throughput and speedy floating-point performance",
  journal =      j-BYTE,
  volume =       "19",
  number =       "11",
  pages =        "113--??",
  month =        nov,
  year =         "1994",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Tue Jan 2 10:01:41 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "BYTE Magazine",
}


bibtype: article
filename: fparith.bib
label: Timmermann:1994:CFP
author: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
title: A CMOS Floating-Point Vector-Arithmetic Unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 29
number: 5
pages: 634--639
month: may
monthnumber: 5
year: 1994
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nj
rawauthor: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
rawtitle: A {CMOS} Floating-Point Vector-Arithmetic Unit
entry:
@Article{Timmermann:1994:CFP,
  author =       "D. Timmermann and B. Rix and H. Hahn and B. J.
                 Hosticka",
  title =        "A {CMOS} Floating-Point Vector-Arithmetic Unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "29",
  number =       "5",
  pages =        "634--639",
  month =        may,
  year =         "1994",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "This work describes a floating-point arithmetic unit
                 based on the CORDIC algorithm. The unit computes a full
                 set of high level arithmetic and elementary functions:
                 multiplication, division, (co)sine, hyperbolic
                 (co)sine, square root, natural logarithm \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Timmermann:1994:CFV
author: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
title: A CMOS floating-point vector-arithmetic unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 29
number: 5
pages: 634--639
month: may
monthnumber: 5
year: 1994
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: Fraunhofer Inst. of Microelectron. Circuits and Syst., Duisburg, Germany
rawauthor: D. Timmermann and B. Rix and H. Hahn and B. J. Hosticka
rawtitle: A {CMOS} floating-point vector-arithmetic unit
abstract:
This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 mu m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

keywords:
1.6 Micron; 220 MFLOPS; CORDIC algorithm; Cosine; Division; Double-metal n-well CMOS technology; Floating-point vector-arithmetic unit; Hyperbolic sine; Inverse tangent; Multiplication; Natural logarithm; Phase; Sine; Square root; Vector norm

thesaurus:
CMOS integrated circuits; Digital arithmetic; Integrated logic circuits; Parallel architectures; Pipeline processing; Vector processor systems

rawabstract:
This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 mu m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

entry:
@Article{Timmermann:1994:CFV,
  author =       "D. Timmermann and B. Rix and H. Hahn and B. J.
                 Hosticka",
  title =        "A {CMOS} floating-point vector-arithmetic unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "29",
  number =       "5",
  pages =        "634--639",
  month =        may,
  year =         "1994",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This work describes a floating-point arithmetic unit
                 based on the CORDIC algorithm. The unit computes a full
                 set of high level arithmetic and elementary functions:
                 multiplication, division, (co)sine, hyperbolic
                 (co)sine, square root, natural logarithm, inverse
                 (hyperbolic) tangent, vector norm, and phase. The chip
                 has been integrated in 1.6 mu m double-metal n-well
                 CMOS technology and achieves a normalized peak
                 performance of 220 MFLOPS.",
  acknowledgement = ack-nhfb,
  affiliation =  "Fraunhofer Inst. of Microelectron. Circuits and Syst.,
                 Duisburg, Germany",
  classification = "B1265B (Logic circuits); B2570D (CMOS integrated
                 circuits); C5120 (Logic and switching circuits); C5220P
                 (Parallel architecture); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "1.6 Micron; 220 MFLOPS; CORDIC algorithm; Cosine;
                 Division; Double-metal n-well CMOS technology;
                 Floating-point vector-arithmetic unit; Hyperbolic sine;
                 Inverse tangent; Multiplication; Natural logarithm;
                 Phase; Sine; Square root; Vector norm",
  numericalindex = "Size 1.6E-06 m; Computer speed 2.2E+08 FLOPS",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Integrated logic circuits; Parallel architectures;
                 Pipeline processing; Vector processor systems",
}


bibtype: article
filename: fparith.bib
label: Turner:1994:SRM
author: Stephen M. Turner
title: Square roots mod $p$
journal: j-AMER-MATH-MONTHLY
volume: 101
number: 5
pages: 443--449
month: may
monthnumber: 5
year: 1994
CODEN: AMMYAE
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
MRclass: 11A07
MRnumber: 95c:11004
MRreviewer: David Lee Hilliker
bibdate: Wed Dec 3 17:17:33 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.12.03 17:17:33 MST
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: https://www.jstor.org/journals/00029890.htm
rawauthor: Stephen M. Turner
rawtitle: Square roots mod $p$
entry:
@Article{Turner:1994:SRM,
  author =       "Stephen M. Turner",
  title =        "Square roots mod $p$",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "101",
  number =       "5",
  pages =        "443--449",
  month =        may,
  year =         "1994",
  CODEN =        "AMMYAE",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  MRclass =      "11A07",
  MRnumber =     "95c:11004",
  MRreviewer =   "David Lee Hilliker",
  bibdate =      "Wed Dec 3 17:17:33 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "https://www.jstor.org/journals/00029890.htm",
}


bibtype: article
filename: fparith.bib
label: Tydeman:1994:WCT
author: Fred Tydeman
title: What causes a Trap in IEEE-754 Floating-Point?
journal: j-SIGNUM
volume: 29
number: 1
pages: 2--4
month: jan
monthnumber: 1
year: 1994
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:24 MDT 2005
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 07:50:24 MDT
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
journalURL: https://dl.acm.org/loi/signum
thesaurus: Digital arithmetic; Standards
rawauthor: Fred Tydeman
rawtitle: What causes a Trap in {IEEE-754} Floating-Point?
abstract:
In the ANSI/IEEE Std 754-1985 (IEEE standard for binary floating-point arithmetic), and the ANSI/IEEE Std 854-1987 (IEEE standard for radix-independent floating-point arithmetic), is signaling a trap an `edge-triggered' or a `level-sensitive' event? The authors discusses the question: Does it matter if an exception is signaled by an arithmetic operation versus a user setting a status flag?.

keywords:
ANSI/IEEE Std 754-1985; ANSI/IEEE Std 854-1987; Binary floating-point arithmetic; Exception; IEEE standard; Radix-independent floating-point arithmetic

rawabstract:
In the ANSI/IEEE Std 754-1985 (IEEE standard for binary floating-point arithmetic), and the ANSI/IEEE Std 854-1987 (IEEE standard for radix-independent floating-point arithmetic), is signaling a trap an `edge-triggered' or a `level-sensitive' event? The authors discusses the question: Does it matter if an exception is signaled by an arithmetic operation versus a user setting a status flag?.

entry:
@Article{Tydeman:1994:WCT,
  author =       "Fred Tydeman",
  title =        "What causes a Trap in {IEEE-754} Floating-Point?",
  journal =      j-SIGNUM,
  volume =       "29",
  number =       "1",
  pages =        "2--4",
  month =        jan,
  year =         "1994",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:24 MDT 2005",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the ANSI/IEEE Std 754-1985 (IEEE standard for
                 binary floating-point arithmetic), and the ANSI/IEEE
                 Std 854-1987 (IEEE standard for radix-independent
                 floating-point arithmetic), is signaling a trap an
                 `edge-triggered' or a `level-sensitive' event? The
                 authors discusses the question: Does it matter if an
                 exception is signaled by an arithmetic operation versus
                 a user setting a status flag?.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classification = "C5230 (Digital arithmetic methods)",
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "https://dl.acm.org/loi/signum",
  keywords =     "ANSI/IEEE Std 754-1985; ANSI/IEEE Std 854-1987; Binary
                 floating-point arithmetic; Exception; IEEE standard;
                 Radix-independent floating-point arithmetic",
  thesaurus =    "Digital arithmetic; Standards",
}


bibtype: article
filename: fparith.bib
label: Upton:1994:RAH
author: Michael Upton and Thomas Huff and Trevor Mudge and Richard Brown
title: Resource allocation in a high clock rate microprocessor
journal: j-SIGPLAN
volume: 29
number: 11
pages: 98--109
month: nov
monthnumber: 11
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:57 MST 2003
bibtimestamp: 2003.12.14 09:16:57 MST
URL: http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p98-upton/
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng. and Computer Science, Michigan University, Ann Arbor, MI, USA
corpsource: Department of Electr. Eng. and Computer Science, Michigan University, Ann Arbor, MI, USA
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: P Practical; T Theoretical or Mathematical
rawauthor: Michael Upton and Thomas Huff and Trevor Mudge and Richard Brown
rawtitle: Resource allocation in a high clock rate microprocessor
bibsource:
http://portal.acm.org/; http://www.acm.org/pubs/toc/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This paper discusses the design of a high clock rate (300 MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.

keywords:
computer architecture; Cost model; cost model; design; floating point arithmetic; Floating point latency; floating point latency; High clock rate microprocessor; high clock rate microprocessor; measurement; microprocessor chips; Nonblocking cache; nonblocking cache; On-chip memories; on-chip memories; performance; performance evaluation; Pipelining; pipelining; Prefetching; prefetching; Processor model performance; processor model performance; Resource allocation; resource allocation; theory; Trace-driven simulation; trace-driven simulation; virtual machines

subject:
bf C.1.2 Computer Systems Organization, PROCESSOR ARCHITECTURES, Multiple Data Stream Architectures (Multiprocessors), Pipeline processors**. bf D.4.2 Software, OPERATING SYSTEMS, Storage Management, Allocation/deallocation strategies. bf C.4 Computer Systems Organization, PERFORMANCE OF SYSTEMS.

thesaurus:
Computer architecture; Floating point arithmetic; Microprocessor chips; Performance evaluation; Resource allocation; Virtual machines

rawabstract:
This paper discusses the design of a high clock rate (300 MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.

entry:
@Article{Upton:1994:RAH,
  author =       "Michael Upton and Thomas Huff and Trevor Mudge and
                 Richard Brown",
  title =        "Resource allocation in a high clock rate
                 microprocessor",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "11",
  pages =        "98--109",
  month =        nov,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:57 MST 2003",
  bibsource =    "http://portal.acm.org/; http://www.acm.org/pubs/toc/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p98-upton/",
  abstract =     "This paper discusses the design of a high clock rate
                 (300 MHz) processor. The architecture is described, and
                 the goals for the design are explained. The performance
                 of three processor models is evaluated using
                 trace-driven simulation. A cost model is used to
                 estimate the resources required to build processors
                 with varying sizes of on-chip memories, in both single
                 and dual issue models. Recommendations are then made to
                 increase the effectiveness of each of the models.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng. and Computer Science,
                 Michigan University, Ann Arbor, MI, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods);
                 C6150J (Operating systems)",
  confdate =     "4-7 Oct. 1994",
  conflocation = "San Jose, CA, USA; 4--7 Oct. 1994",
  confsponsor =  "ACM; IEEE Comput. Soc",
  conftitle =    "Sixth International Conference on Architectural
                 Support for Programming Languages and Operating Systems
                 (ASPLOS-VI)",
  corpsource =   "Department of Electr. Eng. and Computer Science,
                 Michigan University, Ann Arbor, MI, USA",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "computer architecture; Cost model; cost model; design;
                 floating point arithmetic; Floating point latency;
                 floating point latency; High clock rate microprocessor;
                 high clock rate microprocessor; measurement;
                 microprocessor chips; Nonblocking cache; nonblocking
                 cache; On-chip memories; on-chip memories; performance;
                 performance evaluation; Pipelining; pipelining;
                 Prefetching; prefetching; Processor model performance;
                 processor model performance; Resource allocation;
                 resource allocation; theory; Trace-driven simulation;
                 trace-driven simulation; virtual machines",
  sponsororg =   "ACM; IEEE Comput. Soc",
  subject =      "{\bf C.1.2} Computer Systems Organization, PROCESSOR
                 ARCHITECTURES, Multiple Data Stream Architectures
                 (Multiprocessors), Pipeline processors**. {\bf D.4.2}
                 Software, OPERATING SYSTEMS, Storage Management,
                 Allocation/deallocation strategies. {\bf C.4} Computer
                 Systems Organization, PERFORMANCE OF SYSTEMS.",
  thesaurus =    "Computer architecture; Floating point arithmetic;
                 Microprocessor chips; Performance evaluation; Resource
                 allocation; Virtual machines",
  treatment =    "P Practical; T Theoretical or Mathematical",
}


bibtype: book
filename: fparith.bib
label: vanSomeren:1994:ARC
author: Alex van Someren and Carol Atack
title: The ARM RISC Chip: a Programmer's Guide
publisher: pub-AW
address: pub-AW:adr
pages: xviii + 346
year: 1994
ISBN: 0-201-62410-9 OR 0201624109
ISBN13: 978-0-201-62410-6 OR 9780201624106
LCCN: QA76.5.V275 1994
bibdate: Wed Sep 14 22:16:36 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 22:16:36 ???
acknowledgement: ack-nhfb
rawauthor: Alex {van Someren} and Carol Atack
rawtitle: The {ARM RISC} Chip: a Programmer's Guide
entry:
@Book{vanSomeren:1994:ARC,
  author =       "Alex {van Someren} and Carol Atack",
  title =        "The {ARM RISC} Chip: a Programmer's Guide",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xviii + 346",
  year =         "1994",
  ISBN =         "0-201-62410-9",
  ISBN-13 =      "978-0-201-62410-6",
  LCCN =         "QA76.5.V275 1994",
  bibdate =      "Wed Sep 14 22:16:36 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Vinnakota:1994:FCTa
author: B. Vinnakota and V. V. Bapeswara Rao
title: Fast conversion techniques for binary-residue number systems
journal: j-IEEE-TRANS-CIRCUITS-SYST-I-FUNDAM-THEORY-APPL
volume: 41
number: 12
pages: 927--929
month: dec
monthnumber: 12
year: 1994
CODEN: ITCAEX
DOI: https://doi.org/10.1109/81.340862
ISSNL: 1057-7122 OR 10577122
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7979
fjournal: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=81
rawauthor: B. Vinnakota and V. V. Bapeswara Rao
rawtitle: Fast conversion techniques for binary-residue number systems
entry:
@Article{Vinnakota:1994:FCTa,
  author =       "B. Vinnakota and V. V. Bapeswara Rao",
  title =        "Fast conversion techniques for binary-residue number
                 systems",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-I-FUNDAM-THEORY-APPL,
  volume =       "41",
  number =       "12",
  pages =        "927--929",
  month =        dec,
  year =         "1994",
  CODEN =        "ITCAEX",
  DOI =          "https://doi.org/10.1109/81.340862",
  ISSN =         "????",
  ISSN-L =       "1057-7122",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7979",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I:
                 Fundamental Theory and Applications",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=81",
  keywords =     "residue arithmetic; residue number system",
  summary =      "An easy and efficient procedure for converting a
                 binary number into a residue number on moduli 2 n -1, 2
                 n, 2 n+1 is presented. The procedure presented reveals
                 an inversion technique. The paper also includes a
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Vinnakota:1994:FCTb
author: B. Vinnakota and V. V. Bapeswara Rao
title: Fast conversion techniques for binary-residue number systems
journal: j-IEEE-TRANS-CIRCUITS-SYST-I-FUNDAM-THEORY-APPL
volume: 41
number: 12
pages: 927--929
month: dec
monthnumber: 12
year: 1994
CODEN: ITCAEX
DOI: https://doi.org/10.1109/81.340862
ISSNL: 1057-7122 OR 10577122
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7979
fjournal: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=81
rawauthor: B. Vinnakota and V. V. Bapeswara Rao
rawtitle: Fast conversion techniques for binary-residue number systems
entry:
@Article{Vinnakota:1994:FCTb,
  author =       "B. Vinnakota and V. V. Bapeswara Rao",
  title =        "Fast conversion techniques for binary-residue number
                 systems",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-I-FUNDAM-THEORY-APPL,
  volume =       "41",
  number =       "12",
  pages =        "927--929",
  month =        dec,
  year =         "1994",
  CODEN =        "ITCAEX",
  DOI =          "https://doi.org/10.1109/81.340862",
  ISSN =         "????",
  ISSN-L =       "1057-7122",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7979",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I:
                 Fundamental Theory and Applications",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=81",
  keywords =     "residue arithmetic; residue number system",
  summary =      "An easy and efficient procedure for converting a
                 binary number into a residue number on moduli 2 n -1, 2
                 n, 2 n+1 is presented. The procedure presented reveals
                 an inversion technique. The paper also includes a
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Vinnakota:1994:SBR
author: B. Vinnakota
title: Selection of bases for a residue number system
journal: j-ELECT-LETTERS
volume: 30
number: 11
pages: 836--837
day: 26
month: may
monthnumber: 5
year: 1994
CODEN: ELLEAK
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7164
fjournal: Electronics Letters
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: B. Vinnakota
rawtitle: Selection of bases for a residue number system
entry:
@Article{Vinnakota:1994:SBR,
  author =       "B. Vinnakota",
  title =        "Selection of bases for a residue number system",
  journal =      j-ELECT-LETTERS,
  volume =       "30",
  number =       "11",
  pages =        "836--837",
  day =          "26",
  month =        may,
  year =         "1994",
  CODEN =        "ELLEAK",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7164",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
  keywords =     "residue arithmetic; residue number system",
  summary =      "A procedure is presented for selecting the bases in a
                 residue number system (RNS) for which the conversion
                 procedure from RNS to decimal is simple. The conversion
                 procedure is not based on the Chinese remainder
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Vuillemin:1994:CN
author: Jean E. Vuillemin
title: On Circuits and Numbers
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 868--879
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295849
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jean E. Vuillemin
rawtitle: On Circuits and Numbers
entry:
@Article{Vuillemin:1994:CN,
  author =       "Jean E. Vuillemin",
  title =        "On Circuits and Numbers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "868--879",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295849",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Walker:1994:SMA
author: W. J. Walker
title: A summability method for the arithmetic Fourier transform
journal: j-BIT
volume: 34
number: 2
pages: 304--309
month: jun
monthnumber: 6
year: 1994
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/BF01955877
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
MRclass: 42A99 (65T20)
MRnumber: 97i:42010
bibdate: Wed Jan 4 18:52:23 MST 2006
bibtimestamp: 2006.01.04 18:52:23 MST
fjournal: BIT (Nordisk tidskrift for informationsbehandling)
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: W. J. Walker
rawtitle: A summability method for the arithmetic {Fourier} transform
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=34&issue=2; https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www.mai.liu.se/BIT/contents/bit34.html; http://www.springerlink.com/openurl.asp?genre=article&issn=0006-3835&volume=34&issue=2&spage=304

entry:
@Article{Walker:1994:SMA,
  author =       "W. J. Walker",
  title =        "A summability method for the arithmetic {Fourier}
                 transform",
  journal =      j-BIT,
  volume =       "34",
  number =       "2",
  pages =        "304--309",
  month =        jun,
  year =         "1994",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/BF01955877",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  MRclass =      "42A99 (65T20)",
  MRnumber =     "97i:42010",
  bibdate =      "Wed Jan 4 18:52:23 MST 2006",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=34&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.mai.liu.se/BIT/contents/bit34.html;
                 http://www.springerlink.com/openurl.asp?genre=article&issn=0006-3835&volume=34&issue=2&spage=304",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT (Nordisk tidskrift for informationsbehandling)",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: techreport
filename: fparith.bib
label: Walters:1994:CTR
author: H. R. Walters
title: A Complete Term Rewriting System for Decimal Integer Arithmetic
type: Technical report
number: CS-9435
institution: Centrum voor Wiskunde en Informatica (CWI)
address: Amsterdam, The Netherlands
pages: 9
month: aug
monthnumber: 8
year: 1994
bibdate: Fri Nov 28 19:36:09 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 19:36:09 ???
acknowledgement: ack-mfc
rawauthor: H. R. Walters
rawtitle: A Complete Term Rewriting System for Decimal Integer Arithmetic
abstract:
We present a term rewriting system for decimal integers with addition and subtraction. We prove that the system is confluent and terminating.

rawabstract:
We present a term rewriting system for decimal integers with addition and subtraction. We prove that the system is confluent and terminating.

entry:
@TechReport{Walters:1994:CTR,
  author =       "H. R. Walters",
  title =        "A Complete Term Rewriting System for Decimal Integer
                 Arithmetic",
  type =         "Technical report",
  number =       "CS-9435",
  institution =  "Centrum voor Wiskunde en Informatica (CWI)",
  address =      "Amsterdam, The Netherlands",
  pages =        "9",
  month =        aug,
  year =         "1994",
  bibdate =      "Fri Nov 28 19:36:09 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a term rewriting system for decimal
                 integers with addition and subtraction. We prove that
                 the system is confluent and terminating.",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Wang:1994:MQF
title: Multiple Quadratic Forms: a Case Study in the Design of Data-Parallel Algorithms
journal: j-J-PAR-DIST-COMP
volume: 21
number: 1
pages: 124--139
month: apr
monthnumber: 4
year: 1994
CODEN: JPDCER
DOI: https://doi.org/10.1006/jpdc.1994.1046
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Thu Mar 9 09:18:54 MST 2000
bibtimestamp: 2000.03.09 09:18:54 MST
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Department of Computer Science, City University of New York, NY, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: P Practical
rawtitle: Multiple Quadratic Forms: a Case Study in the Design of Data-Parallel Algorithms
author:
Mu-Cheng Wang and Wayne G. Nation and James B. Armstrong and Howard Jay Siegel and Shin Dug Kim and Mark A. Nichols and Michael Gherrity

bibsource:
http://www.idealibrary.com/servlet/useragent?func=showAllIssues&curIssueID=jpdc; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1046/production; http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1046/production/pdf

keywords:
communication overhead; complex arithmetic operation count; complexity; computational complexity; data-parallel algorithms; MasPar; memory storage; MP-1; multiple quadratic forms; nCUBE 2; parallel algorithms; partitioning; PASM; real-time; systems

rawauthor:
Mu-Cheng Wang and Wayne G. Nation and James B. Armstrong and Howard Jay Siegel and Shin Dug Kim and Mark A. Nichols and Michael Gherrity

entry:
@Article{Wang:1994:MQF,
  author =       "Mu-Cheng Wang and Wayne G. Nation and James B.
                 Armstrong and Howard Jay Siegel and Shin Dug Kim and
                 Mark A. Nichols and Michael Gherrity",
  title =        "Multiple Quadratic Forms: a Case Study in the Design
                 of Data-Parallel Algorithms",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "21",
  number =       "1",
  pages =        "124--139",
  month =        apr,
  year =         "1994",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1006/jpdc.1994.1046",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Thu Mar 9 09:18:54 MST 2000",
  bibsource =    "http://www.idealibrary.com/servlet/useragent?func=showAllIssues&curIssueID=jpdc;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1046/production;
                 http://www.idealibrary.com/links/doi/10.1006/jpdc.1994.1046/production/pdf",
  acknowledgement = ack-nhfb,
  classification = "C4240P (Parallel programming and algorithm theory)",
  corpsource =   "Department of Computer Science, City University of New
                 York, NY, USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "communication overhead; complex arithmetic operation
                 count; complexity; computational complexity;
                 data-parallel algorithms; MasPar; memory storage; MP-1;
                 multiple quadratic forms; nCUBE 2; parallel algorithms;
                 partitioning; PASM; real-time; systems",
  treatment =    "P Practical",
}


bibtype: book
filename: fparith.bib
label: Weaver:1994:SAM
author: David L. Weaver and Tom Germond
title: The SPARC Architecture Manual: Version 9
publisher: pub-PHPTR
address: pub-PHPTR:adr
pages: xxii + 357
year: 1994
ISBN: 0-13-099227-5 OR 0130992275
ISBN13: 978-0-13-099227-7 OR 9780130992277
LCCN: QA76.9.A73S648 1992
bibdate: Fri Jul 22 08:37:56 1994
bibtimestamp: 1994.07.22 08:37:56 ???
URL: http://www.sparc.org/standards/SPARCV9.pdf
acknowledgement: ack-nhfb
rawauthor: David L. Weaver and Tom Germond
rawtitle: The {SPARC} Architecture Manual: Version 9
abstract:
SPARC (Scalable Processor Architecture) is the industry's only openly defined and evolved RISC architecture. Version 9 is the new 64-bit incarnation of SPARC --- the most significant change since SPARC's introduction in 1987! Unlike other RISC (Reduced Instruction Set Computer) designs, SPARC specifies not a hardware implementation (``chip''), but an open, standard architecture belonging to the community of SPARC vendors and users. The SPARC specification is defined by the SPARC Architecture Committee, a technical arm of the computer-maker consortium, SPARC International. Version 9 provides 64-bit data and addressing, support for fault tolerance, fast context switching, support for advanced compiler optimizations, efficient design for Superscalar processors, and a clean structure for modern operating systems. The V9 architecture supplements, rather than replaces, the 32-bit Version 8 architecture. The non-privileged features of Version 9 are upward-compatible from Version 8, so 32-bit application software can execute natively, without modification, on Version 9 systems no special ``compatibility mode'' is required. Publication of the Version 9 architecture marks a three-year development effort by SPARC International member companies from a broad cross-section of disciplines.

TOC:
Introduction Overview Definitions Architectural Overview Data Formats Registers Instructions Traps Memory Models (Normative) Instruction Definitions (Normative) IEEE 754-1985 Requirements for SPARC-V9 (Normative) SPARC-V9 Implementation Dependencies (Normative) Formal Specification of the Memory Models (Informative) Opcode Maps (Informative) SPARC-V9 MMU Requirements (Informative) Suggested Assembly Language Syntax (Informative) Software Considerations (Informative) Extending the SPARC-V9 Architecture (Informative) Programming With the Memory Models (Informative) Changes from SPARC-V8 to SPARC-V9 Bibliography Index

rawabstract:
SPARC (Scalable Processor Architecture) is the industry's only openly defined and evolved RISC architecture. Version 9 is the new 64-bit incarnation of SPARC --- the most significant change since SPARC's introduction in 1987! Unlike other RISC (Reduced Instruction Set Computer) designs, SPARC specifies not a hardware implementation (``chip''), but an open, standard architecture belonging to the community of SPARC vendors and users. The SPARC specification is defined by the SPARC Architecture Committee, a technical arm of the computer-maker consortium, SPARC International. Version 9 provides 64-bit data and addressing, support for fault tolerance, fast context switching, support for advanced compiler optimizations, efficient design for Superscalar processors, and a clean structure for modern operating systems. The V9 architecture supplements, rather than replaces, the 32-bit Version 8 architecture. The non-privileged features of Version 9 are upward-compatible from Version 8, so 32-bit application software can execute natively, without modification, on Version 9 systems no special ``compatibility mode'' is required. Publication of the Version 9 architecture marks a three-year development effort by SPARC International member companies from a broad cross-section of disciplines.

rawTOC:
Introduction \\ Overview \\ Definitions \\ Architectural Overview \\ Data Formats \\ Registers \\ Instructions \\ Traps \\ Memory Models \\ (Normative) Instruction Definitions \\ (Normative) IEEE 754-1985 Requirements for SPARC-V9 \\ (Normative) SPARC-V9 Implementation Dependencies \\ (Normative) Formal Specification of the Memory Models \\ (Informative) Opcode Maps \\ (Informative) SPARC-V9 MMU Requirements \\ (Informative) Suggested Assembly Language Syntax \\ (Informative) Software Considerations \\ (Informative) Extending the SPARC-V9 Architecture \\ (Informative) Programming With the Memory Models \\ (Informative) Changes from SPARC-V8 to SPARC-V9 \\ Bibliography \\ Index

entry:
@Book{Weaver:1994:SAM,
  author =       "David L. Weaver and Tom Germond",
  title =        "The {SPARC} Architecture Manual: Version 9",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "xxii + 357",
  year =         "1994",
  ISBN =         "0-13-099227-5",
  ISBN-13 =      "978-0-13-099227-7",
  LCCN =         "QA76.9.A73S648 1992",
  bibdate =      "Fri Jul 22 08:37:56 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$33.00",
  URL =          "http://www.sparc.org/standards/SPARCV9.pdf",
  abstract =     "SPARC (Scalable Processor Architecture) is the
                 industry's only openly defined and evolved RISC
                 architecture. Version 9 is the new 64-bit incarnation
                 of SPARC --- the most significant change since SPARC's
                 introduction in 1987! Unlike other RISC (Reduced
                 Instruction Set Computer) designs, SPARC specifies not
                 a hardware implementation (``chip''), but an open,
                 standard architecture belonging to the community of
                 SPARC vendors and users. The SPARC specification is
                 defined by the SPARC Architecture Committee, a
                 technical arm of the computer-maker consortium, SPARC
                 International. Version 9 provides 64-bit data and
                 addressing, support for fault tolerance, fast context
                 switching, support for advanced compiler optimizations,
                 efficient design for Superscalar processors, and a
                 clean structure for modern operating systems. The V9
                 architecture supplements, rather than replaces, the
                 32-bit Version 8 architecture. The non-privileged
                 features of Version 9 are upward-compatible from
                 Version 8, so 32-bit application software can execute
                 natively, without modification, on Version 9 systems no
                 special ``compatibility mode'' is required. Publication
                 of the Version 9 architecture marks a three-year
                 development effort by SPARC International member
                 companies from a broad cross-section of disciplines.",
  acknowledgement = ack-nhfb,
  tableofcontents = "Introduction \\
                 Overview \\
                 Definitions \\
                 Architectural Overview \\
                 Data Formats \\
                 Registers \\
                 Instructions \\
                 Traps \\
                 Memory Models \\
                 (Normative) Instruction Definitions \\
                 (Normative) IEEE 754-1985 Requirements for SPARC-V9 \\
                 (Normative) SPARC-V9 Implementation Dependencies \\
                 (Normative) Formal Specification of the Memory Models
                 \\
                 (Informative) Opcode Maps \\
                 (Informative) SPARC-V9 MMU Requirements \\
                 (Informative) Suggested Assembly Language Syntax \\
                 (Informative) Software Considerations \\
                 (Informative) Extending the SPARC-V9 Architecture \\
                 (Informative) Programming With the Memory Models \\
                 (Informative) Changes from SPARC-V8 to SPARC-V9 \\
                 Bibliography \\
                 Index",
}


bibtype: inproceedings
filename: fparith.bib
label: Wei:1994:REF
author: D.-Y. D. Wei and J. H. Kim and T. R. N. Rao
booktitle: Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 74--82
year: 1994
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
keywords: floating-point testing
acknowledgement: ack-nhfb
rawauthor: D.-Y. D. Wei and J. H. Kim and T. R. N. Rao
title:
Roundoff error-free tests in algorithm-based fault tolerant matrix operations on $2$-D processor arrays

rawbooktitle:
Proceedings of the {IEEE} International Workshop on Defect and Fault Tolerance in {VLSI} Systems, 1994

rawtitle:
Roundoff error-free tests in algorithm-based fault tolerant matrix operations on {$2$-D} processor arrays

entry:
@InProceedings{Wei:1994:REF,
  author =       "D.-Y. D. Wei and J. H. Kim and T. R. N. Rao",
  booktitle =    "Proceedings of the {IEEE} International Workshop on
                 Defect and Fault Tolerance in {VLSI} Systems, 1994",
  title =        "Roundoff error-free tests in algorithm-based fault
                 tolerant matrix operations on {$2$-D} processor
                 arrays",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "74--82",
  year =         "1994",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point testing",
  summary =      "Assaad and Dutt [1992] proposed the hybrid checksum
                 test method for the floating-point matrix-matrix
                 multiplication in ABFT environment, by which the error
                 coverage can be greatly increased. However, the
                 threshold test in their approach is still \ldots{}",
}


bibtype: book
filename: fparith.bib
label: Weiss:1994:PPP
author: Shlomo Weiss and James E. Smith
title: Power and PowerPC: Principles, Architecture, Implementation
publisher: pub-MORGAN-KAUFMANN
address: pub-MORGAN-KAUFMANN:adr
pages: xvi + 408
year: 1994
ISBN: 1-55860-279-8 OR 1558602798
ISBN13: 978-1-55860-279-3 OR 9781558602793
LCCN: QA76.8.P67 W45 1994
bibdate: Wed Aug 10 10:06:55 1994
bibtimestamp: 1994.08.10 10:06:55 ???
acknowledgement: ack-nhfb
rawauthor: Shlomo Weiss and James E. Smith
rawtitle: {Power} and {PowerPC}: Principles, Architecture, Implementation
TOC:
Foreword by Michael Slater Preface Modern Computer Design Concepts / 1 POWER Architecture / 31 POWER Implementation: Pipelines / 71 POWER1 Implementation / 97 POWER1 Implementation: Cache Memories / 115 POWER2: The Next Generation / 135 PowerPC Architecture / 173 PowerPC 601 Implementation / 223 PowerPC: Support for Multiprocessing / 253 System Organization / 271 PowerPC 601 and Alpha 21064 / 305 App. A. IEEE 754 Floating-Point Standard / 333 App. B. POWER Instruction Formats / 341 App. C. POWER Instruction Set Sorted by Mnemonic / 349 App. D. PowerPC Instruction Formats / 355 App. E. PowerPC Instruction Set Sorted by Mnemonic / 365 App. F. Cross Reference for Changed POWER Mnemonics / 377 Bibliography / 383 Index / 391

rawTOC:
Foreword by Michael Slater \\ Preface \\ Modern Computer Design Concepts / 1 \\ POWER Architecture / 31 \\ POWER Implementation: Pipelines / 71 \\ POWER1 Implementation / 97 \\ POWER1 Implementation: Cache Memories / 115 \\ POWER2: The Next Generation / 135 \\ PowerPC Architecture / 173 \\ PowerPC 601 Implementation / 223 \\ PowerPC: Support for Multiprocessing / 253 \\ System Organization / 271 \\ PowerPC 601 and Alpha 21064 / 305 \\ App. A. IEEE 754 Floating-Point Standard / 333 \\ App. B. POWER Instruction Formats / 341 \\ App. C. POWER Instruction Set Sorted by Mnemonic / 349 \\ App. D. PowerPC Instruction Formats / 355 \\ App. E. PowerPC Instruction Set Sorted by Mnemonic / 365 \\ App. F. Cross Reference for Changed POWER Mnemonics / 377 \\ Bibliography / 383 \\ Index / 391

entry:
@Book{Weiss:1994:PPP,
  author =       "Shlomo Weiss and James E. Smith",
  title =        "{Power} and {PowerPC}: Principles, Architecture,
                 Implementation",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xvi + 408",
  year =         "1994",
  ISBN =         "1-55860-279-8",
  ISBN-13 =      "978-1-55860-279-3",
  LCCN =         "QA76.8.P67 W45 1994",
  bibdate =      "Wed Aug 10 10:06:55 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$54.95",
  acknowledgement = ack-nhfb,
  tableofcontents = "Foreword by Michael Slater \\
                 Preface \\
                 Modern Computer Design Concepts / 1 \\
                 POWER Architecture / 31 \\
                 POWER Implementation: Pipelines / 71 \\
                 POWER1 Implementation / 97 \\
                 POWER1 Implementation: Cache Memories / 115 \\
                 POWER2: The Next Generation / 135 \\
                 PowerPC Architecture / 173 \\
                 PowerPC 601 Implementation / 223 \\
                 PowerPC: Support for Multiprocessing / 253 \\
                 System Organization / 271 \\
                 PowerPC 601 and Alpha 21064 / 305 \\
                 App. A. IEEE 754 Floating-Point Standard / 333 \\
                 App. B. POWER Instruction Formats / 341 \\
                 App. C. POWER Instruction Set Sorted by Mnemonic / 349
                 \\
                 App. D. PowerPC Instruction Formats / 355 \\
                 App. E. PowerPC Instruction Set Sorted by Mnemonic /
                 365 \\
                 App. F. Cross Reference for Changed POWER Mnemonics /
                 377 \\
                 Bibliography / 383 \\
                 Index / 391",
}


bibtype: article
filename: fparith.bib
label: White:1994:PNG
author: S. W. White and S. Dhawan
title: POWER2: Next generation of the RISC System / 6000 family
journal: j-IBM-JRD
volume: 38
number: 5
pages: 493--502
month: sep
monthnumber: 9
year: 1994
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Tue Mar 25 14:26:59 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.03.25 14:26:59 MST
URL: http://www.almaden.ibm.com/journal/rd38-5.html#two
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
affiliation: IBM Corp., Austin, TX, USA
corpsource: IBM Corp., Austin, TX, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
treatment: P Practical
rawauthor: S. W. White and S. Dhawan
rawtitle: {POWER2}: {Next} generation of the {RISC System\slash 6000} family
abstract:
Since its announcement, the IBM RISC System / 6000* processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and speed floating-point-to-integer conversion. The implementation, which exploits these extensions and doubles the number of functional units, is also described. A comparison of performance results on a variety of industry standard benchmarks demonstrates that superscalar capabilities are an attractive alternative to aggressive clock rates.

keywords:
bandwidth; evaluation; floating-point-to-; Floating-point-to-integer conversion; Floating-point-to-integer conversion, POWER2; IBM RISC System/6000 processor; IBM RISC System / 6000 processor; instruction-level; Instruction-level parallelism; integer conversion; microprocessor chips; parallel architectures; parallelism; performance; POWER2; reduced instruction set computing; Square-root computation; square-root computation; storage reference; Storage reference bandwidth; superscalar capability; Superscalar capability

classcodes:
B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5220P (Parallel architecture); C5470 (Performance evaluation and testing)

thesaurus:
Microprocessor chips; Parallel architectures; Performance evaluation; Reduced instruction set computing

rawabstract:
Since its announcement, the IBM RISC System\slash 6000* processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and speed floating-point-to-integer conversion. The implementation, which exploits these extensions and doubles the number of functional units, is also described. A comparison of performance results on a variety of industry standard benchmarks demonstrates that superscalar capabilities are an attractive alternative to aggressive clock rates.

entry:
@Article{White:1994:PNG,
  author =       "S. W. White and S. Dhawan",
  title =        "{POWER2}: {Next} generation of the {RISC System\slash
                 6000} family",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "493--502",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#two",
  abstract =     "Since its announcement, the IBM RISC System\slash
                 6000* processor has characterized the aggressive
                 instruction-level parallelism approach to achieving
                 performance. Recent enhancements to the architecture
                 and implementation provide greater superscalar
                 capability. This paper describes the architectural
                 extensions which improve storage reference bandwidth,
                 allow hardware square-root computation, and speed
                 floating-point-to-integer conversion. The
                 implementation, which exploits these extensions and
                 doubles the number of functional units, is also
                 described. A comparison of performance results on a
                 variety of industry standard benchmarks demonstrates
                 that superscalar capabilities are an attractive
                 alternative to aggressive clock rates.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel architecture);
                 C5470 (Performance evaluation and testing)",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel architecture);
                 C5470 (Performance evaluation and testing)",
  corpsource =   "IBM Corp., Austin, TX, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "bandwidth; evaluation; floating-point-to-;
                 Floating-point-to-integer conversion;
                 Floating-point-to-integer conversion, POWER2; IBM RISC
                 System/6000 processor; IBM RISC System\slash 6000
                 processor; instruction-level; Instruction-level
                 parallelism; integer conversion; microprocessor chips;
                 parallel architectures; parallelism; performance;
                 POWER2; reduced instruction set computing; Square-root
                 computation; square-root computation; storage
                 reference; Storage reference bandwidth; superscalar
                 capability; Superscalar capability",
  thesaurus =    "Microprocessor chips; Parallel architectures;
                 Performance evaluation; Reduced instruction set
                 computing",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Wichmann:1994:CSP
author: B. A. Wichmann
title: Contribution of standard programming languages to software quality
journal: j-SEJ
volume: 9
number: 1
pages: 3--12
month: jan
monthnumber: 1
year: 1994
CODEN: SEJOED
ISSN: 0268-6961 OR 02686961
bibdate: Sun Mar 15 17:49:58 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.03.15 17:49:58 ???
fjournal: Software Engineering Journal
remark: Brief mention of floating-point issues in software validation.
acknowledgement: ack-nhfb
rawauthor: B. A. Wichmann
rawtitle: Contribution of standard programming languages to software quality
entry:
@Article{Wichmann:1994:CSP,
  author =       "B. A. Wichmann",
  title =        "Contribution of standard programming languages to
                 software quality",
  journal =      j-SEJ,
  volume =       "9",
  number =       "1",
  pages =        "3--12",
  month =        jan,
  year =         "1994",
  CODEN =        "SEJOED",
  ISSN =         "0268-6961",
  bibdate =      "Sun Mar 15 17:49:58 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Software Engineering Journal",
  remark =       "Brief mention of floating-point issues in software
                 validation.",
}


bibtype: misc
filename: fparith.bib
label: Williams:1994:MAM
author: T. Williams
pages: 3--12
day: 13
month: sep
monthnumber: 9
year: 1994
bibdate: Fri Nov 28 15:24:41 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 15:24:41 ???
note: U.S. Patent No. 5,347,481.
acknowledgement: ack-nhfb
rawauthor: T. Williams
rawnote: U.S. Patent No. 5,347,481.
title:
Method and apparatus for multiplying denormalized binary floating point numbers without additional delay

rawtitle:
Method and apparatus for multiplying denormalized binary floating point numbers without additional delay

entry:
@Misc{Williams:1994:MAM,
  author =       "T. Williams",
  title =        "Method and apparatus for multiplying denormalized
                 binary floating point numbers without additional
                 delay",
  day =          "13",
  month =        sep,
  year =         "1994",
  bibdate =      "Fri Nov 28 15:24:41 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 5,347,481.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Wong:1994:FEE
author: W. F. Wong and E. Goto
title: Fast evaluation of the elementary functions in double precision
crossref: Mudge:1994:PTS
pages: 349--358
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: Department of Inf. Syst. and Computer Science, Nat. University of Singapore, Singapore
thesaurus: Digital arithmetic; Polynomials; Table lookup
rawauthor: W. F. Wong and E. Goto
rawtitle: Fast evaluation of the elementary functions in double precision
abstract:
One of the most spectacular development in computer technology is the growth in memory density and speed. It is with this development in mind that we intend to tackle the old problem of computing the elementary functions. Since the dawn of computing, the fast and accurate computation of the elementary functions has been a constant concern of numerical computing. It now seems possible to use tables of sizes in the range of megabits to aid in such computation. To this end, in this paper, we propose a method called ATA-M (Add-Table Lookup-Add with Multiplication) for evaluating polynomials with the aid of tables. When applied to the elementary functions, we obtained a set of algorithms which computes the reciprocal, square root, exponential, sine, cosine, logarithm, are tangent and the hyperbolic functions in about 3 to 4 double precision floating point multiplication time and utilizing about 2 Mbyte of tables.

keywords:
Add-Table Lookup-Add with Multiplication; ATA-M; Double precision; Elementary functions; Floating point multiplication time; Hyperbolic functions; Memory density; Memory speed; Numerical computing; Polynomials

rawabstract:
One of the most spectacular development in computer technology is the growth in memory density and speed. It is with this development in mind that we intend to tackle the old problem of computing the elementary functions. Since the dawn of computing, the fast and accurate computation of the elementary functions has been a constant concern of numerical computing. It now seems possible to use tables of sizes in the range of megabits to aid in such computation. To this end, in this paper, we propose a method called ATA-M (Add-Table Lookup-Add with Multiplication) for evaluating polynomials with the aid of tables. When applied to the elementary functions, we obtained a set of algorithms which computes the reciprocal, square root, exponential, sine, cosine, logarithm, are tangent and the hyperbolic functions in about 3 to 4 double precision floating point multiplication time and utilizing about 2 Mbyte of tables.

entry:
@InProceedings{Wong:1994:FEE,
  author =       "W. F. Wong and E. Goto",
  title =        "Fast evaluation of the elementary functions in double
                 precision",
  crossref =     "Mudge:1994:PTS",
  pages =        "349--358",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "One of the most spectacular development in computer
                 technology is the growth in memory density and speed.
                 It is with this development in mind that we intend to
                 tackle the old problem of computing the elementary
                 functions. Since the dawn of computing, the fast and
                 accurate computation of the elementary functions has
                 been a constant concern of numerical computing. It now
                 seems possible to use tables of sizes in the range of
                 megabits to aid in such computation. To this end, in
                 this paper, we propose a method called ATA-M (Add-Table
                 Lookup-Add with Multiplication) for evaluating
                 polynomials with the aid of tables. When applied to the
                 elementary functions, we obtained a set of algorithms
                 which computes the reciprocal, square root,
                 exponential, sine, cosine, logarithm, are tangent and
                 the hyperbolic functions in about 3 to 4 double
                 precision floating point multiplication time and
                 utilizing about 2 Mbyte of tables.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Inf. Syst. and Computer Science, Nat.
                 University of Singapore, Singapore",
  classification = "C4130 (Interpolation and function approximation);
                 C5230 (Digital arithmetic methods)",
  keywords =     "Add-Table Lookup-Add with Multiplication; ATA-M;
                 Double precision; Elementary functions; Floating point
                 multiplication time; Hyperbolic functions; Memory
                 density; Memory speed; Numerical computing;
                 Polynomials",
  thesaurus =    "Digital arithmetic; Polynomials; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Wong:1994:FHB
author: W. F. Wong and E. Goto
title: Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 3
pages: 278--294
month: mar
monthnumber: 3
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.272429
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 7 07:13:54 MDT 2011
bibtimestamp: 2011.07.07 07:13:54 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272429
fjournal: IEEE Transactions on Computers
language: English
acknowledgement: ack-nj
affiliation: Department of Inf. Syst. and Computer Science, Nat. University of Singapore, Singapore
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
thesaurus: Digital arithmetic; Error analysis
rawauthor: W. F. Wong and E. Goto
rawtitle: Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

abstract:
As the name suggests, elementary functions play a vital role in scientific computations. Yet due to their inherent nature, they are a considerable computing task by themselves. Not surprisingly, since the dawn of computing, the goal of speeding up elementary function computation has been pursued. This paper describes new hardware based algorithms for the computation of the common elementary functions, namely division, logarithm, reciprocal square root, arc tangent, sine and cosine. These algorithms exploit microscopic parallelism using specialized hardware with heavy use of truncation based on detailed accuracy analysis. The contribution of this work lies in the fact that these algorithms are very fast and yet are accurate. If we let the time to perform an IEEE Standard 754 double precision floating point multiplication be $ tau _times $, our algorithms to achieve roughly $ 3.68 tau _times $, $ 4.56 tau _times $, $ 5.25 tau _times $, $ 3.69 tau _times $, $ 7.06 tau _times $, and $ 6.5 tau _times $, for division, logarithm, square root, exponential, are tangent and complex exponential (sine and cosine) respectively. The trade-off is the need for tables and some specialized hardware. The total amount of tables required, however, is less than 128 Kbytes. We discuss the hardware, algorithmic and accuracy aspects of these algorithms.

keywords:
Arc tangent; Common elementary functions; Cosine; Elementary function computations; Floating point multiplication; Hardware-based algorithms; Microscopic parallelism; Reciprocal square root; Rectangular multipliers; Scientific computations; Sine

rawabstract:
As the name suggests, elementary functions play a vital role in scientific computations. Yet due to their inherent nature, they are a considerable computing task by themselves. Not surprisingly, since the dawn of computing, the goal of speeding up elementary function computation has been pursued. This paper describes new hardware based algorithms for the computation of the common elementary functions, namely division, logarithm, reciprocal square root, arc tangent, sine and cosine. These algorithms exploit microscopic parallelism using specialized hardware with heavy use of truncation based on detailed accuracy analysis. The contribution of this work lies in the fact that these algorithms are very fast and yet are accurate. If we let the time to perform an IEEE Standard 754 double precision floating point multiplication be $ \tau_\times $, our algorithms to achieve roughly $ 3.68 \tau_\times $, $ 4.56 \tau_\times $, $ 5.25 \tau_\times $, $ 3.69 \tau_\times $, $ 7.06 \tau_\times $, and $ 6.5 \tau_\times $, for division, logarithm, square root, exponential, are tangent and complex exponential (sine and cosine) respectively. The trade-off is the need for tables and some specialized hardware. The total amount of tables required, however, is less than 128 Kbytes. We discuss the hardware, algorithmic and accuracy aspects of these algorithms.

entry:
@Article{Wong:1994:FHB,
  author =       "W. F. Wong and E. Goto",
  title =        "Fast Hardware-Based Algorithms for Elementary Function
                 Computations Using Rectangular Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "3",
  pages =        "278--294",
  month =        mar,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.272429",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 7 07:13:54 MDT 2011",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=272429",
  abstract =     "As the name suggests, elementary functions play a
                 vital role in scientific computations. Yet due to their
                 inherent nature, they are a considerable computing task
                 by themselves. Not surprisingly, since the dawn of
                 computing, the goal of speeding up elementary function
                 computation has been pursued. This paper describes new
                 hardware based algorithms for the computation of the
                 common elementary functions, namely division,
                 logarithm, reciprocal square root, arc tangent, sine
                 and cosine. These algorithms exploit microscopic
                 parallelism using specialized hardware with heavy use
                 of truncation based on detailed accuracy analysis. The
                 contribution of this work lies in the fact that these
                 algorithms are very fast and yet are accurate. If we
                 let the time to perform an IEEE Standard 754 double
                 precision floating point multiplication be $
                 \tau_\times $, our algorithms to achieve roughly $ 3.68
                 \tau_\times $, $ 4.56 \tau_\times $, $ 5.25 \tau_\times
                 $, $ 3.69 \tau_\times $, $ 7.06 \tau_\times $, and $
                 6.5 \tau_\times $, for division, logarithm, square
                 root, exponential, are tangent and complex exponential
                 (sine and cosine) respectively. The trade-off is the
                 need for tables and some specialized hardware. The
                 total amount of tables required, however, is less than
                 128 Kbytes. We discuss the hardware, algorithmic and
                 accuracy aspects of these algorithms.",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  affiliation =  "Department of Inf. Syst. and Computer Science, Nat.
                 University of Singapore, Singapore",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C4110 (Error analysis in numerical methods); C5230
                 (Digital arithmetic methods)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Arc tangent; Common elementary functions; Cosine;
                 Elementary function computations; Floating point
                 multiplication; Hardware-based algorithms; Microscopic
                 parallelism; Reciprocal square root; Rectangular
                 multipliers; Scientific computations; Sine",
  language =     "English",
  pubcountry =   "USA",
  thesaurus =    "Digital arithmetic; Error analysis",
}


bibtype: article
filename: fparith.bib
label: Yang:1994:NIPa
author: Ming-Chwen Yang and Ja-Ling Wu
title: A new interpretation of ``polynomial residue number system''
journal: j-IEEE-TRANS-SIG-PROC
volume: 42
number: 8
pages: 2190--2191
month: aug
monthnumber: 8
year: 1994
CODEN: ITPRED
DOI: https://doi.org/10.1109/78.301857
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7453
fjournal: IEEE Transactions on Signal Processing
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Ming-Chwen Yang and Ja-Ling Wu
rawtitle: A new interpretation of ``polynomial residue number system''
entry:
@Article{Yang:1994:NIPa,
  author =       "Ming-Chwen Yang and Ja-Ling Wu",
  title =        "A new interpretation of ``polynomial residue number
                 system''",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "42",
  number =       "8",
  pages =        "2190--2191",
  month =        aug,
  year =         "1994",
  CODEN =        "ITPRED",
  DOI =          "https://doi.org/10.1109/78.301857",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7453",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors show that the polynomial residue number
                 system can be interpreted in terms of the Chinese
                 remainder theorem for polynomials (CRTP) over a finite
                 ring which is useful for signal \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Yang:1994:NIPb
author: Ming-Chwen Yang and Ja-Ling Wu
title: A new interpretation of ``polynomial residue number system''
journal: j-IEEE-TRANS-SIG-PROC
volume: 42
number: 8
pages: 2190--2191
month: aug
monthnumber: 8
year: 1994
CODEN: ITPRED
DOI: https://doi.org/10.1109/78.301857
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7453
fjournal: IEEE Transactions on Signal Processing
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Ming-Chwen Yang and Ja-Ling Wu
rawtitle: A new interpretation of ``polynomial residue number system''
entry:
@Article{Yang:1994:NIPb,
  author =       "Ming-Chwen Yang and Ja-Ling Wu",
  title =        "A new interpretation of ``polynomial residue number
                 system''",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "42",
  number =       "8",
  pages =        "2190--2191",
  month =        aug,
  year =         "1994",
  CODEN =        "ITPRED",
  DOI =          "https://doi.org/10.1109/78.301857",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7453",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors show that the polynomial residue number
                 system can be interpreted in terms of the Chinese
                 remainder theorem for polynomials (CRTP) over a finite
                 ring which is useful for signal \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Yuen:1994:PMC
author: C. K. Yuen and M. D. Feng
title: Parallel multiplication: a case study in parallel programming
journal: j-SIGPLAN
volume: 29
number: 3
pages: 12--17
month: mar
monthnumber: 3
year: 1994
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:16:48 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:16:48 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
corpsource: Department of Inf. Syst. and Computer Science, Nat. University of Singapore, Singapore
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
treatment: P Practical
rawauthor: C. K. Yuen and M. D. Feng
rawtitle: Parallel multiplication: a case study in parallel programming
keywords:
AND/OR parallel problems; bottom up design method; mathematics computing; parallel multiplication; parallel program; parallel programming; performance evaluation; program structure design; speculative processing; systems analysis; top down design method; tuplespace

entry:
@Article{Yuen:1994:PMC,
  author =       "C. K. Yuen and M. D. Feng",
  title =        "Parallel multiplication: a case study in parallel
                 programming",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "3",
  pages =        "12--17",
  month =        mar,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:48 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C6110P (Parallel programming); C7310 (Mathematics)",
  corpsource =   "Department of Inf. Syst. and Computer Science, Nat.
                 University of Singapore, Singapore",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "AND/OR parallel problems; bottom up design method;
                 mathematics computing; parallel multiplication;
                 parallel program; parallel programming; performance
                 evaluation; program structure design; speculative
                 processing; systems analysis; top down design method;
                 tuplespace",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhang:1994:EMR
author: Qihong Zhang and J. H. Kim
crossref: Lea:1994:PSA
pages: 32--39
year: 1994
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
acknowledgement: ack-nhfb
affiliation: Center for Adv. Comput. Studies, Southwestern Louisiana University, Lafayette, LA, USA
rawauthor: Qihong Zhang and J. H. Kim
title:
An efficient method to reduce roundoff error in matrix multiplication with algorithm-based fault tolerance

abstract:
Algorithm-Based Fault Tolerance (ABFT) schemes have been proposed by a number of researchers recently. Although all errors can be theoretically detected and corrected by using these techniques, some practical problems, especially the roundoff errors, degrade the performance drastically. In this paper, we proposed a new scheme called Extended Mantissa Checksum (EMC) test in which the mantissa of the product of two input matrices are divided into two sections and extended for faulty detection and correction. Using this scheme, the number of undetected errors and false alarms are decreased largely and the error coverage is improved significantly. In addition, the time latency is short and the hardware overhead is small compared with other schemes.

keywords:
Algorithm-based fault tolerance; correct rounding; Error coverage; Extended mantissa checksum test; False alarms; Fault correction; Fault detection; Floating point test; Hardware overhead; Matrix multiplication; Roundoff error; Time latency

thesaurus:
Algorithm theory; Digital arithmetic; Error correction; Error detection; Fault tolerant computing; Matrix algebra; Roundoff errors

rawabstract:
Algorithm-Based Fault Tolerance (ABFT) schemes have been proposed by a number of researchers recently. Although all errors can be theoretically detected and corrected by using these techniques, some practical problems, especially the roundoff errors, degrade the performance drastically. In this paper, we proposed a new scheme called Extended Mantissa Checksum (EMC) test in which the mantissa of the product of two input matrices are divided into two sections and extended for faulty detection and correction. Using this scheme, the number of undetected errors and false alarms are decreased largely and the error coverage is improved significantly. In addition, the time latency is short and the hardware overhead is small compared with other schemes.

rawtitle:
An efficient method to reduce roundoff error in matrix multiplication with algorithm-based fault tolerance

entry:
@InProceedings{Zhang:1994:EMR,
  author =       "Qihong Zhang and J. H. Kim",
  title =        "An efficient method to reduce roundoff error in matrix
                 multiplication with algorithm-based fault tolerance",
  crossref =     "Lea:1994:PSA",
  pages =        "32--39",
  year =         "1994",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Algorithm-Based Fault Tolerance (ABFT) schemes have
                 been proposed by a number of researchers recently.
                 Although all errors can be theoretically detected and
                 corrected by using these techniques, some practical
                 problems, especially the roundoff errors, degrade the
                 performance drastically. In this paper, we proposed a
                 new scheme called Extended Mantissa Checksum (EMC) test
                 in which the mantissa of the product of two input
                 matrices are divided into two sections and extended for
                 faulty detection and correction. Using this scheme, the
                 number of undetected errors and false alarms are
                 decreased largely and the error coverage is improved
                 significantly. In addition, the time latency is short
                 and the hardware overhead is small compared with other
                 schemes.",
  acknowledgement = ack-nhfb,
  affiliation =  "Center for Adv. Comput. Studies, Southwestern
                 Louisiana University, Lafayette, LA, USA",
  classification = "C1110 (Algebra); C4240P (Parallel programming and
                 algorithm theory); C5230 (Digital arithmetic methods)",
  keywords =     "Algorithm-based fault tolerance; correct rounding;
                 Error coverage; Extended mantissa checksum test; False
                 alarms; Fault correction; Fault detection; Floating
                 point test; Hardware overhead; Matrix multiplication;
                 Roundoff error; Time latency",
  thesaurus =    "Algorithm theory; Digital arithmetic; Error
                 correction; Error detection; Fault tolerant computing;
                 Matrix algebra; Roundoff errors",
}


bibtype: article
filename: fparith.bib
label: Zhang:1994:TDN
author: M. Zhang and J. G. Delgado-Frias and S. Vassiliadis
title: Table driven Newton scheme for high precision logarithm generation
journal: j-IEE-PROC-COMPUT-DIGIT-TECH
volume: 141
number: 5
pages: 281--292
month: sep
monthnumber: 9
year: 1994
CODEN: ICDTEA
ISSN: 1350-2387 (print), 1359-7027 (electronic) OR 13502387 (print), 13597027 (electronic)
ISSNL: 1350-2387 OR 13502387
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
fjournal: IEE Proceedings. Computers and Digital Techniques
acknowledgement: ack-nhfb
affiliation: McCaw Cellular Commun. Inc., Kirkland, WA, USA
thesaurus: Digital arithmetic; Iterative methods; Table lookup
rawauthor: M. Zhang and J. G. Delgado-Frias and S. Vassiliadis
rawtitle: Table driven {Newton} scheme for high precision logarithm generation
abstract:
Based on the Newton method, a table driven iterative scheme is proposed to compute the logarithm function. The proposed scheme provides high performance and high precision and it is implementable with currently available technologies. It is shown, assuming the availability of a parallel multiplier and an adder and the IEEE floating point format, that a computation delay of 12 machine cycles can be obtained with precision of 0.761*2/sup -53/ requiring 18432 bytes of read only memory (ROM). Based on performance and look-up table size estimations of other existing schemes also using table driven approaches a speed-up of over 1.5 for the proposed scheme can be obtained.

keywords:
12 Machine cycles; Adder; High precision logarithm generation; IEEE floating point format; Iterative scheme; Newton method; Parallel multiplier; Table driven

rawabstract:
Based on the Newton method, a table driven iterative scheme is proposed to compute the logarithm function. The proposed scheme provides high performance and high precision and it is implementable with currently available technologies. It is shown, assuming the availability of a parallel multiplier and an adder and the IEEE floating point format, that a computation delay of 12 machine cycles can be obtained with precision of 0.761*2/sup -53/ requiring 18432 bytes of read only memory (ROM). Based on performance and look-up table size estimations of other existing schemes also using table driven approaches a speed-up of over 1.5 for the proposed scheme can be obtained.

entry:
@Article{Zhang:1994:TDN,
  author =       "M. Zhang and J. G. Delgado-Frias and S. Vassiliadis",
  title =        "Table driven {Newton} scheme for high precision
                 logarithm generation",
  journal =      j-IEE-PROC-COMPUT-DIGIT-TECH,
  volume =       "141",
  number =       "5",
  pages =        "281--292",
  month =        sep,
  year =         "1994",
  CODEN =        "ICDTEA",
  ISSN =         "1350-2387 (print), 1359-7027 (electronic)",
  ISSN-L =       "1350-2387",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Based on the Newton method, a table driven iterative
                 scheme is proposed to compute the logarithm function.
                 The proposed scheme provides high performance and high
                 precision and it is implementable with currently
                 available technologies. It is shown, assuming the
                 availability of a parallel multiplier and an adder and
                 the IEEE floating point format, that a computation
                 delay of 12 machine cycles can be obtained with
                 precision of 0.761*2/sup -53/ requiring 18432 bytes of
                 read only memory (ROM). Based on performance and
                 look-up table size estimations of other existing
                 schemes also using table driven approaches a speed-up
                 of over 1.5 for the proposed scheme can be obtained.",
  acknowledgement = ack-nhfb,
  affiliation =  "McCaw Cellular Commun. Inc., Kirkland, WA, USA",
  classification = "C5230 (Digital arithmetic methods); C6130 (Data
                 handling techniques)",
  fjournal =     "IEE Proceedings. Computers and Digital Techniques",
  keywords =     "12 Machine cycles; Adder; High precision logarithm
                 generation; IEEE floating point format; Iterative
                 scheme; Newton method; Parallel multiplier; Table
                 driven",
  pubcountry =   "UK",
  thesaurus =    "Digital arithmetic; Iterative methods; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Zuras:1994:MSM
author: D. Zuras
title: More On Squaring and Multiplying Large Integers
journal: j-IEEE-TRANS-COMPUT
volume: 43
number: 8
pages: 899--908
month: aug
monthnumber: 8
year: 1994
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.295852
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon May 20 06:16:49 MDT 2002
bibtimestamp: 2002.05.20 06:16:49 MDT
fjournal: IEEE Transactions on Computers
remark: Selected revised and extended papers from ARITH'11 cite Swartzlander:1993:SCA.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Zuras
rawtitle: More On Squaring and Multiplying Large Integers
entry:
@Article{Zuras:1994:MSM,
  author =       "D. Zuras",
  title =        "More On Squaring and Multiplying Large Integers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "43",
  number =       "8",
  pages =        "899--908",
  month =        aug,
  year =         "1994",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.295852",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon May 20 06:16:49 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  remark =       "Selected revised and extended papers from ARITH'11
                 \cite{Swartzlander:1993:SCA}.",
}


bibtype: article
filename: fparith.bib
label: Zuse:1994:PPV
author: K. Zuse
title: Past and present view on computer architecture
journal: j-IFIP-TRANS-A
volume: A-52
pages: 248--250
year: 1994
CODEN: ITATEC
ISSN: 0926-5473 OR 09265473
bibdate: Tue Dec 12 09:29:07 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:29:07 MST
note: Applications and Impacts. Information Processing '94 IFIP 13th World Computer Congress.
fjournal: IFIP Transactions. A. Computer Science and Technology
acknowledgement: ack-nhfb
thesaurus: Computer architecture; Digital computers; History
rawauthor: K. Zuse
rawnote: Applications and Impacts. Information Processing '94 IFIP 13th World Computer Congress.
rawtitle: Past and present view on computer architecture
abstract:
The author discusses his work in developing binary instruction stream based computers. He chose the half-logarithmic form, where he stored only the exponent in a logarithmic notation, which is the same as the floating point numbers, used in today's computers. Following this principle, he developed new machines. He started with a mechanical working construction. This was a storage utility which was concentrated and enabled the storage of a thousand words. This storage device was completed in 1936. It occurred to him that one could also build this machine with electrical parts. First he built small computers, the model Z2 and immediately after this the model Z3, which was based entirely on relays. Both machines worked satisfactory. Then he discovered Boolean algebra. He could now design a computer on paper. He continued to develop machines and founded a company in Germany where a number of machines such as the Z11 were built.

keywords:
Binary instruction stream based computers; Boolean algebra; Computer architecture; Exponent; Floating point numbers; Half-logarithmic form; Storage device; Z11; Z2; Z3; ZUSE KG

rawabstract:
The author discusses his work in developing binary instruction stream based computers. He chose the half-logarithmic form, where he stored only the exponent in a logarithmic notation, which is the same as the floating point numbers, used in today's computers. Following this principle, he developed new machines. He started with a mechanical working construction. This was a storage utility which was concentrated and enabled the storage of a thousand words. This storage device was completed in 1936. It occurred to him that one could also build this machine with electrical parts. First he built small computers, the model Z2 and immediately after this the model Z3, which was based entirely on relays. Both machines worked satisfactory. Then he discovered Boolean algebra. He could now design a computer on paper. He continued to develop machines and founded a company in Germany where a number of machines such as the Z11 were built.

entry:
@Article{Zuse:1994:PPV,
  author =       "K. Zuse",
  title =        "Past and present view on computer architecture",
  journal =      j-IFIP-TRANS-A,
  volume =       "A-52",
  pages =        "248--250",
  month =        "????",
  year =         "1994",
  CODEN =        "ITATEC",
  ISSN =         "0926-5473",
  bibdate =      "Tue Dec 12 09:29:07 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Applications and Impacts. Information Processing '94
                 IFIP 13th World Computer Congress.",
  abstract =     "The author discusses his work in developing binary
                 instruction stream based computers. He chose the
                 half-logarithmic form, where he stored only the
                 exponent in a logarithmic notation, which is the same
                 as the floating point numbers, used in today's
                 computers. Following this principle, he developed new
                 machines. He started with a mechanical working
                 construction. This was a storage utility which was
                 concentrated and enabled the storage of a thousand
                 words. This storage device was completed in 1936. It
                 occurred to him that one could also build this machine
                 with electrical parts. First he built small computers,
                 the model Z2 and immediately after this the model Z3,
                 which was based entirely on relays. Both machines
                 worked satisfactory. Then he discovered Boolean
                 algebra. He could now design a computer on paper. He
                 continued to develop machines and founded a company in
                 Germany where a number of machines such as the Z11 were
                 built.",
  acknowledgement = ack-nhfb,
  classification = "C0200 (General computer topics); C5220 (Computer
                 architecture); C5420 (Mainframes and minicomputers)",
  confdate =     "28 Aug.-2 Sept. 1994",
  conflocation = "Hamburg, Germany",
  fjournal =     "IFIP Transactions. A. Computer Science and
                 Technology",
  keywords =     "Binary instruction stream based computers; Boolean
                 algebra; Computer architecture; Exponent; Floating
                 point numbers; Half-logarithmic form; Storage device;
                 Z11; Z2; Z3; ZUSE KG",
  pubcountry =   "Netherlands",
  thesaurus =    "Computer architecture; Digital computers; History",
}


bibtype: inproceedings
filename: fparith.bib
label: Aagaard:1995:FVP
author: M. Aagaard and C. Seger
title: The formal verification of a pipelined double-precision IEEE floating-point multiplier
crossref: IEEE:1995:IAI
pages: 7--10
year: 1995
bibdate: Sat Jun 02 07:46:35 2001
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2001.06.02 07:46:35 ???
acknowledgement: ack-nhfb
rawauthor: M. Aagaard and C. Seger
rawtitle: The formal verification of a pipelined double-precision {IEEE} floating-point multiplier
entry:
@InProceedings{Aagaard:1995:FVP,
  author =       "M. Aagaard and C. Seger",
  title =        "The formal verification of a pipelined
                 double-precision {IEEE} floating-point multiplier",
  crossref =     "IEEE:1995:IAI",
  pages =        "7--10",
  year =         "1995",
  bibdate =      "Sat Jun 02 07:46:35 2001",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Abdallah:1995:SASa
author: M. Abdallah and A. Skavantzos
booktitle: Proceedings of the Twenty-Seventh Southeastern Symposium on System Theory, 12--14 March 1995
title: A systematic approach for selecting practical moduli sets for residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 445--449
year: 1995
DOI: https://doi.org/10.1109/SSST.1995.390542
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Abdallah and A. Skavantzos
rawbooktitle: Proceedings of the Twenty-Seventh Southeastern Symposium on System Theory, 12--14 March 1995
rawtitle: A systematic approach for selecting practical moduli sets for residue number systems
entry:
@InProceedings{Abdallah:1995:SASa,
  author =       "M. Abdallah and A. Skavantzos",
  booktitle =    "Proceedings of the Twenty-Seventh Southeastern
                 Symposium on System Theory, 12--14 March 1995",
  title =        "A systematic approach for selecting practical moduli
                 sets for residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "445--449",
  year =         "1995",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/SSST.1995.390542",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The residue number system (RNS) is a useful tool for
                 digital signal processing (DSP) since it can support
                 parallel, carry free, high speed arithmetic. An RNS is
                 defined by a set of relatively prime integers called
                 the moduli set. The most important \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Abdallah:1995:SASb
author: M. Abdallah and A. Skavantzos
booktitle: Proceedings of the Twenty-Seventh Southeastern Symposium on System Theory, 12--14 March 1995
title: A systematic approach for selecting practical moduli sets for residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 445--449
year: 1995
DOI: https://doi.org/10.1109/SSST.1995.390542
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Abdallah and A. Skavantzos
rawbooktitle: Proceedings of the Twenty-Seventh Southeastern Symposium on System Theory, 12--14 March 1995
rawtitle: A systematic approach for selecting practical moduli sets for residue number systems
entry:
@InProceedings{Abdallah:1995:SASb,
  author =       "M. Abdallah and A. Skavantzos",
  booktitle =    "Proceedings of the Twenty-Seventh Southeastern
                 Symposium on System Theory, 12--14 March 1995",
  title =        "A systematic approach for selecting practical moduli
                 sets for residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "445--449",
  year =         "1995",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/SSST.1995.390542",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The residue number system (RNS) is a useful tool for
                 digital signal processing (DSP) since it can support
                 parallel, carry free, high speed arithmetic. An RNS is
                 defined by a set of relatively prime integers called
                 the moduli set. The most important \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Al-Mouhamed:1995:ELF
author: Mayez Al-Mouhamed and Lubomir Bic
title: Effects of Loop Fusion and Statement Migration on the Speedup of Vector Multiprocessors
journal: j-J-PAR-DIST-COMP
volume: 31
number: 1
pages: 56--64
day: 15
month: nov
monthnumber: 11
year: 1995
CODEN: JPDCER
DOI: https://doi.org/10.1006/jpdc.1995.1144
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Thu Mar 9 09:18:58 MST 2000
bibtimestamp: 2000.03.09 09:18:58 MST
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Department of Comput. Eng., King Fahd University of Pet. and Miner., Dhahran, Saudi Arabia
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: P Practical
rawauthor: Mayez Al-Mouhamed and Lubomir Bic
rawtitle: Effects of Loop Fusion and Statement Migration on the Speedup of Vector Multiprocessors
URL:
http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1144/production; http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1144/production/pdf

keywords:
arithmetic pipelines; C240; cache reuse; commercial optimizing compiler; load and store operations; loop fusion; optimising compilers; optimization; parallel architectures; parallel-vector loops; processor; resource allocation; scheduled; scheduling; statement migration; vector multiprocessors; vector processor systems

entry:
@Article{Al-Mouhamed:1995:ELF,
  author =       "Mayez Al-Mouhamed and Lubomir Bic",
  title =        "Effects of Loop Fusion and Statement Migration on the
                 Speedup of Vector Multiprocessors",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "31",
  number =       "1",
  pages =        "56--64",
  day =          "15",
  month =        nov,
  year =         "1995",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1006/jpdc.1995.1144",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Thu Mar 9 09:18:58 MST 2000",
  bibsource =    "http://www.idealibrary.com/servlet/useragent?func=showAllIssues&curIssueID=jpdc;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1144/production;
                 http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1144/production/pdf",
  acknowledgement = ack-nhfb,
  classification = "C5220P (Parallel architecture); C6150C (Compilers,
                 interpreters and other processors); C6150N (Distributed
                 systems software)",
  corpsource =   "Department of Comput. Eng., King Fahd University of
                 Pet. and Miner., Dhahran, Saudi Arabia",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "arithmetic pipelines; C240; cache reuse; commercial
                 optimizing compiler; load and store operations; loop
                 fusion; optimising compilers; optimization; parallel
                 architectures; parallel-vector loops; processor;
                 resource allocation; scheduled; scheduling; statement
                 migration; vector multiprocessors; vector processor
                 systems",
  treatment =    "P Practical",
}


bibtype: techreport
filename: fparith.bib
label: Altwaijry:1995:PAT
author: H. Altwaijry and M. Flynn
title: Performance / area tradeoffs in Booth multipliers
type: Technical Report
number: CSL-TR-95-684
institution: Computer Systems Laboratory, Stanford University
address: Stanford, CA, USA
pages: 56--64
month: nov
monthnumber: 11
year: 1995
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
acknowledgement: ack-sfo
rawauthor: H. Altwaijry and M. Flynn
rawtitle: Performance\slash area tradeoffs in {Booth} multipliers
entry:
@TechReport{Altwaijry:1995:PAT,
  author =       "H. Altwaijry and M. Flynn",
  title =        "Performance\slash area tradeoffs in {Booth}
                 multipliers",
  type =         "Technical Report",
  number =       "CSL-TR-95-684",
  institution =  "Computer Systems Laboratory, Stanford University",
  address =      "Stanford, CA, USA",
  month =        nov,
  year =         "1995",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Anonymous:1995:FEF
author: Anonymous
title: Fraction eliminate floating-point multiply
journal: j-EDN
volume: 40
number: 24
pages: 88--??
year: 1995
CODEN: EDNSBH
ISSN: 0012-7515, 0364-6637 OR 00127515, 03646637
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: EDN
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Fraction eliminate floating-point multiply
entry:
@Article{Anonymous:1995:FEF,
  author =       "Anonymous",
  title =        "Fraction eliminate floating-point multiply",
  journal =      j-EDN,
  volume =       "40",
  number =       "24",
  pages =        "88--??",
  year =         "1995",
  CODEN =        "EDNSBH",
  ISSN =         "0012-7515, 0364-6637",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "EDN",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1995:INM
author: Anonymous
journal: j-OPEN-SYSTEMS-TODAY
number: 169
pages: 32--??
month: feb
monthnumber: 2
year: 1995
ISSN: 1061-0839 OR 10610839
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Open Systems Today
acknowledgement: ack-nhfb
rawauthor: Anonymous
title:
IBM's new Model 3CT RS / 6000 workstation provides the industry's best floating-point price / performance numbers in the US$35,000 to US$50,000 price range

rawtitle:
{IBM}'s new {Model 3CT RS\slash 6000} workstation provides the industry's best floating-point price\slash performance numbers in the {US}\$35,000 to {US}\$50,000 price range

entry:
@Article{Anonymous:1995:INM,
  author =       "Anonymous",
  title =        "{IBM}'s new {Model 3CT RS\slash 6000} workstation
                 provides the industry's best floating-point price\slash
                 performance numbers in the {US}\$35,000 to {US}\$50,000
                 price range",
  journal =      j-OPEN-SYSTEMS-TODAY,
  volume =       "??",
  number =       "169",
  pages =        "32--??",
  month =        feb,
  year =         "1995",
  ISSN =         "1061-0839",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Open Systems Today",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1995:MVW
author: Anonymous
journal: j-IEEE-MICRO
volume: 15
number: 2
pages: 88--??
month: mar
monthnumber: 3
year: 1995
CODEN: IEMIDZ
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: Anonymous
title:
Micro View --- What lessons can chip makers and their customers take from the Pentium floating-point divide flaw and the resultant tidal wave of publicity?

rawtitle:
Micro View --- What lessons can chip makers and their customers take from the {Pentium} floating-point divide flaw and the resultant tidal wave of publicity?

entry:
@Article{Anonymous:1995:MVW,
  author =       "Anonymous",
  title =        "Micro View --- What lessons can chip makers and their
                 customers take from the {Pentium} floating-point divide
                 flaw and the resultant tidal wave of publicity?",
  journal =      j-IEEE-MICRO,
  volume =       "15",
  number =       "2",
  pages =        "88--??",
  month =        mar # "\slash " # apr,
  year =         "1995",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: article
filename: fparith.bib
label: Anonymous:1995:PCH
author: Anonymous
title: Program converts hex to floating point
journal: j-EDN
volume: 40
number: 15
pages: 76--??
year: 1995
CODEN: EDNSBH
ISSN: 0012-7515, 0364-6637 OR 00127515, 03646637
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: EDN
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Program converts hex to floating point
entry:
@Article{Anonymous:1995:PCH,
  author =       "Anonymous",
  title =        "Program converts hex to floating point",
  journal =      j-EDN,
  volume =       "40",
  number =       "15",
  pages =        "76--??",
  year =         "1995",
  CODEN =        "EDNSBH",
  ISSN =         "0012-7515, 0364-6637",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "EDN",
}


bibtype: inproceedings
filename: fparith.bib
label: Antelo:1995:RCR
author: Elisardo Antelo and Javier D. Bruguera and Julio Villalba and Emilio L. Zapata
title: Redundant CORDIC Rotator Based on Parallel Prediction
crossref: Knowles:1995:PSC
pages: 172--179
year: 1995
bibdate: Mon May 20 06:05:24 MDT 2002
bibtimestamp: 2002.05.20 06:05:24 MDT
URL: http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Antelo.pdf
keywords: ARITH-12
acknowledgement: ack-nhfb
rawauthor: Elisardo Antelo and Javier D. Bruguera and Julio Villalba and Emilio L. Zapata
rawtitle: Redundant {CORDIC} Rotator Based on Parallel Prediction
bibsource:
https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database

entry:
@InProceedings{Antelo:1995:RCR,
  author =       "Elisardo Antelo and Javier D. Bruguera and Julio
                 Villalba and Emilio L. Zapata",
  title =        "Redundant {CORDIC} Rotator Based on Parallel
                 Prediction",
  crossref =     "Knowles:1995:PSC",
  pages =        "172--179",
  year =         "1995",
  bibdate =      "Mon May 20 06:05:24 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC
                 Proceedings database",
  URL =          "http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Antelo.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-12",
}


bibtype: article
filename: fparith.bib
label: Bailey:1995:FBM
author: David H. Bailey
title: A Fortran-90 Based Multiprecision System
journal: j-TOMS
volume: 21
number: 4
pages: 379--387
month: dec
monthnumber: 12
year: 1995
CODEN: ACMSCU
DOI: https://doi.org/10.1145/212066.212075
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Thu Apr 29 15:15:44 1999
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1999.04.29 15:15:44 ???
note: See also extension to complex arithmetic cite Smith:1998:AMP.
URL: http://www.acm.org/pubs/citations/journals/toms/1995-21-4/p379-bailey/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: arithmetic; Fortran 90; multiprecision
acknowledgement: ack-rfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: David H. Bailey
rawnote: See also extension to complex arithmetic \cite{Smith:1998:AMP}.
rawtitle: A {Fortran-90} Based Multiprecision System
subject:
D.3.2 [Programming Languages]: Language Classifications -- Fortran 90; D.3.4 [Programming Languages]: Processors; G.1.0 [Numerical Analysis]: General; G.1.2 [Numerical Analysis]: Approximation

entry:
@Article{Bailey:1995:FBM,
  author =       "David H. Bailey",
  title =        "A {Fortran-90} Based Multiprecision System",
  journal =      j-TOMS,
  volume =       "21",
  number =       "4",
  pages =        "379--387",
  month =        dec,
  year =         "1995",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/212066.212075",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Thu Apr 29 15:15:44 1999",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See also extension to complex arithmetic
                 \cite{Smith:1998:AMP}.",
  URL =          "http://www.acm.org/pubs/citations/journals/toms/1995-21-4/p379-bailey/",
  acknowledgement = ack-rfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "arithmetic; Fortran 90; multiprecision",
  subject =      "D.3.2 [Programming Languages]: Language
                 Classifications -- Fortran 90; D.3.4 [Programming
                 Languages]: Processors; G.1.0 [Numerical Analysis]:
                 General; G.1.2 [Numerical Analysis]: Approximation",
}


bibtype: inproceedings
filename: fparith.bib
label: Bannon:1995:IAA
author: P. Bannon and J. Keller
title: Internal architecture of Alpha 21164 microprocessor
crossref: IEEE:1995:DPC
pages: 79--87
month: mar
monthnumber: 3
year: 1995
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
acknowledgement: ack-sfo
rawauthor: P. Bannon and J. Keller
rawtitle: Internal architecture of {Alpha 21164} microprocessor
entry:
@InProceedings{Bannon:1995:IAA,
  author =       "P. Bannon and J. Keller",
  title =        "Internal architecture of {Alpha 21164}
                 microprocessor",
  crossref =     "IEEE:1995:DPC",
  pages =        "79--87",
  month =        mar,
  year =         "1995",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Baron:1995:FPP
author: P. Baron and A. Joudon and F. Lugiez and M. Rouger
title: Floating Point Processor for Photomultiplier Tube Signals
journal: j-IEEE-TRANS-NUCL-SCI
volume: 42
number: 4
pages: 750--752
month: aug
monthnumber: 8
year: 1995
CODEN: IRNSAM
ISSN: 0018-9499 (print), 1558-1578 (electronic) OR 00189499 (print), 15581578 (electronic)
ISSNL: 0018-9499 OR 00189499
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Nuclear Science
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23
rawauthor: P. Baron and A. Joudon and F. Lugiez and M. Rouger
rawtitle: Floating Point Processor for Photomultiplier Tube Signals
entry:
@Article{Baron:1995:FPP,
  author =       "P. Baron and A. Joudon and F. Lugiez and M. Rouger",
  title =        "Floating Point Processor for Photomultiplier Tube
                 Signals",
  journal =      j-IEEE-TRANS-NUCL-SCI,
  volume =       "42",
  number =       "4",
  pages =        "750--752",
  month =        aug,
  year =         "1995",
  CODEN =        "IRNSAM",
  ISSN =         "0018-9499 (print), 1558-1578 (electronic)",
  ISSN-L =       "0018-9499",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Nuclear Science",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23",
  summary =      "A fast digital readout system has been designed for
                 synchronous processing of the current signals delivered
                 by a 64-channel multichannel photomultiplier tube
                 (MCPMT) associated with fast scintillators. This mixed
                 analog digital full custom chip uses \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Bauer:1995:AEB
author: P. H. Bauer
title: Absolute Error Bounds for Block Floating-Point Direct-Form Digital Filters
journal: j-IEEE-TRANS-SIG-PROC
volume: 43
number: 8
pages: 1994--1996
month: aug
monthnumber: 8
year: 1995
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: P. H. Bauer
rawtitle: Absolute Error Bounds for Block Floating-Point Direct-Form Digital Filters
entry:
@Article{Bauer:1995:AEB,
  author =       "P. H. Bauer",
  title =        "Absolute Error Bounds for Block Floating-Point
                 Direct-Form Digital Filters",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "43",
  number =       "8",
  pages =        "1994--1996",
  month =        aug,
  year =         "1995",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "Provides an asymptotic response analysis of digital
                 filters, which are implemented in block floating-point
                 format. Using absolute bounds on the quantization
                 error, conditions for the existence of certain response
                 types and the corresponding bounds on \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Bauer:1995:ARE
author: P. H. Bauer
title: Absolute Response Error Bounds for Floating Point Digital Filters in State Space Representation
journal: j-IEEE-TRANS-CIRCUITS-SYST-2
volume: 42
number: 9
pages: 610--613
month: sep
monthnumber: 9
year: 1995
CODEN: ICSPE5
DOI: https://doi.org/10.1109/82.466642
ISSN: 1057-7130 (print), 1558-125X (electronic) OR 10577130 (print), 1558125X (electronic)
ISSNL: 1057-7130 OR 10577130
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82
rawauthor: P. H. Bauer
rawtitle: Absolute Response Error Bounds for Floating Point Digital Filters in State Space Representation
entry:
@Article{Bauer:1995:ARE,
  author =       "P. H. Bauer",
  title =        "Absolute Response Error Bounds for Floating Point
                 Digital Filters in State Space Representation",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-2,
  volume =       "42",
  number =       "9",
  pages =        "610--613",
  month =        sep,
  year =         "1995",
  CODEN =        "ICSPE5",
  DOI =          "https://doi.org/10.1109/82.466642",
  ISSN =         "1057-7130 (print), 1558-125X (electronic)",
  ISSN-L =       "1057-7130",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems. 2, Analog
                 and Digital Signal Processing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82",
  summary =      "A deterministic study of the zero input asymptotic
                 behavior of second order state space digital filters
                 with floating point arithmetic is carried out. Using a
                 consecutive bound reduction method, asymptotic bounds
                 on the state response are derived. It \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Baumhof:1995:NVV
author: Christoph Baumhof
title: A New VLSI Vector Arithmetic Coprocessor for the PC
crossref: Knowles:1995:PSC
pages: 210--215
year: 1995
bibdate: Mon May 20 06:05:24 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:05:24 MDT
URL: http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Baumhof.pdf
keywords: ARITH-12
acknowledgement: ack-nhfb
rawauthor: Christoph Baumhof
rawtitle: A New {VLSI} Vector Arithmetic Coprocessor for the {PC}
entry:
@InProceedings{Baumhof:1995:NVV,
  author =       "Christoph Baumhof",
  title =        "A New {VLSI} Vector Arithmetic Coprocessor for the
                 {PC}",
  crossref =     "Knowles:1995:PSC",
  pages =        "210--215",
  year =         "1995",
  bibdate =      "Mon May 20 06:05:24 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  URL =          "http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Baumhof.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-12",
}


bibtype: article
filename: fparith.bib
label: Beaty:1995:EAS
author: Steven J. Beaty and Gearold R. Johnson
title: Effect of adding a scalar D-cache to the Cray-4 vector processor
journal: j-IEEE-INT-CONF-ALG-ARCH-PAR-PROC
volume: 1
pages: 227--230
year: 1995
bibdate: Mon Aug 26 10:51:12 MDT 1996
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.08.26 10:51:12 MDT
note: IEEE catalog number 95TH0682-5.
fjournal: IEEE International Conference on Algorithms and Architectures for Parallel Processing
acknowledgement: ack-nhfb
affiliation: Cray Computer Corp
affiliationaddress: Colorado Springs, CO, USA
journalabr: IEEE Int Conf Algorithms Archit Parall Process
rawauthor: Steven J. Beaty and Gearold R. Johnson
rawnote: IEEE catalog number 95TH0682-5.
rawtitle: Effect of adding a scalar {D-cache} to the {Cray-4} vector processor
abstract:
In the past, vector supercomputers achieved high performance with long arithmetic pipelines coupled with fast scalar processors. Processor speed has increased at a rate greater than memory speed. Indeed, current vector processors have cycle times far faster than the memories they are connected to. When compilers can predict memory access patterns, they vectorize computations and thereby hide the processor / memory disparity. When memory access patterns are not known until run-time, caches can pay large dividends. This paper studies the effects of adding a scalar data cache to a modern vector processor and shows some encouraging results.

keywords:
Buffer storage; Cray memory hierarchy; Cray-4 vector processor; Data processing; Hierarchical systems; Program processors; Scalar D-cache; Supercomputers; Systems analysis

rawabstract:
In the past, vector supercomputers achieved high performance with long arithmetic pipelines coupled with fast scalar processors. Processor speed has increased at a rate greater than memory speed. Indeed, current vector processors have cycle times far faster than the memories they are connected to. When compilers can predict memory access patterns, they vectorize computations and thereby hide the processor\slash memory disparity. When memory access patterns are not known until run-time, caches can pay large dividends. This paper studies the effects of adding a scalar data cache to a modern vector processor and shows some encouraging results.

entry:
@Article{Beaty:1995:EAS,
  author =       "Steven J. Beaty and Gearold R. Johnson",
  title =        "Effect of adding a scalar {D-cache} to the {Cray-4}
                 vector processor",
  journal =      j-IEEE-INT-CONF-ALG-ARCH-PAR-PROC,
  volume =       "1",
  pages =        "227--230",
  year =         "1995",
  bibdate =      "Mon Aug 26 10:51:12 MDT 1996",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IEEE catalog number 95TH0682-5.",
  abstract =     "In the past, vector supercomputers achieved high
                 performance with long arithmetic pipelines coupled with
                 fast scalar processors. Processor speed has increased
                 at a rate greater than memory speed. Indeed, current
                 vector processors have cycle times far faster than the
                 memories they are connected to. When compilers can
                 predict memory access patterns, they vectorize
                 computations and thereby hide the processor\slash
                 memory disparity. When memory access patterns are not
                 known until run-time, caches can pay large dividends.
                 This paper studies the effects of adding a scalar data
                 cache to a modern vector processor and shows some
                 encouraging results.",
  acknowledgement = ack-nhfb,
  affiliation =  "Cray Computer Corp",
  affiliationaddress = "Colorado Springs, CO, USA",
  classification = "722.1; 722.4; 723.1; 723.2",
  conference =   "Proceedings of the IEEE 1st International Conference
                 on Algorithms and Architectures for Parallel
                 Processing. Part 1 (of 2)",
  fjournal =     "IEEE International Conference on Algorithms and
                 Architectures for Parallel Processing",
  journalabr =   "IEEE Int Conf Algorithms Archit Parall Process",
  keywords =     "Buffer storage; Cray memory hierarchy; Cray-4 vector
                 processor; Data processing; Hierarchical systems;
                 Program processors; Scalar D-cache; Supercomputers;
                 Systems analysis",
  meetingaddress = "Brisbane, Aust",
  meetingdate =  "Apr 19--21 1995",
  meetingdate2 = "04/19--21/95",
  sponsor =      "IEEE",
}


bibtype: inproceedings
filename: fparith.bib
label: Bederr:1995:AAE
author: H. Bederr and M. Nicolaidis and A. Guyot
title: Analytic Approach for Error Masking Elimination in On-Line Multipliers
crossref: Knowles:1995:PSC
pages: 30--37
year: 1995
bibdate: Mon May 20 06:05:24 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:05:24 MDT
URL: http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Bederr.pdf
keywords: ARITH-12
acknowledgement: ack-nhfb
rawauthor: H. Bederr and M. Nicolaidis and A. Guyot
rawtitle: Analytic Approach for Error Masking Elimination in On-Line Multipliers
entry:
@InProceedings{Bederr:1995:AAE,
  author =       "H. Bederr and M. Nicolaidis and A. Guyot",
  title =        "Analytic Approach for Error Masking Elimination in
                 On-Line Multipliers",
  crossref =     "Knowles:1995:PSC",
  pages =        "30--37",
  year =         "1995",
  bibdate =      "Mon May 20 06:05:24 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  URL =          "http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Bederr.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-12",
}


bibtype: article
filename: fparith.bib
label: Bickerstaff:1995:PRA
author: K'Andrea C. Bickerstaff and Michael J. Schulte and Earl E. Swartzlander, Jr.
title: Parallel reduced area multipliers
journal: j-J-VLSI-SIGNAL-PROC
volume: 9
number: 3
pages: 181--191
month: apr
monthnumber: 4
year: 1995
CODEN: JVSPED
DOI: https://doi.org/10.1007/BF02407084
ISSN: 0922-5773 (print), 1573-109X (electronic) OR 09225773 (print), 1573109X (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Mon Mar 05 08:29:38 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.05 08:29:38 ???
URL: http://springerlink.metapress.com/content/761m0225754r4440/fulltext.pdf
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: K'Andrea C. Bickerstaff and Michael J. Schulte and Earl E. {Swartzlander, Jr.}
rawtitle: Parallel reduced area multipliers
entry:
@Article{Bickerstaff:1995:PRA,
  author =       "K'Andrea C. Bickerstaff and Michael J. Schulte and
                 Earl E. {Swartzlander, Jr.}",
  title =        "Parallel reduced area multipliers",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "9",
  number =       "3",
  pages =        "181--191",
  month =        apr,
  year =         "1995",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/BF02407084",
  ISSN =         "0922-5773 (print), 1573-109X (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Mon Mar 05 08:29:38 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://springerlink.metapress.com/content/761m0225754r4440/fulltext.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: article
filename: fparith.bib
label: Bierman:1995:FAI
author: Keith Bierman
title: Fortran access to IEEE 754 exceptions
journal: j-FORTRAN-FORUM
volume: 14
number: 3
pages: 15--18
month: sep
monthnumber: 9
year: 1995
ISSN: 1061-7264 (print), 1931-1311 (electronic) OR 10617264 (print), 19311311 (electronic)
ISSNL: 1061-7264 OR 10617264
bibdate: Wed Feb 6 18:50:05 MST 2002
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.06 18:50:05 MST
fjournal: ACM Fortran Forum
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/toc.cfm?id=J286
issue: 43
rawauthor: Keith Bierman
rawtitle: {Fortran} access to {IEEE 754} exceptions
entry:
@Article{Bierman:1995:FAI,
  author =       "Keith Bierman",
  title =        "{Fortran} access to {IEEE 754} exceptions",
  journal =      j-FORTRAN-FORUM,
  volume =       "14",
  number =       "3",
  pages =        "15--18",
  month =        sep,
  year =         "1995",
  CODEN =        "????",
  ISSN =         "1061-7264 (print), 1931-1311 (electronic)",
  ISSN-L =       "1061-7264",
  bibdate =      "Wed Feb 6 18:50:05 MST 2002",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Fortran Forum",
  issue =        "43",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J286",
}


bibtype: article
filename: fparith.bib
label: Boley:1995:FPF
author: D. Boley and G. H. Golub and S. Makar and N. Saxena and E. J. McCluskey
title: Floating Point Fault Tolerance with Backward Error Assertions
journal: j-IEEE-TRANS-COMPUT
volume: 44
number: 2
pages: 302--311
month: feb
monthnumber: 2
year: 1995
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.364541
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:01:26 MDT 2011
bibtimestamp: 2011.07.06 08:01:26 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=364541
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Minnesota University, Minneapolis, MN, USA
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Boley and G. H. Golub and S. Makar and N. Saxena and E. J. McCluskey
rawtitle: Floating Point Fault Tolerance with Backward Error Assertions
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/g/golub-gene-h.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib

abstract:
The paper introduces an assertion scheme based on the backward error analysis for error detection in algorithms that solve dense systems of linear equations, Ax=b. Unlike previous methods, this backward error assertion model is specifically designed to operate in an environment of floating point arithmetic subject to round-off errors, and it can be easily instrumented in a Watchdog processor environment. The complexity of verifying assertions is O(n/sup 2/), compared to the O(n/sup 3/) complexity of algorithms solving Ax=b. Unlike other proposed error detection methods, this assertion model does not require any encoding of the matrix A. Experimental results under various error models are presented to validate the effectiveness of this assertion scheme.

keywords:
Assertion scheme; Backward error analysis; Backward error assertions; Complexity; Dense systems; Error detection; Error models; Floating point arithmetic; Floating point fault tolerance; Linear equations; Round-off errors; Watchdog processor environment

thesaurus:
Computational complexity; Error analysis; Error detection; Fault tolerant computing; Floating point arithmetic; Linear algebra

rawabstract:
The paper introduces an assertion scheme based on the backward error analysis for error detection in algorithms that solve dense systems of linear equations, Ax=b. Unlike previous methods, this backward error assertion model is specifically designed to operate in an environment of floating point arithmetic subject to round-off errors, and it can be easily instrumented in a Watchdog processor environment. The complexity of verifying assertions is O(n/sup 2/), compared to the O(n/sup 3/) complexity of algorithms solving Ax=b. Unlike other proposed error detection methods, this assertion model does not require any encoding of the matrix A. Experimental results under various error models are presented to validate the effectiveness of this assertion scheme.

entry:
@Article{Boley:1995:FPF,
  author =       "D. Boley and G. H. Golub and S. Makar and N. Saxena
                 and E. J. McCluskey",
  title =        "Floating Point Fault Tolerance with Backward Error
                 Assertions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "44",
  number =       "2",
  pages =        "302--311",
  month =        feb,
  year =         "1995",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.364541",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:01:26 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/g/golub-gene-h.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=364541",
  abstract =     "The paper introduces an assertion scheme based on the
                 backward error analysis for error detection in
                 algorithms that solve dense systems of linear
                 equations, Ax=b. Unlike previous methods, this backward
                 error assertion model is specifically designed to
                 operate in an environment of floating point arithmetic
                 subject to round-off errors, and it can be easily
                 instrumented in a Watchdog processor environment. The
                 complexity of verifying assertions is O(n/sup 2/),
                 compared to the O(n/sup 3/) complexity of algorithms
                 solving Ax=b. Unlike other proposed error detection
                 methods, this assertion model does not require any
                 encoding of the matrix A. Experimental results under
                 various error models are presented to validate the
                 effectiveness of this assertion scheme.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Minnesota University,
                 Minneapolis, MN, USA",
  ajournal =     "IEEE Trans. Comput.",
  classification = "C4140 (Linear algebra); C4240C (Computational
                 complexity); C5230 (Digital arithmetic methods); C5470
                 (Performance evaluation and testing)",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Assertion scheme; Backward error analysis; Backward
                 error assertions; Complexity; Dense systems; Error
                 detection; Error models; Floating point arithmetic;
                 Floating point fault tolerance; Linear equations;
                 Round-off errors; Watchdog processor environment",
  summary =      "The paper introduces an assertion scheme based on the
                 backward error analysis for error detection in
                 algorithms that solve dense systems of linear
                 equations, Ax=b. Unlike previous methods, this backward
                 error assertion model is specifically designed
                 \ldots{}",
  thesaurus =    "Computational complexity; Error analysis; Error
                 detection; Fault tolerant computing; Floating point
                 arithmetic; Linear algebra",
}


bibtype: article
filename: fparith.bib
label: Bomar:1995:RNA
author: B. W. Bomar and L. M. Smith and R. D. Joseph
journal: Proceedings - IEEE International Symposium on Circuits and Systems
number: 3
pages: III-2023
year: 1995
ISSN: 0271-4310 OR 02714310
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: B. W. Bomar and L. M. Smith and R. D. Joseph
title:
Roundoff Noise Analysis of State-Space Digital Filters Implemented on Floating-Point Digital Signal Processors

rawtitle:
Roundoff Noise Analysis of State-Space Digital Filters Implemented on Floating-Point Digital Signal Processors

entry:
@Article{Bomar:1995:RNA,
  author =       "B. W. Bomar and L. M. Smith and R. D. Joseph",
  title =        "Roundoff Noise Analysis of State-Space Digital Filters
                 Implemented on Floating-Point Digital Signal
                 Processors",
  journal =      "Proceedings - IEEE International Symposium on Circuits
                 and Systems",
  volume =       "??",
  number =       "3",
  pages =        "III-2023",
  year =         "1995",
  ISSN =         "0271-4310",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Booker:1995:FER
author: Alan Booker
title: Floating-Point Emulation and Representation
journal: j-EMBED-SYS-PROG
volume: 8
number: 9
pages: 111--??
year: 1995
CODEN: EYPRE4
ISSN: 1040-3272 OR 10403272
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Embedded Systems Programming
acknowledgement: ack-nhfb
rawauthor: Alan Booker
rawtitle: Floating-Point Emulation and Representation
entry:
@Article{Booker:1995:FER,
  author =       "Alan Booker",
  title =        "Floating-Point Emulation and Representation",
  journal =      j-EMBED-SYS-PROG,
  volume =       "8",
  number =       "9",
  pages =        "111--??",
  year =         "1995",
  CODEN =        "EYPRE4",
  ISSN =         "1040-3272",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Embedded Systems Programming",
}


bibtype: article
filename: fparith.bib
label: BrinchHansen:1995:LDA
author: Per Brinch Hansen
title: The Long Division Algorithm of Linger, Mills and Witt
journal: j-SPE
volume: 25
number: 1
pages: 109--109
month: jan
monthnumber: 1
year: 1995
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.4380250107
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Sat May 31 13:36:16 MDT 1997
bibtimestamp: 1997.05.31 13:36:16 MDT
note: See cite Linger:1979:SPT,BrinchHansen:1994:MLD.
fjournal: Software --- Practice and Experience
acknowledgement: ack-nhfb
ajournal: Softw. Pract. Exp.
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 30 Oct 2006
rawauthor: Per {Brinch Hansen}
rawnote: See \cite{Linger:1979:SPT,BrinchHansen:1994:MLD}.
rawtitle: The Long Division Algorithm of {Linger}, {Mills} and {Witt}
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/hansen-per-brinch.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/litprog.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib

abstract:
The long division algorithm of Linger, Mills and Witt cite Linger:1979:SPT is discussed and found to be significantly slower than a recent algorithm developed by the author.

rawabstract:
The long division algorithm of Linger, Mills and Witt \cite{Linger:1979:SPT} is discussed and found to be significantly slower than a recent algorithm developed by the author.

entry:
@Article{BrinchHansen:1995:LDA,
  author =       "Per {Brinch Hansen}",
  title =        "The Long Division Algorithm of {Linger}, {Mills} and
                 {Witt}",
  journal =      j-SPE,
  volume =       "25",
  number =       "1",
  pages =        "109--109",
  month =        jan,
  year =         "1995",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.4380250107",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Sat May 31 13:36:16 MDT 1997",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/hansen-per-brinch.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/litprog.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib",
  note =         "See \cite{Linger:1979:SPT,BrinchHansen:1994:MLD}.",
  abstract =     "The long division algorithm of Linger, Mills and Witt
                 \cite{Linger:1979:SPT} is discussed and found to be
                 significantly slower than a recent algorithm developed
                 by the author.",
  acknowledgement = ack-nhfb,
  ajournal =     "Softw. Pract. Exp.",
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  onlinedate =   "30 Oct 2006",
}


bibtype: article
filename: fparith.bib
label: Burgess:1995:COT
author: N. Burgess and T. Williams
title: Choices of operand truncation in the SRT division algorithm
journal: j-IEEE-TRANS-COMPUT
volume: 44
number: 7
pages: 933--937
month: jul
monthnumber: 7
year: 1995
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.392852
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jul 6 08:01:28 MDT 2011
bibtimestamp: 2011.07.06 08:01:28 MDT
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=392852
fjournal: IEEE Transactions on Computers
acknowledgement: ack-sfo
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: N. Burgess and T. Williams
rawtitle: Choices of operand truncation in the {SRT} division algorithm
entry:
@Article{Burgess:1995:COT,
  author =       "N. Burgess and T. Williams",
  title =        "Choices of operand truncation in the {SRT} division
                 algorithm",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "44",
  number =       "7",
  pages =        "933--937",
  month =        jul,
  year =         "1995",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.392852",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jul 6 08:01:28 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  URL =          "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=392852",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Burnikel:1995:EGC
title: Exact Geometric Computation in LEDA
crossref: ACM:1995:PEA
pages: C18--C19
year: 1995
bibdate: Tue Nov 13 21:49:22 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.13 21:49:22 ???
acknowledgement: ack-nhfb
rawtitle: Exact Geometric Computation in {LEDA}
author:
Christoph Burnikel and Jochen Konemann and Kurt Mehlhorn and Stefan Naher and Stefan Schirra and Christian Uhrig

rawauthor:
Christoph Burnikel and Jochen Konemann and Kurt Mehlhorn and Stefan Naher and Stefan Schirra and Christian Uhrig

entry:
@InProceedings{Burnikel:1995:EGC,
  author =       "Christoph Burnikel and Jochen Konemann and Kurt
                 Mehlhorn and Stefan Naher and Stefan Schirra and
                 Christian Uhrig",
  title =        "Exact Geometric Computation in {LEDA}",
  crossref =     "ACM:1995:PEA",
  pages =        "C18--C19",
  year =         "1995",
  bibdate =      "Tue Nov 13 21:49:22 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Carreno:1995:IIF
author: Victor A. Carreno
title: Interpretation of IEEE-854 floating-point standard and definition in the HOL system
type: NASA technical memorandum
number: 110189
institution: pub-NASA
address: pub-NASA:adr
year: 1995
bibdate: Thu Oct 24 14:19:35 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.24 14:19:35 MDT
note: Shipping list no. 96-0366-M.
keywords: floating-point arithmetic; formalism; standards
acknowledgement: ack-nhfb
rawauthor: Victor A. Carreno
rawnote: Shipping list no. 96-0366-M.
rawtitle: Interpretation of {IEEE-854} floating-point standard and definition in the {HOL} system
entry:
@TechReport{Carreno:1995:IIF,
  author =       "Victor A. Carreno",
  title =        "Interpretation of {IEEE-854} floating-point standard
                 and definition in the {HOL} system",
  type =         "{NASA} technical memorandum",
  number =       "110189",
  institution =  pub-NASA,
  address =      pub-NASA:adr,
  pages =        "????",
  year =         "1995",
  bibdate =      "Thu Oct 24 14:19:35 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Shipping list no. 96-0366-M.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; formalism; standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Carreno:1995:SIF
author: Victor A. Carreno and Paul S. Miner
title: Specification of the IEEE-854 Floating-Point Standard in HOL and PVS
crossref: Anonymous:1995:HEI
year: 1995
bibdate: Wed Nov 24 09:09:34 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.24 09:09:34 ???
URL: http://shemesh.larc.nasa.gov/fm/ftp/larc/vac/hug95.ps
acknowledgement: ack-mfc
rawauthor: Victor A. Carre{\~n}o and Paul S. Miner
rawtitle: Specification of the {IEEE-854} Floating-Point Standard in {HOL} and {PVS}
entry:
@InProceedings{Carreno:1995:SIF,
  author =       "Victor A. Carre{\~n}o and Paul S. Miner",
  title =        "Specification of the {IEEE-854} Floating-Point
                 Standard in {HOL} and {PVS}",
  crossref =     "Anonymous:1995:HEI",
  year =         "1995",
  bibdate =      "Wed Nov 24 09:09:34 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://shemesh.larc.nasa.gov/fm/ftp/larc/vac/hug95.ps",
  acknowledgement = ack-mfc # " and " # ack-nhfb,
  pagecount =    "16",
}


bibtype: inproceedings
filename: fparith.bib
label: Chang:1995:REA
author: P. S. Chang and A. N. Willson, Jr.
booktitle: Conference Record of the Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, 1995
title: A roundoff error analysis of the normalized LMS algorithm
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1337--1341
year: 1995
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: P. S. Chang and A. N. {Willson, Jr.}
rawbooktitle: Conference Record of the Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, 1995
rawtitle: A roundoff error analysis of the normalized {LMS} algorithm
entry:
@InProceedings{Chang:1995:REA,
  author =       "P. S. Chang and A. N. {Willson, Jr.}",
  booktitle =    "Conference Record of the Twenty-Ninth Asilomar
                 Conference on Signals, Systems and Computers, 1995",
  title =        "A roundoff error analysis of the normalized {LMS}
                 algorithm",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1337--1341",
  year =         "1995",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper describes an analysis of the normalized LMS
                 algorithm under finite word-length effects. It is shown
                 that, using the averaging principle, it is possible to
                 derive a good approximation for the total MSE in
                 steady-state. Implementation \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1995:UCA
author: San-Gee Chen and Chieh-Chih Li
booktitle: IEEE Signal Processing Society Workshop on VLSI Signal Processing, VIII, 1995
title: A unified cellular array for multiplication, division and square root
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 533--541
year: 1995
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: San-Gee Chen and Chieh-Chih Li
rawbooktitle: {IEEE} Signal Processing Society Workshop on {VLSI} Signal Processing, {VIII, 1995}
rawtitle: A unified cellular array for multiplication, division and square root
entry:
@InProceedings{Chen:1995:UCA,
  author =       "San-Gee Chen and Chieh-Chih Li",
  booktitle =    "{IEEE} Signal Processing Society Workshop on {VLSI}
                 Signal Processing, {VIII, 1995}",
  title =        "A unified cellular array for multiplication, division
                 and square root",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "533--541",
  year =         "1995",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "A unified fast, small-area processor capable of
                 executing multiplication, division and square-root
                 operations, all starting from MSD is proposed. Unlike
                 the existing designs which require both addition and
                 subtraction operations, and complicated \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Cheng:1995:PBS
author: Fuhua Cheng and G. W. Wasilkowski and Jiaye Wang and Caiming Zhang and Wenping Wang
title: Parallel B-Spline Surface Interpolation on a Mesh-Connected Processor Array
journal: j-J-PAR-DIST-COMP
volume: 24
number: 2
pages: 224--229
day: 1
month: feb
monthnumber: 2
year: 1995
CODEN: JPDCER
DOI: https://doi.org/10.1006/jpdc.1995.1022
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Thu Mar 9 09:18:56 MST 2000
bibtimestamp: 2000.03.09 09:18:56 MST
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
corpsource: Department of Computer Science, Kentucky University, Lexington, KY, USA
journalURL: http://www.sciencedirect.com/science/journal/07437315
treatment: T Theoretical or Mathematical
rawauthor: Fuhua Cheng and G. W. Wasilkowski and Jiaye Wang and Caiming Zhang and Wenping Wang
rawtitle: Parallel {B}-Spline Surface Interpolation on a Mesh-Connected Processor Array
URL:
http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1022/production; http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1022/production/pdf

keywords:
algorithms; B-spline surface interpolation; bicubic B-spline surface; Chebyshev approximation; Chebyshev method; computational complexity; constant; control; data points; finite precision; floating-point arithmetic; interconnection networks; interpolation; iterative methods; mesh-connected processor array; multiprocessor; numerical stability; optimal; parallel; parallel implementation; points; splines (mathematics); time

entry:
@Article{Cheng:1995:PBS,
  author =       "Fuhua Cheng and G. W. Wasilkowski and Jiaye Wang and
                 Caiming Zhang and Wenping Wang",
  title =        "Parallel {B}-Spline Surface Interpolation on a
                 Mesh-Connected Processor Array",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "24",
  number =       "2",
  pages =        "224--229",
  day =          "1",
  month =        feb,
  year =         "1995",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1006/jpdc.1995.1022",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Thu Mar 9 09:18:56 MST 2000",
  bibsource =    "http://www.idealibrary.com/servlet/useragent?func=showAllIssues&curIssueID=jpdc;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1022/production;
                 http://www.idealibrary.com/links/doi/10.1006/jpdc.1995.1022/production/pdf",
  acknowledgement = ack-nhfb,
  classification = "B0290F (Interpolation and function approximation);
                 C4130 (Interpolation and function approximation);
                 C4240C (Computational complexity); C4240P (Parallel
                 programming and algorithm theory)",
  corpsource =   "Department of Computer Science, Kentucky University,
                 Lexington, KY, USA",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  keywords =     "algorithms; B-spline surface interpolation; bicubic
                 B-spline surface; Chebyshev approximation; Chebyshev
                 method; computational complexity; constant; control;
                 data points; finite precision; floating-point
                 arithmetic; interconnection networks; interpolation;
                 iterative methods; mesh-connected processor array;
                 multiprocessor; numerical stability; optimal; parallel;
                 parallel implementation; points; splines (mathematics);
                 time",
  treatment =    "T Theoretical or Mathematical",
}


bibtype: phdthesis
filename: fparith.bib
label: Chesneaux:1995:LSL
author: Jean-Marie Chesneaux
type: Habilitation a diriger des recherches
school: Universite Pierre et Marie Curie
address: Paris, France
year: 1995
bibdate: Mon Mar 19 14:07:57 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.19 14:07:57 ???
acknowledgement: ack-nhfb
rawauthor: Jean-Marie Chesneaux
title:
L'arithmetique stochastique et le logiciel CADNA. (French) [Stochastic arithmetic and CADNA software]

rawtitle:
L'arithm{\'e}tique stochastique et le logiciel {CADNA}. ({French}) [{Stochastic} arithmetic and {CADNA} software]

entry:
@PhdThesis{Chesneaux:1995:LSL,
  author =       "Jean-Marie Chesneaux",
  title =        "L'arithm{\'e}tique stochastique et le logiciel
                 {CADNA}. ({French}) [{Stochastic} arithmetic and
                 {CADNA} software]",
  type =         "Habilitation {\`a} diriger des recherches",
  school =       "Universit{\'e} Pierre et Marie Curie",
  address =      "Paris, France",
  pages =        "????",
  year =         "1995",
  bibdate =      "Mon Mar 19 14:07:57 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Coe:1995:CAP
author: Tim Coe and Terje Mathisen and Cleve Moler and Vaughan Pratt
title: Computational Aspects of the Pentium Affair
journal: j-IEEE-COMPUT-SCI-ENG
volume: 2
number: 1
pages: 18--30
month: Spring
year: 1995
CODEN: ISCEE4
ISSN: 1070-9924 (print), 1558-190X (electronic) OR 10709924 (print), 1558190X (electronic)
ISSNL: 1070-9924 OR 10709924
bibdate: Sat Jan 9 08:57:23 MST 1999
bibtimestamp: 1999.01.09 08:57:23 MST
URL: http://www.computer.org/cse/cs1998/c1018abs.htm
fjournal: IEEE Computational Science & Engineering
acknowledgement: ack-nhfb
affiliation: Vitesse Semicond. Corp., Camarillo, CA, USA
classcodes: C5130 (Microprocessor chips); C5230 (Digital arithmetic methods)
corpsource: Vitesse Semicond. Corp., Camarillo, CA, USA
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=99
thesaurus: Floating point arithmetic; Microprocessor chips
treatment: P Practical; T Theoretical or Mathematical
rawauthor: Tim Coe and Terje Mathisen and Cleve Moler and Vaughan Pratt
rawtitle: Computational Aspects of the {Pentium} Affair
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The Pentium affair has been widely publicized. It started with an obscure defect in the floating-point unit of Intel Corporation's flagship Pentium microprocessor. This is the story of how the Pentium floating-point division problem was discovered, and what you need to know about the maths and computer engineering involved before deciding whether to replace the chip, install the workaround provided here, or do nothing. The paper also discusses broader issues of computational correctness.

keywords:
computational aspects; computational correctness; computer engineering; division problem; floating point arithmetic; Floating-point division problem; floating-point unit; Intel Corporation; microprocessor chips; Pentium affair; Pentium microprocessor

rawabstract:
The Pentium affair has been widely publicized. It started with an obscure defect in the floating-point unit of Intel Corporation's flagship Pentium microprocessor. This is the story of how the Pentium floating-point division problem was discovered, and what you need to know about the maths and computer engineering involved before deciding whether to replace the chip, install the workaround provided here, or do nothing. The paper also discusses broader issues of computational correctness.

entry:
@Article{Coe:1995:CAP,
  author =       "Tim Coe and Terje Mathisen and Cleve Moler and Vaughan
                 Pratt",
  title =        "Computational Aspects of the {Pentium} Affair",
  journal =      j-IEEE-COMPUT-SCI-ENG,
  volume =       "2",
  number =       "1",
  pages =        "18--30",
  month =        "Spring",
  year =         "1995",
  CODEN =        "ISCEE4",
  ISSN =         "1070-9924 (print), 1558-190X (electronic)",
  ISSN-L =       "1070-9924",
  bibdate =      "Sat Jan 9 08:57:23 MST 1999",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.computer.org/cse/cs1998/c1018abs.htm",
  abstract =     "The Pentium affair has been widely publicized. It
                 started with an obscure defect in the floating-point
                 unit of Intel Corporation's flagship Pentium
                 microprocessor. This is the story of how the Pentium
                 floating-point division problem was discovered, and
                 what you need to know about the maths and computer
                 engineering involved before deciding whether to replace
                 the chip, install the workaround provided here, or do
                 nothing. The paper also discusses broader issues of
                 computational correctness.",
  acknowledgement = ack-nhfb,
  affiliation =  "Vitesse Semicond. Corp., Camarillo, CA, USA",
  classcodes =   "C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods)",
  classification = "C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods)",
  corpsource =   "Vitesse Semicond. Corp., Camarillo, CA, USA",
  fjournal =     "IEEE Computational Science \& Engineering",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=99",
  keywords =     "computational aspects; computational correctness;
                 computer engineering; division problem; floating point
                 arithmetic; Floating-point division problem;
                 floating-point unit; Intel Corporation; microprocessor
                 chips; Pentium affair; Pentium microprocessor",
  thesaurus =    "Floating point arithmetic; Microprocessor chips",
  treatment =    "P Practical; T Theoretical or Mathematical",
}


bibtype: article
filename: fparith.bib
label: Coe:1995:IPF
author: Tim Coe
title: Inside the Pentium FDIV Bug
journal: j-DDJ
volume: 20
number: 4
pages: 129--??
month: apr
monthnumber: 4
year: 1995
CODEN: DDJOEB
ISSN: 1044-789X OR 1044789X
bibdate: Mon Sep 2 09:09:39 MDT 1996
bibtimestamp: 1996.09.02 09:09:39 MDT
fjournal: Dr. Dobb's Journal of Software Tools
keywords: Intel Pentium divide flaw; Thomas R. Nicely
acknowledgement: ack-nhfb
rawauthor: Tim Coe
rawtitle: Inside the {Pentium FDIV} Bug
bibsource:
http://www.ddj.com/documents/s=992/ddj9504l/; http://www.ddj.com/index/author/index.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Coe:1995:IPF,
  author =       "Tim Coe",
  title =        "Inside the {Pentium FDIV} Bug",
  journal =      j-DDJ,
  volume =       "20",
  number =       "4",
  pages =        "129--??",
  month =        apr,
  year =         "1995",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Mon Sep 2 09:09:39 MDT 1996",
  bibsource =    "http://www.ddj.com/documents/s=992/ddj9504l/;
                 http://www.ddj.com/index/author/index.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Dr. Dobb's Journal of Software Tools",
  keywords =     "Intel Pentium divide flaw; Thomas R. Nicely",
}


bibtype: inproceedings
filename: fparith.bib
label: Coe:1995:ITS
author: Tim Coe and Ping Tak Peter Tang
title: It Takes Six Ones to Reach a Flaw
crossref: Knowles:1995:PSC
pages: 140--148
year: 1995
bibdate: Mon May 20 06:05:24 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:05:24 MDT
note: Also available as Chinese University of Hong Kong technical report 95-5 (61), 1995.
URL: http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Coe.pdf
keywords: ARITH-12; Pentium divide flaw
acknowledgement: ack-nhfb
rawauthor: Tim Coe and Ping Tak Peter Tang
rawnote: Also available as Chinese University of Hong Kong technical report 95-5 (61), 1995.
rawtitle: It Takes Six Ones to Reach a Flaw
entry:
@InProceedings{Coe:1995:ITS,
  author =       "Tim Coe and Ping Tak Peter Tang",
  title =        "It Takes Six Ones to Reach a Flaw",
  crossref =     "Knowles:1995:PSC",
  pages =        "140--148",
  year =         "1995",
  bibdate =      "Mon May 20 06:05:24 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  note =         "Also available as Chinese University of Hong Kong
                 technical report 95-5 (61), 1995.",
  URL =          "http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Coe.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-12; Pentium divide flaw",
}


bibtype: article
filename: fparith.bib
label: Crenshaw:1995:PTFa
author: Jack W. Crenshaw
title: Programmer's Toolbox: Floating-Point Math
journal: j-EMBED-SYS-PROG
volume: 8
number: 11
pages: 25--??
year: 1995
CODEN: EYPRE4
ISSN: 1040-3272 OR 10403272
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Embedded Systems Programming
acknowledgement: ack-nhfb
rawauthor: Jack W. Crenshaw
rawtitle: Programmer's Toolbox: Floating-Point Math
entry:
@Article{Crenshaw:1995:PTFa,
  author =       "Jack W. Crenshaw",
  title =        "Programmer's Toolbox: Floating-Point Math",
  journal =      j-EMBED-SYS-PROG,
  volume =       "8",
  number =       "11",
  pages =        "25--??",
  year =         "1995",
  CODEN =        "EYPRE4",
  ISSN =         "1040-3272",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Embedded Systems Programming",
}


bibtype: article
filename: fparith.bib
label: Crenshaw:1995:PTFb
author: Jack W. Crenshaw
title: Programmer's Toolbox: Floating-Point Math, Part 2
journal: j-EMBED-SYS-PROG
volume: 8
number: 12
pages: 29--??
year: 1995
CODEN: EYPRE4
ISSN: 1040-3272 OR 10403272
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
fjournal: Embedded Systems Programming
acknowledgement: ack-nhfb
rawauthor: Jack W. Crenshaw
rawtitle: Programmer's Toolbox: Floating-Point Math, Part 2
entry:
@Article{Crenshaw:1995:PTFb,
  author =       "Jack W. Crenshaw",
  title =        "Programmer's Toolbox: Floating-Point Math, Part 2",
  journal =      j-EMBED-SYS-PROG,
  volume =       "8",
  number =       "12",
  pages =        "29--??",
  year =         "1995",
  CODEN =        "EYPRE4",
  ISSN =         "1040-3272",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Embedded Systems Programming",
}


bibtype: inproceedings
filename: fparith.bib
label: Cui:1995:GIFa
author: S. Cui and N. Burgess and M. Liebelt and K. Eshraghian
title: A 32-bit GaAs IEEE floating point multiplier using Trailing-1's rounding algorithm
crossref: Jain:1995:PET
pages: 246--252
year: 1995
bibdate: Thu Dec 14 11:25:18 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.14 11:25:18 MST
URL: http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Jain.pdf
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Electron. Eng., Adelaide University, SA, Australia
rawauthor: S. Cui and N. Burgess and M. Liebelt and K. Eshraghian
rawtitle: A 32-bit {GaAs IEEE} floating point multiplier using {Trailing-1}'s rounding algorithm
abstract:
The paper presents a GaAs 32-bit IEEE floating point multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. This chip uses a new layout methodology for easy design structure and improved GaAs technology layout density. The combination of the fast arithmetic architecture and compact layout style achieves 4ns multiplication time with 3.5 W power dissipation at 75 degrees C. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8 mu m GaAs technology. (11 Refs.)

keywords:
3.5 W; 32 Bit; 32 Bit GaAs IEEE floating point multiplier; 75 DegC; Booth algorithm; Compact layout style; Easy design structure; Fast arithmetic architecture; GaAs technology; Improved GaAs technology layout density; Layout methodology; Modified carry save array; Multiplication time; Partial product addition; Power dissipation; Special rounding technique; Trailing-1s rounding algorithm; Transistors

thesaurus:
Floating point arithmetic; Gallium arsenide; Microprocessor chips; Multiplying circuits; Roundoff errors; Societies

rawabstract:
The paper presents a GaAs 32-bit IEEE floating point multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. This chip uses a new layout methodology for easy design structure and improved GaAs technology layout density. The combination of the fast arithmetic architecture and compact layout style achieves 4ns multiplication time with 3.5 W power dissipation at 75 degrees C. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28000 transistors to give a density of 3056 transistors/mm/sup 2/ for 0.8 mu m GaAs technology. (11 Refs.)

entry:
@InProceedings{Cui:1995:GIFa,
  author =       "S. Cui and N. Burgess and M. Liebelt and K.
                 Eshraghian",
  title =        "A 32-bit {GaAs IEEE} floating point multiplier using
                 {Trailing-1}'s rounding algorithm",
  crossref =     "Jain:1995:PET",
  pages =        "246--252",
  year =         "1995",
  bibdate =      "Thu Dec 14 11:25:18 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Jain.pdf",
  abstract =     "The paper presents a GaAs 32-bit IEEE floating point
                 multiplier. A modified carry save array is used in
                 conjunction with Booth's algorithm to reduce the
                 partial product addition and interconnection. A special
                 rounding technique called Trailing-1's Predictor is
                 used to speed up the final addition and rounding. This
                 chip uses a new layout methodology for easy design
                 structure and improved GaAs technology layout density.
                 The combination of the fast arithmetic architecture and
                 compact layout style achieves 4ns multiplication time
                 with 3.5 W power dissipation at 75 degrees C. The area
                 is 2.43 mm by 3.77 mm (excluding pads) and uses 28000
                 transistors to give a density of 3056
                 transistors/mm/sup 2/ for 0.8 mu m GaAs technology. (11
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Electron. Eng., Adelaide
                 University, SA, Australia",
  classification = "B1265B (Logic circuits); C5120 (Logic and switching
                 circuits); C5130 (Microprocessor chips); C5230 (Digital
                 arithmetic methods)",
  keywords =     "3.5 W; 32 Bit; 32 Bit GaAs IEEE floating point
                 multiplier; 75 DegC; Booth algorithm; Compact layout
                 style; Easy design structure; Fast arithmetic
                 architecture; GaAs technology; Improved GaAs technology
                 layout density; Layout methodology; Modified carry save
                 array; Multiplication time; Partial product addition;
                 Power dissipation; Special rounding technique;
                 Trailing-1s rounding algorithm; Transistors",
  numericalindex = "Word length 3.2E+01 bit; Power 3.5E+00 W;
                 Temperature 3.48E+02 K",
  thesaurus =    "Floating point arithmetic; Gallium arsenide;
                 Microprocessor chips; Multiplying circuits; Roundoff
                 errors; Societies",
}


bibtype: inproceedings
filename: fparith.bib
label: Cui:1995:GIFb
author: S. Cui and N. Burgess and M. Liebelt and K. Eshraghian
title: A GaAs IEEE Floating Point Standard Single Precision Multiplier
crossref: Knowles:1995:PSC
pages: 91--97
year: 1995
bibdate: Mon May 20 06:05:24 MDT 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; OCLC Proceedings database
bibtimestamp: 2002.05.20 06:05:24 MDT
URL: http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Cui.pdf
keywords: ARITH-12
acknowledgement: ack-nhfb
rawauthor: S. Cui and N. Burgess and M. Liebelt and K. Eshraghian
rawtitle: A {GaAs} {IEEE} Floating Point Standard Single Precision Multiplier
entry:
@InProceedings{Cui:1995:GIFb,
  author =       "S. Cui and N. Burgess and M. Liebelt and K.
                 Eshraghian",
  title =        "A {GaAs} {IEEE} Floating Point Standard Single
                 Precision Multiplier",
  crossref =     "Knowles:1995:PSC",
  pages =        "91--97",
  year =         "1995",
  bibdate =      "Mon May 20 06:05:24 MDT 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 OCLC Proceedings database",
  URL =          "http://www.acsel-lab.com/arithmetic/arith12/papers/ARITH12_Cui.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-12",
}


bibtype: article
filename: fparith.bib
label: Das:1995:IFC
author: D. Das and K. Mukhopadhyaya and B. P. Sinha
title: Implementation of four common functions on an LNS co-processor
journal: j-IEEE-TRANS-COMPUT
volume: 44
number: 1
pages: 155--161
month: jan
monthnumber: 1
year: 1995
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.367997
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibtimestamp: 2005.07.16 16:14:38 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Das and K. Mukhopadhyaya and B. P. Sinha
rawtitle: Implementation of four common functions on an {LNS} co-processor
entry:
@Article{Das:1995:IFC,
  author =       "D. Das and K. Mukhopadhyaya and B. P. Sinha",
  title =        "Implementation of four common functions on an {LNS}
                 co-processor",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "44",
  number =       "1",
  pages =        "155--161",
  month =        jan,
  year =         "1995",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.367997",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1990.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "We propose a scheme for evaluating four commonly used
                 functions namely, (1) inverse trigonometric functions,
                 (2) trigonometric functions, (3) the exponential
                 function, and (4) the logarithmic function with the
                 help of a logarithmic number system (\ldots{})",
}


