# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Dinda:2020:SFP
author: Peter Dinda and Alex Bernat and Conor Hetland
title: Spying on the floating point behavior of existing, unmodified scientific applications
pages: 5--16
year: 2020
bibdate: Mon Sep 11 06:53:07 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 06:53:07 ???
acknowledgement: ack-nhfb
rawauthor: Peter Dinda and Alex Bernat and Conor Hetland
rawtitle: Spying on the floating point behavior of existing, unmodified scientific applications
booktitle:
Proceedings of the 29th International Symposium on High-Performance Parallel and Distributed Computing

rawbooktitle:
Proceedings of the 29th International Symposium on High-Performance Parallel and Distributed Computing

entry:
@InProceedings{Dinda:2020:SFP,
  author =       "Peter Dinda and Alex Bernat and Conor Hetland",
  editor =       "????",
  booktitle =    "Proceedings of the 29th International Symposium on
                 High-Performance Parallel and Distributed Computing",
  title =        "Spying on the floating point behavior of existing,
                 unmodified scientific applications",
  publisher =    "????",
  address =      "????",
  pages =        "5--16",
  year =         "2020",
  bibdate =      "Mon Sep 11 06:53:07 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Dolgov:2020:PCI
author: Sergey Dolgov and Dmitry Savostyanov
title: Parallel cross interpolation for high-precision calculation of high-dimensional integrals
journal: j-COMP-PHYS-COMM
volume: 246
pages: Article 106869
month: jan
monthnumber: 1
year: 2020
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2019.106869
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Tue Oct 29 14:07:57 MDT 2019
bibtimestamp: 2019.10.29 14:07:57 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0010465519302565
fjournal: Computer Physics Communications
remark: See cite Bailey:2006:IIC,Bailey:2015:HPA.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Sergey Dolgov and Dmitry Savostyanov
rawtitle: Parallel cross interpolation for high-precision calculation of high-dimensional integrals
ORCID: Bailey, David H./0000-0002-7574-8342; Borwein, Jonathan/0000-0002-1263-0646
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/b/borwein-jonathan-m.bib; https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
Cross interpolation; High precision; High-dimensional integration; Ising integrals; Ising model; Monte Carlo integration; Parallel algorithms; quasi Monte Carlo integration; Tensor train format

entry:
@Article{Dolgov:2020:PCI,
  author =       "Sergey Dolgov and Dmitry Savostyanov",
  title =        "Parallel cross interpolation for high-precision
                 calculation of high-dimensional integrals",
  journal =      j-COMP-PHYS-COMM,
  volume =       "246",
  number =       "??",
  pages =        "Article 106869",
  month =        jan,
  year =         "2020",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2019.106869",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Tue Oct 29 14:07:57 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/b/borwein-jonathan-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465519302565",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
  keywords =     "Cross interpolation; High precision; High-dimensional
                 integration; Ising integrals; Ising model; Monte Carlo
                 integration; Parallel algorithms; quasi Monte Carlo
                 integration; Tensor train format",
  ORCID-numbers = "Bailey, David H./0000-0002-7574-8342; Borwein,
                 Jonathan/0000-0002-1263-0646",
  remark =       "See \cite{Bailey:2006:IIC,Bailey:2015:HPA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Dutt:2020:HSL
author: Rashi Dutt and Amit Acharyya
booktitle: 2020 European Conference on Circuit Theory and Design (ECCTD)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2020
DOI: https://doi.org/10.1109/ECCTD49232.2020.9218287
bibdate: Mon Oct 27 10:32:44 2025
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Rashi Dutt and Amit Acharyya
rawbooktitle: {2020 European Conference on Circuit Theory and Design (ECCTD)}
title:
A High Speed and Low Complexity Architecture Design Methodology for Square Root Unscented Kalman Filter based SLAM

keywords:
Complexity theory; Computational modeling; Computer architecture; Covariance matrices; Householder CORDIC; Kalman filters; Low Complexity Architecture; Simultaneous localization and mapping; Simultaneous Localization and Mapping; Square Root Unscented Kalman Filter

rawtitle:
A High Speed and Low Complexity Architecture Design Methodology for Square Root Unscented {Kalman} Filter based {SLAM}

entry:
@InProceedings{Dutt:2020:HSL,
  author =       "Rashi Dutt and Amit Acharyya",
  booktitle =    "{2020 European Conference on Circuit Theory and Design
                 (ECCTD)}",
  title =        "A High Speed and Low Complexity Architecture Design
                 Methodology for Square Root Unscented {Kalman} Filter
                 based {SLAM}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ECCTD49232.2020.9218287",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Complexity theory; Computational modeling; Computer
                 architecture; Covariance matrices; Householder CORDIC;
                 Kalman filters; Low Complexity Architecture;
                 Simultaneous localization and mapping; Simultaneous
                 Localization and Mapping; Square Root Unscented Kalman
                 Filter",
}


bibtype: inproceedings
filename: fparith.bib
label: Elkhatib:2020:HOM
author: Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
title: Highly Optimized Montgomery Multiplier for SIKE Primes on FPGA
crossref: Cornea:2020:ISC
pages: 64--71
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00018
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
rawtitle: Highly Optimized {Montgomery} Multiplier for {SIKE} Primes on {FPGA}
abstract:
New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were overestimated [1], [2]. In this paper, we develop a highly optimized Ep Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We then implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 29% faster and occupies 30% less hardware resources in comparison to the leading counterpart available in the literature [3] and implementations for other security levels achieved similar improvement.

keywords:
ARITH 2020; ARITH-27; Computer architecture; Elliptic curve cryptography; Hardware; hardware architectures; isogeny-based cryptography; Montgomery multiplication; NIST; post-quantum cryptography; SIKE

rawabstract:
New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were overestimated [1], [2]. In this paper, we develop a highly optimized Ep Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We then implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 29\% faster and occupies 30\% less hardware resources in comparison to the leading counterpart available in the literature [3] and implementations for other security levels achieved similar improvement.

entry:
@InProceedings{Elkhatib:2020:HOM,
  author =       "Rami Elkhatib and Reza Azarderakhsh and Mehran
                 Mozaffari-Kermani",
  title =        "Highly Optimized {Montgomery} Multiplier for {SIKE}
                 Primes on {FPGA}",
  crossref =     "Cornea:2020:ISC",
  pages =        "64--71",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00018",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "New primes were proposed for Supersingular Isogeny Key
                 Encapsulation (SIKE) in NIST standardization process of
                 Round 2 after further cryptanalysis research showed
                 that the security levels of the initial primes chosen
                 were overestimated [1], [2]. In this paper, we develop
                 a highly optimized Ep Montgomery multiplication
                 algorithm and architecture that further utilizes the
                 special form of SIKE prime compared to previous
                 implementations available in the literature. We then
                 implement SIKE for all Round 2 NIST security levels
                 (SIKEp434 for NIST security level 1, SIKEp503 for NIST
                 security level 2, SIKEp610 for NIST security level 3,
                 and SIKEp751 for NIST security level 5) on Xilinx
                 Virtex 7 using the proposed multiplier. Our best
                 implementation (NIST security level 1) runs 29\% faster
                 and occupies 30\% less hardware resources in comparison
                 to the leading counterpart available in the literature
                 [3] and implementations for other security levels
                 achieved similar improvement.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Computer architecture; Elliptic
                 curve cryptography; Hardware; hardware architectures;
                 isogeny-based cryptography; Montgomery multiplication;
                 NIST; post-quantum cryptography; SIKE",
}


bibtype: misc
filename: fparith.bib
label: Erickson:2020:GNF
author: Jack Erickson
title: Generate Native Floating-Point FPGA Implementations for Field-Oriented Control of Motors
pages: 64--71
day: 17
month: feb
monthnumber: 2
year: 2020
bibdate: Mon Feb 17 10:32:39 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.17 10:32:39 ???
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Jack Erickson
rawtitle: Generate Native Floating-Point {FPGA} Implementations for Field-Oriented Control of Motors
URL:
https://www.mathworks.com/videos/generate-native-floating-point-fpga-implementations-for-field-oriented-control-of-motors.html

abstract:
HDL Coder now supports native floating-point code generation, where you can implement your high-dynamic range operations in single-precision floating point, and generate VHDL or Verilog code directly without converting to fixed-point types and operations.

rawabstract:
HDL Coder now supports native floating-point code generation, where you can implement your high-dynamic range operations in single-precision floating point, and generate VHDL or Verilog code directly without converting to fixed-point types and operations.

entry:
@Misc{Erickson:2020:GNF,
  author =       "Jack Erickson",
  title =        "Generate Native Floating-Point {FPGA} Implementations
                 for Field-Oriented Control of Motors",
  howpublished = "MathWorks Web site.",
  day =          "17",
  month =        feb,
  year =         "2020",
  bibdate =      "Mon Feb 17 10:32:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.mathworks.com/videos/generate-native-floating-point-fpga-implementations-for-field-oriented-control-of-motors.html",
  abstract =     "HDL Coder now supports native floating-point code
                 generation, where you can implement your high-dynamic
                 range operations in single-precision floating point,
                 and generate VHDL or Verilog code directly without
                 converting to fixed-point types and operations.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Fang:2020:URC
author: Linlin Fang and Bingyi Li and Yizhuang Xie and He Chen and Long Pang
title: A unified reconfigurable CORDIC processor for floating-point arithmetic
journal: j-INT-J-ELECTRON
volume: 107
number: 9
pages: 1436--1450
month: feb
monthnumber: 2
year: 2020
CODEN: IJELA2
DOI: https://doi.org/10.1080/00207217.2020.1726497
ISSN: 1362-3060 OR 13623060
ISSNL: 0020-7217 OR 00207217
bibdate: Tue Nov 11 14:27:07 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.11.11 14:27:07 ???
fjournal: International Journal of Electronics Theoretical & Experimental
acknowledgement: ack-nhfb
rawauthor: Linlin Fang and Bingyi Li and Yizhuang Xie and He Chen and Long Pang
rawtitle: A unified reconfigurable {CORDIC} processor for floating-point arithmetic
entry:
@Article{Fang:2020:URC,
  author =       "Linlin Fang and Bingyi Li and Yizhuang Xie and He Chen
                 and Long Pang",
  title =        "A unified reconfigurable {CORDIC} processor for
                 floating-point arithmetic",
  journal =      j-INT-J-ELECTRON,
  volume =       "107",
  number =       "9",
  pages =        "1436--1450",
  month =        feb,
  year =         "2020",
  CODEN =        "IJELA2",
  DOI =          "https://doi.org/10.1080/00207217.2020.1726497",
  ISSN =         "1362-3060",
  ISSN-L =       "0020-7217",
  bibdate =      "Tue Nov 11 14:27:07 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Electronics Theoretical \&
                 Experimental",
}


bibtype: techreport
filename: fparith.bib
label: Fog:2020:FPE
author: Agner Fog
title: Floating point exception tracking and NAN propagation
type: Report
institution: Technical University of Denmark
address: Lyngby, Denmark
pages: 10
day: 27
month: apr
monthnumber: 4
year: 2020
bibdate: Wed May 17 11:52:28 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.05.17 11:52:28 ???
URL: https://www.agner.org/optimize/nan_propagation.pdf
remark: See also later revisions cite Fog:2023:FPE and cite Fog:2024:FPE.
acknowledgement: ack-nhfb
rawauthor: Agner Fog
rawtitle: Floating point exception tracking and {NAN} propagation
abstract:
The most common methods for detecting floating point errors are based on exception trapping or a global status register. These methods are inefficient in modern systems that use out-of-order parallelism and single-instruction-multiple-data (SIMD) parallelism for improving performance. It is argued that a method based on NAN propagation is more efficient and deterministic. Problems with NAN propagation in current systems are discussed. Examples of implementation in the C++ vector class library and in an experimental instruction set named ForwardCom are presented. The IEEE-754 standard for floating point arithmetic may need adjustment to accommodate the needs of modern forms of parallelism.

rawabstract:
The most common methods for detecting floating point errors are based on exception trapping or a global status register. These methods are inefficient in modern systems that use out-of-order parallelism and single-instruction-multiple-data (SIMD) parallelism for improving performance. It is argued that a method based on NAN propagation is more efficient and deterministic. Problems with NAN propagation in current systems are discussed. Examples of implementation in the C++ vector class library and in an experimental instruction set named ForwardCom are presented. The IEEE-754 standard for floating point arithmetic may need adjustment to accommodate the needs of modern forms of parallelism.

entry:
@TechReport{Fog:2020:FPE,
  author =       "Agner Fog",
  title =        "Floating point exception tracking and {NAN}
                 propagation",
  type =         "Report",
  institution =  "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "10",
  day =          "27",
  month =        apr,
  year =         "2020",
  bibdate =      "Wed May 17 11:52:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/nan_propagation.pdf",
  abstract =     "The most common methods for detecting floating point
                 errors are based on exception trapping or a global
                 status register. These methods are inefficient in
                 modern systems that use out-of-order parallelism and
                 single-instruction-multiple-data (SIMD) parallelism for
                 improving performance. It is argued that a method based
                 on NAN propagation is more efficient and deterministic.
                 Problems with NAN propagation in current systems are
                 discussed. Examples of implementation in the C++ vector
                 class library and in an experimental instruction set
                 named ForwardCom are presented. The IEEE-754 standard
                 for floating point arithmetic may need adjustment to
                 accommodate the needs of modern forms of parallelism.",
  acknowledgement = ack-nhfb,
  remark =       "See also later revisions \cite{Fog:2023:FPE} and
                 \cite{Fog:2024:FPE}.",
}


bibtype: article
filename: fparith.bib
label: Gallois-Wong:2020:OIP
author: Diane Gallois-Wong and Sylvie Boldo and Pascal Cuoq
title: Optimal inverse projection of floating-point addition
journal: j-NUMER-ALGORITHMS
volume: 83
number: 3
pages: 957--986
month: mar
monthnumber: 3
year: 2020
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-019-00711-z
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Tue Feb 18 08:09:21 MST 2020
bibtimestamp: 2020.02.18 08:09:21 MST
fjournal: Numerical Algorithms
keywords: floating-point arithmetic; interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Diane Gallois-Wong and Sylvie Boldo and Pascal Cuoq
rawtitle: Optimal inverse projection of floating-point addition
bibsource:
http://link.springer.com/journal/11075/83/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib

entry:
@Article{Gallois-Wong:2020:OIP,
  author =       "Diane Gallois-Wong and Sylvie Boldo and Pascal Cuoq",
  title =        "Optimal inverse projection of floating-point
                 addition",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "83",
  number =       "3",
  pages =        "957--986",
  month =        mar,
  year =         "2020",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-019-00711-z",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Tue Feb 18 08:09:21 MST 2020",
  bibsource =    "http://link.springer.com/journal/11075/83/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  keywords =     "floating-point arithmetic; interval arithmetic",
}


bibtype: article
filename: fparith.bib
label: Godunov:2020:ACC
author: A. Godunov
title: Algorithms for Calculating Correctly Rounded Exponential Function in Double-Precision Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 9
pages: 1388--1400
month: sep
monthnumber: 9
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2020.2972901
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Aug 12 14:58:16 2020
bibtimestamp: 2020.08.12 14:58:16 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Godunov
rawtitle: Algorithms for Calculating Correctly Rounded Exponential Function in Double-Precision Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

abstract:
Correct rounding provides the best approximation of the exponential function by double-precision numbers. To obtain the correctly rounded exponential of some arguments, the exponential should be calculated with high accuracy. For small arguments, even higher accuracy is required. This article presents simple and very fast algorithms for small arguments. Yet another algorithm presented here demonstrates a good maximum execution time, which may be important for critical applications. This algorithm can be combined with some other already existing algorithms to achieve the best maximum and average execution times. All proposed algorithms calculate the correctly rounded exponential function for all rounding modes and use only double-precision arithmetic for computation. In the argument reduction step, precalculated tables are used. Test implementations of these algorithms were developed in C language and are portable. Full proofs are presented either in this article itself or in its appendices.

rawabstract:
Correct rounding provides the best approximation of the exponential function by double-precision numbers. To obtain the correctly rounded exponential of some arguments, the exponential should be calculated with high accuracy. For small arguments, even higher accuracy is required. This article presents simple and very fast algorithms for small arguments. Yet another algorithm presented here demonstrates a good maximum execution time, which may be important for critical applications. This algorithm can be combined with some other already existing algorithms to achieve the best maximum and average execution times. All proposed algorithms calculate the correctly rounded exponential function for all rounding modes and use only double-precision arithmetic for computation. In the argument reduction step, precalculated tables are used. Test implementations of these algorithms were developed in C language and are portable. Full proofs are presented either in this article itself or in its appendices.

entry:
@Article{Godunov:2020:ACC,
  author =       "A. Godunov",
  title =        "Algorithms for Calculating Correctly Rounded
                 Exponential Function in Double-Precision Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "9",
  pages =        "1388--1400",
  month =        sep,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2020.2972901",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Aug 12 14:58:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Correct rounding provides the best approximation of
                 the exponential function by double-precision numbers.
                 To obtain the correctly rounded exponential of some
                 arguments, the exponential should be calculated with
                 high accuracy. For small arguments, even higher
                 accuracy is required. This article presents simple and
                 very fast algorithms for small arguments. Yet another
                 algorithm presented here demonstrates a good maximum
                 execution time, which may be important for critical
                 applications. This algorithm can be combined with some
                 other already existing algorithms to achieve the best
                 maximum and average execution times. All proposed
                 algorithms calculate the correctly rounded exponential
                 function for all rounding modes and use only
                 double-precision arithmetic for computation. In the
                 argument reduction step, precalculated tables are used.
                 Test implementations of these algorithms were developed
                 in C language and are portable. Full proofs are
                 presented either in this article itself or in its
                 appendices.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Gonzalez-Navarro:2020:NRN
author: S. Gonzalez-Navarro and J. Hormigo
title: New Results on Non-Normalized Floating-Point Formats
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 12
pages: 1733--1744
month: dec
monthnumber: 12
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2929039
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Nov 24 09:42:22 2020
bibtimestamp: 2020.11.24 09:42:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Gonz{\'a}lez-Navarro and J. Hormigo
rawtitle: New Results on Non-Normalized Floating-Point Formats
entry:
@Article{Gonzalez-Navarro:2020:NRN,
  author =       "S. Gonz{\'a}lez-Navarro and J. Hormigo",
  title =        "New Results on Non-Normalized Floating-Point Formats",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "12",
  pages =        "1733--1744",
  month =        dec,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2929039",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Nov 24 09:42:22 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Goualard:2020:GRF
author: Frederic Goualard
title: Generating Random Floating-Point Numbers by Dividing Integers: a Case Study
crossref: Krzhizhanovskaya:2020:CSI
pages: 15--28
year: 2020
DOI: https://doi.org/10.1007/978-3-030-50417-5_2
bibdate: Thu Jun 25 07:31:47 2020
bibtimestamp: 2020.06.25 07:31:47 ???
acknowledgement: ack-nhfb
rawauthor: Fr{\'e}d{\'e}ric Goualard
rawtitle: Generating Random Floating-Point Numbers by Dividing Integers: a Case Study
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/julia.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib

keywords:
error analysis; floating-point number; GMP; Julia; Matlab; Mersenne Twister; PRNG; pseudo-random numbers; random number

entry:
@InProceedings{Goualard:2020:GRF,
  author =       "Fr{\'e}d{\'e}ric Goualard",
  title =        "Generating Random Floating-Point Numbers by Dividing
                 Integers: a Case Study",
  crossref =     "Krzhizhanovskaya:2020:CSI",
  pages =        "15--28",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-50417-5_2",
  bibdate =      "Thu Jun 25 07:31:47 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/julia.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  acknowledgement = ack-nhfb,
  keywords =     "error analysis; floating-point number; GMP; Julia;
                 Matlab; Mersenne Twister; PRNG; pseudo-random numbers;
                 random number",
}


bibtype: inproceedings
filename: fparith.bib
label: Graillat:2020:ASF
author: Stef Graillat and Vincent Lefevre and Jean-Michel Muller
title: Alternative Split Functions and Dekker's Product
crossref: Cornea:2020:ISC
pages: 41--47
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00015
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Vincent Lef{\`e}vre and Jean-Michel Muller
rawtitle: Alternative Split Functions and {Dekker}'s Product
abstract:
We introduce algorithms for splitting a positive binary floating-point number into two numbers of around half the system precision, using arithmetic operations all rounded either toward $-$ or toward $+$. We use these algorithms to compute exact products (i.e., to express the product of two floating-point numbers as the unevaluated sum of two floating-point numbers, the rounded product and an error term). This is similar to the classical Dekker product, adapted here to directed roundings.

keywords:
accurate products; Approximation algorithms; ARITH 2020; ARITH-27; Cognition; Digital arithmetic; Floating-point arithmetic; Indexes; Lips; split functions; Standards; Switches

rawabstract:
We introduce algorithms for splitting a positive binary floating-point number into two numbers of around half the system precision, using arithmetic operations all rounded either toward $-$ or toward $+$. We use these algorithms to compute exact products (i.e., to express the product of two floating-point numbers as the unevaluated sum of two floating-point numbers, the rounded product and an error term). This is similar to the classical Dekker product, adapted here to directed roundings.

entry:
@InProceedings{Graillat:2020:ASF,
  author =       "Stef Graillat and Vincent Lef{\`e}vre and Jean-Michel
                 Muller",
  title =        "Alternative Split Functions and {Dekker}'s Product",
  crossref =     "Cornea:2020:ISC",
  pages =        "41--47",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00015",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We introduce algorithms for splitting a positive
                 binary floating-point number into two numbers of around
                 half the system precision, using arithmetic operations
                 all rounded either toward $-$ or toward $+$. We use
                 these algorithms to compute exact products (i.e., to
                 express the product of two floating-point numbers as
                 the unevaluated sum of two floating-point numbers, the
                 rounded product and an error term). This is similar to
                 the classical Dekker product, adapted here to directed
                 roundings.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate products; Approximation algorithms; ARITH
                 2020; ARITH-27; Cognition; Digital arithmetic;
                 Floating-point arithmetic; Indexes; Lips; split
                 functions; Standards; Switches",
}


bibtype: article
filename: fparith.bib
label: Grutzmacher:2020:APC
author: Thomas Grutzmacher and Terry Cojean and Goran Flegar and Hartwig Anzt and Enrique S. Quintana-Orti
title: Acceleration of PageRank with Customized Precision Based on Mantissa Segmentation
journal: j-TOPC
volume: 7
number: 1
pages: 4:1--4:19
month: apr
monthnumber: 4
year: 2020
DOI: https://doi.org/10.1145/3380934
ISSN: 2329-4949 (print), 2329-4957 (electronic) OR 23294949 (print), 23294957 (electronic)
ISSNL: 2329-4949 OR 23294949
bibdate: Mon Apr 6 08:56:55 MDT 2020
bibtimestamp: 2020.04.06 08:56:55 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3380934
fjournal: ACM Transactions on Parallel Computing
acknowledgement: ack-nhfb
articleno: 4
journalURL: https://dl.acm.org/loi/topc
rawtitle: Acceleration of {PageRank} with Customized Precision Based on Mantissa Segmentation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pagerank.bib; https://www.math.utah.edu/pub/tex/bib/topc.bib

abstract:
We describe the application of a communication-reduction technique for the PageRank algorithm that dynamically adapts the precision of the data access to the numerical requirements of the algorithm as the iteration converges. Our variable-precision strategy, using a customized precision format based on mantissa segmentation (CPMS), abandons the IEEE 754 single- and double-precision number representation formats employed in the standard implementation of PageRank, and instead handles the data in memory using a customized floating-point format. The customized format enables fast data access in different accuracy, prevents overflow/underflow by preserving the IEEE 754 double-precision exponent, and efficiently avoids data duplication, since all bits of the original IEEE 754 double-precision mantissa are preserved in memory, but re-organized for efficient reduced precision access. With this approach, the truncated values (omitting significand bits), as well as the original IEEE double-precision values, can be retrieved without duplicating the data in different formats.par Our numerical experiments on an NVIDIA V100 GPU (Volta architecture) and a server equipped with two Intel Xeon Platinum 8168 CPUs (48 cores in total) expose that, compared with a standard IEEE double-precision implementation, the CPMS-based PageRank completes about 10% faster if high-accuracy output is needed, and about 30% faster if reduced output accuracy is acceptable.

rawabstract:
We describe the application of a communication-reduction technique for the PageRank algorithm that dynamically adapts the precision of the data access to the numerical requirements of the algorithm as the iteration converges. Our variable-precision strategy, using a customized precision format based on mantissa segmentation (CPMS), abandons the IEEE 754 single- and double-precision number representation formats employed in the standard implementation of PageRank, and instead handles the data in memory using a customized floating-point format. The customized format enables fast data access in different accuracy, prevents overflow/underflow by preserving the IEEE 754 double-precision exponent, and efficiently avoids data duplication, since all bits of the original IEEE 754 double-precision mantissa are preserved in memory, but re-organized for efficient reduced precision access. With this approach, the truncated values (omitting significand bits), as well as the original IEEE double-precision values, can be retrieved without duplicating the data in different formats.\par Our numerical experiments on an NVIDIA V100 GPU (Volta architecture) and a server equipped with two Intel Xeon Platinum 8168 CPUs (48 cores in total) expose that, compared with a standard IEEE double-precision implementation, the CPMS-based PageRank completes about 10\% faster if high-accuracy output is needed, and about 30\% faster if reduced output accuracy is acceptable.

rawauthor:
Thomas Gr{\"u}tzmacher and Terry Cojean and Goran Flegar and Hartwig Anzt and Enrique S. Quintana-Ort{\'\i}

entry:
@Article{Grutzmacher:2020:APC,
  author =       "Thomas Gr{\"u}tzmacher and Terry Cojean and Goran
                 Flegar and Hartwig Anzt and Enrique S.
                 Quintana-Ort{\'\i}",
  title =        "Acceleration of {PageRank} with Customized Precision
                 Based on Mantissa Segmentation",
  journal =      j-TOPC,
  volume =       "7",
  number =       "1",
  pages =        "4:1--4:19",
  month =        apr,
  year =         "2020",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3380934",
  ISSN =         "2329-4949 (print), 2329-4957 (electronic)",
  ISSN-L =       "2329-4949",
  bibdate =      "Mon Apr 6 08:56:55 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pagerank.bib;
                 https://www.math.utah.edu/pub/tex/bib/topc.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3380934",
  abstract =     "We describe the application of a
                 communication-reduction technique for the PageRank
                 algorithm that dynamically adapts the precision of the
                 data access to the numerical requirements of the
                 algorithm as the iteration converges. Our
                 variable-precision strategy, using a customized
                 precision format based on mantissa segmentation (CPMS),
                 abandons the IEEE 754 single- and double-precision
                 number representation formats employed in the standard
                 implementation of PageRank, and instead handles the
                 data in memory using a customized floating-point
                 format. The customized format enables fast data access
                 in different accuracy, prevents overflow/underflow by
                 preserving the IEEE 754 double-precision exponent, and
                 efficiently avoids data duplication, since all bits of
                 the original IEEE 754 double-precision mantissa are
                 preserved in memory, but re-organized for efficient
                 reduced precision access. With this approach, the
                 truncated values (omitting significand bits), as well
                 as the original IEEE double-precision values, can be
                 retrieved without duplicating the data in different
                 formats.\par

                 Our numerical experiments on an NVIDIA V100 GPU (Volta
                 architecture) and a server equipped with two Intel Xeon
                 Platinum 8168 CPUs (48 cores in total) expose that,
                 compared with a standard IEEE double-precision
                 implementation, the CPMS-based PageRank completes about
                 10\% faster if high-accuracy output is needed, and
                 about 30\% faster if reduced output accuracy is
                 acceptable.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Transactions on Parallel Computing",
  journal-URL =  "https://dl.acm.org/loi/topc",
}


bibtype: inproceedings
filename: fparith.bib
label: Gu:2020:NMM
author: Zhen Gu and Shuguo Li
title: A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication
crossref: Cornea:2020:ISC
pages: 33--40
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00014
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Zhen Gu and Shuguo Li
rawtitle: A Novel Method of Modular Multiplication Based on {Karatsuba}-like Multiplication
abstract:
In this paper, we propose a novel method of modular multiplication which embeds the modular reduction in the evaluation and interpolation parts of the Karatsuba-like multiplication. Before, the modular reduction can only be performed independently between multiplication. However, applying our method, the interpolation of the previous multiplication, modular reduction and evaluation of the next multiplication are merged as a whole step, which leads to the simplification of computations and improvement of parallelism. This method can be applied to the modular multiplication with simple moduli like NIST primes, and for general moduli, we can apply this method by using Montgomery modular multiplication instead.

keywords:
ARITH 2020; ARITH-27; Digital arithmetic; Interpolation; Karatsuba-like multiplication; Microelectronics; Modular multiplication; Montgomery modular multiplication; NIST; Public key cryptography; Transforms

rawabstract:
In this paper, we propose a novel method of modular multiplication which embeds the modular reduction in the evaluation and interpolation parts of the Karatsuba-like multiplication. Before, the modular reduction can only be performed independently between multiplication. However, applying our method, the interpolation of the previous multiplication, modular reduction and evaluation of the next multiplication are merged as a whole step, which leads to the simplification of computations and improvement of parallelism. This method can be applied to the modular multiplication with simple moduli like NIST primes, and for general moduli, we can apply this method by using Montgomery modular multiplication instead.

entry:
@InProceedings{Gu:2020:NMM,
  author =       "Zhen Gu and Shuguo Li",
  title =        "A Novel Method of Modular Multiplication Based on
                 {Karatsuba}-like Multiplication",
  crossref =     "Cornea:2020:ISC",
  pages =        "33--40",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00014",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we propose a novel method of modular
                 multiplication which embeds the modular reduction in
                 the evaluation and interpolation parts of the
                 Karatsuba-like multiplication. Before, the modular
                 reduction can only be performed independently between
                 multiplication. However, applying our method, the
                 interpolation of the previous multiplication, modular
                 reduction and evaluation of the next multiplication are
                 merged as a whole step, which leads to the
                 simplification of computations and improvement of
                 parallelism. This method can be applied to the modular
                 multiplication with simple moduli like NIST primes, and
                 for general moduli, we can apply this method by using
                 Montgomery modular multiplication instead.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Digital arithmetic;
                 Interpolation; Karatsuba-like multiplication;
                 Microelectronics; Modular multiplication; Montgomery
                 modular multiplication; NIST; Public key cryptography;
                 Transforms",
}


bibtype: inproceedings
filename: fparith.bib
label: Guo:2020:EGE
author: Hui Guo and Cindy Rubio-Gonzalez
booktitle: Proceedings of the ACM/IEEE 42nd International Conference on Software Engineering
title: Efficient generation of error-inducing floating-point inputs via symbolic execution
publisher: pub-ACM
address: pub-ACM:adr
pages: 33--40
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1145/3377811.3380359
bibdate: Sat Dec 9 08:57:26 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.09 08:57:26 ???
acknowledgement: ack-nhfb
rawauthor: Hui Guo and Cindy Rubio-Gonz{\'a}lez
rawbooktitle: Proceedings of the {ACM/IEEE 42nd International Conference on Software Engineering}
rawtitle: Efficient generation of error-inducing floating-point inputs via symbolic execution
abstract:
Floating point is widely used in software to emulate arithmetic over reals. Unfortunately, floating point leads to rounding errors that propagate and accumulate during execution. Generating inputs to maximize the numerical error is critical when evaluating the accuracy of floating-point code. In this paper, we formulate the problem of generating high error-inducing floating-point inputs as a code coverage maximization problem solved using symbolic execution. Specifically, we define inaccuracy checks to detect large precision loss and cancellation. We inject these checks at strategic program locations to construct specialized branches that, when covered by a given input, are likely to lead to large errors in the result. We apply symbolic execution to generate inputs that exercise these specialized branches, and describe optimizations that make our approach practical. We implement a tool named FPGen and present an evaluation on 21 numerical programs including matrix computation and statistics libraries. We show that FPGen exposes errors for 20 of these programs and triggers errors that are, on average, over 2 orders of magnitude larger than the state of the art.

rawabstract:
Floating point is widely used in software to emulate arithmetic over reals. Unfortunately, floating point leads to rounding errors that propagate and accumulate during execution. Generating inputs to maximize the numerical error is critical when evaluating the accuracy of floating-point code. In this paper, we formulate the problem of generating high error-inducing floating-point inputs as a code coverage maximization problem solved using symbolic execution. Specifically, we define inaccuracy checks to detect large precision loss and cancellation. We inject these checks at strategic program locations to construct specialized branches that, when covered by a given input, are likely to lead to large errors in the result. We apply symbolic execution to generate inputs that exercise these specialized branches, and describe optimizations that make our approach practical. We implement a tool named FPGen and present an evaluation on 21 numerical programs including matrix computation and statistics libraries. We show that FPGen exposes errors for 20 of these programs and triggers errors that are, on average, over 2 orders of magnitude larger than the state of the art.

entry:
@InProceedings{Guo:2020:EGE,
  author =       "Hui Guo and Cindy Rubio-Gonz{\'a}lez",
  booktitle =    "Proceedings of the {ACM/IEEE 42nd International
                 Conference on Software Engineering}",
  title =        "Efficient generation of error-inducing floating-point
                 inputs via symbolic execution",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1145/3377811.3380359",
  bibdate =      "Sat Dec 9 08:57:26 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point is widely used in software to emulate
                 arithmetic over reals. Unfortunately, floating point
                 leads to rounding errors that propagate and accumulate
                 during execution. Generating inputs to maximize the
                 numerical error is critical when evaluating the
                 accuracy of floating-point code. In this paper, we
                 formulate the problem of generating high error-inducing
                 floating-point inputs as a code coverage maximization
                 problem solved using symbolic execution. Specifically,
                 we define inaccuracy checks to detect large precision
                 loss and cancellation. We inject these checks at
                 strategic program locations to construct specialized
                 branches that, when covered by a given input, are
                 likely to lead to large errors in the result. We apply
                 symbolic execution to generate inputs that exercise
                 these specialized branches, and describe optimizations
                 that make our approach practical. We implement a tool
                 named FPGen and present an evaluation on 21 numerical
                 programs including matrix computation and statistics
                 libraries. We show that FPGen exposes errors for 20 of
                 these programs and triggers errors that are, on
                 average, over 2 orders of magnitude larger than the
                 state of the art.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Guo:2020:PIL
author: Hui Guo and Ignacio Laguna and Cindy Rubio-Gonzalez
title: pLiner: isolating lines of floating-point code for compiler-induced variability
crossref: IEEE:2020:SPI
pages: 1--14
year: 2020
bibdate: Mon Sep 11 08:22:13 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 08:22:13 ???
acknowledgement: ack-nhfb
articleno: 49
rawauthor: Hui Guo and Ignacio Laguna and Cindy Rubio-Gonz{\'a}lez
rawtitle: {pLiner}: isolating lines of floating-point code for compiler-induced variability
abstract:
Scientific applications are often impacted by numerical inconsistencies when using different compilers or when a compiler is used with different optimization levels; such inconsistencies hinder reproducibility and can be hard to diagnose. We present pLiner, a tool to automatically pinpoint code lines that trigger compiler-induced variability. pLiner uses a novel approach to enhance floating-point precision at different levels of code granularity, and performs a guided search to identify locations affected by numerical inconsistencies. We demonstrate pLiner on a real-world numerical inconsistency that required weeks to diagnose, which pLiner isolates in minutes. We also evaluate pLiner on 100 synthetic programs, and the NAS Parallel Benchmarks (NPB). On the synthetic programs, pLiner detects the affected lines of code 87% of the time while the state-of-the-art approach only detects the affected lines 6% of the time. Furthermore, pLiner successfully isolates all numerical inconsistencies found in the NPB.

rawabstract:
Scientific applications are often impacted by numerical inconsistencies when using different compilers or when a compiler is used with different optimization levels; such inconsistencies hinder reproducibility and can be hard to diagnose. We present pLiner, a tool to automatically pinpoint code lines that trigger compiler-induced variability. pLiner uses a novel approach to enhance floating-point precision at different levels of code granularity, and performs a guided search to identify locations affected by numerical inconsistencies. We demonstrate pLiner on a real-world numerical inconsistency that required weeks to diagnose, which pLiner isolates in minutes. We also evaluate pLiner on 100 synthetic programs, and the NAS Parallel Benchmarks (NPB). On the synthetic programs, pLiner detects the affected lines of code 87\% of the time while the state-of-the-art approach only detects the affected lines 6\% of the time. Furthermore, pLiner successfully isolates all numerical inconsistencies found in the NPB.

entry:
@InProceedings{Guo:2020:PIL,
  author =       "Hui Guo and Ignacio Laguna and Cindy
                 Rubio-Gonz{\'a}lez",
  title =        "{pLiner}: isolating lines of floating-point code for
                 compiler-induced variability",
  crossref =     "IEEE:2020:SPI",
  pages =        "1--14",
  year =         "2020",
  bibdate =      "Mon Sep 11 08:22:13 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Scientific applications are often impacted by
                 numerical inconsistencies when using different
                 compilers or when a compiler is used with different
                 optimization levels; such inconsistencies hinder
                 reproducibility and can be hard to diagnose. We present
                 pLiner, a tool to automatically pinpoint code lines
                 that trigger compiler-induced variability. pLiner uses
                 a novel approach to enhance floating-point precision at
                 different levels of code granularity, and performs a
                 guided search to identify locations affected by
                 numerical inconsistencies. We demonstrate pLiner on a
                 real-world numerical inconsistency that required weeks
                 to diagnose, which pLiner isolates in minutes. We also
                 evaluate pLiner on 100 synthetic programs, and the NAS
                 Parallel Benchmarks (NPB). On the synthetic programs,
                 pLiner detects the affected lines of code 87\% of the
                 time while the state-of-the-art approach only detects
                 the affected lines 6\% of the time. Furthermore, pLiner
                 successfully isolates all numerical inconsistencies
                 found in the NPB.",
  acknowledgement = ack-nhfb,
  articleno =    "49",
}


bibtype: article
filename: fparith.bib
label: Harris:2020:APN
title: Array programming with NumPy
journal: j-NATURE
volume: 585
number: 7825
pages: 357--362
month: sep
monthnumber: 9
year: 2020
CODEN: NATUAS
DOI: https://doi.org/10.1038/s41586-020-2649-2
ISSN: 0028-0836 (print), 1476-4687 (electronic) OR 00280836 (print), 14764687 (electronic)
ISSNL: 0028-0836 OR 00280836
bibdate: Tue Jan 28 06:28:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.01.28 06:28:18 ???
fjournal: Nature
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://www.nature.com/nature/archive/
rawtitle: Array programming with {NumPy}
author:
Charles R. Harris and K. Jarrod Millman and Stefan J. van der Walt and Ralf Gommers and Pauli Virtanen and David Cournapeau and Eric Wieser and Julian Taylor and Sebastian Berg and Nathaniel J. Smith and Robert Kern and Matti Picus and Stephan Hoyer and Marten H. van Kerkwijk and Matthew Brett and Allan Haldane and Jaime Fernandez del Rio and Mark Wiebe and Pearu Peterson and Pierre Gerard-Marchant and Kevin Sheppard and Tyler Reddy and Warren Weckesser and Hameer Abbasi and Christoph Gohlke and Travis E. Oliphant

rawauthor:
Charles R. Harris and K. Jarrod Millman and St{\'e}fan J. van der Walt and Ralf Gommers and Pauli Virtanen and David Cournapeau and Eric Wieser and Julian Taylor and Sebastian Berg and Nathaniel J. Smith and Robert Kern and Matti Picus and Stephan Hoyer and Marten H. van Kerkwijk and Matthew Brett and Allan Haldane and Jaime Fern{\'a}ndez del R{\'\i}o and Mark Wiebe and Pearu Peterson and Pierre G{\'e}rard-Marchant and Kevin Sheppard and Tyler Reddy and Warren Weckesser and Hameer Abbasi and Christoph Gohlke and Travis E. Oliphant

entry:
@Article{Harris:2020:APN,
  author =       "Charles R. Harris and K. Jarrod Millman and St{\'e}fan
                 J. van der Walt and Ralf Gommers and Pauli Virtanen and
                 David Cournapeau and Eric Wieser and Julian Taylor and
                 Sebastian Berg and Nathaniel J. Smith and Robert Kern
                 and Matti Picus and Stephan Hoyer and Marten H. van
                 Kerkwijk and Matthew Brett and Allan Haldane and Jaime
                 Fern{\'a}ndez del R{\'\i}o and Mark Wiebe and Pearu
                 Peterson and Pierre G{\'e}rard-Marchant and Kevin
                 Sheppard and Tyler Reddy and Warren Weckesser and
                 Hameer Abbasi and Christoph Gohlke and Travis E.
                 Oliphant",
  title =        "Array programming with {NumPy}",
  journal =      j-NATURE,
  volume =       "585",
  number =       "7825",
  pages =        "357--362",
  month =        sep,
  year =         "2020",
  CODEN =        "NATUAS",
  DOI =          "https://doi.org/10.1038/s41586-020-2649-2",
  ISSN =         "0028-0836 (print), 1476-4687 (electronic)",
  ISSN-L =       "0028-0836",
  bibdate =      "Tue Jan 28 06:28:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Nature",
  journal-URL =  "http://www.nature.com/nature/archive/",
  keywords =     "accurate floating-point summation",
}


bibtype: techreport
filename: fparith.bib
label: Harvey:2020:IMT
author: David Harvey and Joris van der Hoeven
title: Integer multiplication in time $ O(n log n) $
type: Report
number: hal-02070778
institution: School of Mathematics and Statistics, University of New South Wales
address: Sydney NSW 2052, Australia
pages: 45
day: 28
month: nov
monthnumber: 11
year: 2020
bibdate: Thu May 16 15:51:09 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.16 15:51:09 ???
URL: https://hal.science/hal-02070778v2
acknowledgement: ack-nhfb
rawauthor: David Harvey and Joris van der Hoeven
rawtitle: Integer multiplication in time {$ O(n \log n) $}
abstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n log n)$ bit operations, thus confirming a conjecture of Schonhage and Strassen from 1971. Our complexity analysis takes place in the multitape Turing machine model, with integers encoded in the usual binary representation. Central to the new algorithm is a novel Gaussian resampling technique that enables us to reduce the integer multiplication problem to a collection of multidimensional discrete Fourier transforms over the complex numbers, whose dimensions are all powers of two. These transforms may then be evaluated rapidly by means of Nussbaumer's fast polynomial transforms.

rawabstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n \log n)$ bit operations, thus confirming a conjecture of Sch{\"o}nhage and Strassen from 1971. Our complexity analysis takes place in the multitape Turing machine model, with integers encoded in the usual binary representation. Central to the new algorithm is a novel Gaussian resampling technique that enables us to reduce the integer multiplication problem to a collection of multidimensional discrete Fourier transforms over the complex numbers, whose dimensions are all powers of two. These transforms may then be evaluated rapidly by means of Nussbaumer's fast polynomial transforms.

entry:
@TechReport{Harvey:2020:IMT,
  author =       "David Harvey and Joris van der Hoeven",
  title =        "Integer multiplication in time {$ O(n \log n) $}",
  type =         "Report",
  number =       "hal-02070778",
  institution =  "School of Mathematics and Statistics, University of
                 New South Wales",
  address =      "Sydney NSW 2052, Australia",
  pages =        "45",
  day =          "28",
  month =        nov,
  year =         "2020",
  bibdate =      "Thu May 16 15:51:09 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-02070778v2",
  abstract =     "We present an algorithm that computes the product of
                 two $n$-bit integers in $ O(n \log n)$ bit operations,
                 thus confirming a conjecture of Sch{\"o}nhage and
                 Strassen from 1971. Our complexity analysis takes place
                 in the multitape Turing machine model, with integers
                 encoded in the usual binary representation. Central to
                 the new algorithm is a novel Gaussian resampling
                 technique that enables us to reduce the integer
                 multiplication problem to a collection of
                 multidimensional discrete Fourier transforms over the
                 complex numbers, whose dimensions are all powers of
                 two. These transforms may then be evaluated rapidly by
                 means of Nussbaumer's fast polynomial transforms.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hickmann:2020:INN
title: Intel Nervana Neural Network Processor-T (NNP-T) Fused Floating Point Many-Term Dot Product
crossref: Cornea:2020:ISC
pages: 133--136
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00029
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawtitle: {Intel Nervana Neural Network Processor-T (NNP-T)} Fused Floating Point Many-Term Dot Product
author:
Brian Hickmann and Jieasheng Chen and Michael Rotzin and Andrew Yang and Maciej Urbanski and Sasikanth Avancha

abstract:
Intel's Nervana Neural Network Processor for Training (NNP-T) contains at its core an advanced floating point dot product design to accelerate the matrix multiplication operations found in many AI applications. Each Matrix Processing Unit (MPU) on the Intel NNP-T can process a 32x32 BFloat16 matrix multiplication every 32 cycles, accumulating the result in single precision (FP32). To reduce hardware costs, the MPU uses a fused many-term floating point dot product design with block alignment of the many input terms during addition, resulting in a unique datapath with several interesting design trade-offs. In this paper, we describe the details of the MPU pipeline, discuss the trade-offs made in the design, and present information on the accuracy of the computation as compared to traditional FMA implementations.

keywords:
Adders; ARITH 2020; ARITH-27; Artificial neural networks; deep learning; floating point dot product; Hardware; Machine learning; matrix multiplication; Tensile stress; tensor; Training

rawabstract:
Intel's Nervana Neural Network Processor for Training (NNP-T) contains at its core an advanced floating point dot product design to accelerate the matrix multiplication operations found in many AI applications. Each Matrix Processing Unit (MPU) on the Intel NNP-T can process a 32x32 BFloat16 matrix multiplication every 32 cycles, accumulating the result in single precision (FP32). To reduce hardware costs, the MPU uses a fused many-term floating point dot product design with block alignment of the many input terms during addition, resulting in a unique datapath with several interesting design trade-offs. In this paper, we describe the details of the MPU pipeline, discuss the trade-offs made in the design, and present information on the accuracy of the computation as compared to traditional FMA implementations.

rawauthor:
Brian Hickmann and Jieasheng Chen and Michael Rotzin and Andrew Yang and Maciej Urbanski and Sasikanth Avancha

entry:
@InProceedings{Hickmann:2020:INN,
  author =       "Brian Hickmann and Jieasheng Chen and Michael Rotzin
                 and Andrew Yang and Maciej Urbanski and Sasikanth
                 Avancha",
  title =        "{Intel Nervana Neural Network Processor-T (NNP-T)}
                 Fused Floating Point Many-Term Dot Product",
  crossref =     "Cornea:2020:ISC",
  pages =        "133--136",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00029",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Intel's Nervana Neural Network Processor for Training
                 (NNP-T) contains at its core an advanced floating point
                 dot product design to accelerate the matrix
                 multiplication operations found in many AI
                 applications. Each Matrix Processing Unit (MPU) on the
                 Intel NNP-T can process a 32x32 BFloat16 matrix
                 multiplication every 32 cycles, accumulating the result
                 in single precision (FP32). To reduce hardware costs,
                 the MPU uses a fused many-term floating point dot
                 product design with block alignment of the many input
                 terms during addition, resulting in a unique datapath
                 with several interesting design trade-offs. In this
                 paper, we describe the details of the MPU pipeline,
                 discuss the trade-offs made in the design, and present
                 information on the accuracy of the computation as
                 compared to traditional FMA implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH 2020; ARITH-27; Artificial neural
                 networks; deep learning; floating point dot product;
                 Hardware; Machine learning; matrix multiplication;
                 Tensile stress; tensor; Training",
}


bibtype: article
filename: fparith.bib
label: Hopkins:2020:SRR
author: Michael Hopkins and Mantas Mikaitis and Dave R. Lester and Steve Furber
journal: j-PHILOS-TRANS-R-SOC-LOND-SER-A
volume: 378
number: 2166
pages: 20190052
month: jan
monthnumber: 1
year: 2020
CODEN: PTRMAD, PTMSFB
DOI: https://doi.org/10.1098/rsta.2019.0052
ISSN: 1364-503X (print), 1471-2962 (electronic) OR 1364503X (print), 14712962 (electronic)
ISSNL: 1364-503X OR 1364503X
bibdate: Fri Sep 22 17:51:44 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:51:44 ???
fjournal: Philosophical Transactions of the Royal Society A: Mathematical, Physical, and Engineering Sciences
acknowledgement: ack-nhfb
journalURL: http://rsta.royalsocietypublishing.org/
rawauthor: Michael Hopkins and Mantas Mikaitis and Dave R. Lester and Steve Furber
title:
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations

rawtitle:
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations

entry:
@Article{Hopkins:2020:SRR,
  author =       "Michael Hopkins and Mantas Mikaitis and Dave R. Lester
                 and Steve Furber",
  title =        "Stochastic rounding and reduced-precision fixed-point
                 arithmetic for solving neural ordinary differential
                 equations",
  journal =      j-PHILOS-TRANS-R-SOC-LOND-SER-A,
  volume =       "378",
  number =       "2166",
  pages =        "20190052",
  month =        jan,
  year =         "2020",
  CODEN =        "PTRMAD, PTMSFB",
  DOI =          "https://doi.org/10.1098/rsta.2019.0052",
  ISSN =         "1364-503X (print), 1471-2962 (electronic)",
  ISSN-L =       "1364-503X",
  bibdate =      "Fri Sep 22 17:51:44 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Philosophical Transactions of the Royal Society A:
                 Mathematical, Physical, and Engineering Sciences",
  journal-URL =  "http://rsta.royalsocietypublishing.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Hormigo:2020:FPF
author: Javier Hormigo and Julio Villalba-Moreno and Sonia Gonzalez-Navarro
title: Floating Point Fused Multiply Add under HUB Format
crossref: Cornea:2020:ISC
pages: 1--8
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00010
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Javier Hormigo and Julio Villalba-Moreno and Sonia Gonzalez-Navarro
rawtitle: Floating Point Fused Multiply Add under {HUB} Format
abstract:
The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation ($ A times B + C$) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38% and 35%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15%, and even then, reduces the area and power by 26% and 12%, respectively.

keywords:
ARITH 2020; ARITH-27; Computer architecture; Deep-learning; Delays; Digital arithmetic; DSP applications; Fused multiplication-addition; Hardware; HUB format; Inverters; Program processors; Standards

rawabstract:
The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation ($ A \times B + C$) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38\% and 35\%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15\%, and even then, reduces the area and power by 26\% and 12\%, respectively.

entry:
@InProceedings{Hormigo:2020:FPF,
  author =       "Javier Hormigo and Julio Villalba-Moreno and Sonia
                 Gonzalez-Navarro",
  title =        "Floating Point Fused Multiply Add under {HUB} Format",
  crossref =     "Cornea:2020:ISC",
  pages =        "1--8",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00010",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Half-Unit-Biased (HUB) format has interesting
                 advantages for implementing floating-point arithmetic
                 which has been proved for the four basic arithmetic
                 operations as well as square root. Nevertheless,
                 although Floating-point Fused Multiply-add (FMA)
                 operation ($ A \times B + C$) is one of the most
                 important and complex arithmetic instructions in modern
                 processors, FMA operation for HUB numbers has not been
                 confronted yet. In this paper, we present a design to
                 deal with this operation under HUB format. The key
                 points to turn the conventional FMA architecture into a
                 HUB unit are explained. Comparing the ASIC
                 implementation of a HUB FMA unit with the conventional
                 one, the former reduces the required area and power up
                 to 38\% and 35\%, respectively, for single-precision.
                 For BFloat16, the HUB FMA increases the speed a 15\%,
                 and even then, reduces the area and power by 26\% and
                 12\%, respectively.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Computer architecture;
                 Deep-learning; Delays; Digital arithmetic; DSP
                 applications; Fused multiplication-addition; Hardware;
                 HUB format; Inverters; Program processors; Standards",
}


bibtype: article
filename: fparith.bib
label: Hrycak:2020:ELP
author: Tomasz Hrycak and Sebastian Schmutzhard
title: Evaluation of Legendre polynomials by a three-term recurrence in floating-point arithmetic
journal: j-IMA-J-NUMER-ANAL
volume: 40
number: 1
pages: 587--605
month: jan
monthnumber: 1
year: 2020
CODEN: IJNADH
DOI: https://doi.org/10.1093/imanum/dry079
ISSN: 0272-4979 (print), 1464-3642 (electronic) OR 02724979 (print), 14643642 (electronic)
ISSNL: 0272-4979 OR 02724979
bibdate: Sat Feb 29 14:22:43 MST 2020
bibtimestamp: 2020.02.29 14:22:43 MST
URL: http://academic.oup.com/imajna/article/40/1/587/5162990
fjournal: IMA Journal of Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://imajna.oxfordjournals.org/content/by/year
rawauthor: Tomasz Hrycak and Sebastian Schmutzhard
rawtitle: Evaluation of {Legendre} polynomials by a three-term recurrence in floating-point arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/imajnumeranal.bib

entry:
@Article{Hrycak:2020:ELP,
  author =       "Tomasz Hrycak and Sebastian Schmutzhard",
  title =        "Evaluation of {Legendre} polynomials by a three-term
                 recurrence in floating-point arithmetic",
  journal =      j-IMA-J-NUMER-ANAL,
  volume =       "40",
  number =       "1",
  pages =        "587--605",
  month =        jan,
  year =         "2020",
  CODEN =        "IJNADH",
  DOI =          "https://doi.org/10.1093/imanum/dry079",
  ISSN =         "0272-4979 (print), 1464-3642 (electronic)",
  ISSN-L =       "0272-4979",
  bibdate =      "Sat Feb 29 14:22:43 MST 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/imajnumeranal.bib",
  URL =          "http://academic.oup.com/imajna/article/40/1/587/5162990",
  acknowledgement = ack-nhfb,
  fjournal =     "IMA Journal of Numerical Analysis",
  journal-URL =  "http://imajna.oxfordjournals.org/content/by/year",
}


bibtype: article
filename: fparith.bib
label: Ipsen:2020:PEA
author: Ilse C. F. Ipsen and Hua Zhou
title: Probabilistic Error Analysis for Inner Products
journal: j-SIAM-J-MAT-ANA-APPL
volume: 41
number: 4
pages: 1726--1741
year: 2020
CODEN: SJMAEL
DOI: https://doi.org/10.1137/19M1270434
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
bibdate: Fri Mar 12 10:18:05 MST 2021
bibtimestamp: 2021.03.12 10:18:05 MST
fjournal: SIAM Journal on Matrix Analysis and Applications
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/simax
onlinedate: January 2020
rawauthor: Ilse C. F. Ipsen and Hua Zhou
rawtitle: Probabilistic Error Analysis for Inner Products
bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/41/4; https://www.math.utah.edu/pub/bibnet/authors/i/ipsen-ilse-c-f.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib

entry:
@Article{Ipsen:2020:PEA,
  author =       "Ilse C. F. Ipsen and Hua Zhou",
  title =        "Probabilistic Error Analysis for Inner Products",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "41",
  number =       "4",
  pages =        "1726--1741",
  month =        "????",
  year =         "2020",
  CODEN =        "SJMAEL",
  DOI =          "https://doi.org/10.1137/19M1270434",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  bibdate =      "Fri Mar 12 10:18:05 MST 2021",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/41/4;
                 https://www.math.utah.edu/pub/bibnet/authors/i/ipsen-ilse-c-f.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
  onlinedate =   "January 2020",
}


bibtype: book
filename: fparith.bib
label: ISO:2020:III
author: ISO
publisher: pub-ISO
address: pub-ISO:adr
pages: 74
year: 2020
bibdate: Thu Jan 28 07:09:28 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/isostd.bib
bibtimestamp: 2021.01.28 07:09:28 ???
URL: https://www.iso.org/standard/80985.html
remark: This is the international version of IEEE 754-2019. It replaces ISO/IEC/IEEE 60559:2011.
acknowledgement: ack-nhfb
rawauthor: {ISO}
title:
ISO / IEC 60559:2020 Information technology --- Microprocessor Systems --- Floating-Point arithmetic

rawtitle:
{ISO\slash IEC 60559:2020} Information technology --- Microprocessor Systems --- Floating-Point arithmetic

entry:
@Book{ISO:2020:III,
  author =       "{ISO}",
  title =        "{ISO\slash IEC 60559:2020} Information technology ---
                 Microprocessor Systems --- Floating-Point arithmetic",
  publisher =    pub-ISO,
  address =      pub-ISO:adr,
  pages =        "74",
  year =         "2020",
  bibdate =      "Thu Jan 28 07:09:28 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/isostd.bib",
  URL =          "https://www.iso.org/standard/80985.html",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
  remark =       "This is the international version of IEEE 754-2019. It
                 replaces ISO/IEC/IEEE 60559:2011.",
}


bibtype: inproceedings
filename: fparith.bib
label: Isono:2020:TWM
booktitle: 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2020
DOI: https://doi.org/10.1109/A-SSCC48613.2020.9336137
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)}
author:
Takanori Isono and Makoto Yamakura and Satoshi Shimaya and Isao Kawamoto and Nobuhiro Tsuboi and Masaaki Mineo and Wataru Nakajima and Kenichi Ishida and Shin Sasaki and Toshio Higuchi and Masahiro Hoshaku and Daisuke Murakami and Toshifumi Iwasaki and Hiroshi Hirai

title:
A 12.1 TOPS/W Mixed-precision Quantized Deep Convolutional Neural Network Accelerator for Low Power on Edge / Endpoint Device

keywords:
Bandwidth; Binary; Convolutional neural networks; deep Neural network; Memory management; Mixed-precision; NPU; Power demand; Quantized; Redundancy; Solid state circuits; System-on-chip; Ternary

rawauthor:
Takanori Isono and Makoto Yamakura and Satoshi Shimaya and Isao Kawamoto and Nobuhiro Tsuboi and Masaaki Mineo and Wataru Nakajima and Kenichi Ishida and Shin Sasaki and Toshio Higuchi and Masahiro Hoshaku and Daisuke Murakami and Toshifumi Iwasaki and Hiroshi Hirai

rawtitle:
A 12.1 {TOPS/W} Mixed-precision Quantized Deep Convolutional Neural Network Accelerator for Low Power on Edge\slash Endpoint Device

entry:
@InProceedings{Isono:2020:TWM,
  author =       "Takanori Isono and Makoto Yamakura and Satoshi Shimaya
                 and Isao Kawamoto and Nobuhiro Tsuboi and Masaaki Mineo
                 and Wataru Nakajima and Kenichi Ishida and Shin Sasaki
                 and Toshio Higuchi and Masahiro Hoshaku and Daisuke
                 Murakami and Toshifumi Iwasaki and Hiroshi Hirai",
  booktitle =    "{2020 IEEE Asian Solid-State Circuits Conference
                 (A-SSCC)}",
  title =        "A 12.1 {TOPS/W} Mixed-precision Quantized Deep
                 Convolutional Neural Network Accelerator for Low Power
                 on Edge\slash Endpoint Device",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/A-SSCC48613.2020.9336137",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Bandwidth; Binary; Convolutional neural networks; deep
                 Neural network; Memory management; Mixed-precision;
                 NPU; Power demand; Quantized; Redundancy; Solid state
                 circuits; System-on-chip; Ternary",
}


bibtype: article
filename: fparith.bib
label: Isupov:2020:DIM
author: Konstantin Isupov and Vladimir Knyazkov and Alexander Kuvaev
journal: j-J-PAR-DIST-COMP
volume: 140
pages: 25--36
month: jun
monthnumber: 6
year: 2020
CODEN: JPDCER
DOI: https://doi.org/10.1016/j.jpdc.2020.02.006
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Wed May 26 16:11:01 MDT 2021
bibtimestamp: 2021.05.26 16:11:01 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0743731519303302
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Konstantin Isupov and Vladimir Knyazkov and Alexander Kuvaev
title:
Design and implementation of multiple-precision BLAS Level 1 functions for graphics processing units

rawtitle:
Design and implementation of multiple-precision {BLAS Level 1} functions for graphics processing units

entry:
@Article{Isupov:2020:DIM,
  author =       "Konstantin Isupov and Vladimir Knyazkov and Alexander
                 Kuvaev",
  title =        "Design and implementation of multiple-precision {BLAS
                 Level 1} functions for graphics processing units",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "140",
  number =       "??",
  pages =        "25--36",
  month =        jun,
  year =         "2020",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1016/j.jpdc.2020.02.006",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Wed May 26 16:11:01 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731519303302",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: misc
filename: fparith.bib
label: Isupov:2020:MPB
author: Konstantin Isupov and Vladimir Knyazkov
title: Multiple-Precision BLAS Library for Graphics Processing Units
pages: 25--36
day: 30
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.36227/techrxiv.12580301.v1
bibdate: Fri Sep 29 14:30:54 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 14:30:54 ???
remark: Preprint submitted to Russian Supercomputing Days 2020.
acknowledgement: ack-nhfb
howpublished: TechRxiv preprint.
rawauthor: Konstantin Isupov and Vladimir Knyazkov
rawtitle: Multiple-Precision {BLAS} Library for Graphics Processing Units
abstract:
The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

rawabstract:
The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

entry:
@Misc{Isupov:2020:MPB,
  author =       "Konstantin Isupov and Vladimir Knyazkov",
  title =        "Multiple-Precision {BLAS} Library for Graphics
                 Processing Units",
  howpublished = "TechRxiv preprint.",
  day =          "30",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.36227/techrxiv.12580301.v1",
  bibdate =      "Fri Sep 29 14:30:54 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The binary32 and binary64 floating-point formats
                 provide good performance on current hardware, but also
                 introduce a rounding error in almost every arithmetic
                 operation. Consequently, the accumulation of rounding
                 errors in large computations can cause accuracy issues.
                 One way to prevent these issues is to use
                 multiple-precision floating-point arithmetic. This
                 preprint, submitted to Russian Supercomputing Days
                 2020, presents a new library of basic linear algebra
                 operations with multiple precision for graphics
                 processing units. The library is written in CUDA C/C++
                 and uses the residue number system to represent
                 multiple-precision significands of floating-point
                 numbers. The supported data types, memory layout, and
                 main features of the library are considered.
                 Experimental results are presented showing the
                 performance of the library.",
  acknowledgement = ack-nhfb,
  remark =       "Preprint submitted to Russian Supercomputing Days
                 2020.",
}


bibtype: article
filename: fparith.bib
label: Isupov:2020:UFP
author: Konstantin Isupov
title: Using Floating-Point Intervals for Non-Modular Computations in Residue Number System
journal: j-IEEE-ACCESS
volume: 8
pages: 58603--58619
year: 2020
DOI: https://doi.org/10.1109/ACCESS.2020.2982365
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:08:36 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:08:36 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Konstantin Isupov
rawtitle: Using Floating-Point Intervals for Non-Modular Computations in Residue Number System
keywords:
Cathode ray tubes; Cryptography; CUDA; division; Dynamic range; floating-point arithmetic; graphics processing unit; Graphics processing units; Heuristic algorithms; high performance; magnitude comparison; Memory management; non-modular operations; parallel algorithms; Residue number system; Signal processing algorithms

entry:
@Article{Isupov:2020:UFP,
  author =       "Konstantin Isupov",
  title =        "Using Floating-Point Intervals for Non-Modular
                 Computations in Residue Number System",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  pages =        "58603--58619",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.2982365",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:08:36 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Cathode ray tubes; Cryptography; CUDA; division;
                 Dynamic range; floating-point arithmetic; graphics
                 processing unit; Graphics processing units; Heuristic
                 algorithms; high performance; magnitude comparison;
                 Memory management; non-modular operations; parallel
                 algorithms; Residue number system; Signal processing
                 algorithms",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2020:RAX
author: Claude-Pierre Jeannerod
title: The relative accuracy of $ (x + y) * (x - y) $
journal: j-J-COMPUT-APPL-MATH
volume: 369
pages: Article 112613
day: 1
month: may
monthnumber: 5
year: 2020
CODEN: JCAMDI
DOI: https://doi.org/10.1016/j.cam.2019.112613
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Wed May 13 06:58:31 MDT 2020
bibtimestamp: 2020.05.13 06:58:31 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0377042719306181
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
articleno: 112613
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Claude-Pierre Jeannerod
rawtitle: The relative accuracy of $ (x + y) * (x - y) $
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2020.bib

entry:
@Article{Jeannerod:2020:RAX,
  author =       "Claude-Pierre Jeannerod",
  title =        "The relative accuracy of $ (x + y) * (x - y) $",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "369",
  number =       "??",
  pages =        "Article 112613",
  day =          "1",
  month =        may,
  year =         "2020",
  CODEN =        "JCAMDI",
  DOI =          "https://doi.org/10.1016/j.cam.2019.112613",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Wed May 13 06:58:31 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042719306181",
  acknowledgement = ack-nhfb,
  articleno =    "112613",
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Johnson:2020:EAHa
author: Jeff Johnson
title: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
journal: arxiv.org
pages: 1--8
day: 14
month: may
monthnumber: 5
year: 2020
bibdate: Tue Jul 06 18:17:13 2021
bibtimestamp: 2021.07.06 18:17:13 ???
URL: https://arxiv.org/pdf/2004.09313.pdf
remark: Published in cite Johnson:2020:EAHb.
acknowledgement: ack-nhfb
rawauthor: Jeff Johnson
rawtitle: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
abstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify.par We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio.Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 times $ and $ 4.6 times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation $ 5.4 times $ and $ 3.2 times $ more energy efficient, at $ 0.23 times $ and $ 0.37 times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

keywords:
approximate arithmetic; elementary function evaluation; hardware linear algebra; logarithmic arithmetic

rawabstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify.\par We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio.Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 \times $ and $ 4.6 \times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation $ 5.4 \times $ and $ 3.2 \times $ more energy efficient, at $ 0.23 \times $ and $ 0.37 \times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

entry:
@Article{Johnson:2020:EAHa,
  author =       "Jeff Johnson",
  title =        "Efficient, arbitrarily high precision hardware
                 logarithmic arithmetic for linear algebra",
  journal =      "arxiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--8",
  day =          "14",
  month =        may,
  year =         "2020",
  bibdate =      "Tue Jul 06 18:17:13 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/pdf/2004.09313.pdf",
  abstract =     "The logarithmic number system (LNS) is arguably not
                 broadly used due to exponential circuit overheads for
                 summation tables relative to arithmetic precision.
                 Methods to reduce this overhead have been proposed, yet
                 still yield designs with high chip area and power
                 requirements. Use remains limited to lower precision or
                 high multiply/add ratio cases, while much of linear
                 algebra (near 1:1 multiply/add ratio) does not
                 qualify.\par

                 We present a dual-base approximate logarithmic
                 arithmetic comparable to floating point in use, yet
                 unlike LNS it is easily fully pipelined, extendable to
                 arbitrary precision with $ O(n^2) $ overhead, and
                 energy efficient at a 1:1 multiply/add ratio.Compared
                 to float32 or float64 vector inner product with FMA,
                 our design is respectively $ 2.3 \times $ and $ 4.6
                 \times $ more energy efficient in 7 nm CMOS. It depends
                 on exp and log evaluation $ 5.4 \times $ and $ 3.2
                 \times $ more energy efficient, at $ 0.23 \times $ and
                 $ 0.37 \times $ the chip area for equivalent accuracy
                 versus standard hyperbolic CORDIC using shift-and-add
                 and approximated ODE integration in the style of Revol
                 and Yakoubsohn. This technique is a novel alternative
                 for low power, high precision hardened linear algebra
                 in computer vision, graphics and machine learning
                 applications.",
  acknowledgement = ack-nhfb,
  keywords =     "approximate arithmetic; elementary function
                 evaluation; hardware linear algebra; logarithmic
                 arithmetic",
  remark =       "Published in \cite{Johnson:2020:EAHb}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Johnson:2020:EAHb
author: Jeff Johnson
title: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
crossref: Cornea:2020:ISC
pages: 25--32
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00013
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Jeff Johnson
rawtitle: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
abstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify. We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio. Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 times $ and $ 4.6 times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation 5.4 and $ 3.2 times $ more energy efficient, at $ 0.23 times $ and $ 0.37 times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

keywords:
Adders; approximate arithmetic; ARITH 2020; ARITH-27; Clocks; elementary function evaluation; Hardware; hardware linear algebra; Linear algebra; logarithmic arithmetic; Pipeline processing; Read only memory; Switches

rawabstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify. We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio. Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 \times $ and $ 4.6 \times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation 5.4 and $ 3.2 \times $ more energy efficient, at $ 0.23 \times $ and $ 0.37 \times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

entry:
@InProceedings{Johnson:2020:EAHb,
  author =       "Jeff Johnson",
  title =        "Efficient, arbitrarily high precision hardware
                 logarithmic arithmetic for linear algebra",
  crossref =     "Cornea:2020:ISC",
  pages =        "25--32",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00013",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The logarithmic number system (LNS) is arguably not
                 broadly used due to exponential circuit overheads for
                 summation tables relative to arithmetic precision.
                 Methods to reduce this overhead have been proposed, yet
                 still yield designs with high chip area and power
                 requirements. Use remains limited to lower precision or
                 high multiply/add ratio cases, while much of linear
                 algebra (near 1:1 multiply/add ratio) does not qualify.
                 We present a dual-base approximate logarithmic
                 arithmetic comparable to floating point in use, yet
                 unlike LNS it is easily fully pipelined, extendable to
                 arbitrary precision with $ O(n^2) $ overhead, and
                 energy efficient at a 1:1 multiply/add ratio. Compared
                 to float32 or float64 vector inner product with FMA,
                 our design is respectively $ 2.3 \times $ and $ 4.6
                 \times $ more energy efficient in 7 nm CMOS. It depends
                 on exp and log evaluation 5.4 and $ 3.2 \times $ more
                 energy efficient, at $ 0.23 \times $ and $ 0.37 \times
                 $ the chip area for equivalent accuracy versus standard
                 hyperbolic CORDIC using shift-and-add and approximated
                 ODE integration in the style of Revol and Yakoubsohn.
                 This technique is a novel alternative for low power,
                 high precision hardened linear algebra in computer
                 vision, graphics and machine learning applications.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; approximate arithmetic; ARITH 2020; ARITH-27;
                 Clocks; elementary function evaluation; Hardware;
                 hardware linear algebra; Linear algebra; logarithmic
                 arithmetic; Pipeline processing; Read only memory;
                 Switches",
}


bibtype: inproceedings
filename: fparith.bib
label: Joldes:2020:AMQ
author: Mioara Joldes and Jean-Michel Muller
title: Algorithms for Manipulating Quaternions in Floating-Point Arithmetic
crossref: Cornea:2020:ISC
pages: 48--55
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00016
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Mioara Jolde{\c{s}} and Jean-Michel Muller
rawtitle: Algorithms for Manipulating Quaternions in Floating-Point Arithmetic
abstract:
Quaternions form a set of four global but not unique parameters, which can represent three-dimensional rotations in a non-singular way. They are frequently used in computer graphics, drone and aerospace vehicle control. Floating-point quaternion operations (addition, multiplication, reciprocal, norm) are often implemented by the book. Although all usual implementations are algebraically equivalent, their numerical behavior can be quite different. For instance, the arithmetic operations on quaternions as well as conversion algorithms to/from rotation matrices are subject to spurious under/overflow (an intermediate calculation underflows or overflows, making the computed final result irrelevant, although the exact result is in the domain of the representable numbers). The goal of this paper is to analyze and then propose workarounds and better accuracy alternatives for such algorithms.

keywords:
Aerospace control; Algebra; ARITH 2020; ARITH-27; Computer graphics; Drones; Error analysis; Floating-point arithmetic; Quaternions; quaternions; rounding error analysis; Standards

rawabstract:
Quaternions form a set of four global but not unique parameters, which can represent three-dimensional rotations in a non-singular way. They are frequently used in computer graphics, drone and aerospace vehicle control. Floating-point quaternion operations (addition, multiplication, reciprocal, norm) are often implemented by the book. Although all usual implementations are algebraically equivalent, their numerical behavior can be quite different. For instance, the arithmetic operations on quaternions as well as conversion algorithms to/from rotation matrices are subject to spurious under/overflow (an intermediate calculation underflows or overflows, making the computed final result irrelevant, although the exact result is in the domain of the representable numbers). The goal of this paper is to analyze and then propose workarounds and better accuracy alternatives for such algorithms.

entry:
@InProceedings{Joldes:2020:AMQ,
  author =       "Mioara Jolde{\c{s}} and Jean-Michel Muller",
  title =        "Algorithms for Manipulating Quaternions in
                 Floating-Point Arithmetic",
  crossref =     "Cornea:2020:ISC",
  pages =        "48--55",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00016",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Quaternions form a set of four global but not unique
                 parameters, which can represent three-dimensional
                 rotations in a non-singular way. They are frequently
                 used in computer graphics, drone and aerospace vehicle
                 control. Floating-point quaternion operations
                 (addition, multiplication, reciprocal, norm) are often
                 implemented by the book. Although all usual
                 implementations are algebraically equivalent, their
                 numerical behavior can be quite different. For
                 instance, the arithmetic operations on quaternions as
                 well as conversion algorithms to/from rotation matrices
                 are subject to spurious under/overflow (an intermediate
                 calculation underflows or overflows, making the
                 computed final result irrelevant, although the exact
                 result is in the domain of the representable numbers).
                 The goal of this paper is to analyze and then propose
                 workarounds and better accuracy alternatives for such
                 algorithms.",
  acknowledgement = ack-nhfb,
  keywords =     "Aerospace control; Algebra; ARITH 2020; ARITH-27;
                 Computer graphics; Drones; Error analysis;
                 Floating-point arithmetic; Quaternions; quaternions;
                 rounding error analysis; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Jugade:2020:FEM
author: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
editor: IEEE
booktitle: 2020 59th IEEE Conference on Decision and Control (CDC)
title: A Framework for Embedded Model Predictive Control using Posits
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2509--2514
year: 2020
DOI: https://doi.org/10.1109/CDC42340.2020.9304262
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
rawbooktitle: {2020 59th IEEE Conference on Decision and Control (CDC)}
raweditor: {IEEE}
rawtitle: A Framework for Embedded Model Predictive Control using Posits
entry:
@InProceedings{Jugade:2020:FEM,
  author =       "Chaitanya Jugade and Deepak Ingole and Dayaram
                 Sonawane and Michal Kvasnica and John Gustafson",
  editor =       "{IEEE}",
  booktitle =    "{2020 59th IEEE Conference on Decision and Control
                 (CDC)}",
  title =        "A Framework for Embedded Model Predictive Control
                 using Posits",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2509--2514",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CDC42340.2020.9304262",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kim:2020:PPC
booktitle: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
title: PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1199--1204
year: 2020
DOI: https://doi.org/10.23919/DATE48585.2020.9116530
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2020 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
rawtitle: {PCM}: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training
author:
Boyeal Kim and Sang Hyun Lee and Hyun Kim and Duy-Thanh Nguyen and Minh-Son Le and Ik Joon Chang and Dohun Kwon and Jin Hyeok Yoo and Jun Won Choi and Hyuk-Jae Lee

keywords:
Approximate Computing; Deep Neural Network; Energy consumption; General Purpose Graphic Processing Unit; Hardware; High Bandwidth Memory; Memory management; Phase change materials; Precision Control; Random access memory; Refresh Period Control; Training

rawauthor:
Boyeal Kim and Sang Hyun Lee and Hyun Kim and Duy-Thanh Nguyen and Minh-Son Le and Ik Joon Chang and Dohun Kwon and Jin Hyeok Yoo and Jun Won Choi and Hyuk-Jae Lee

entry:
@InProceedings{Kim:2020:PPC,
  author =       "Boyeal Kim and Sang Hyun Lee and Hyun Kim and
                 Duy-Thanh Nguyen and Minh-Son Le and Ik Joon Chang and
                 Dohun Kwon and Jin Hyeok Yoo and Jun Won Choi and
                 Hyuk-Jae Lee",
  booktitle =    "{2020 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{PCM}: Precision-Controlled Memory System for Energy
                 Efficient Deep Neural Network Training",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1199--1204",
  year =         "2020",
  DOI =          "https://doi.org/10.23919/DATE48585.2020.9116530",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Approximate Computing; Deep Neural Network; Energy
                 consumption; General Purpose Graphic Processing Unit;
                 Hardware; High Bandwidth Memory; Memory management;
                 Phase change materials; Precision Control; Random
                 access memory; Refresh Period Control; Training",
}


bibtype: article
filename: fparith.bib
label: Klarreich:2020:NMH
author: Erica Klarreich
title: News: Multiplication hits the speed limit
journal: j-CACM
volume: 63
number: 1
pages: 11--13
month: jan
monthnumber: 1
year: 2020
CODEN: CACMA2
DOI: https://doi.org/10.1145/3371387
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Thu Jan 2 16:41:05 MST 2020
bibtimestamp: 2020.01.02 16:41:05 MST
URL: https://dl.acm.org/doi/abs/10.1145/3371387
abstract: A problem ``around since antiquity'' may have been resolved by a new algorithm.
fjournal: Communications of the ACM
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawabstract: A problem ``around since antiquity'' may have been resolved by a new algorithm.
rawauthor: Erica Klarreich
rawtitle: News: Multiplication hits the speed limit
bibsource:
https://www.math.utah.edu/pub/tex/bib/cacm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Klarreich:2020:NMH,
  author =       "Erica Klarreich",
  title =        "News: Multiplication hits the speed limit",
  journal =      j-CACM,
  volume =       "63",
  number =       "1",
  pages =        "11--13",
  month =        jan,
  year =         "2020",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/3371387",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Thu Jan 2 16:41:05 MST 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cacm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3371387",
  abstract =     "A problem ``around since antiquity'' may have been
                 resolved by a new algorithm.",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
}


bibtype: article
filename: fparith.bib
label: Klower:2020:NFE
author: Milan Klower and Peter D. Duben and Tim N. Palmer
journal: j-J-ADV-MODEL-EARTH-SYST
volume: 12
number: 10
pages: 1--17
month: oct
monthnumber: 10
year: 2020
DOI: https://doi.org/10.1029/2020MS002246
ISSN: 1942-2466 (print), 1942-2466 (electronic) OR 19422466 (print), 19422466 (electronic)
ISSNL: 1942-2466 OR 19422466
bibdate: Fri Dec 15 11:03:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:03:12 ???
fjournal: Journal of Advances in Modeling Earth Systems
acknowledgement: ack-nhfb
ajournal: J. Adv. Model. Earth Syst. [JAMES]
journalURL: https://agupubs.onlinelibrary.wiley.com/journal/19422466
rawauthor: Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N. Palmer
title:
Number Formats, Error Mitigation, and Scope for 16-Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model

rawtitle:
Number Formats, Error Mitigation, and Scope for 16-Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model

entry:
@Article{Klower:2020:NFE,
  author =       "Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N.
                 Palmer",
  title =        "Number Formats, Error Mitigation, and Scope for 16-Bit
                 Arithmetics in Weather and Climate Modeling Analyzed
                 With a Shallow Water Model",
  journal =      j-J-ADV-MODEL-EARTH-SYST,
  volume =       "12",
  number =       "10",
  pages =        "1--17",
  month =        oct,
  year =         "2020",
  DOI =          "https://doi.org/10.1029/2020MS002246",
  ISSN =         "1942-2466 (print), 1942-2466 (electronic)",
  ISSN-L =       "1942-2466",
  bibdate =      "Fri Dec 15 11:03:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Adv. Model. Earth Syst. [JAMES]",
  fjournal =     "Journal of Advances in Modeling Earth Systems",
  journal-URL =  "https://agupubs.onlinelibrary.wiley.com/journal/19422466",
}


bibtype: inproceedings
filename: fparith.bib
label: Knobbe:2020:CRS
author: Simon Knobbe and Moritz Barthel and Steffen Paul and Jochen Rust
booktitle: 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)
title: Complexity Reduction for Sphere Decoding using Unum-Type-II-Based SORN-Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2020
DOI: https://doi.org/10.1109/MOCAST49295.2020.9200263
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Simon Knobbe and Moritz B{\"a}rthel and Steffen Paul and Jochen Rust
rawbooktitle: {2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)}
rawtitle: Complexity Reduction for Sphere Decoding using {Unum-Type-II}-Based {SORN}-Arithmetic
entry:
@InProceedings{Knobbe:2020:CRS,
  author =       "Simon Knobbe and Moritz B{\"a}rthel and Steffen Paul
                 and Jochen Rust",
  booktitle =    "{2020 9th International Conference on Modern Circuits
                 and Systems Technologies (MOCAST)}",
  title =        "Complexity Reduction for Sphere Decoding using
                 {Unum-Type-II}-Based {SORN}-Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/MOCAST49295.2020.9200263",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Koc:2020:AIM
author: Cetin Kaya Koc
title: Algorithms for Inversion Mod $ p^k $
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 6
pages: 907--913
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2020.2970411
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 23 16:03:24 2020
bibtimestamp: 2020.07.23 16:03:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: Algorithms for Inversion Mod $ p^k $
abstract:
This article describes and analyzes all existing algorithms for computing $ x = a^-1 (bmod p^k) $ for a prime $p$, and also introduces a new algorithm based on the exact solution of linear equations using $p$-adic expansions. The algorithm starts with the initial value $ c = a^-1 (bmod p)$ and iteratively computes the digits of the inverse $ x = a^-1 (bmod p^k)$ in base $p$. The $ bmod 2$ version of the algorithm is more efficient than all existing algorithms for small values of $k$. Moreover, it stands out as being the only one that works for any $p$, any $k$, and digit-by-digit. While the new algorithm is asymptotically worse off, it requires the minimal number of arithmetic operations (just a single addition) per step, as compared to all existing algorithms.

rawabstract:
This article describes and analyzes all existing algorithms for computing $ x = a^{-1} (\bmod p^k) $ for a prime $p$, and also introduces a new algorithm based on the exact solution of linear equations using $p$-adic expansions. The algorithm starts with the initial value $ c = a^{-1} (\bmod p)$ and iteratively computes the digits of the inverse $ x = a^{-1} (\bmod p^k)$ in base $p$. The $ \bmod 2$ version of the algorithm is more efficient than all existing algorithms for small values of $k$. Moreover, it stands out as being the only one that works for any $p$, any $k$, and digit-by-digit. While the new algorithm is asymptotically worse off, it requires the minimal number of arithmetic operations (just a single addition) per step, as compared to all existing algorithms.

entry:
@Article{Koc:2020:AIM,
  author =       "{\c{C}}etin Kaya Ko{\c{c}}",
  title =        "Algorithms for Inversion Mod $ p^k $",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "6",
  pages =        "907--913",
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2020.2970411",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 23 16:03:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "This article describes and analyzes all existing
                 algorithms for computing $ x = a^{-1} (\bmod p^k) $ for
                 a prime $p$, and also introduces a new algorithm based
                 on the exact solution of linear equations using
                 $p$-adic expansions. The algorithm starts with the
                 initial value $ c = a^{-1} (\bmod p)$ and iteratively
                 computes the digits of the inverse $ x = a^{-1} (\bmod
                 p^k)$ in base $p$. The $ \bmod 2$ version of the
                 algorithm is more efficient than all existing
                 algorithms for small values of $k$. Moreover, it stands
                 out as being the only one that works for any $p$, any
                 $k$, and digit-by-digit. While the new algorithm is
                 asymptotically worse off, it requires the minimal
                 number of arithmetic operations (just a single
                 addition) per step, as compared to all existing
                 algorithms.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Kudo:2020:INT
author: Shuhei Kudo and Keigo Nitadori and Takuya Ina and Toshiyuki Imamura
title: Implementation and Numerical Techniques for One Eflop/s HPL-AI Benchmark on Fugaku
publisher: PUB-IEEE
address: PUB-IEEE:ADR
pages: 69--76
year: 2020
DOI: https://doi.org/10.1109/scala51936.2020.00014
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Shuhei Kudo and Keigo Nitadori and Takuya Ina and Toshiyuki Imamura
rawtitle: Implementation and Numerical Techniques for One Eflop/s {HPL-AI} Benchmark on {Fugaku}
booktitle:
2020 IEEE / ACM 11TH Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (SCALA)

keywords:
artificial intelligence; benchmark testing; computer architecture; exaflop/s; FP16; FP32; Fugaku; HPL-AI; iterative methods; Jacobian matrices; matrix decomposition; mixed-precision; supercomputers

rawbooktitle:
{2020 IEEE\slash ACM 11TH Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (SCALA)}

entry:
@InProceedings{Kudo:2020:INT,
  author =       "Shuhei Kudo and Keigo Nitadori and Takuya Ina and
                 Toshiyuki Imamura",
  booktitle =    "{2020 IEEE\slash ACM 11TH Workshop on Latest Advances
                 in Scalable Algorithms for Large-Scale Systems
                 (SCALA)}",
  title =        "Implementation and Numerical Techniques for One
                 Eflop/s {HPL-AI} Benchmark on {Fugaku}",
  publisher =    PUB-IEEE,
  address =      PUB-IEEE:ADR,
  pages =        "69--76",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/scala51936.2020.00014",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "artificial intelligence; benchmark testing; computer
                 architecture; exaflop/s; FP16; FP32; Fugaku; HPL-AI;
                 iterative methods; Jacobian matrices; matrix
                 decomposition; mixed-precision; supercomputers",
}


bibtype: inproceedings
filename: fparith.bib
label: Kudo:2020:PRE
author: Shuhei Kudo and Keigo Nitadori and Takuya Ina and Toshiyuki Imamura
booktitle: 2020 IEEE International Conference on Cluster Computing (CLUSTER)
title: Prompt Report on Exa-Scale HPL-AI Benchmark
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 418--419
year: 2020
DOI: https://doi.org/10.1109/CLUSTER49012.2020.00058
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Shuhei Kudo and Keigo Nitadori and Takuya Ina and Toshiyuki Imamura
rawbooktitle: {2020 IEEE International Conference on Cluster Computing (CLUSTER)}
rawtitle: Prompt Report on Exa-Scale {HPL-AI} Benchmark
keywords:
Benchmark testing; Conferences; Exa flop/s; Floating-point arithmetic; Fugaku; Guidelines; HPL-AI; mixed-precision; Numerical analysis; Optimization; Supercomputers

entry:
@InProceedings{Kudo:2020:PRE,
  author =       "Shuhei Kudo and Keigo Nitadori and Takuya Ina and
                 Toshiyuki Imamura",
  booktitle =    "{2020 IEEE International Conference on Cluster
                 Computing (CLUSTER)}",
  title =        "Prompt Report on Exa-Scale {HPL-AI} Benchmark",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "418--419",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CLUSTER49012.2020.00058",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Benchmark testing; Conferences; Exa flop/s;
                 Floating-point arithmetic; Fugaku; Guidelines; HPL-AI;
                 mixed-precision; Numerical analysis; Optimization;
                 Supercomputers",
}


bibtype: inproceedings
filename: fparith.bib
label: Laguna:2020:VQF
author: Ignacio Laguna
booktitle: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
title: Varity: Quantifying Floating-Point Variations in HPC Systems Through Randomized Testing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 622--633
month: may
monthnumber: 5
year: 2020
DOI: https://doi.org/10.1109/ipdps47924.2020.00070
bibdate: Tue Jan 28 06:34:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.01.28 06:34:18 ???
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
rawauthor: Ignacio Laguna
rawbooktitle: 2020 {IEEE} International Parallel and Distributed Processing Symposium ({IPDPS})
rawtitle: {Varity}: Quantifying Floating-Point Variations in {HPC} Systems Through Randomized Testing
entry:
@InProceedings{Laguna:2020:VQF,
  author =       "Ignacio Laguna",
  booktitle =    "2020 {IEEE} International Parallel and Distributed
                 Processing Symposium ({IPDPS})",
  title =        "{Varity}: Quantifying Floating-Point Variations in
                 {HPC} Systems Through Randomized Testing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "622--633",
  month =        may,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ipdps47924.2020.00070",
  bibdate =      "Tue Jan 28 06:34:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Lange:2020:FRF
author: Marko Lange and Siegfried M. Rump
title: Faithfully Rounded Floating-point Computations
journal: j-TOMS
volume: 46
number: 3
pages: 21:1--21:20
month: sep
monthnumber: 9
year: 2020
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3290955
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Sep 26 07:28:19 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2020.09.26 07:28:19 MDT
URL: https://dl.acm.org/doi/10.1145/3290955
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 21
journalURL: https://dl.acm.org/loi/toms
rawauthor: Marko Lange and Siegfried M. Rump
rawtitle: Faithfully Rounded Floating-point Computations
abstract:
We present a pair arithmetic for the four basic operations and square root. It can be regarded as a simplified, more-efficient double-double arithmetic. The central assumption on the underlying arithmetic is the first standard model for error analysis for operations on a discrete set of real numbers. Neither do we require a floating-point grid nor a rounding to nearest property. Based on that, we define a relative rounding error unit $u$ and prove rigorous error bounds for the computed result of an arbitrary arithmetic expression depending on $u$, the size of the expression, and possibly a condition measure. In the second part of this note, we extend the error analysis by examining requirements to ensure faithfully rounded outputs and apply our results to IEEE 754 standard conform floating-point systems. For a class of mathematical expressions, using an IEEE 754 standard conform arithmetic with base $ beta $, the result is proved to be faithfully rounded for up to $ 1 / sqrt beta u - 2$ operations. Our findings cover a number of previously published algorithms to compute faithfully rounded results, among them Horner's scheme, products, sums, dot products, or Euclidean norm. Beyond that, several other problems can be analyzed, such as polynomial interpolation, orientation problems, Householder transformations, or the smallest singular value of Hilbert matrices of large size.

rawabstract:
We present a pair arithmetic for the four basic operations and square root. It can be regarded as a simplified, more-efficient double-double arithmetic. The central assumption on the underlying arithmetic is the first standard model for error analysis for operations on a discrete set of real numbers. Neither do we require a floating-point grid nor a rounding to nearest property. Based on that, we define a relative rounding error unit $u$ and prove rigorous error bounds for the computed result of an arbitrary arithmetic expression depending on $u$, the size of the expression, and possibly a condition measure. In the second part of this note, we extend the error analysis by examining requirements to ensure faithfully rounded outputs and apply our results to IEEE 754 standard conform floating-point systems. For a class of mathematical expressions, using an IEEE 754 standard conform arithmetic with base $ \beta $, the result is proved to be faithfully rounded for up to $ 1 / \sqrt {\beta u - 2}$ operations. Our findings cover a number of previously published algorithms to compute faithfully rounded results, among them Horner's scheme, products, sums, dot products, or Euclidean norm. Beyond that, several other problems can be analyzed, such as polynomial interpolation, orientation problems, Householder transformations, or the smallest singular value of Hilbert matrices of large size.

entry:
@Article{Lange:2020:FRF,
  author =       "Marko Lange and Siegfried M. Rump",
  title =        "Faithfully Rounded Floating-point Computations",
  journal =      j-TOMS,
  volume =       "46",
  number =       "3",
  pages =        "21:1--21:20",
  month =        sep,
  year =         "2020",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3290955",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Sep 26 07:28:19 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3290955",
  abstract =     "We present a pair arithmetic for the four basic
                 operations and square root. It can be regarded as a
                 simplified, more-efficient double-double arithmetic.
                 The central assumption on the underlying arithmetic is
                 the first standard model for error analysis for
                 operations on a discrete set of real numbers. Neither
                 do we require a floating-point grid nor a rounding to
                 nearest property. Based on that, we define a relative
                 rounding error unit $u$ and prove rigorous error bounds
                 for the computed result of an arbitrary arithmetic
                 expression depending on $u$, the size of the
                 expression, and possibly a condition measure. In the
                 second part of this note, we extend the error analysis
                 by examining requirements to ensure faithfully rounded
                 outputs and apply our results to IEEE 754 standard
                 conform floating-point systems. For a class of
                 mathematical expressions, using an IEEE 754 standard
                 conform arithmetic with base $ \beta $, the result is
                 proved to be faithfully rounded for up to $ 1 / \sqrt
                 {\beta u - 2}$ operations. Our findings cover a number
                 of previously published algorithms to compute
                 faithfully rounded results, among them Horner's scheme,
                 products, sums, dot products, or Euclidean norm. Beyond
                 that, several other problems can be analyzed, such as
                 polynomial interpolation, orientation problems,
                 Householder transformations, or the smallest singular
                 value of Hilbert matrices of large size.",
  acknowledgement = ack-nhfb,
  articleno =    "21",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Lange:2020:NDF
author: Marko Lange and Shin'ichi Oishi
title: A note on Dekker's FastTwoSum algorithm
journal: j-NUM-MATH
volume: 145
number: 2
pages: 383--403
month: jun
monthnumber: 6
year: 2020
CODEN: NUMMA7
DOI: https://doi.org/10.1007/s00211-020-01114-2
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
bibdate: Thu Jun 4 12:18:54 MDT 2020
bibtimestamp: 2020.06.04 12:18:54 MDT
note: See correction cite Lange:2021:CND.
URL: https://link.springer.com/article/10.1007/s00211-020-01114-2
fjournal: Numerische Mathematik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/211
rawauthor: Marko Lange and Shin'ichi Oishi
rawnote: See correction \cite{Lange:2021:CND}.
rawtitle: A note on {Dekker}'s {FastTwoSum} algorithm
bibsource:
http://link.springer.com/journal/211/145/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/nummath2020.bib

entry:
@Article{Lange:2020:NDF,
  author =       "Marko Lange and Shin'ichi Oishi",
  title =        "A note on {Dekker}'s {FastTwoSum} algorithm",
  journal =      j-NUM-MATH,
  volume =       "145",
  number =       "2",
  pages =        "383--403",
  month =        jun,
  year =         "2020",
  CODEN =        "NUMMA7",
  DOI =          "https://doi.org/10.1007/s00211-020-01114-2",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  bibdate =      "Thu Jun 4 12:18:54 MDT 2020",
  bibsource =    "http://link.springer.com/journal/211/145/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/nummath2020.bib",
  note =         "See correction \cite{Lange:2021:CND}.",
  URL =          "https://link.springer.com/article/10.1007/s00211-020-01114-2",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
}


bibtype: inproceedings
filename: fparith.bib
label: Langroudi:2020:APP
author: Hamed F. Langroudi and Vedant Karia and John L. Gustafson and Dhireesha Kudithipudi
editor: IEEE
booktitle: 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)
title: Adaptive Posit: Parameter aware numerical format for deep learning inference on the edge
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 3123--3131
year: 2020
DOI: https://doi.org/10.1109/CVPRW50498.2020.00371
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Hamed F. Langroudi and Vedant Karia and John L. Gustafson and Dhireesha Kudithipudi
rawbooktitle: {2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)}
raweditor: {IEEE}
rawtitle: Adaptive Posit: Parameter aware numerical format for deep learning inference on the edge
entry:
@InProceedings{Langroudi:2020:APP,
  author =       "Hamed F. Langroudi and Vedant Karia and John L.
                 Gustafson and Dhireesha Kudithipudi",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE/CVF Conference on Computer Vision and
                 Pattern Recognition Workshops (CVPRW)}",
  title =        "Adaptive Posit: Parameter aware numerical format for
                 deep learning inference on the edge",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "3123--3131",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CVPRW50498.2020.00371",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lauter:2020:FSA
author: Christoph Lauter and Anastasia Volkova
title: A Framework for Semi-Automatic Precision and Accuracy Analysis for Fast and Rigorous Deep Learning
crossref: Cornea:2020:ISC
pages: 103--110
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00023
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Christoph Lauter and Anastasia Volkova
rawtitle: A Framework for Semi-Automatic Precision and Accuracy Analysis for Fast and Rigorous Deep Learning
abstract:
Deep Neural Networks (DNN) represent a performance-hungry application. Floating-Point (FP) and custom floating-point-like arithmetic satisfies this hunger. While there is need for speed, inference in DNNs does not seem to have any need for precision. Many papers experimentally observe that DNNs can successfully run at almost ridiculously low precision. The aim of this paper is two-fold: first, to shed some theoretical light upon why a DNN's FP accuracy stays high for low FP precision. We observe that the loss of relative accuracy in the convolutional steps is recovered by the activation layers, which are extremely well-conditioned. We give an interpretation for the link between precision and accuracy in DNNs. Second, the paper presents a software framework for semi-automatic FP error analysis for the inference phase of deep-learning. Compatible with common Tensorflow/Keras models, it leverages the frugally-deep Python/C++ library to transform a neural network into C++ code in order to analyze the network's need for precision. This rigorous analysis is based an Interval and Affine arithmetics to compute absolute and relative error bounds for a DNN. We demonstrate our tool with several examples.

keywords:
affine arithmetic; Analytical models; ARITH 2020; ARITH-27; Biological neural networks; Computational modeling; deep learning; Digital arithmetic; error analysis; floating-point arithmetic; interval arithmetic; Machine learning; Neurons; Tools

rawabstract:
Deep Neural Networks (DNN) represent a performance-hungry application. Floating-Point (FP) and custom floating-point-like arithmetic satisfies this hunger. While there is need for speed, inference in DNNs does not seem to have any need for precision. Many papers experimentally observe that DNNs can successfully run at almost ridiculously low precision. The aim of this paper is two-fold: first, to shed some theoretical light upon why a DNN's FP accuracy stays high for low FP precision. We observe that the loss of relative accuracy in the convolutional steps is recovered by the activation layers, which are extremely well-conditioned. We give an interpretation for the link between precision and accuracy in DNNs. Second, the paper presents a software framework for semi-automatic FP error analysis for the inference phase of deep-learning. Compatible with common Tensorflow/Keras models, it leverages the frugally-deep Python/C++ library to transform a neural network into C++ code in order to analyze the network's need for precision. This rigorous analysis is based an Interval and Affine arithmetics to compute absolute and relative error bounds for a DNN. We demonstrate our tool with several examples.

entry:
@InProceedings{Lauter:2020:FSA,
  author =       "Christoph Lauter and Anastasia Volkova",
  title =        "A Framework for Semi-Automatic Precision and Accuracy
                 Analysis for Fast and Rigorous Deep Learning",
  crossref =     "Cornea:2020:ISC",
  pages =        "103--110",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00023",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Deep Neural Networks (DNN) represent a
                 performance-hungry application. Floating-Point (FP) and
                 custom floating-point-like arithmetic satisfies this
                 hunger. While there is need for speed, inference in
                 DNNs does not seem to have any need for precision. Many
                 papers experimentally observe that DNNs can
                 successfully run at almost ridiculously low precision.
                 The aim of this paper is two-fold: first, to shed some
                 theoretical light upon why a DNN's FP accuracy stays
                 high for low FP precision. We observe that the loss of
                 relative accuracy in the convolutional steps is
                 recovered by the activation layers, which are extremely
                 well-conditioned. We give an interpretation for the
                 link between precision and accuracy in DNNs. Second,
                 the paper presents a software framework for
                 semi-automatic FP error analysis for the inference
                 phase of deep-learning. Compatible with common
                 Tensorflow/Keras models, it leverages the frugally-deep
                 Python/C++ library to transform a neural network into
                 C++ code in order to analyze the network's need for
                 precision. This rigorous analysis is based an Interval
                 and Affine arithmetics to compute absolute and relative
                 error bounds for a DNN. We demonstrate our tool with
                 several examples.",
  acknowledgement = ack-nhfb,
  keywords =     "affine arithmetic; Analytical models; ARITH 2020;
                 ARITH-27; Biological neural networks; Computational
                 modeling; deep learning; Digital arithmetic; error
                 analysis; floating-point arithmetic; interval
                 arithmetic; Machine learning; Neurons; Tools",
}


bibtype: inproceedings
filename: fparith.bib
label: Lindstrom:2020:VRC
author: Peter Lindstrom
title: Variable-Radix Coding of the Reals
crossref: Cornea:2020:ISC
pages: 111--116
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00024
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Peter Lindstrom
rawtitle: Variable-Radix Coding of the Reals
abstract:
Recently proposed real number systems like Posits and Elias codes make use of tapered accuracy resulting from variable-length coding of exponents and significands. Several quite different interpretations of these number systems have been provided, though most often these rely on some combination of fixed- and variable-length codes for exponent and significand. We provide a new perspective on these number systems that unifies known representations while suggesting new ones. Our framework is based on multibit radix representations that encode the exponent in unary, the leading nonzero digit in a variable-length code, and the remaining digits in fixed-length binary code. We show how Posits, the various Elias codes, and IEEE 754 like representations can be expressed in this framework. Moreover, we show that Posits and the Elias and codes represent the leading digit using the canonical Huffman code for a probability distribution given by Benford's law, which governs the probability of leading digits. We further show that Posits correspond to the use of a fixed radix while Elias and codes are based on simple sequences of increasing radix. Our approach provides for an intuitive and uniform framework for representing numbers that reveals a visual mapping between codewords and the binary representation of real numbers obscured by prior frameworks. This new interpretation suggests a generalization of Posits and other number systems and provides simple rules for designing information-theoretically optimal codes.

keywords:
ARITH 2020; ARITH-27; Benford's law; Binary codes; Digital arithmetic; Elias codes; Encoding; floating point; Huffman code; Indexes; posits; Probability distribution; Proposals; real number systems; tapered accuracy; Visualization

rawabstract:
Recently proposed real number systems like Posits and Elias codes make use of tapered accuracy resulting from variable-length coding of exponents and significands. Several quite different interpretations of these number systems have been provided, though most often these rely on some combination of fixed- and variable-length codes for exponent and significand. We provide a new perspective on these number systems that unifies known representations while suggesting new ones. Our framework is based on multibit radix representations that encode the exponent in unary, the leading nonzero digit in a variable-length code, and the remaining digits in fixed-length binary code. We show how Posits, the various Elias codes, and IEEE 754 like representations can be expressed in this framework. Moreover, we show that Posits and the Elias and codes represent the leading digit using the canonical Huffman code for a probability distribution given by Benford's law, which governs the probability of leading digits. We further show that Posits correspond to the use of a fixed radix while Elias and codes are based on simple sequences of increasing radix. Our approach provides for an intuitive and uniform framework for representing numbers that reveals a visual mapping between codewords and the binary representation of real numbers obscured by prior frameworks. This new interpretation suggests a generalization of Posits and other number systems and provides simple rules for designing information-theoretically optimal codes.

entry:
@InProceedings{Lindstrom:2020:VRC,
  author =       "Peter Lindstrom",
  title =        "Variable-Radix Coding of the Reals",
  crossref =     "Cornea:2020:ISC",
  pages =        "111--116",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00024",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/benfords-law.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Recently proposed real number systems like Posits and
                 Elias codes make use of tapered accuracy resulting from
                 variable-length coding of exponents and significands.
                 Several quite different interpretations of these number
                 systems have been provided, though most often these
                 rely on some combination of fixed- and variable-length
                 codes for exponent and significand. We provide a new
                 perspective on these number systems that unifies known
                 representations while suggesting new ones. Our
                 framework is based on multibit radix representations
                 that encode the exponent in unary, the leading nonzero
                 digit in a variable-length code, and the remaining
                 digits in fixed-length binary code. We show how Posits,
                 the various Elias codes, and IEEE 754 like
                 representations can be expressed in this framework.
                 Moreover, we show that Posits and the Elias and codes
                 represent the leading digit using the canonical Huffman
                 code for a probability distribution given by Benford's
                 law, which governs the probability of leading digits.
                 We further show that Posits correspond to the use of a
                 fixed radix while Elias and codes are based on simple
                 sequences of increasing radix. Our approach provides
                 for an intuitive and uniform framework for representing
                 numbers that reveals a visual mapping between codewords
                 and the binary representation of real numbers obscured
                 by prior frameworks. This new interpretation suggests a
                 generalization of Posits and other number systems and
                 provides simple rules for designing
                 information-theoretically optimal codes.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Benford's law; Binary codes;
                 Digital arithmetic; Elias codes; Encoding; floating
                 point; Huffman code; Indexes; posits; Probability
                 distribution; Proposals; real number systems; tapered
                 accuracy; Visualization",
}


bibtype: article
filename: fparith.bib
label: Luo:2020:ADN
author: Y. Luo and S. Yu
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 8
pages: 1113--1127
year: 2020
CODEN: ITCOB4
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 23 16:03:24 2020
bibtimestamp: 2020.07.23 16:03:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Y. Luo and S. Yu
title:
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses

rawtitle:
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses

entry:
@Article{Luo:2020:ADN,
  author =       "Y. Luo and S. Yu",
  title =        "Accelerating Deep Neural Network In-Situ Training With
                 Non-Volatile and Volatile Memory Based Hybrid Precision
                 Synapses",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "8",
  pages =        "1113--1127",
  year =         "2020",
  CODEN =        "ITCOB4",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 23 16:03:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Lyakhov:2020:HPD
author: Pavel Lyakhov and Maria Valueva and Georgii Valuev and Nikolai Nagornov
journal: j-IEEE-ACCESS
volume: 8
pages: 209181--209190
year: 2020
DOI: https://doi.org/10.1109/ACCESS.2020.3038496
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Wed Oct 1 06:08:36 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:08:36 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Pavel Lyakhov and Maria Valueva and Georgii Valuev and Nikolai Nagornov
title:
High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

keywords:
Adders; Delays; digital filter; Digital signal processing; Filtering; Finite impulse response filters; Hardware; modular Multiply-Accumulate unit; Performance evaluation; residue number system

rawtitle:
High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

entry:
@Article{Lyakhov:2020:HPD,
  author =       "Pavel Lyakhov and Maria Valueva and Georgii Valuev and
                 Nikolai Nagornov",
  title =        "High-Performance Digital Filtering on Truncated
                 Multiply-Accumulate Units in the Residue Number
                 System",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  pages =        "209181--209190",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.3038496",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Wed Oct 1 06:08:36 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Adders; Delays; digital filter; Digital signal
                 processing; Filtering; Finite impulse response filters;
                 Hardware; modular Multiply-Accumulate unit; Performance
                 evaluation; residue number system",
}


bibtype: inproceedings
filename: fparith.bib
label: Marquer:2020:HLI
author: Yoann Marquer and Tania Richmond
title: A Hole in the Ladder: Interleaved Variables in Iterative Conditional Branching
crossref: Cornea:2020:ISC
pages: 56--63
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00017
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Yoann Marquer and Tania Richmond
rawtitle: A Hole in the Ladder: Interleaved Variables in Iterative Conditional Branching
abstract:
The modular exponentiation is crucial to the RSA cryptographic protocol, and variants inspired by the Montgomery ladder have been studied to provide more secure algorithms. In this paper, we abstract away the iterative conditional branching used in the Montgomery ladder, and formalize systems of equations necessary to obtain what we call the semi-interleaved and fully-interleaved ladder properties. In particular, we design fault-injection attacks able to obtain bits of the secret against semi-interleaved ladders, including the Montgomery ladder, but not against fully-interleaved ladders that are more secure. We also apply these equations to extend the Montgomery ladder for both the semi- and fully-interleaved cases, thus proposing novel and more secure algorithms to compute the modular exponentiation.

keywords:
ARITH 2020; ARITH-27; Countermeasures (computer); Cryptography; Fault detection; Iterative algorithms; Mathematical model; Public-key cryptography; Registers; Security; Side-channel attacks; Space exploration

rawabstract:
The modular exponentiation is crucial to the RSA cryptographic protocol, and variants inspired by the Montgomery ladder have been studied to provide more secure algorithms. In this paper, we abstract away the iterative conditional branching used in the Montgomery ladder, and formalize systems of equations necessary to obtain what we call the semi-interleaved and fully-interleaved ladder properties. In particular, we design fault-injection attacks able to obtain bits of the secret against semi-interleaved ladders, including the Montgomery ladder, but not against fully-interleaved ladders that are more secure. We also apply these equations to extend the Montgomery ladder for both the semi- and fully-interleaved cases, thus proposing novel and more secure algorithms to compute the modular exponentiation.

entry:
@InProceedings{Marquer:2020:HLI,
  author =       "Yoann Marquer and Tania Richmond",
  title =        "A Hole in the Ladder: Interleaved Variables in
                 Iterative Conditional Branching",
  crossref =     "Cornea:2020:ISC",
  pages =        "56--63",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00017",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The modular exponentiation is crucial to the RSA
                 cryptographic protocol, and variants inspired by the
                 Montgomery ladder have been studied to provide more
                 secure algorithms. In this paper, we abstract away the
                 iterative conditional branching used in the Montgomery
                 ladder, and formalize systems of equations necessary to
                 obtain what we call the semi-interleaved and
                 fully-interleaved ladder properties. In particular, we
                 design fault-injection attacks able to obtain bits of
                 the secret against semi-interleaved ladders, including
                 the Montgomery ladder, but not against
                 fully-interleaved ladders that are more secure. We also
                 apply these equations to extend the Montgomery ladder
                 for both the semi- and fully-interleaved cases, thus
                 proposing novel and more secure algorithms to compute
                 the modular exponentiation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Countermeasures (computer);
                 Cryptography; Fault detection; Iterative algorithms;
                 Mathematical model; Public-key cryptography; Registers;
                 Security; Side-channel attacks; Space exploration",
}


bibtype: techreport
filename: fparith.bib
label: Meurant:2020:PFM
author: Gerard Meurant
title: pkg FLOATP_toolbox, Matlab software, variable precision floating point arithmetic.
type: Report
institution: Commissariat a l'Energie Atomique (CEA)
address: ????, France
pages: 56--63
year: 2020
bibdate: Sat Dec 23 12:13:27 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2023.12.23 12:13:27 ???
URL: https://gerard-meurant.pagesperso-orange.fr/soft_meurant_n.html
remark: URL links to almost-empty home page.
acknowledgement: ack-nhfb
rawauthor: G{\'e}rard Meurant
rawtitle: \pkg{FLOATP\_toolbox}, {Matlab} software, variable precision floating point arithmetic.
entry:
@TechReport{Meurant:2020:PFM,
  author =       "G{\'e}rard Meurant",
  title =        "\pkg{FLOATP\_toolbox}, {Matlab} software, variable
                 precision floating point arithmetic.",
  type =         "Report",
  number =       "????",
  institution =  "Commissariat a l'{\'E}nergie Atomique (CEA)",
  address =      "????, France",
  year =         "2020",
  bibdate =      "Sat Dec 23 12:13:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://gerard-meurant.pagesperso-orange.fr/soft_meurant_n.html",
  acknowledgement = ack-nhfb,
  remark =       "URL links to almost-empty home page.",
}


bibtype: inproceedings
filename: fparith.bib
label: Mikaitis:2020:IRG
author: Mantas Mikaitis
crossref: Cornea:2020:ISC
pages: 129--132
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00028
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/gnu.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Mantas Mikaitis
title:
Issues with rounding in the GCC implementation of the ISO 18037:2008 standard fixed-point arithmetic

abstract:
We describe various issues caused by the lack of round-to-nearest mode in the gcc compiler implementation of the fixed-point arithmetic data types and operations. We demonstrate that round-to-nearest is not performed in the conversion of constants, conversion from one numerical type to a less precise type and results of multiplications. Furthermore, we show that mixed-precision operations in fixed-point arithmetic lose precision on arguments, even before carrying out arithmetic operations. The ISO 18037:2008 standard was created to standardize C language extensions, including fixed-point arithmetic, for embedded systems. Embedded systems are usually based on ARM processors, of which approximately 100 billion have been manufactured by now. Therefore, the observations about numerical issues that we discuss in this paper can be rather dangerous and are important to address, given the wide ranging type of applications that these embedded systems are running.

keywords:
ARITH 2020; ARITH-27; Computer languages; Embedded systems; fixed-point arithmetic; Hardware; ISO 18037:2008; ISO Standards; Libraries; Program processors; rounding

rawabstract:
We describe various issues caused by the lack of round-to-nearest mode in the gcc compiler implementation of the fixed-point arithmetic data types and operations. We demonstrate that round-to-nearest is not performed in the conversion of constants, conversion from one numerical type to a less precise type and results of multiplications. Furthermore, we show that mixed-precision operations in fixed-point arithmetic lose precision on arguments, even before carrying out arithmetic operations. The ISO 18037:2008 standard was created to standardize C language extensions, including fixed-point arithmetic, for embedded systems. Embedded systems are usually based on ARM processors, of which approximately 100 billion have been manufactured by now. Therefore, the observations about numerical issues that we discuss in this paper can be rather dangerous and are important to address, given the wide ranging type of applications that these embedded systems are running.

rawtitle:
Issues with rounding in the {GCC} implementation of the {ISO 18037:2008} standard fixed-point arithmetic

entry:
@InProceedings{Mikaitis:2020:IRG,
  author =       "Mantas Mikaitis",
  title =        "Issues with rounding in the {GCC} implementation of
                 the {ISO 18037:2008} standard fixed-point arithmetic",
  crossref =     "Cornea:2020:ISC",
  pages =        "129--132",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00028",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib",
  abstract =     "We describe various issues caused by the lack of
                 round-to-nearest mode in the gcc compiler
                 implementation of the fixed-point arithmetic data types
                 and operations. We demonstrate that round-to-nearest is
                 not performed in the conversion of constants,
                 conversion from one numerical type to a less precise
                 type and results of multiplications. Furthermore, we
                 show that mixed-precision operations in fixed-point
                 arithmetic lose precision on arguments, even before
                 carrying out arithmetic operations. The ISO 18037:2008
                 standard was created to standardize C language
                 extensions, including fixed-point arithmetic, for
                 embedded systems. Embedded systems are usually based on
                 ARM processors, of which approximately 100 billion have
                 been manufactured by now. Therefore, the observations
                 about numerical issues that we discuss in this paper
                 can be rather dangerous and are important to address,
                 given the wide ranging type of applications that these
                 embedded systems are running.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Computer languages; Embedded
                 systems; fixed-point arithmetic; Hardware; ISO
                 18037:2008; ISO Standards; Libraries; Program
                 processors; rounding",
}


bibtype: article
filename: fparith.bib
label: Mikaitis:2020:SRA
author: Mantas Mikaitis
title: Stochastic Rounding: Algorithms and Hardware Accelerator
journal: arXiv.org
pages: 1--6
day: 29
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.48550/arXiv.2001.01501
bibdate: Wed Aug 07 16:03:40 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib
bibtimestamp: 2024.08.07 16:03:40 ???
URL: https://arxiv.org/abs/2001.01501#
acknowledgement: ack-nhfb
rawauthor: Mantas Mikaitis
rawtitle: Stochastic Rounding: Algorithms and Hardware Accelerator
abstract:
Algorithms and a hardware accelerator for performing stochastic rounding (SR) are presented. The main goal is to augment the ARM M4F based multi-core processor SpiNNaker2 with a more flexible rounding functionality than is available in the ARM processor itself. The motivation of adding such an accelerator in hardware is based on our previous results showing improvements in numerical accuracy of ODE solvers in fixed-point arithmetic with SR, compared to standard round to nearest or bit truncation rounding modes. Furthermore, performing SR purely in software can be expensive, due to requirement of a pseudorandom number generator (PRNG), multiple masking and shifting instructions, and an addition operation. Also, saturation of the rounded values is included, since rounding is usually followed by saturation, which is especially important in fixed-point arithmetic due to a narrow dynamic range of representable values. The main intended use of the accelerator is to round fixed-point multiplier outputs, which are returned unrounded by the ARM processor in a wider fixed-point format than the arguments.

rawabstract:
Algorithms and a hardware accelerator for performing stochastic rounding (SR) are presented. The main goal is to augment the ARM M4F based multi-core processor SpiNNaker2 with a more flexible rounding functionality than is available in the ARM processor itself. The motivation of adding such an accelerator in hardware is based on our previous results showing improvements in numerical accuracy of ODE solvers in fixed-point arithmetic with SR, compared to standard round to nearest or bit truncation rounding modes. Furthermore, performing SR purely in software can be expensive, due to requirement of a pseudorandom number generator (PRNG), multiple masking and shifting instructions, and an addition operation. Also, saturation of the rounded values is included, since rounding is usually followed by saturation, which is especially important in fixed-point arithmetic due to a narrow dynamic range of representable values. The main intended use of the accelerator is to round fixed-point multiplier outputs, which are returned unrounded by the ARM processor in a wider fixed-point format than the arguments.

entry:
@Article{Mikaitis:2020:SRA,
  author =       "Mantas Mikaitis",
  title =        "Stochastic Rounding: Algorithms and Hardware
                 Accelerator",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--6",
  day =          "29",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.48550/arXiv.2001.01501",
  bibdate =      "Wed Aug 07 16:03:40 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  URL =          "https://arxiv.org/abs/2001.01501#",
  abstract =     "Algorithms and a hardware accelerator for performing
                 stochastic rounding (SR) are presented. The main goal
                 is to augment the ARM M4F based multi-core processor
                 SpiNNaker2 with a more flexible rounding functionality
                 than is available in the ARM processor itself. The
                 motivation of adding such an accelerator in hardware is
                 based on our previous results showing improvements in
                 numerical accuracy of ODE solvers in fixed-point
                 arithmetic with SR, compared to standard round to
                 nearest or bit truncation rounding modes. Furthermore,
                 performing SR purely in software can be expensive, due
                 to requirement of a pseudorandom number generator
                 (PRNG), multiple masking and shifting instructions, and
                 an addition operation. Also, saturation of the rounded
                 values is included, since rounding is usually followed
                 by saturation, which is especially important in
                 fixed-point arithmetic due to a narrow dynamic range of
                 representable values. The main intended use of the
                 accelerator is to round fixed-point multiplier outputs,
                 which are returned unrounded by the ARM processor in a
                 wider fixed-point format than the arguments.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Muller:2020:EFA
author: Jean-Michel Muller
title: Elementary Functions and Approximate Computing
journal: j-PROC-IEEE
volume: 108
number: 12
pages: 2136--2149
month: dec
monthnumber: 12
year: 2020
CODEN: IEEPAD
DOI: https://doi.org/10.1109/jproc.2020.2991885
ISSN: 0018-9219 (print), 1558-2256 (electronic) OR 00189219 (print), 15582256 (electronic)
ISSNL: 0018-9219 OR 00189219
bibdate: Tue Mar 1 06:07:02 2022
bibtimestamp: 2022.03.01 06:07:02 ???
fjournal: Proceedings of the IEEE
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5
rawauthor: Jean-Michel Muller
rawtitle: Elementary Functions and Approximate Computing
abstract:
In this article, we review some of the classical methods used for quickly obtaining low-precision approximations to the elementary functions. Then, for each of the three main classes of elementary function algorithms (shift-and-add algorithms, polynomial or rational approximations, and table-based methods) and for the additional, specific to approximate computing, ``bit-manipulation'' techniques, we examine what can be done for obtaining very fast estimates of a function, at the cost of a (controlled) loss in terms of accuracy.

rawabstract:
In this article, we review some of the classical methods used for quickly obtaining low-precision approximations to the elementary functions. Then, for each of the three main classes of elementary function algorithms (shift-and-add algorithms, polynomial or rational approximations, and table-based methods) and for the additional, specific to approximate computing, ``bit-manipulation'' techniques, we examine what can be done for obtaining very fast estimates of a function, at the cost of a (controlled) loss in terms of accuracy.

entry:
@Article{Muller:2020:EFA,
  author =       "Jean-Michel Muller",
  title =        "Elementary Functions and Approximate Computing",
  journal =      j-PROC-IEEE,
  volume =       "108",
  number =       "12",
  pages =        "2136--2149",
  month =        dec,
  year =         "2020",
  CODEN =        "IEEPAD",
  DOI =          "https://doi.org/10.1109/jproc.2020.2991885",
  ISSN =         "0018-9219 (print), 1558-2256 (electronic)",
  ISSN-L =       "0018-9219",
  bibdate =      "Tue Mar 1 06:07:02 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this article, we review some of the classical
                 methods used for quickly obtaining low-precision
                 approximations to the elementary functions. Then, for
                 each of the three main classes of elementary function
                 algorithms (shift-and-add algorithms, polynomial or
                 rational approximations, and table-based methods) and
                 for the additional, specific to approximate computing,
                 ``bit-manipulation'' techniques, we examine what can be
                 done for obtaining very fast estimates of a function,
                 at the cost of a (controlled) loss in terms of
                 accuracy.",
  acknowledgement = ack-nhfb,
  fjournal =     "Proceedings of the IEEE",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2020:CPA
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella
editor: IEEE
booktitle: IEEE International Symposium on Circuits and Systems (ISCAS): Seville, Spain, October 11--14, 2020
title: Customized Posit Adders and Multipliers using the FloPoCo Core Generator
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2020
DOI: https://doi.org/10.1109/ISCAS45731.2020.9180771
ISBN: 1-72813-320-3 OR 1728133203
ISBN13: 978-1-72813-320-1 OR 9781728133201
ISSN: 0271-4302 (print), 2158-1525 (electronic) OR 02714302 (print), 21581525 (electronic)
ISSNL: 0271-4302 OR 02714302
bibdate: Thu Dec 14 17:18:33 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 17:18:33 ???
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1109/ISCAS45731.2020
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella
raweditor: {IEEE}
rawtitle: Customized Posit Adders and Multipliers using the {FloPoCo} Core Generator
rawbooktitle:
{IEEE International Symposium on Circuits and Systems (ISCAS): Seville, Spain, October 11--14, 2020}

entry:
@InProceedings{Murillo:2020:CPA,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella",
  editor =       "{IEEE}",
  booktitle =    "{IEEE International Symposium on Circuits and Systems
                 (ISCAS): Seville, Spain, October 11--14, 2020}",
  title =        "Customized Posit Adders and Multipliers using the
                 {FloPoCo} Core Generator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9180771",
  ISBN =         "1-72813-320-3",
  ISBN-13 =      "978-1-72813-320-1",
  ISSN =         "0271-4302 (print), 2158-1525 (electronic)",
  ISSN-L =       "0271-4302",
  bibdate =      "Thu Dec 14 17:18:33 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1109/ISCAS45731.2020",
}


bibtype: article
filename: fparith.bib
label: Murillo:2020:DPD
author: R. Murillo and A. A. Del Barrio and G. Botella
title: Deep PeNSieve: a deep learning framework based on the posit number system
journal: j-DIGIT-SIGNAL-PROCESS
volume: 102
pages: 1--8
month: jul
monthnumber: 7
year: 2020
CODEN: DSPREJ
DOI: https://doi.org/10.1016/j.dsp.2020.102762
ISSN: 1051-2004 (print), 1095-4333 (electronic) OR 10512004 (print), 10954333 (electronic)
ISSNL: 1051-2004 OR 10512004
bibdate: Thu Dec 14 17:04:34 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 17:04:34 ???
URL: https://www.sciencedirect.com/science/article/pii/S105120042030107X
fjournal: Digital Signal Processing
acknowledgement: ack-nhfb
articleno: 102762
journalURL: https://www.sciencedirect.com/journal/digital-signal-processing
rawauthor: R. Murillo and A. A. {Del Barrio} and G. Botella
rawtitle: {Deep PeNSieve}: a deep learning framework based on the posit number system
entry:
@Article{Murillo:2020:DPD,
  author =       "R. Murillo and A. A. {Del Barrio} and G. Botella",
  title =        "{Deep PeNSieve}: a deep learning framework based on
                 the posit number system",
  journal =      j-DIGIT-SIGNAL-PROCESS,
  volume =       "102",
  pages =        "1--8",
  month =        jul,
  year =         "2020",
  CODEN =        "DSPREJ",
  DOI =          "https://doi.org/10.1016/j.dsp.2020.102762",
  ISSN =         "1051-2004 (print), 1095-4333 (electronic)",
  ISSN-L =       "1051-2004",
  bibdate =      "Thu Dec 14 17:04:34 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S105120042030107X",
  acknowledgement = ack-nhfb,
  articleno =    "102762",
  fjournal =     "Digital Signal Processing",
  journal-URL =  "https://www.sciencedirect.com/journal/digital-signal-processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:2020:VPB
author: Alberto Nannarelli
title: Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors
crossref: Cornea:2020:ISC
pages: 96--102
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00022
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli
rawtitle: Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors
abstract:
The increasing demand of computation at the edge and the tight power budgets push designers to migrate double and single-precision calculations to formats of reduced precision and dynamic range for applications that can tolerate some inaccuracy.In this context, we introduce a variable format for reduced precision floating-point with storage limited to 16 bits. This format is suitable for applications in signal processing, machine learning and other applications in embedded systems. We present the hardware implementations for multiplication and division units that can sustain a throughput of one result per clock cycle designed for vector processing. We also show some examples of applications that can benefit from the proposed format.

keywords:
Adders; ARITH 2020; ARITH-27; customizable bias; Dynamic range; Encoding; Floating-point; Hardware; Program processors; Signal processing; Standards; variable precision

rawabstract:
The increasing demand of computation at the edge and the tight power budgets push designers to migrate double and single-precision calculations to formats of reduced precision and dynamic range for applications that can tolerate some inaccuracy.In this context, we introduce a variable format for reduced precision floating-point with storage limited to 16 bits. This format is suitable for applications in signal processing, machine learning and other applications in embedded systems. We present the hardware implementations for multiplication and division units that can sustain a throughput of one result per clock cycle designed for vector processing. We also show some examples of applications that can benefit from the proposed format.

entry:
@InProceedings{Nannarelli:2020:VPB,
  author =       "Alberto Nannarelli",
  title =        "Variable Precision 16-Bit Floating-Point Vector Unit
                 for Embedded Processors",
  crossref =     "Cornea:2020:ISC",
  pages =        "96--102",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00022",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The increasing demand of computation at the edge and
                 the tight power budgets push designers to migrate
                 double and single-precision calculations to formats of
                 reduced precision and dynamic range for applications
                 that can tolerate some inaccuracy.In this context, we
                 introduce a variable format for reduced precision
                 floating-point with storage limited to 16 bits. This
                 format is suitable for applications in signal
                 processing, machine learning and other applications in
                 embedded systems. We present the hardware
                 implementations for multiplication and division units
                 that can sustain a throughput of one result per clock
                 cycle designed for vector processing. We also show some
                 examples of applications that can benefit from the
                 proposed format.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH 2020; ARITH-27; customizable bias;
                 Dynamic range; Encoding; Floating-point; Hardware;
                 Program processors; Signal processing; Standards;
                 variable precision",
}


bibtype: misc
filename: fparith.bib
label: Nass:2020:GUL
author: Rich Nass
title: GreenWaves Ultra-Low Power GAP9 IoT Apps Processor Suits Intelligence at the Edge
pages: 96--102
day: 21
month: jan
monthnumber: 1
year: 2020
bibdate: Wed Jan 22 07:07:03 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.22 07:07:03 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Rich Nass
rawtitle: {GreenWaves} Ultra-Low Power {GAP9} {IoT} Apps Processor Suits Intelligence at the Edge
note:
GAP9 offers vectorized 2-bit and 4-bit fixed-point arithmetic, and 8-, 16-, and 32-bit floating-point arithmetic.

URL:
https://www.embedded-computing.com/guest-blogs/greenwaves-ultra-low-power-gap9-iot-apps-processor-suits-intelligence-at-the-edge

rawnote:
GAP9 offers vectorized 2-bit and 4-bit fixed-point arithmetic, and 8-, 16-, and 32-bit floating-point arithmetic.

entry:
@Misc{Nass:2020:GUL,
  author =       "Rich Nass",
  title =        "{GreenWaves} Ultra-Low Power {GAP9} {IoT} Apps
                 Processor Suits Intelligence at the Edge",
  howpublished = "Web site",
  day =          "21",
  month =        jan,
  year =         "2020",
  bibdate =      "Wed Jan 22 07:07:03 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "GAP9 offers vectorized 2-bit and 4-bit fixed-point
                 arithmetic, and 8-, 16-, and 32-bit floating-point
                 arithmetic.",
  URL =          "https://www.embedded-computing.com/guest-blogs/greenwaves-ultra-low-power-gap9-iot-apps-processor-suits-intelligence-at-the-edge",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Neves:2020:DFM
author: Nuno Neves and Pedro Tomas and Nuno Roma
editor: IEEE
booktitle: 2020 IEEE Workshop on Signal Processing Systems (SiPS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2020
DOI: https://doi.org/10.1109/SiPS50750.2020.9195256
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Nuno Neves and Pedro Tom{\'a}s and Nuno Roma
rawbooktitle: {2020 IEEE Workshop on Signal Processing Systems (SiPS)}
raweditor: {IEEE}
title:
Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications

rawtitle:
Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision {DSP} Applications

entry:
@InProceedings{Neves:2020:DFM,
  author =       "Nuno Neves and Pedro Tom{\'a}s and Nuno Roma",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Workshop on Signal Processing Systems
                 (SiPS)}",
  title =        "Dynamic Fused Multiply-Accumulate Posit Unit with
                 Variable Exponent Size for Low-Precision {DSP}
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/SiPS50750.2020.9195256",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Neves:2020:RSB
author: Nuno Neves and Pedro Tomas and Nuno Roma
editor: IEEE
title: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 149--156
year: 2020
DOI: https://doi.org/10.1109/ASAP49362.2020.00033
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Nuno Neves and Pedro Tom{\'a}s and Nuno Roma
raweditor: {IEEE}
rawtitle: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
booktitle:
2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)

rawbooktitle:
{2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)}

entry:
@InProceedings{Neves:2020:RSB,
  author =       "Nuno Neves and Pedro Tom{\'a}s and Nuno Roma",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 31st International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "Reconfigurable Stream-based Tensor Unit with
                 Variable-Precision Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "149--156",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ASAP49362.2020.00033",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Niasar:2020:FSA
author: Mojtaba Bisheh Niasar and Rami El Khatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
title: Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
crossref: Cornea:2020:ISC
pages: 72--79
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00019
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Mojtaba Bisheh Niasar and Rami {El Khatib} and Reza Azarderakhsh and Mehran Mozaffari-Kermani
rawtitle: Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on {Curve25519}
abstract:
This paper demonstrates fast and compact implementations of Elliptic Curve Cryptography (ECC) for efficient key agreement over Curve25519. Curve25519 has been recently adopted as a key exchange method for several applications and included in the National Institute of Standards and Technology (NIST) recommendations for public key cryptography. This paper presents three different performance level designs including lightweight, area-time efficient, and high-performance architectures. Lightweight hardware implementations are used for several Internet of Things (IoT) applications due to their resources being at premium. Our lightweight architecture utilizes 90% less resources compared to the best previous work while it is still more optimized in term of A $ cdot $ T (area $ times $ time). For efficient implementation from either time or utilized resources, our area-time efficient architecture can establish almost 7,000 key sessions per second which is 64% faster than the previous works. The area-time efficient architecture uses well scheduled interleaved multiplication combined with a reduction algorithm. Additionally, we offer a fast architecture for high performance applications based on the 4-level Karatsuba method and Carry-Compact Addition (CCA). Our high-performance architecture also outperforms previous work in terms of A middot; T. The results show 9% and 29% improvement in A middot; T and Admiddot; T (DSP_count $ times $ time), respectively. All architectures are variable-base-point implemented on the Xilinx Zynq-7020 FPGA family where performance and implementation metrics are reported and compared. Finally, various side-channel attack countermeasures are embedded in the proposed architectures.

keywords:
ARITH 2020; ARITH-27; Computer architecture; Curve25519; Elliptic curve cryptography; elliptic curve Diffie-Hellman (ECDH); Elliptic curves; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; NIST; point multiplication; Random access memory

rawabstract:
This paper demonstrates fast and compact implementations of Elliptic Curve Cryptography (ECC) for efficient key agreement over Curve25519. Curve25519 has been recently adopted as a key exchange method for several applications and included in the National Institute of Standards and Technology (NIST) recommendations for public key cryptography. This paper presents three different performance level designs including lightweight, area-time efficient, and high-performance architectures. Lightweight hardware implementations are used for several Internet of Things (IoT) applications due to their resources being at premium. Our lightweight architecture utilizes 90\% less resources compared to the best previous work while it is still more optimized in term of A $ \cdot $ T (area $ \times $ time). For efficient implementation from either time or utilized resources, our area-time efficient architecture can establish almost 7,000 key sessions per second which is 64\% faster than the previous works. The area-time efficient architecture uses well scheduled interleaved multiplication combined with a reduction algorithm. Additionally, we offer a fast architecture for high performance applications based on the 4-level Karatsuba method and Carry-Compact Addition (CCA). Our high-performance architecture also outperforms previous work in terms of A middot; T. The results show 9\% and 29\% improvement in A middot; T and Admiddot; T (DSP\_count $ \times $ time), respectively. All architectures are variable-base-point implemented on the Xilinx Zynq-7020 FPGA family where performance and implementation metrics are reported and compared. Finally, various side-channel attack countermeasures are embedded in the proposed architectures.

entry:
@InProceedings{Niasar:2020:FSA,
  author =       "Mojtaba Bisheh Niasar and Rami {El Khatib} and Reza
                 Azarderakhsh and Mehran Mozaffari-Kermani",
  title =        "Fast, Small, and Area-Time Efficient Architectures for
                 Key-Exchange on {Curve25519}",
  crossref =     "Cornea:2020:ISC",
  pages =        "72--79",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00019",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper demonstrates fast and compact
                 implementations of Elliptic Curve Cryptography (ECC)
                 for efficient key agreement over Curve25519. Curve25519
                 has been recently adopted as a key exchange method for
                 several applications and included in the National
                 Institute of Standards and Technology (NIST)
                 recommendations for public key cryptography. This paper
                 presents three different performance level designs
                 including lightweight, area-time efficient, and
                 high-performance architectures. Lightweight hardware
                 implementations are used for several Internet of Things
                 (IoT) applications due to their resources being at
                 premium. Our lightweight architecture utilizes 90\%
                 less resources compared to the best previous work while
                 it is still more optimized in term of A $ \cdot $ T
                 (area $ \times $ time). For efficient implementation
                 from either time or utilized resources, our area-time
                 efficient architecture can establish almost 7,000 key
                 sessions per second which is 64\% faster than the
                 previous works. The area-time efficient architecture
                 uses well scheduled interleaved multiplication combined
                 with a reduction algorithm. Additionally, we offer a
                 fast architecture for high performance applications
                 based on the 4-level Karatsuba method and Carry-Compact
                 Addition (CCA). Our high-performance architecture also
                 outperforms previous work in terms of A middot; T. The
                 results show 9\% and 29\% improvement in A middot; T
                 and Admiddot; T (DSP\_count $ \times $ time),
                 respectively. All architectures are variable-base-point
                 implemented on the Xilinx Zynq-7020 FPGA family where
                 performance and implementation metrics are reported and
                 compared. Finally, various side-channel attack
                 countermeasures are embedded in the proposed
                 architectures.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2020; ARITH-27; Computer architecture;
                 Curve25519; Elliptic curve cryptography; elliptic curve
                 Diffie-Hellman (ECDH); Elliptic curves; Field
                 programmable gate arrays; field-programmable gate array
                 (FPGA); Hardware; NIST; point multiplication; Random
                 access memory",
}


bibtype: inproceedings
filename: fparith.bib
label: Papachatzopoulos:2020:MDM
author: Kleanthis Papachatzopoulos and Vassilis Paliouras
title: Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations
crossref: Cornea:2020:ISC
pages: 88--95
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00021
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Kleanthis Papachatzopoulos and Vassilis Paliouras
rawtitle: Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations
abstract:
This paper introduces a delay modeling formulation for several Parallel-Prefix Adders in the presence of threshold voltage variability. A path-based model is derived for the delay variability of Kogge-Stone, Knowles, Sklansky, Brent-Kung, Han-Carlson, Ladner-Fischer, and New Adder architectures. The delay model accuracy is evaluated for the specific adders on the basis of SPICE Monte-Carlo Simulations at 45 nm and 16 nm nodes. The presented analysis reveals that the proposed path-based model estimates the maximum delay Probability Density Function of the particular adder architectures with sufficient accuracy, assuming 3 intra-die threshold voltage variations as high as 10% of nominal value. Delay yield estimations produced by the proposed model are found to agree with those of Monte-Carlo Simulations for a number of highly probable critical paths, presenting an error less than 2%. For the particular adders and technology nodes, an approximately 10-fold reduction in simulation time is obtained when exploiting the proposed model. The particular observation indicates that the computational time for delay yield estimation of Parallel-Prefix Adders can be exponentially reduced with negligible accuracy loss when the analysis focuses solely on the Nominal-Maximum Delay critical path. Finally, a quantitative comparison of prefix adders to the Borrow-Save Adder is offered, in terms of complexity and susceptibility to variations.

keywords:
Adders; ARITH 2020; ARITH-27; critical path; delay yield; Delays; Gaussian distribution; Monte Carlo methods; parallel-prefix adders; SPICE; Threshold voltage; threshold voltage variations; variability

rawabstract:
This paper introduces a delay modeling formulation for several Parallel-Prefix Adders in the presence of threshold voltage variability. A path-based model is derived for the delay variability of Kogge-Stone, Knowles, Sklansky, Brent-Kung, Han-Carlson, Ladner-Fischer, and New Adder architectures. The delay model accuracy is evaluated for the specific adders on the basis of SPICE Monte-Carlo Simulations at 45 nm and 16 nm nodes. The presented analysis reveals that the proposed path-based model estimates the maximum delay Probability Density Function of the particular adder architectures with sufficient accuracy, assuming 3 intra-die threshold voltage variations as high as 10\% of nominal value. Delay yield estimations produced by the proposed model are found to agree with those of Monte-Carlo Simulations for a number of highly probable critical paths, presenting an error less than 2\%. For the particular adders and technology nodes, an approximately 10-fold reduction in simulation time is obtained when exploiting the proposed model. The particular observation indicates that the computational time for delay yield estimation of Parallel-Prefix Adders can be exponentially reduced with negligible accuracy loss when the analysis focuses solely on the Nominal-Maximum Delay critical path. Finally, a quantitative comparison of prefix adders to the Borrow-Save Adder is offered, in terms of complexity and susceptibility to variations.

entry:
@InProceedings{Papachatzopoulos:2020:MDM,
  author =       "Kleanthis Papachatzopoulos and Vassilis Paliouras",
  title =        "Maximum Delay Models for Parallel-Prefix Adders in the
                 Presence of Threshold Voltage Variations",
  crossref =     "Cornea:2020:ISC",
  pages =        "88--95",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00021",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper introduces a delay modeling formulation for
                 several Parallel-Prefix Adders in the presence of
                 threshold voltage variability. A path-based model is
                 derived for the delay variability of Kogge-Stone,
                 Knowles, Sklansky, Brent-Kung, Han-Carlson,
                 Ladner-Fischer, and New Adder architectures. The delay
                 model accuracy is evaluated for the specific adders on
                 the basis of SPICE Monte-Carlo Simulations at 45 nm and
                 16 nm nodes. The presented analysis reveals that the
                 proposed path-based model estimates the maximum delay
                 Probability Density Function of the particular adder
                 architectures with sufficient accuracy, assuming 3
                 intra-die threshold voltage variations as high as 10\%
                 of nominal value. Delay yield estimations produced by
                 the proposed model are found to agree with those of
                 Monte-Carlo Simulations for a number of highly probable
                 critical paths, presenting an error less than 2\%. For
                 the particular adders and technology nodes, an
                 approximately 10-fold reduction in simulation time is
                 obtained when exploiting the proposed model. The
                 particular observation indicates that the computational
                 time for delay yield estimation of Parallel-Prefix
                 Adders can be exponentially reduced with negligible
                 accuracy loss when the analysis focuses solely on the
                 Nominal-Maximum Delay critical path. Finally, a
                 quantitative comparison of prefix adders to the
                 Borrow-Save Adder is offered, in terms of complexity
                 and susceptibility to variations.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH 2020; ARITH-27; critical path; delay
                 yield; Delays; Gaussian distribution; Monte Carlo
                 methods; parallel-prefix adders; SPICE; Threshold
                 voltage; threshold voltage variations; variability",
}


bibtype: inproceedings
filename: fparith.bib
label: Payer:2020:SMF
title: SIMD Multi Format Floating-Point Unit on the IBM z15
crossref: Cornea:2020:ISC
pages: 125--128
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00027
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawtitle: {SIMD} Multi Format Floating-Point Unit on the {IBM z15}
author:
Stefan Payer and Cedric Lichtenau and Michael Klein and Kerstin Schelm and Petra Leber and Nicol Hofmann and Tina Babinsky

abstract:
The IBM z Systems(TM) is the backbone of the insurance, banking, and retail industry. Innovation in these markets is driving the demand for new and additional applications to better serve the customers. These workloads like machine learning, data analytics, AI, etc. require a rapidly increasing number of computations in smaller precision formats. With IBM z15(TM) we completely redesigned the binary and hexadecimal floating-point unit to efficiently implement SIMD operations at 5.2GHz while maintaining the industry leading reliability, availability and serviceability standard. This paper describes the new design and special techniques used to achieve these goals like reusing the existing double precision unit pipeline for lower precision parallel SIMD, new approaches to formally verify the design, and improving error detection for the 14nm technology node.

keywords:
AI; ARITH 2020; ARITH-27; Binary; Digital arithmetic; Floating Point Unit; Formal Verification; Hafnium; Hexadecimal; IBM z15(TM); Machine Learning; Multi Format; SIMD

rawabstract:
The IBM z Systems(TM) is the backbone of the insurance, banking, and retail industry. Innovation in these markets is driving the demand for new and additional applications to better serve the customers. These workloads like machine learning, data analytics, AI, etc. require a rapidly increasing number of computations in smaller precision formats. With IBM z15(TM) we completely redesigned the binary and hexadecimal floating-point unit to efficiently implement SIMD operations at 5.2GHz while maintaining the industry leading reliability, availability and serviceability standard. This paper describes the new design and special techniques used to achieve these goals like reusing the existing double precision unit pipeline for lower precision parallel SIMD, new approaches to formally verify the design, and improving error detection for the 14nm technology node.

rawauthor:
Stefan Payer and Cedric Lichtenau and Michael Klein and Kerstin Schelm and Petra Leber and Nicol Hofmann and Tina Babinsky

entry:
@InProceedings{Payer:2020:SMF,
  author =       "Stefan Payer and Cedric Lichtenau and Michael Klein
                 and Kerstin Schelm and Petra Leber and Nicol Hofmann
                 and Tina Babinsky",
  title =        "{SIMD} Multi Format Floating-Point Unit on the {IBM
                 z15}",
  crossref =     "Cornea:2020:ISC",
  pages =        "125--128",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00027",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IBM z Systems(TM) is the backbone of the
                 insurance, banking, and retail industry. Innovation in
                 these markets is driving the demand for new and
                 additional applications to better serve the customers.
                 These workloads like machine learning, data analytics,
                 AI, etc. require a rapidly increasing number of
                 computations in smaller precision formats. With IBM
                 z15(TM) we completely redesigned the binary and
                 hexadecimal floating-point unit to efficiently
                 implement SIMD operations at 5.2GHz while maintaining
                 the industry leading reliability, availability and
                 serviceability standard. This paper describes the new
                 design and special techniques used to achieve these
                 goals like reusing the existing double precision unit
                 pipeline for lower precision parallel SIMD, new
                 approaches to formally verify the design, and improving
                 error detection for the 14nm technology node.",
  acknowledgement = ack-nhfb,
  keywords =     "AI; ARITH 2020; ARITH-27; Binary; Digital arithmetic;
                 Floating Point Unit; Formal Verification; Hafnium;
                 Hexadecimal; IBM z15(TM); Machine Learning; Multi
                 Format; SIMD",
}


bibtype: inproceedings
filename: fparith.bib
label: RAos:2020:EMP
booktitle: 2020 19th IEEE International Conference on Machine Learning and Applications (ICMLA)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 49--56
year: 2020
DOI: https://doi.org/10.1109/ICMLA51294.2020.00017
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2020 19th IEEE International Conference on Machine Learning and Applications (ICMLA)}
author:
John Osorio Rios and Adria Armejach and Gulrukh Khattak and Eric Petit and Sofia Vallecorsa and Marc Casas

title:
Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors

keywords:
3DGAN; Binary Analysis Tool; Brain Float 16 (BF16); Computational modeling; Detectors; Generative adversarial networks; Generative Adversarial Networks; Hardware; High Energy Physics; Mixed Precision (MP); Numerical models; Reduced Precision; Tools; Training

rawauthor:
John Osorio R{\'\i}os and Adri{\`a} Armejach and Gulrukh Khattak and Eric Petit and Sofia Vallecorsa and Marc Casas

rawtitle:
Evaluating Mixed-Precision Arithmetic for {3D} Generative Adversarial Networks to Simulate High Energy Physics Detectors

entry:
@InProceedings{RAos:2020:EMP,
  author =       "John Osorio R{\'\i}os and Adri{\`a} Armejach and
                 Gulrukh Khattak and Eric Petit and Sofia Vallecorsa and
                 Marc Casas",
  booktitle =    "{2020 19th IEEE International Conference on Machine
                 Learning and Applications (ICMLA)}",
  title =        "Evaluating Mixed-Precision Arithmetic for {3D}
                 Generative Adversarial Networks to Simulate High Energy
                 Physics Detectors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "49--56",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICMLA51294.2020.00017",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "3DGAN; Binary Analysis Tool; Brain Float 16 (BF16);
                 Computational modeling; Detectors; Generative
                 adversarial networks; Generative Adversarial Networks;
                 Hardware; High Energy Physics; Mixed Precision (MP);
                 Numerical models; Reduced Precision; Tools; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Raveendran:2020:NPF
author: Aneesh Raveendran and Sandra Jean and J. Mervin and D. Vivian and David Selvakumar
editor: IEEE
title: A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 207--212
month: jan
monthnumber: 1
year: 2020
DOI: https://doi.org/10.1109/vlsid49098.2020.00053
ISBN: 1-72815-701-3 OR 1728157013
ISBN13: 978-1-72815-701-6 OR 9781728157016
ISSN: 1063-9667 (print), 2380-6923 (electronic) OR 10639667 (print), 23806923 (electronic)
ISSNL: 1063-9667 OR 10639667
bibdate: Fri Dec 15 07:29:26 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:29:26 ???
acknowledgement: ack-nhfb
rawauthor: Aneesh Raveendran and Sandra Jean and J. Mervin and D. Vivian and David Selvakumar
raweditor: {IEEE}
rawtitle: A Novel Parametrized Fused Division and Square-Root {POSIT} Arithmetic Architecture
booktitle:
2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Bengaluru, India, 4--8 January 2020

rawbooktitle:
{2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Bengaluru, India, 4--8 January 2020}

entry:
@InProceedings{Raveendran:2020:NPF,
  author =       "Aneesh Raveendran and Sandra Jean and J. Mervin and D.
                 Vivian and David Selvakumar",
  editor =       "{IEEE}",
  booktitle =    "{2020 33rd International Conference on VLSI Design and
                 2020 19th International Conference on Embedded Systems
                 (VLSID), Bengaluru, India, 4--8 January 2020}",
  title =        "A Novel Parametrized Fused Division and Square-Root
                 {POSIT} Arithmetic Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "207--212",
  month =        jan,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/vlsid49098.2020.00053",
  ISBN =         "1-72815-701-3",
  ISBN-13 =      "978-1-72815-701-6",
  ISSN =         "1063-9667 (print), 2380-6923 (electronic)",
  ISSN-L =       "1063-9667",
  bibdate =      "Fri Dec 15 07:29:26 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Saadat:2020:WWC
author: Hassaan Saadat and Haris Javaid and Aleksandar Ignjatovic and Sri Parameswaran
booktitle: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
title: WEID: Worst-case Error Improvement in Approximate Dividers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 8D-1--8D-6
month: jan
monthnumber: 1
year: 2020
DOI: https://doi.org/10.1109/asp-dac47756.2020.9045504
bibdate: Wed Dec 20 08:02:22 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 08:02:22 ???
acknowledgement: ack-nhfb
rawauthor: Hassaan Saadat and Haris Javaid and Aleksandar Ignjatovic and Sri Parameswaran
rawbooktitle: {2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)}
rawtitle: {WEID}: Worst-case Error Improvement in Approximate Dividers
abstract:
Approximate integer dividers suffer from unreasonably high worst-case relative errors (such as 50% or 100%), which can adversely affect the application-level output. In this paper, we propose WEID, which is a novel lightweight method to improve the worst-case relative errors in approximate integer dividers. We first present an in-depth analysis to gain insights into the cause of the high worst-case relative error. Based on our insights, we propose a novel method to detect when an error occurs in an approximate divider, and modify the output to reduce the error. Further, we present the hardware realization of WEID method and demonstrate that it can be generically coupled with several state-of-the-art approximate dividers. Our results show that for 32-by-16 dividers, WEID reduces worst-case relative errors from 100% to $ approx 20 $ %, while still achieving $ approx 80 % $ and $ approx 70 % $ reduction in delay and energy compared to an accurate array divider.

rawabstract:
Approximate integer dividers suffer from unreasonably high worst-case relative errors (such as 50\% or 100\%), which can adversely affect the application-level output. In this paper, we propose WEID, which is a novel lightweight method to improve the worst-case relative errors in approximate integer dividers. We first present an in-depth analysis to gain insights into the cause of the high worst-case relative error. Based on our insights, we propose a novel method to detect when an error occurs in an approximate divider, and modify the output to reduce the error. Further, we present the hardware realization of WEID method and demonstrate that it can be generically coupled with several state-of-the-art approximate dividers. Our results show that for 32-by-16 dividers, WEID reduces worst-case relative errors from 100\% to $ \approx 20 $ \%, while still achieving $ \approx 80 \% $ and $ \approx 70 \% $ reduction in delay and energy compared to an accurate array divider.

entry:
@InProceedings{Saadat:2020:WWC,
  author =       "Hassaan Saadat and Haris Javaid and Aleksandar
                 Ignjatovic and Sri Parameswaran",
  booktitle =    "{2020 25th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "{WEID}: Worst-case Error Improvement in Approximate
                 Dividers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "8D-1--8D-6",
  month =        jan,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/asp-dac47756.2020.9045504",
  bibdate =      "Wed Dec 20 08:02:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Approximate integer dividers suffer from unreasonably
                 high worst-case relative errors (such as 50\% or
                 100\%), which can adversely affect the
                 application-level output. In this paper, we propose
                 WEID, which is a novel lightweight method to improve
                 the worst-case relative errors in approximate integer
                 dividers. We first present an in-depth analysis to gain
                 insights into the cause of the high worst-case relative
                 error. Based on our insights, we propose a novel method
                 to detect when an error occurs in an approximate
                 divider, and modify the output to reduce the error.
                 Further, we present the hardware realization of WEID
                 method and demonstrate that it can be generically
                 coupled with several state-of-the-art approximate
                 dividers. Our results show that for 32-by-16 dividers,
                 WEID reduces worst-case relative errors from 100\% to $
                 \approx 20 $ \%, while still achieving $ \approx 80 \%
                 $ and $ \approx 70 \% $ reduction in delay and energy
                 compared to an accurate array divider.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: SEGGER:2020:SFP
author: SEGGER Microcontroller
title: SEGGER Floating-Point Library
pages: 8D-1--8D-6
month: jan
monthnumber: 1
year: 2020
bibdate: Fri Feb 07 06:02:26 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.07 06:02:26 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: {SEGGER Microcontroller}
rawtitle: {SEGGER} Floating-Point Library
URL:
https://www.segger.com/products/development-tools/runtime-library/technology/floating-point-library/

abstract:
The floating-point library contains complete, fully optimized and verified floating point functionality, which is required for devices without an FPU. The floating-point emulator, a crucial part of the floating-point library, of the Arm and RISC-V variants are written in assembly language, optimized either for small code size or increased execution speed. For other processor architectures the library has a portable C implementation. ldots The SEGGER Floating-Point Library is delivered in source code, with optional rights for redistribution in object code form. All source files, a mix of C code and assembly, are fully commented. The floating-point emulator, providing the low-level functions, is entirely written in assembly. Higher level functions are implemented as a mix of primarily C code with some assembly routines. The code can be compiled with any ANSO-compliant C compiler, such as GCC, Clang, or IAR.

rawabstract:
The floating-point library contains complete, fully optimized and verified floating point functionality, which is required for devices without an FPU. The floating-point emulator, a crucial part of the floating-point library, of the Arm and RISC-V variants are written in assembly language, optimized either for small code size or increased execution speed. For other processor architectures the library has a portable C implementation. \ldots{} The SEGGER Floating-Point Library is delivered in source code, with optional rights for redistribution in object code form. All source files, a mix of C code and assembly, are fully commented. The floating-point emulator, providing the low-level functions, is entirely written in assembly. Higher level functions are implemented as a mix of primarily C code with some assembly routines. The code can be compiled with any ANSO-compliant C compiler, such as GCC, Clang, or IAR.

entry:
@Misc{SEGGER:2020:SFP,
  author =       "{SEGGER Microcontroller}",
  title =        "{SEGGER} Floating-Point Library",
  howpublished = "Web site.",
  month =        jan,
  year =         "2020",
  bibdate =      "Fri Feb 07 06:02:26 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.segger.com/products/development-tools/runtime-library/technology/floating-point-library/",
  abstract =     "The floating-point library contains complete, fully
                 optimized and verified floating point functionality,
                 which is required for devices without an FPU. The
                 floating-point emulator, a crucial part of the
                 floating-point library, of the Arm and RISC-V variants
                 are written in assembly language, optimized either for
                 small code size or increased execution speed. For other
                 processor architectures the library has a portable C
                 implementation. \ldots{} The SEGGER Floating-Point
                 Library is delivered in source code, with optional
                 rights for redistribution in object code form. All
                 source files, a mix of C code and assembly, are fully
                 commented. The floating-point emulator, providing the
                 low-level functions, is entirely written in assembly.
                 Higher level functions are implemented as a mix of
                 primarily C code with some assembly routines. The code
                 can be compiled with any ANSO-compliant C compiler,
                 such as GCC, Clang, or IAR.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sharma:2020:CRV
title: CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
journal: arXiv.org
pages: 1--20
day: 30
month: may
monthnumber: 5
year: 2020
DOI: https://doi.org/10.48550/arXiv.2006.00364
bibdate: Sat Dec 16 10:27:27 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 10:27:27 ???
URL: https://arxiv.org/abs/2006.00364
acknowledgement: ack-nhfb
rawtitle: {CLARINET}: A {RISC-V} Based Framework for Posit Arithmetic Empiricism
author:
Niraj Sharma and Riya Jain and Madhumita Mohan and Sachin Patkar and Rainer Leupers and Nikhil Rishiyur and Farhad Merchant

abstract:
Many engineering and scientific applications require high precision arithmetic. IEEE 754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The positTM data representation and arithmetic claim several absolute advantages over the floating-point format and arithmetic, including higher dynamic range, better accuracy, and superior performance-area trade-offs. However, there does not exist any accessible, holistic framework that facilitates the validation of these claims of posit arithmetic, especially when the claims involve long accumulations (quire).par In this paper, we present a consolidated general-purpose processor-based framework to support posit arithmetic empiricism. The end-users of the framework have the liberty to seamlessly experiment with their applications using posit and floating-point arithmetic since the framework is designed for the two number systems to coexist. Melodica is a posit arithmetic core that implements parametric fused operations that uniquely involve the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core. To show the effectiveness of the Clarinet platform, we perform an extensive application study and benchmark some of the common linear algebra and computer vision kernels. We emulate Clarinet on a Xilinx FPGA and present utilization and timing data. Clarinet and Melodica remain actively under development and are available in open-source for posit arithmetic empiricism.

rawabstract:
Many engineering and scientific applications require high precision arithmetic. IEEE 754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The posit{\TM} data representation and arithmetic claim several absolute advantages over the floating-point format and arithmetic, including higher dynamic range, better accuracy, and superior performance-area trade-offs. However, there does not exist any accessible, holistic framework that facilitates the validation of these claims of posit arithmetic, especially when the claims involve long accumulations (quire).\par In this paper, we present a consolidated general-purpose processor-based framework to support posit arithmetic empiricism. The end-users of the framework have the liberty to seamlessly experiment with their applications using posit and floating-point arithmetic since the framework is designed for the two number systems to coexist. Melodica is a posit arithmetic core that implements parametric fused operations that uniquely involve the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core. To show the effectiveness of the Clarinet platform, we perform an extensive application study and benchmark some of the common linear algebra and computer vision kernels. We emulate Clarinet on a Xilinx FPGA and present utilization and timing data. Clarinet and Melodica remain actively under development and are available in open-source for posit arithmetic empiricism.

rawauthor:
Niraj Sharma and Riya Jain and Madhumita Mohan and Sachin Patkar and Rainer Leupers and Nikhil Rishiyur and Farhad Merchant

entry:
@Article{Sharma:2020:CRV,
  author =       "Niraj Sharma and Riya Jain and Madhumita Mohan and
                 Sachin Patkar and Rainer Leupers and Nikhil Rishiyur
                 and Farhad Merchant",
  title =        "{CLARINET}: A {RISC-V} Based Framework for Posit
                 Arithmetic Empiricism",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--20",
  day =          "30",
  month =        may,
  year =         "2020",
  DOI =          "https://doi.org/10.48550/arXiv.2006.00364",
  bibdate =      "Sat Dec 16 10:27:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2006.00364",
  abstract =     "Many engineering and scientific applications require
                 high precision arithmetic. IEEE 754-2008 compliant
                 (floating-point) arithmetic is the de facto standard
                 for performing these computations. Recently, posit
                 arithmetic has been proposed as a drop-in replacement
                 for floating-point arithmetic. The posit{\TM} data
                 representation and arithmetic claim several absolute
                 advantages over the floating-point format and
                 arithmetic, including higher dynamic range, better
                 accuracy, and superior performance-area trade-offs.
                 However, there does not exist any accessible, holistic
                 framework that facilitates the validation of these
                 claims of posit arithmetic, especially when the claims
                 involve long accumulations (quire).\par

                 In this paper, we present a consolidated
                 general-purpose processor-based framework to support
                 posit arithmetic empiricism. The end-users of the
                 framework have the liberty to seamlessly experiment
                 with their applications using posit and floating-point
                 arithmetic since the framework is designed for the two
                 number systems to coexist. Melodica is a posit
                 arithmetic core that implements parametric fused
                 operations that uniquely involve the quire data type.
                 Clarinet is a Melodica-enabled processor based on the
                 RISC-V ISA. To the best of our knowledge, this is the
                 first-ever integration of quire with a RISC-V core. To
                 show the effectiveness of the Clarinet platform, we
                 perform an extensive application study and benchmark
                 some of the common linear algebra and computer vision
                 kernels. We emulate Clarinet on a Xilinx FPGA and
                 present utilization and timing data. Clarinet and
                 Melodica remain actively under development and are
                 available in open-source for posit arithmetic
                 empiricism.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Shibata:2020:SPV
author: Naoki Shibata and Francesco Petrogalli
title: SLEEF: A Portable Vectorized Library of C Standard Mathematical Functions
journal: j-IEEE-TRANS-PAR-DIST-SYS
volume: 31
number: 6
pages: 1316--1327
month: jun
monthnumber: 6
year: 2020
CODEN: ITDSEO
DOI: https://doi.org/10.1109/TPDS.2019.2960333
ISSN: 1045-9219 (print), 1558-2183 (electronic) OR 10459219 (print), 15582183 (electronic)
ISSNL: 1045-9219 OR 10459219
bibdate: Thu Feb 20 10:08:58 2020
bibtimestamp: 2020.02.20 10:08:58 ???
fjournal: IEEE Transactions on Parallel and Distributed Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71
rawauthor: Naoki Shibata and Francesco Petrogalli
rawtitle: {SLEEF}: A Portable Vectorized Library of {C} Standard Mathematical Functions
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranspardistsys.bib

keywords:
elementary functions; floating-point arithmetic; Parallel and vector implementations; SIMD processors

entry:
@Article{Shibata:2020:SPV,
  author =       "Naoki Shibata and Francesco Petrogalli",
  title =        "{SLEEF}: A Portable Vectorized Library of {C} Standard
                 Mathematical Functions",
  journal =      j-IEEE-TRANS-PAR-DIST-SYS,
  volume =       "31",
  number =       "6",
  pages =        "1316--1327",
  month =        jun,
  year =         "2020",
  CODEN =        "ITDSEO",
  DOI =          "https://doi.org/10.1109/TPDS.2019.2960333",
  ISSN =         "1045-9219 (print), 1558-2183 (electronic)",
  ISSN-L =       "1045-9219",
  bibdate =      "Thu Feb 20 10:08:58 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranspardistsys.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Parallel and Distributed
                 Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71",
  keywords =     "elementary functions; floating-point arithmetic;
                 Parallel and vector implementations; SIMD processors",
}


bibtype: misc
filename: fparith.bib
label: Shirriff:2020:AMC
author: Ken Shirriff
title: Die analysis of the 8087 math coprocessor's fast bit shifter
pages: 16
month: may
monthnumber: 5
year: 2020
bibdate: Sat Aug 23 07:23:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.08.23 07:23:18 ???
acknowledgement: ack-nhfb
howpublished: Blog post
rawauthor: Ken Shirriff
rawtitle: Die analysis of the 8087 math coprocessor's fast bit shifter
note:
Analysis of the barrel shifter at the heart of both the arithmetic operations and the CORDIC-like transcendental functions in the 8087. See patent cite Palmer:1985:PBS.

URL:
https://ieeemilestones.ethw.org/w/images/0/0c/Shirriff_8087_barrel_shifter.pdf; https://www.righto.com/2020/05/die-analysis-of-8087-math-coprocessors.html

rawnote:
Analysis of the barrel shifter at the heart of both the arithmetic operations and the CORDIC-like transcendental functions in the 8087. See patent \cite{Palmer:1985:PBS}.

entry:
@Misc{Shirriff:2020:AMC,
  author =       "Ken Shirriff",
  title =        "Die analysis of the 8087 math coprocessor's fast bit
                 shifter",
  howpublished = "Blog post",
  pages =        "16",
  month =        may,
  year =         "2020",
  bibdate =      "Sat Aug 23 07:23:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Analysis of the barrel shifter at the heart of both
                 the arithmetic operations and the CORDIC-like
                 transcendental functions in the 8087. See patent
                 \cite{Palmer:1985:PBS}.",
  URL =          "https://ieeemilestones.ethw.org/w/images/0/0c/Shirriff_8087_barrel_shifter.pdf;
                 https://www.righto.com/2020/05/die-analysis-of-8087-math-coprocessors.html",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Shirriff:2020:ERC
author: Ken Shirriff
title: Extracting ROM constants from the 8087 math coprocessor's die
pages: 16
month: may
monthnumber: 5
year: 2020
bibdate: Sat Aug 23 07:21:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.08.23 07:21:18 ???
URL: https://ieeemilestones.ethw.org/w/images/8/87/Shirriff_8087_ROM_constants.pdf
acknowledgement: ack-nhfb
howpublished: Blog posting
rawauthor: Ken Shirriff
rawtitle: Extracting {ROM} constants from the 8087 math coprocessor's die
entry:
@Misc{Shirriff:2020:ERC,
  author =       "Ken Shirriff",
  title =        "Extracting {ROM} constants from the 8087 math
                 coprocessor's die",
  howpublished = "Blog posting",
  pages =        "16",
  month =        may,
  year =         "2020",
  bibdate =      "Sat Aug 23 07:21:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeemilestones.ethw.org/w/images/8/87/Shirriff_8087_ROM_constants.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Smith:2020:HMC
author: Ernie Smith
pages: 16
day: 14
month: sep
monthnumber: 9
year: 2020
bibdate: Thu Jan 28 17:58:10 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.01.28 17:58:10 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Ernie Smith
title:
How a Minor Calculation Error Cost Intel Half a Billion Dollars: How one of the most famous computer bugs of all time, the Intel Pentium floating-point division glitch, blew out of proportion into a PR crisis

URL:
https://www.vice.com/en/article/dyzqdj/how-a-minor-calculation-error-cost-intel-half-a-billion-dollars

remark:
This is a retrospective on the infamous Pentium divide flaw of the 1990s. Near the end, it remarks about the discoverer of the bug ``[Thomas] Nicely, who died last year and was largely seen as legendary by his peers, spent roughly three decades at the University of Lynchburg before retiring in 2000.''

rawtitle:
How a Minor Calculation Error Cost {Intel} Half a Billion Dollars: How one of the most famous computer bugs of all time, the {Intel Pentium} floating-point division glitch, blew out of proportion into a {PR} crisis

entry:
@Misc{Smith:2020:HMC,
  author =       "Ernie Smith",
  title =        "How a Minor Calculation Error Cost {Intel} Half a
                 Billion Dollars: How one of the most famous computer
                 bugs of all time, the {Intel Pentium} floating-point
                 division glitch, blew out of proportion into a {PR}
                 crisis",
  howpublished = "Web site.",
  day =          "14",
  month =        sep,
  year =         "2020",
  bibdate =      "Thu Jan 28 17:58:10 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.vice.com/en/article/dyzqdj/how-a-minor-calculation-error-cost-intel-half-a-billion-dollars",
  acknowledgement = ack-nhfb,
  remark =       "This is a retrospective on the infamous Pentium divide
                 flaw of the 1990s. Near the end, it remarks about the
                 discoverer of the bug ``[Thomas] Nicely, who died last
                 year and was largely seen as legendary by his peers,
                 spent roughly three decades at the University of
                 Lynchburg before retiring in 2000.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Sommer:2020:CAN
author: Lukas Sommer and Lukas Weber and Martin Kumm and Andreas Koch
title: Comparison of Arithmetic Number Formats for Inference in Sum--Product Networks on FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 75--83
year: 2020
DOI: https://doi.org/10.1109/FCCM48280.2020.00020
bibdate: Fri Sep 22 08:07:44 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 08:07:44 ???
acknowledgement: ack-nhfb
rawauthor: Lukas Sommer and Lukas Weber and Martin Kumm and Andreas Koch
rawtitle: Comparison of Arithmetic Number Formats for Inference in Sum--Product Networks on {FPGAs}
booktitle:
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

rawbooktitle:
{2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}

entry:
@InProceedings{Sommer:2020:CAN,
  author =       "Lukas Sommer and Lukas Weber and Martin Kumm and
                 Andreas Koch",
  booktitle =    "{2020 IEEE 28th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "Comparison of Arithmetic Number Formats for Inference
                 in Sum--Product Networks on {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "75--83",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FCCM48280.2020.00020",
  bibdate =      "Fri Sep 22 08:07:44 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sousa:2020:TIR
author: L. Sousa and R. Paludo and P. Martins and H. Pettenghi
title: Towards the Integration of Reverse Converters into the RNS Channels
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 3
pages: 342--348
month: mar
monthnumber: 3
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2948335
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Mar 5 13:54:11 2020
bibtimestamp: 2020.03.05 13:54:11 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: L. Sousa and R. Paludo and P. Martins and H. Pettenghi
rawtitle: Towards the Integration of Reverse Converters into the {RNS} Channels
keywords:
Adders; arithmetic units; Computer architecture; Delays; Logic gates; modular arithmetic; Power demand; Program processors; Proposals; Residue number systems; reverse conversion

entry:
@Article{Sousa:2020:TIR,
  author =       "L. Sousa and R. Paludo and P. Martins and H.
                 Pettenghi",
  title =        "Towards the Integration of Reverse Converters into the
                 {RNS} Channels",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "3",
  pages =        "342--348",
  month =        mar,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2948335",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Mar 5 13:54:11 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; arithmetic units; Computer architecture;
                 Delays; Logic gates; modular arithmetic; Power demand;
                 Program processors; Proposals; Residue number systems;
                 reverse conversion",
}


bibtype: inproceedings
filename: fparith.bib
label: Stine:2020:AIV
author: James E. Stine and Milo D. Ercegovac and Jean-Michel Muller
editor: Michael B. Matthews
title: An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 529--533
year: 2020
DOI: https://doi.org/10.1109/IEEECONF51394.2020.9443498
ISBN: 0-7381-3126-1 OR 0738131261
ISBN13: 978-0-7381-3126-9 OR 9780738131269
bibdate: Fri Sep 29 11:01:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 11:01:45 ???
acknowledgement: ack-nhfb
rawauthor: James E. Stine and Milo D. Ercegovac and Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division
booktitle:
2020 54th Asilomar Conference on Signals, Systems, and Computers. November 1--5, 2020. Pacific Grove, California

rawbooktitle:
{2020 54th Asilomar Conference on Signals, Systems, and Computers. November 1--5, 2020. Pacific Grove, California}

entry:
@InProceedings{Stine:2020:AIV,
  author =       "James E. Stine and Milo D. Ercegovac and Jean-Michel
                 Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{2020 54th Asilomar Conference on Signals, Systems,
                 and Computers. November 1--5, 2020. Pacific Grove,
                 California}",
  title =        "An Architecture for Improving Variable Radix Real and
                 Complex Division Using Recurrence Division",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "529--533",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/IEEECONF51394.2020.9443498",
  ISBN =         "0-7381-3126-1",
  ISBN-13 =      "978-0-7381-3126-9",
  bibdate =      "Fri Sep 29 11:01:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Sun:2020:ULP
editor: H. Larochelle and M. Ranzato and R. Hadsell and M. F. Balcan and H. Lin
booktitle: Advances in Neural Information Processing Systems (NeurIPS 2020)
title: Ultra-low precision 4-bit training of deep neural networks
publisher: Curran Associates, Inc.
address: Red Hook, NY, USA
pages: 1796--1807
year: 2020
ISBN: 1-71382-954-1 OR 1713829541
ISBN13: 978-1-71382-954-6 OR 9781713829546
bibdate: Wed Aug 07 16:44:01 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.07 16:44:01 ???
acknowledgement: ack-nhfb
rawbooktitle: Advances in Neural Information Processing Systems ({NeurIPS 2020})
raweditor: H. Larochelle and M. Ranzato and R. Hadsell and M. F. Balcan and H. Lin
rawtitle: Ultra-low precision 4-bit training of deep neural networks
author:
Xiao Sun and Naigang Wang and Chia-Yu Chen and Jiamin Ni and Ankur Agrawal and Xiaodong Cui and Swagath Venkataramani and Kaoutar El Maghraoui and Vijayalakshmi (Viji) Srinivasan and Kailash Gopalakrishnan

URL:
https://proceedings.neurips.cc/paper_files/paper/2020/file/13b919438259814cd5be8cb45877d577-Paper.pdf

abstract:
In this paper, we propose a number of novel techniques and numerical representation formats that enable, for the very first time, the precision of training systems to be aggressively scaled from 8-bits to 4-bits. To enable this advance, we explore a novel adaptive Gradient Scaling technique (Gradscale) that addresses the challenges of insufficient range and resolution in quantized gradients as well as explores the impact of quantization errors observed during model training. We theoretically analyze the role of bias in gradient quantization and propose solutions that mitigate the impact of this bias on model convergence. Finally, we examine our techniques on a spectrum of deep learning models in computer vision, speech, and NLP. In combination with previously proposed solutions for 4-bit quantization of weight and activation tensors, 4-bit training shows a non-significant loss in accuracy across application domains while enabling significant hardware acceleration (> 7X over state-of-the-art FP16 systems).

rawabstract:
In this paper, we propose a number of novel techniques and numerical representation formats that enable, for the very first time, the precision of training systems to be aggressively scaled from 8-bits to 4-bits. To enable this advance, we explore a novel adaptive Gradient Scaling technique (Gradscale) that addresses the challenges of insufficient range and resolution in quantized gradients as well as explores the impact of quantization errors observed during model training. We theoretically analyze the role of bias in gradient quantization and propose solutions that mitigate the impact of this bias on model convergence. Finally, we examine our techniques on a spectrum of deep learning models in computer vision, speech, and NLP. In combination with previously proposed solutions for 4-bit quantization of weight and activation tensors, 4-bit training shows a non-significant loss in accuracy across application domains while enabling significant hardware acceleration (> 7X over state-of-the-art FP16 systems).

rawauthor:
Xiao Sun and Naigang Wang and Chia-Yu Chen and Jiamin Ni and Ankur Agrawal and Xiaodong Cui and Swagath Venkataramani and Kaoutar El Maghraoui and Vijayalakshmi (Viji) Srinivasan and Kailash Gopalakrishnan

entry:
@InProceedings{Sun:2020:ULP,
  author =       "Xiao Sun and Naigang Wang and Chia-Yu Chen and Jiamin
                 Ni and Ankur Agrawal and Xiaodong Cui and Swagath
                 Venkataramani and Kaoutar El Maghraoui and
                 Vijayalakshmi (Viji) Srinivasan and Kailash
                 Gopalakrishnan",
  editor =       "H. Larochelle and M. Ranzato and R. Hadsell and M. F.
                 Balcan and H. Lin",
  booktitle =    "Advances in Neural Information Processing Systems
                 ({NeurIPS 2020})",
  title =        "Ultra-low precision 4-bit training of deep neural
                 networks",
  publisher =    "Curran Associates, Inc.",
  address =      "Red Hook, NY, USA",
  pages =        "1796--1807",
  year =         "2020",
  ISBN =         "1-71382-954-1",
  ISBN-13 =      "978-1-71382-954-6",
  LCCN =         "????",
  bibdate =      "Wed Aug 07 16:44:01 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://proceedings.neurips.cc/paper_files/paper/2020/file/13b919438259814cd5be8cb45877d577-Paper.pdf",
  abstract =     "In this paper, we propose a number of novel techniques
                 and numerical representation formats that enable, for
                 the very first time, the precision of training systems
                 to be aggressively scaled from 8-bits to 4-bits. To
                 enable this advance, we explore a novel adaptive
                 Gradient Scaling technique (Gradscale) that addresses
                 the challenges of insufficient range and resolution in
                 quantized gradients as well as explores the impact of
                 quantization errors observed during model training. We
                 theoretically analyze the role of bias in gradient
                 quantization and propose solutions that mitigate the
                 impact of this bias on model convergence. Finally, we
                 examine our techniques on a spectrum of deep learning
                 models in computer vision, speech, and NLP. In
                 combination with previously proposed solutions for
                 4-bit quantization of weight and activation tensors,
                 4-bit training shows a non-significant loss in accuracy
                 across application domains while enabling significant
                 hardware acceleration (> 7X over state-of-the-art FP16
                 systems).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Ternovoy:2020:CAF
editor: IEEE
title: Comparative Analysis of Floating-Point Accuracy of IEEE 754 and Posit Standards
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1883--186
year: 2020
DOI: https://doi.org/10.1109/EIConRus49466.2020.9039521
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
raweditor: {IEEE}
rawtitle: Comparative Analysis of Floating-Point Accuracy of {IEEE 754} and Posit Standards
author:
E. Ternovoy and Mikhail G. Popov and Dmitrii V. Kaleev and Yurii V. Savchenko and Alexey L. Pereverzev

booktitle:
2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)

rawauthor:
E. Ternovoy and Mikhail G. Popov and Dmitrii V. Kaleev and Yurii V. Savchenko and Alexey L. Pereverzev

rawbooktitle:
{2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)}

entry:
@InProceedings{Ternovoy:2020:CAF,
  author =       "E. Ternovoy and Mikhail G. Popov and Dmitrii V. Kaleev
                 and Yurii V. Savchenko and Alexey L. Pereverzev",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Conference of Russian Young Researchers in
                 Electrical and Electronic Engineering (EIConRus)}",
  title =        "Comparative Analysis of Floating-Point Accuracy of
                 {IEEE 754} and Posit Standards",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1883--186",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/EIConRus49466.2020.9039521",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: ThoughtWorks:2020:PER
author: ThoughtWorks
title: Posit Enhanced Rocket Chip (PERC)
pages: 1883--186
year: 2020
bibdate: Sat Dec 16 15:25:19 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 15:25:19 ???
URL: https://www.thoughtworks.com/engineering-research/perc
acknowledgement: ack-nhfb
howpublished: Web software.
rawauthor: {ThoughtWorks}
rawtitle: {Posit Enhanced Rocket Chip (PERC)}
entry:
@Misc{ThoughtWorks:2020:PER,
  author =       "{ThoughtWorks}",
  title =        "{Posit Enhanced Rocket Chip (PERC)}",
  howpublished = "Web software.",
  year =         "2020",
  bibdate =      "Sat Dec 16 15:25:19 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.thoughtworks.com/engineering-research/perc",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Turley:2020:WBA
author: Jim Turley
title: What Is bfloat16, Anyway? New Floating-Point Format is Suddenly Popular for Machine Learning
pages: 1883--186
day: 23
month: mar
monthnumber: 3
year: 2020
bibdate: Fri Apr 03 09:07:54 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.04.03 09:07:54 ???
URL: https://www.eejournal.com/article/what-is-bfloat16-anyway/
acknowledgement: ack-nhfb
howpublished: Electronic Engineering journal Web site
rawauthor: Jim Turley
rawtitle: What Is bfloat16, Anyway? {New} Floating-Point Format is Suddenly Popular for Machine Learning
entry:
@Misc{Turley:2020:WBA,
  author =       "Jim Turley",
  title =        "What Is bfloat16, Anyway? {New} Floating-Point Format
                 is Suddenly Popular for Machine Learning",
  howpublished = "Electronic Engineering journal Web site",
  day =          "23",
  month =        mar,
  year =         "2020",
  bibdate =      "Fri Apr 03 09:07:54 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.eejournal.com/article/what-is-bfloat16-anyway/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Uguen:2020:ASA
author: Yohann Uguen and Florent De Dinechin and Victor Lezaud and Steven Derrien
title: Application-Specific Arithmetic in High-Level Synthesis Tools
journal: j-TACO
volume: 17
number: 1
pages: 5:1--5:23
month: mar
monthnumber: 3
year: 2020
DOI: https://doi.org/10.1145/3377403
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Tue Mar 10 08:30:23 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib
bibtimestamp: 2020.03.10 08:30:23 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3377403
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 5
journalURL: https://dl.acm.org/loi/taco
rawauthor: Yohann Uguen and Florent {De Dinechin} and Victor Lezaud and Steven Derrien
rawtitle: Application-Specific Arithmetic in High-Level Synthesis Tools
abstract:
This work studies hardware-specific optimization opportunities currently unexploited by high-level synthesis compilers. Some of these optimizations are specializations of floating-point operations that respect the usual semantics of the input program without changing the numerical result. Some other optimizations, locally triggered by the programmer thanks to a pragma, assume a different semantics, where floating-point code is interpreted as the specification of computation with real numbers. The compiler is then in charge to ensure an application-level accuracy constraint expressed in the pragma and has the freedom to use non-standard arithmetic hardware when more efficient. These two classes of optimizations are prototyped in the GeCoS source-to-source compiler and evaluated on the Polybench and EEMBC benchmark suites. Latency is reduced by up to 93%, and resource usage is reduced by up to 58%.

rawabstract:
This work studies hardware-specific optimization opportunities currently unexploited by high-level synthesis compilers. Some of these optimizations are specializations of floating-point operations that respect the usual semantics of the input program without changing the numerical result. Some other optimizations, locally triggered by the programmer thanks to a pragma, assume a different semantics, where floating-point code is interpreted as the specification of computation with real numbers. The compiler is then in charge to ensure an application-level accuracy constraint expressed in the pragma and has the freedom to use non-standard arithmetic hardware when more efficient. These two classes of optimizations are prototyped in the GeCoS source-to-source compiler and evaluated on the Polybench and EEMBC benchmark suites. Latency is reduced by up to 93\%, and resource usage is reduced by up to 58\%.

entry:
@Article{Uguen:2020:ASA,
  author =       "Yohann Uguen and Florent {De Dinechin} and Victor
                 Lezaud and Steven Derrien",
  title =        "Application-Specific Arithmetic in High-Level
                 Synthesis Tools",
  journal =      j-TACO,
  volume =       "17",
  number =       "1",
  pages =        "5:1--5:23",
  month =        mar,
  year =         "2020",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3377403",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Tue Mar 10 08:30:23 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3377403",
  abstract =     "This work studies hardware-specific optimization
                 opportunities currently unexploited by high-level
                 synthesis compilers. Some of these optimizations are
                 specializations of floating-point operations that
                 respect the usual semantics of the input program
                 without changing the numerical result. Some other
                 optimizations, locally triggered by the programmer
                 thanks to a pragma, assume a different semantics, where
                 floating-point code is interpreted as the specification
                 of computation with real numbers. The compiler is then
                 in charge to ensure an application-level accuracy
                 constraint expressed in the pragma and has the freedom
                 to use non-standard arithmetic hardware when more
                 efficient. These two classes of optimizations are
                 prototyped in the GeCoS source-to-source compiler and
                 evaluated on the Polybench and EEMBC benchmark suites.
                 Latency is reduced by up to 93\%, and resource usage is
                 reduced by up to 58\%.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}


bibtype: article
filename: fparith.bib
label: Valueva:2020:ARN
author: M. V. Valueva and N. N. Nagornov and P. A. Lyakhov and G. V. Valuev and N. I. Chervyakov
journal: j-MATH-COMPUT-SIMUL
volume: 177
pages: 232--243
month: nov
monthnumber: 11
year: 2020
CODEN: MCSIDR
DOI: https://doi.org/10.1016/j.matcom.2020.04.031
ISSN: 0378-4754 (print), 1872-7166 (electronic) OR 03784754 (print), 18727166 (electronic)
ISSNL: 0378-4754 OR 03784754
bibdate: Fri Aug 15 14:51:15 MDT 2025
bibtimestamp: 2025.08.15 14:51:15 MDT
URL: https://www.sciencedirect.com/science/article/pii/S0378475420301580
fjournal: Mathematics and Computers in Simulation
acknowledgement: ack-nhfb
ajournal: Math. Comput. Simul.
journalURL: https://www.sciencedirect.com/science/journal/03784754
rawauthor: M. V. Valueva and N. N. Nagornov and P. A. Lyakhov and G. V. Valuev and N. I. Chervyakov
title:
Application of the residue number system to reduce hardware costs of the convolutional neural network implementation

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomputsimul2020.bib

rawtitle:
Application of the residue number system to reduce hardware costs of the convolutional neural network implementation

entry:
@Article{Valueva:2020:ARN,
  author =       "M. V. Valueva and N. N. Nagornov and P. A. Lyakhov and
                 G. V. Valuev and N. I. Chervyakov",
  title =        "Application of the residue number system to reduce
                 hardware costs of the convolutional neural network
                 implementation",
  journal =      j-MATH-COMPUT-SIMUL,
  volume =       "177",
  pages =        "232--243",
  month =        nov,
  year =         "2020",
  CODEN =        "MCSIDR",
  DOI =          "https://doi.org/10.1016/j.matcom.2020.04.031",
  ISSN =         "0378-4754 (print), 1872-7166 (electronic)",
  ISSN-L =       "0378-4754",
  bibdate =      "Fri Aug 15 14:51:15 MDT 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomputsimul2020.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S0378475420301580",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput. Simul.",
  fjournal =     "Mathematics and Computers in Simulation",
  journal-URL =  "https://www.sciencedirect.com/science/journal/03784754",
}


bibtype: article
filename: fparith.bib
label: Volkova:2020:AAR
author: A. Volkova and T. Hilaire and C. Lauter
title: Arithmetic Approaches for Rigorous Design of Reliable Fixed-Point LTI Filters
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 4
pages: 489--504
month: apr
monthnumber: 4
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2950658
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Mar 12 16:58:27 2020
bibtimestamp: 2020.03.12 16:58:27 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Volkova and T. Hilaire and C. Lauter
rawtitle: Arithmetic Approaches for Rigorous Design of Reliable Fixed-Point {LTI} Filters
keywords:
digital filters; eigendecomposition; Error analysis; fixed-point arithmetic; Floating-point arithmetic; Gershgorin circles; Heuristic algorithms; interval arithmetic; Linear matrix inequalities; Linear systems; Mathematical model; multiple precision; Reliability; reliable computations; Signal processing algorithms; table maker's dilemma

entry:
@Article{Volkova:2020:AAR,
  author =       "A. Volkova and T. Hilaire and C. Lauter",
  title =        "Arithmetic Approaches for Rigorous Design of Reliable
                 Fixed-Point {LTI} Filters",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "4",
  pages =        "489--504",
  month =        apr,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2950658",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Mar 12 16:58:27 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "digital filters; eigendecomposition; Error analysis;
                 fixed-point arithmetic; Floating-point arithmetic;
                 Gershgorin circles; Heuristic algorithms; interval
                 arithmetic; Linear matrix inequalities; Linear systems;
                 Mathematical model; multiple precision; Reliability;
                 reliable computations; Signal processing algorithms;
                 table maker's dilemma",
}


bibtype: article
filename: fparith.bib
label: Wang:2020:GCB
author: Yuxuan Wang and Yuanyong Luo and Zhongfeng Wang and Qinghong Shen and Hongbing Pan
title: GH CORDIC-based Architecture for Computing $N$-th Root of Single-Precision Floating-Point Number
journal: j-IEEE-TRANS-VLSI-SYST
volume: 28
number: 4
pages: 864--875
year: 2020
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2019.2959847
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Yuxuan Wang and Yuanyong Luo and Zhongfeng Wang and Qinghong Shen and Hongbing Pan
keywords:
Binary floating point (BFP); Computer architecture; COordinate Rotation Digital Computer (CORDIC); Field programmable gate arrays; Graphics; Hardware; high speed; Mathematical model; Nth root; Standards; Very large scale integration

rawtitle:
{GH} {CORDIC}-based Architecture for Computing {$N$}-th Root of Single-Precision Floating-Point Number

entry:
@Article{Wang:2020:GCB,
  author =       "Yuxuan Wang and Yuanyong Luo and Zhongfeng Wang and
                 Qinghong Shen and Hongbing Pan",
  title =        "{GH} {CORDIC}-based Architecture for Computing
                 {$N$}-th Root of Single-Precision Floating-Point
                 Number",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "28",
  number =       "4",
  pages =        "864--875",
  year =         "2020",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2019.2959847",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  keywords =     "Binary floating point (BFP); Computer architecture;
                 COordinate Rotation Digital Computer (CORDIC); Field
                 programmable gate arrays; Graphics; Hardware; high
                 speed; Mathematical model; Nth root; Standards; Very
                 large scale integration",
}


bibtype: article
filename: fparith.bib
label: Ward-Foxton:2020:AIG
author: Sally Ward-Foxton
title: Artificial Intelligence Gets Its Own System of Numbers
journal: EE Times
pages: ??--??
day: 14
month: feb
monthnumber: 2
year: 2020
bibdate: Wed May 19 11:58:46 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.05.19 11:58:46 ???
URL: https://www.eetimes.com/artificial-intelligence-gets-its-own-system-of-numbers/
keywords: BF16 (1 + 8 + 7); FP16 (1 + 5 + 10); Nervana Flexpoint
acknowledgement: ack-nhfb
rawauthor: Sally Ward-Foxton
rawtitle: Artificial Intelligence Gets Its Own System of Numbers
entry:
@Article{Ward-Foxton:2020:AIG,
  author =       "Sally Ward-Foxton",
  title =        "Artificial Intelligence Gets Its Own System of
                 Numbers",
  journal =      "EE Times",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "14",
  month =        feb,
  year =         "2020",
  bibdate =      "Wed May 19 11:58:46 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.eetimes.com/artificial-intelligence-gets-its-own-system-of-numbers/",
  acknowledgement = ack-nhfb,
  keywords =     "BF16 (1 + 8 + 7); FP16 (1 + 5 + 10); Nervana
                 Flexpoint",
}


bibtype: article
filename: fparith.bib
label: Xiao:2020:PAH
author: Feibao Xiao and Feng Liang and Bin Wu and Junzhe Liang and Shuting Cheng and Guohe Zhang
title: Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and Square Root
journal: j-ELECTRONICS
volume: 9
number: 10
pages: 1622:1--1622:16
month: oct
monthnumber: 10
year: 2020
DOI: https://doi.org/10.3390/electronics9101622
ISSN: 2079-9292 OR 20799292
ISSNL: 2079-9292 OR 20799292
bibdate: Fri Dec 15 07:25:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:25:40 ???
fjournal: Electronics
acknowledgement: ack-nhfb
journalURL: https://www.mdpi.com/journal/electronics
rawauthor: Feibao Xiao and Feng Liang and Bin Wu and Junzhe Liang and Shuting Cheng and Guohe Zhang
rawtitle: Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and Square Root
entry:
@Article{Xiao:2020:PAH,
  author =       "Feibao Xiao and Feng Liang and Bin Wu and Junzhe Liang
                 and Shuting Cheng and Guohe Zhang",
  title =        "Posit Arithmetic Hardware Implementations with The
                 Minimum Cost Divider and Square Root",
  journal =      j-ELECTRONICS,
  volume =       "9",
  number =       "10",
  pages =        "1622:1--1622:16",
  month =        oct,
  year =         "2020",
  DOI =          "https://doi.org/10.3390/electronics9101622",
  ISSN =         "2079-9292",
  ISSN-L =       "2079-9292",
  bibdate =      "Fri Dec 15 07:25:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics",
  journal-URL =  "https://www.mdpi.com/journal/electronics",
}


bibtype: inproceedings
filename: fparith.bib
label: Yin-Di:2020:HMH
author: Zhang Yin-Di and Liu Ming and Wang Ming-Jiang
booktitle: 2020 IEEE 5th International Conference on Signal and Image Processing (ICSIP)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1040--1044
year: 2020
DOI: https://doi.org/10.1109/ICSIP49896.2020.9339409
bibdate: Mon Oct 27 10:32:44 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/cordic.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.27 10:32:44 ???
acknowledgement: ack-nhfb
rawauthor: Zhang Yin-Di and Liu Ming and Wang Ming-Jiang
rawbooktitle: {2020 IEEE 5th International Conference on Signal and Image Processing (ICSIP)}
title:
A Hardware Modeling of High Precision Floating Point Arcsine / Arccosine Function Based on CORDIC Algorithm

keywords:
arcsine/arccosine; Clocks; CORDIC; floating point; four-step rotation prediction iteration; Hardware; Hardware design languages; Image processing; Indexes; Prediction algorithms; Standards

rawtitle:
A Hardware Modeling of High Precision Floating Point Arcsine\slash Arccosine Function Based on {CORDIC} Algorithm

entry:
@InProceedings{Yin-Di:2020:HMH,
  author =       "Zhang Yin-Di and Liu Ming and Wang Ming-Jiang",
  booktitle =    "{2020 IEEE 5th International Conference on Signal and
                 Image Processing (ICSIP)}",
  title =        "A Hardware Modeling of High Precision Floating Point
                 Arcsine\slash Arccosine Function Based on {CORDIC}
                 Algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1040--1044",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICSIP49896.2020.9339409",
  bibdate =      "Mon Oct 27 10:32:44 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cordic.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "arcsine/arccosine; Clocks; CORDIC; floating point;
                 four-step rotation prediction iteration; Hardware;
                 Hardware design languages; Image processing; Indexes;
                 Prediction algorithms; Standards",
}


bibtype: article
filename: fparith.bib
label: Yun:2020:LEP
author: Juwon Yun and Jinyoung Lee and Woo-Nam Chung and Cheong Ghil Kim and Woo-Chan Park
title: A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers
journal: j-IEEE-ACCESS
volume: 8
pages: 165740--165747
year: 2020
DOI: https://doi.org/10.1109/ACCESS.2020.3022657
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Juwon Yun and Jinyoung Lee and Woo-Nam Chung and Cheong Ghil Kim and Woo-Chan Park
rawtitle: A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers
keywords:
Computer arithmetic; division; Error analysis; floating-point; Hardware; lookup table; Pipelines; Signal processing algorithms; Table lookup; Taylor series

entry:
@Article{Yun:2020:LEP,
  author =       "Juwon Yun and Jinyoung Lee and Woo-Nam Chung and
                 Cheong Ghil Kim and Woo-Chan Park",
  title =        "A Latency-Effective Pipelined Divider for
                 Double-Precision Floating-Point Numbers",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  pages =        "165740--165747",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.3022657",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Computer arithmetic; division; Error analysis;
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                 Signal processing algorithms; Table lookup; Taylor
                 series",
}


bibtype: inproceedings
filename: fparith.bib
label: Zaruba:2020:CRV
author: Florian Zaruba and Fabian Schuiki and Luca Benini
editor: IEEE
booktitle: 2020 IEEE Hot Chips 32 Symposium (HCS)
title: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--24
year: 2020
DOI: https://doi.org/10.1109/HCS49909.2020.9220474
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
remark: This article consists only of a collection of slides from the author's conference presentation
acknowledgement: ack-nhfb
rawauthor: Florian Zaruba and Fabian Schuiki and Luca Benini
rawbooktitle: {2020 IEEE Hot Chips 32 Symposium (HCS)}
raweditor: {IEEE}
rawtitle: A 4096-core {RISC-V} Chiplet Architecture for Ultra-efficient Floating-point Computing
entry:
@InProceedings{Zaruba:2020:CRV,
  author =       "Florian Zaruba and Fabian Schuiki and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Hot Chips 32 Symposium (HCS)}",
  title =        "A 4096-core {RISC-V} Chiplet Architecture for
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  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--24",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/HCS49909.2020.9220474",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
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  acknowledgement = ack-nhfb,
  remark =       "This article consists only of a collection of slides
                 from the author's conference presentation",
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bibtype: article
filename: fparith.bib
label: Zhang:2020:DPE
author: Hao Zhang and Seok-Bum Ko
title: Design of Power Efficient Posit Multiplier
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 67
number: 5
pages: 861--865
year: 2020
DOI: https://doi.org/10.1109/TCSII.2020.2980531
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Hao Zhang and Seok-Bum Ko
rawtitle: Design of Power Efficient Posit Multiplier
entry:
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  author =       "Hao Zhang and Seok-Bum Ko",
  title =        "Design of Power Efficient Posit Multiplier",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "67",
  number =       "5",
  pages =        "861--865",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/TCSII.2020.2980531",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Fri Dec 15 09:21:55 2023",
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  acknowledgement = ack-nhfb,
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bibtype: article
filename: fparith.bib
label: Zhang:2020:NAE
author: N. Zhang and Q. Qin and H. Yuan and C. Zhou and S. Yin and S. Wei and L. Liu
title: NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 4
pages: 520--533
month: apr
monthnumber: 4
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2958334
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Mar 12 16:58:27 2020
bibtimestamp: 2020.03.12 16:58:27 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: N. Zhang and Q. Qin and H. Yuan and C. Zhou and S. Yin and S. Wei and L. Liu
rawtitle: {NTTU}: An Area-Efficient Low-Power {NTT}-Uncoupled Architecture for {NTT}-Based Multiplication
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

keywords:
Clocks; Cloud computing; Complexity theory; Computer architecture; Encryption; Fully homomorphic encryption; large integer multiplication; number theoretical conversion; polynomial multiplication; Random access memory; Transforms

entry:
@Article{Zhang:2020:NAE,
  author =       "N. Zhang and Q. Qin and H. Yuan and C. Zhou and S. Yin
                 and S. Wei and L. Liu",
  title =        "{NTTU}: An Area-Efficient Low-Power {NTT}-Uncoupled
                 Architecture for {NTT}-Based Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "4",
  pages =        "520--533",
  month =        apr,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2958334",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Mar 12 16:58:27 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Clocks; Cloud computing; Complexity theory; Computer
                 architecture; Encryption; Fully homomorphic encryption;
                 large integer multiplication; number theoretical
                 conversion; polynomial multiplication; Random access
                 memory; Transforms",
}


bibtype: article
filename: fparith.bib
label: Zhang:2020:NFM
author: H. Zhang and D. Chen and S. Ko
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 1
pages: 26--38
month: jan
monthnumber: 1
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2936192
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jan 9 07:48:57 2020
bibtimestamp: 2020.01.09 07:48:57 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Zhang and D. Chen and S. Ko
title:
New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference

keywords:
Adders; computer arithmetic; Deep learning; deep neural network computing; flexible precision arithmetic; Hardware; multiple-precision arithmetic; Multiply-accumulate unit; Neural networks; Pipelines; Standards; Training

rawtitle:
New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference

entry:
@Article{Zhang:2020:NFM,
  author =       "H. Zhang and D. Chen and S. Ko",
  title =        "New Flexible Multiple-Precision Multiply-Accumulate
                 Unit for Deep Neural Network Training and Inference",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "1",
  pages =        "26--38",
  month =        jan,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2936192",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jan 9 07:48:57 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; computer arithmetic; Deep learning; deep
                 neural network computing; flexible precision
                 arithmetic; Hardware; multiple-precision arithmetic;
                 Multiply-accumulate unit; Neural networks; Pipelines;
                 Standards; Training",
}


bibtype: article
filename: fparith.bib
label: Zhang:2020:SAA
author: Longlong Zhang and Yuanxi Peng and Ahui Huang and Xiao Hu
journal: j-IEEE-ACCESS
volume: 8
pages: 92469--92478
year: 2020
DOI: https://doi.org/10.1109/ACCESS.2020.2994657
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Tue Sep 30 17:30:28 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.09.30 17:30:28 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Longlong Zhang and Yuanxi Peng and Ahui Huang and Xiao Hu
title:
A Scalable Architecture for Accelerating Multi-Operation and Continuous Floating-Point Matrix Computing on FPGAs

keywords:
Acceleration; accelerator; Arrays; Data transfer; Field programmable gate arrays; floating-point; FPGAs; Matrix computing; Registers; scalability

rawtitle:
A Scalable Architecture for Accelerating Multi-Operation and Continuous Floating-Point Matrix Computing on {FPGAs}

entry:
@Article{Zhang:2020:SAA,
  author =       "Longlong Zhang and Yuanxi Peng and Ahui Huang and Xiao
                 Hu",
  title =        "A Scalable Architecture for Accelerating
                 Multi-Operation and Continuous Floating-Point Matrix
                 Computing on {FPGAs}",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  pages =        "92469--92478",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.2994657",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Tue Sep 30 17:30:28 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
  keywords =     "Acceleration; accelerator; Arrays; Data transfer;
                 Field programmable gate arrays; floating-point; FPGAs;
                 Matrix computing; Registers; scalability",
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2020:AMFa
author: Paul Zimmermann
title: Accuracy of Mathematical Functions in Single Precision
pages: 2
day: 3
month: feb
monthnumber: 2
year: 2020
bibdate: Mon Aug 17 15:41:19 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.08.17 15:41:19 ???
URL: https://members.loria.fr/PZimmermann/papers/accuracy.pdf
remark: Tabular comparison of GNU and Intel -lm libraries for correct rounding, versus results from MPFR.
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
rawtitle: Accuracy of Mathematical Functions in Single Precision
note:
Previous versions dated 4 February 2020, 10 May 2020, 26 May 2020, 7 August 2020, 25 August 2020, 28 August 2020, 15 September 2020, 17 September 2020.

rawnote:
Previous versions dated 4 February 2020, 10 May 2020, 26 May 2020, 7 August 2020, 25 August 2020, 28 August 2020, 15 September 2020, 17 September 2020.

entry:
@TechReport{Zimmermann:2020:AMFa,
  author =       "Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single
                 Precision",
  institution =  "????",
  pages =        "2",
  day =          "3",
  month =        feb,
  year =         "2020",
  bibdate =      "Mon Aug 17 15:41:19 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Previous versions dated 4 February 2020, 10 May 2020,
                 26 May 2020, 7 August 2020, 25 August 2020, 28 August
                 2020, 15 September 2020, 17 September 2020.",
  URL =          "https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of GNU and Intel -lm libraries for
                 correct rounding, versus results from MPFR.",
}


bibtype: techreport
filename: fparith.bib
label: Zimmermann:2020:AMFb
author: Paul Zimmermann
title: Accuracy of Mathematical Functions in Single, Double, and Quadruple Precision
pages: 14
day: 4
month: dec
monthnumber: 12
year: 2020
bibdate: Fri Dec 04 11:52:43 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.12.04 11:52:43 ???
note: Revised February 4, May 10, May 26 and August 7 [2020].
URL: https://members.loria.fr/PZimmermann/papers/accuracy.pdf
acknowledgement: ack-nhfb
rawauthor: Paul Zimmermann
rawnote: Revised February 4, May 10, May 26 and August 7 [2020].
rawtitle: Accuracy of Mathematical Functions in Single, Double, and Quadruple Precision
remark:
Tabular comparison of AMD, GNU, Intel, RedHat, OpenLibm, and Musl -lm libraries for correct rounding, versus results from MPFR.

entry:
@TechReport{Zimmermann:2020:AMFb,
  author =       "Paul Zimmermann",
  title =        "Accuracy of Mathematical Functions in Single, Double,
                 and Quadruple Precision",
  institution =  "????",
  pages =        "14",
  day =          "4",
  month =        dec,
  year =         "2020",
  bibdate =      "Fri Dec 04 11:52:43 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Revised February 4, May 10, May 26 and August 7
                 [2020].",
  URL =          "https://members.loria.fr/PZimmermann/papers/accuracy.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Tabular comparison of AMD, GNU, Intel, RedHat,
                 OpenLibm, and Musl -lm libraries for correct rounding,
                 versus results from MPFR.",
}


bibtype: article
filename: fparith.bib
label: Zou:2020:DFP
author: Daming Zou and Muhan Zeng and Yingfei Xiong and Zhoulai Fu and Lu Zhang and Zhendong Su
title: Detecting floating-point errors via atomic conditions
journal: j-PACMPL
volume: 4
number: POPL
pages: 60:1--60:27
month: jan
monthnumber: 1
year: 2020
DOI: https://doi.org/10.1145/3371128
ISSN: 2475-1421 OR 24751421
bibdate: Fri Aug 7 18:46:52 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2020.08.07 18:46:52 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3371128
fjournal: Proceedings of the ACM on Programming Languages
acknowledgement: ack-nhfb
articleno: 60
journalURL: https://pacmpl.acm.org/
rawauthor: Daming Zou and Muhan Zeng and Yingfei Xiong and Zhoulai Fu and Lu Zhang and Zhendong Su
rawtitle: Detecting floating-point errors via atomic conditions
abstract:
This paper tackles the important, difficult problem of detecting program inputs that trigger large floating-point errors in numerical code. It introduces a novel, principled em dynamic analysis that leverages the mathematically rigorously analyzed em condition numbers for atomic numerical operations, which we call em atomic conditions, to effectively guide the search for large floating-point errors. Compared with existing approaches, our work based on atomic conditions has several distinctive benefits: (1) it does not rely on high-precision implementations to act as approximate oracles, which are difficult to obtain in general and computationally costly; and (2) atomic conditions provide accurate, modular search guidance. These benefits in combination lead to a highly effective approach that detects more significant errors in real-world code (e.g., widely-used numerical library functions) and achieves several orders of speedups over the state-of-the-art, thus making error analysis significantly more practical. We expect the methodology and principles behind our approach to benefit other floating-point program analysis tasks such as debugging, repair and synthesis. To facilitate the reproduction of our work, we have made our implementation, evaluation data and results publicly available on GitHub at url https://github.com/FP-Analysis/atomic-condition

rawabstract:
This paper tackles the important, difficult problem of detecting program inputs that trigger large floating-point errors in numerical code. It introduces a novel, principled {\em dynamic analysis\/} that leverages the mathematically rigorously analyzed {\em condition numbers\/} for atomic numerical operations, which we call {\em atomic conditions}, to effectively guide the search for large floating-point errors. Compared with existing approaches, our work based on atomic conditions has several distinctive benefits: (1) it does not rely on high-precision implementations to act as approximate oracles, which are difficult to obtain in general and computationally costly; and (2) atomic conditions provide accurate, modular search guidance. These benefits in combination lead to a highly effective approach that detects more significant errors in real-world code (e.g., widely-used numerical library functions) and achieves several orders of speedups over the state-of-the-art, thus making error analysis significantly more practical. We expect the methodology and principles behind our approach to benefit other floating-point program analysis tasks such as debugging, repair and synthesis. To facilitate the reproduction of our work, we have made our implementation, evaluation data and results publicly available on GitHub at \url{https://github.com/FP-Analysis/atomic-condition}

entry:
@Article{Zou:2020:DFP,
  author =       "Daming Zou and Muhan Zeng and Yingfei Xiong and
                 Zhoulai Fu and Lu Zhang and Zhendong Su",
  title =        "Detecting floating-point errors via atomic
                 conditions",
  journal =      j-PACMPL,
  volume =       "4",
  number =       "POPL",
  pages =        "60:1--60:27",
  month =        jan,
  year =         "2020",
  DOI =          "https://doi.org/10.1145/3371128",
  ISSN =         "2475-1421",
  bibdate =      "Fri Aug 7 18:46:52 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3371128",
  abstract =     "This paper tackles the important, difficult problem of
                 detecting program inputs that trigger large
                 floating-point errors in numerical code. It introduces
                 a novel, principled {\em dynamic analysis\/} that
                 leverages the mathematically rigorously analyzed {\em
                 condition numbers\/} for atomic numerical operations,
                 which we call {\em atomic conditions}, to effectively
                 guide the search for large floating-point errors.
                 Compared with existing approaches, our work based on
                 atomic conditions has several distinctive benefits: (1)
                 it does not rely on high-precision implementations to
                 act as approximate oracles, which are difficult to
                 obtain in general and computationally costly; and (2)
                 atomic conditions provide accurate, modular search
                 guidance. These benefits in combination lead to a
                 highly effective approach that detects more significant
                 errors in real-world code (e.g., widely-used numerical
                 library functions) and achieves several orders of
                 speedups over the state-of-the-art, thus making error
                 analysis significantly more practical. We expect the
                 methodology and principles behind our approach to
                 benefit other floating-point program analysis tasks
                 such as debugging, repair and synthesis. To facilitate
                 the reproduction of our work, we have made our
                 implementation, evaluation data and results publicly
                 available on GitHub at
                 \url{https://github.com/FP-Analysis/atomic-condition}",
  acknowledgement = ack-nhfb,
  articleno =    "60",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Agrawal:2021:CAC
booktitle: 2021 IEEE International Solid-State Circuits Conference (ISSCC)
volume: 64
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 144--146
year: 2021
DOI: https://doi.org/10.1109/ISSCC42613.2021.9365791
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2021 IEEE International Solid-State Circuits Conference (ISSCC)}
author:
Ankur Agrawal and Sae Kyu Lee and Joel Silberman and Matthew Ziegler and Mingu Kang and Swagath Venkataramani and Nianzheng Cao and Bruce Fleischer and Michael Guillorn and Matthew Cohen and Silvia Mueller and Jinwook Oh and Martin Lutz and Jinwook Jung and Siyu Koswatta and Ching Zhou and Vidhi Zalani and James Bonanno and Robert Casatuta and Chia-Yu Chen and Jungwook Choi and Howard Haynie and Alyssa Herbert and Radhika Jain and Monodeep Kar and Kyu-Hyoun Kim and Yulong Li and Zhibin Ren and Scot Rider and Marcel Schaal and Kerstin Schelm and Michael Scheuermann and Xiao Sun and Hung Tran and Naigang Wang and Wei Wang and Xin Zhang and Vinay Shah and Brian Curran and Vijayalakshmi Srinivasan and Pong-Fei Lu and Sunil Shukla and Leland Chang and Kailash Gopalakrishnan

title:
9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

keywords:
AI accelerators; Inference algorithms; Integrated circuit modeling; Optimization; Power system management; Solid state circuits; Training

rawauthor:
Ankur Agrawal and Sae Kyu Lee and Joel Silberman and Matthew Ziegler and Mingu Kang and Swagath Venkataramani and Nianzheng Cao and Bruce Fleischer and Michael Guillorn and Matthew Cohen and Silvia Mueller and Jinwook Oh and Martin Lutz and Jinwook Jung and Siyu Koswatta and Ching Zhou and Vidhi Zalani and James Bonanno and Robert Casatuta and Chia-Yu Chen and Jungwook Choi and Howard Haynie and Alyssa Herbert and Radhika Jain and Monodeep Kar and Kyu-Hyoun Kim and Yulong Li and Zhibin Ren and Scot Rider and Marcel Schaal and Kerstin Schelm and Michael Scheuermann and Xiao Sun and Hung Tran and Naigang Wang and Wei Wang and Xin Zhang and Vinay Shah and Brian Curran and Vijayalakshmi Srinivasan and Pong-Fei Lu and Sunil Shukla and Leland Chang and Kailash Gopalakrishnan

rawtitle:
9.1 A 7nm 4-Core {AI} Chip with {25.6TFLOPS} Hybrid {FP8} Training, {102.4TOPS} {INT4} Inference and Workload-Aware Throttling

entry:
@InProceedings{Agrawal:2021:CAC,
  author =       "Ankur Agrawal and Sae Kyu Lee and Joel Silberman and
                 Matthew Ziegler and Mingu Kang and Swagath
                 Venkataramani and Nianzheng Cao and Bruce Fleischer and
                 Michael Guillorn and Matthew Cohen and Silvia Mueller
                 and Jinwook Oh and Martin Lutz and Jinwook Jung and
                 Siyu Koswatta and Ching Zhou and Vidhi Zalani and James
                 Bonanno and Robert Casatuta and Chia-Yu Chen and
                 Jungwook Choi and Howard Haynie and Alyssa Herbert and
                 Radhika Jain and Monodeep Kar and Kyu-Hyoun Kim and
                 Yulong Li and Zhibin Ren and Scot Rider and Marcel
                 Schaal and Kerstin Schelm and Michael Scheuermann and
                 Xiao Sun and Hung Tran and Naigang Wang and Wei Wang
                 and Xin Zhang and Vinay Shah and Brian Curran and
                 Vijayalakshmi Srinivasan and Pong-Fei Lu and Sunil
                 Shukla and Leland Chang and Kailash Gopalakrishnan",
  booktitle =    "{2021 IEEE International Solid-State Circuits
                 Conference (ISSCC)}",
  title =        "9.1 A 7nm 4-Core {AI} Chip with {25.6TFLOPS} Hybrid
                 {FP8} Training, {102.4TOPS} {INT4} Inference and
                 Workload-Aware Throttling",
  volume =       "64",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "144--146",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISSCC42613.2021.9365791",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AI accelerators; Inference algorithms; Integrated
                 circuit modeling; Optimization; Power system
                 management; Solid state circuits; Training",
}


bibtype: article
filename: fparith.bib
label: Ahn:2021:KSK
title: Keeping science on keel when software moves
journal: j-CACM
volume: 64
number: 2
pages: 66--74
month: feb
monthnumber: 2
year: 2021
CODEN: CACMA2
DOI: https://doi.org/10.1145/3382037
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Tue Jan 26 14:34:25 MST 2021
bibtimestamp: 2021.01.26 14:34:25 MST
URL: https://dl.acm.org/doi/10.1145/3382037
abstract: An approach to reproducibility problems related to porting software across machines and compilers.
fjournal: Communications of the ACM
acknowledgement: ack-nhfb
ajournal: Commun. ACM
journalURL: https://dl.acm.org/loi/cacm
rawabstract: An approach to reproducibility problems related to porting software across machines and compilers.
rawtitle: Keeping science on keel when software moves
author:
Dong H. Ahn and Allison H. Baker and Michael Bentley and Ian Briggs and Ganesh Gopalakrishnan and Dorit M. Hammerling and Ignacio Laguna and Gregory L. Lee and Daniel J. Milroy and Mariana Vertenstein

bibsource:
https://www.math.utah.edu/pub/tex/bib/cacm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawauthor:
Dong H. Ahn and Allison H. Baker and Michael Bentley and Ian Briggs and Ganesh Gopalakrishnan and Dorit M. Hammerling and Ignacio Laguna and Gregory L. Lee and Daniel J. Milroy and Mariana Vertenstein

entry:
@Article{Ahn:2021:KSK,
  author =       "Dong H. Ahn and Allison H. Baker and Michael Bentley
                 and Ian Briggs and Ganesh Gopalakrishnan and Dorit M.
                 Hammerling and Ignacio Laguna and Gregory L. Lee and
                 Daniel J. Milroy and Mariana Vertenstein",
  title =        "Keeping science on keel when software moves",
  journal =      j-CACM,
  volume =       "64",
  number =       "2",
  pages =        "66--74",
  month =        feb,
  year =         "2021",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/3382037",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Tue Jan 26 14:34:25 MST 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cacm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3382037",
  abstract =     "An approach to reproducibility problems related to
                 porting software across machines and compilers.",
  acknowledgement = ack-nhfb,
  ajournal =     "Commun. ACM",
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
}


bibtype: inproceedings
filename: fparith.bib
label: Alouani:2021:IIR
author: Ihsen Alouani and Anouar Ben Khalifa and Farhad Merchant and Rainer Leupers
editor: IEEE
title: An Investigation on Inherent Robustness of Posit Data Representation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 276--281
year: 2021
DOI: https://doi.org/10.1109/VLSID51830.2021.00052
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Ihsen Alouani and Anouar {Ben Khalifa} and Farhad Merchant and Rainer Leupers
raweditor: {IEEE}
rawtitle: An Investigation on Inherent Robustness of Posit Data Representation
booktitle:
2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)

rawbooktitle:
{2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)}

entry:
@InProceedings{Alouani:2021:IIR,
  author =       "Ihsen Alouani and Anouar {Ben Khalifa} and Farhad
                 Merchant and Rainer Leupers",
  editor =       "{IEEE}",
  booktitle =    "{2021 34th International Conference on VLSI Design and
                 2021 20th International Conference on Embedded Systems
                 (VLSID)}",
  title =        "An Investigation on Inherent Robustness of Posit Data
                 Representation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "276--281",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/VLSID51830.2021.00052",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Andrysco:2021:SFP
title: On Subnormal Floating Point and Abnormal Timing
type: Report
institution: Department of Computer Science and Engineering University of California, San Diego
address: La Jolla, California, USA
pages: 17
day: 2
month: jan
monthnumber: 1
year: 2021
bibdate: Fri Sep 06 10:04:19 2024
bibtimestamp: 2024.09.06 10:04:19 ???
acknowledgement: ack-nhfb
rawtitle: On Subnormal Floating Point and Abnormal Timing
author:
Marc Andrysco and David Kohlbrenner and Keaton Mowery and Ranjit Jhala and Sorin Lerner and Hovav Shacham

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We identify a timing channel in the floating point instructions of modern x86 processors: the running time of floating point addition and multiplication instructions can vary by two orders of magnitude depending on their operands. We develop a benchmark measuring the timing variability of floating point operations and report on its results. We use floating point data timing variability to demonstrate practical attacks on the security of the Firefox browser (versions 23 through 27) and the Fuzz differentially private database. Finally, we initiate the study of mitigations to floating point data timing channels with libfixedtimefixedpoint, a new fixed-point, constant-time math library.par Modern floating point standards and implementations are sophisticated, complex, and subtle, a fact that has not been sufficiently recognized by the security community. More work is needed to assess the implications of the use of floating point instructions in security-relevant software.

rawabstract:
We identify a timing channel in the floating point instructions of modern x86 processors: the running time of floating point addition and multiplication instructions can vary by two orders of magnitude depending on their operands. We develop a benchmark measuring the timing variability of floating point operations and report on its results. We use floating point data timing variability to demonstrate practical attacks on the security of the Firefox browser (versions 23 through 27) and the Fuzz differentially private database. Finally, we initiate the study of mitigations to floating point data timing channels with libfixedtimefixedpoint, a new fixed-point, constant-time math library.\par Modern floating point standards and implementations are sophisticated, complex, and subtle, a fact that has not been sufficiently recognized by the security community. More work is needed to assess the implications of the use of floating point instructions in security-relevant software.

entry:
@TechReport{Andrysco:2021:SFP,
  author =       "Marc Andrysco and David Kohlbrenner and Keaton Mowery
                 and Ranjit Jhala and Sorin Lerner and Hovav Shacham",
  title =        "On Subnormal Floating Point and Abnormal Timing",
  type =         "Report",
  institution =  "Department of Computer Science and Engineering
                 University of California, San Diego",
  address =      "La Jolla, California, USA",
  pages =        "17",
  day =          "2",
  month =        jan,
  year =         "2021",
  bibdate =      "Fri Sep 06 10:04:19 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We identify a timing channel in the floating point
                 instructions of modern x86 processors: the running time
                 of floating point addition and multiplication
                 instructions can vary by two orders of magnitude
                 depending on their operands. We develop a benchmark
                 measuring the timing variability of floating point
                 operations and report on its results. We use floating
                 point data timing variability to demonstrate practical
                 attacks on the security of the Firefox browser
                 (versions 23 through 27) and the Fuzz differentially
                 private database. Finally, we initiate the study of
                 mitigations to floating point data timing channels with
                 libfixedtimefixedpoint, a new fixed-point,
                 constant-time math library.\par

                 Modern floating point standards and implementations are
                 sophisticated, complex, and subtle, a fact that has not
                 been sufficiently recognized by the security community.
                 More work is needed to assess the implications of the
                 use of floating point instructions in security-relevant
                 software.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:AI
author: Anonymous
title: Author Index
crossref: IEEE:2021:ISC
pages: 141--141
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00037
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Author Index
entry:
@InProceedings{Anonymous:2021:AI,
  author =       "Anonymous",
  title =        "Author Index",
  crossref =     "IEEE:2021:ISC",
  pages =        "141--141",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00037",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:CN
author: Anonymous
title: [Copyright notice]
crossref: IEEE:2021:ISC
pages: 1--1
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00003
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: [{Copyright} notice]
entry:
@InProceedings{Anonymous:2021:CN,
  author =       "Anonymous",
  title =        "[{Copyright} notice]",
  crossref =     "IEEE:2021:ISC",
  pages =        "1--1",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00003",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:FC
author: Anonymous
title: [Front cover]
crossref: IEEE:2021:ISC
pages: 1--1
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00002
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: [{Front} cover]
entry:
@InProceedings{Anonymous:2021:FC,
  author =       "Anonymous",
  title =        "[{Front} cover]",
  crossref =     "IEEE:2021:ISC",
  pages =        "1--1",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00002",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:IPA
author: Anonymous
title: Industry Panel ARITH 2021: Processors for the Computing of the 2020s
crossref: IEEE:2021:ISC
pages: xv--xv
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00010
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Industry Panel {ARITH 2021}: Processors for the Computing of the 2020s
entry:
@InProceedings{Anonymous:2021:IPA,
  author =       "Anonymous",
  title =        "Industry Panel {ARITH 2021}: Processors for the
                 Computing of the 2020s",
  crossref =     "IEEE:2021:ISC",
  pages =        "xv--xv",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00010",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:PCA
author: Anonymous
title: Program Committee ARITH 2021
crossref: IEEE:2021:ISC
pages: xii--xii
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00007
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Program Committee {ARITH 2021}
entry:
@InProceedings{Anonymous:2021:PCA,
  author =       "Anonymous",
  title =        "Program Committee {ARITH 2021}",
  crossref =     "IEEE:2021:ISC",
  pages =        "xii--xii",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00007",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:SA
author: Anonymous
title: Sponsors ARITH 2021
crossref: IEEE:2021:ISC
pages: xviii--xviii
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00012
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Sponsors {ARITH 2021}
entry:
@InProceedings{Anonymous:2021:SA,
  author =       "Anonymous",
  title =        "Sponsors {ARITH 2021}",
  crossref =     "IEEE:2021:ISC",
  pages =        "xviii--xviii",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00012",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:SCA
author: Anonymous
title: Steering Committee ARITH 2021
crossref: IEEE:2021:ISC
pages: xiii--xiii
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00008
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Steering Committee {ARITH 2021}
entry:
@InProceedings{Anonymous:2021:SCA,
  author =       "Anonymous",
  title =        "Steering Committee {ARITH 2021}",
  crossref =     "IEEE:2021:ISC",
  pages =        "xiii--xiii",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00008",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:TC
author: Anonymous
title: Table of Contents
crossref: IEEE:2021:ISC
pages: v--viii
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00004
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Table of Contents
entry:
@InProceedings{Anonymous:2021:TC,
  author =       "Anonymous",
  title =        "Table of Contents",
  crossref =     "IEEE:2021:ISC",
  pages =        "v--viii",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00004",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2021:TP
author: Anonymous
title: [Title page]
crossref: IEEE:2021:ISC
pages: 1--1
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00001
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: [{Title} page]
entry:
@InProceedings{Anonymous:2021:TP,
  author =       "Anonymous",
  title =        "[{Title} page]",
  crossref =     "IEEE:2021:ISC",
  pages =        "1--1",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00001",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Ashmawy:2021:FHI
author: Doaa Ashmawy and Arash Reyhani-Masoleh
title: A Faster Hardware Implementation of the AES S-box
crossref: IEEE:2021:ISC
pages: 123--130
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00034
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Doaa Ashmawy and Arash Reyhani-Masoleh
rawtitle: A Faster Hardware Implementation of the {AES} {S}-box
entry:
@InProceedings{Ashmawy:2021:FHI,
  author =       "Doaa Ashmawy and Arash Reyhani-Masoleh",
  title =        "A Faster Hardware Implementation of the {AES}
                 {S}-box",
  crossref =     "IEEE:2021:ISC",
  pages =        "123--130",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00034",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Bagnara:2021:PAV
author: Roberto Bagnara and Michele Chiari and Roberta Gori and Abramo Bagnara
journal: j-TOSEM
volume: 30
number: 1
pages: 9:1--9:53
month: jan
monthnumber: 1
year: 2021
CODEN: ATSMER
DOI: https://doi.org/10.1145/3410875
ISSN: 1049-331X (print), 1557-7392 (electronic) OR 1049331X (print), 15577392 (electronic)
ISSNL: 1049-331X OR 1049331X
bibdate: Fri Jan 22 07:02:14 MST 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tosem.bib
bibtimestamp: 2021.01.22 07:02:14 MST
URL: https://dl.acm.org/doi/10.1145/3410875
fjournal: ACM Transactions on Software Engineering and Methodology
acknowledgement: ack-nhfb
articleno: 9
journalURL: https://dl.acm.org/loi/tosem
rawauthor: Roberto Bagnara and Michele Chiari and Roberta Gori and Abramo Bagnara
title:
A Practical Approach to Verification of Floating-Point C / C++ Programs with tt math.h / tt cmath Functions

abstract:
Verification of C/C++ programs has seen considerable progress in several areas, but not for programs that use these languages' mathematical libraries. The reason is that all libraries in widespread use come with no guarantees about the computed results. This would seem to prevent any attempt at formal verification of programs that use them: without a specification for the functions, no conclusion can be drawn statically about the behavior of the program. We propose an alternative to surrender. We introduce a pragmatic approach that leverages the fact that most tt math.h / tt cmath functions are almost piecewise monotonic: as we discovered through exhaustive testing, they may have glitches, often of very small size and in small numbers. We develop interval refinement techniques for such functions based on a modified dichotomic search, which enable verification via symbolic execution based model checking, abstract interpretation, and test data generation. To the best of our knowledge, our refinement algorithms are the first in the literature to be able to handle non-correctly rounded function implementations, enabling verification in the presence of the most common implementations. We experimentally evaluate our approach on real-world code, showing its ability to detect or rule out anomalous behaviors.

rawabstract:
Verification of C/C++ programs has seen considerable progress in several areas, but not for programs that use these languages' mathematical libraries. The reason is that all libraries in widespread use come with no guarantees about the computed results. This would seem to prevent any attempt at formal verification of programs that use them: without a specification for the functions, no conclusion can be drawn statically about the behavior of the program. We propose an alternative to surrender. We introduce a pragmatic approach that leverages the fact that most {\tt math.h}\slash {\tt cmath} functions are almost piecewise monotonic: as we discovered through exhaustive testing, they may have glitches, often of very small size and in small numbers. We develop interval refinement techniques for such functions based on a modified dichotomic search, which enable verification via symbolic execution based model checking, abstract interpretation, and test data generation. To the best of our knowledge, our refinement algorithms are the first in the literature to be able to handle non-correctly rounded function implementations, enabling verification in the presence of the most common implementations. We experimentally evaluate our approach on real-world code, showing its ability to detect or rule out anomalous behaviors.

rawtitle:
A Practical Approach to Verification of Floating-Point {C\slash C++} Programs with {\tt math.h}\slash {\tt cmath} Functions

entry:
@Article{Bagnara:2021:PAV,
  author =       "Roberto Bagnara and Michele Chiari and Roberta Gori
                 and Abramo Bagnara",
  title =        "A Practical Approach to Verification of Floating-Point
                 {C\slash C++} Programs with {\tt math.h}\slash {\tt
                 cmath} Functions",
  journal =      j-TOSEM,
  volume =       "30",
  number =       "1",
  pages =        "9:1--9:53",
  month =        jan,
  year =         "2021",
  CODEN =        "ATSMER",
  DOI =          "https://doi.org/10.1145/3410875",
  ISSN =         "1049-331X (print), 1557-7392 (electronic)",
  ISSN-L =       "1049-331X",
  bibdate =      "Fri Jan 22 07:02:14 MST 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tosem.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3410875",
  abstract =     "Verification of C/C++ programs has seen considerable
                 progress in several areas, but not for programs that
                 use these languages' mathematical libraries. The reason
                 is that all libraries in widespread use come with no
                 guarantees about the computed results. This would seem
                 to prevent any attempt at formal verification of
                 programs that use them: without a specification for the
                 functions, no conclusion can be drawn statically about
                 the behavior of the program. We propose an alternative
                 to surrender. We introduce a pragmatic approach that
                 leverages the fact that most {\tt math.h}\slash {\tt
                 cmath} functions are almost piecewise monotonic: as we
                 discovered through exhaustive testing, they may have
                 glitches, often of very small size and in small
                 numbers. We develop interval refinement techniques for
                 such functions based on a modified dichotomic search,
                 which enable verification via symbolic execution based
                 model checking, abstract interpretation, and test data
                 generation. To the best of our knowledge, our
                 refinement algorithms are the first in the literature
                 to be able to handle non-correctly rounded function
                 implementations, enabling verification in the presence
                 of the most common implementations. We experimentally
                 evaluate our approach on real-world code, showing its
                 ability to detect or rule out anomalous behaviors.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Transactions on Software Engineering and
                 Methodology",
  journal-URL =  "https://dl.acm.org/loi/tosem",
}


bibtype: misc
filename: fparith.bib
label: Bailey:2021:PMN
author: David H. Bailey
title: pkg MPFUN2020: A new thread-safe arbitrary precision package
pages: 54
day: 18
month: may
monthnumber: 5
year: 2021
bibdate: Mon Dec 05 07:32:16 2022
bibtimestamp: 2022.12.05 07:32:16 ???
URL: https://www.davidhbailey.com/dhbpapers/mpfun2020.pdf
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: David H. Bailey
rawtitle: \pkg{MPFUN2020}: A new thread-safe arbitrary precision package
abstract:
Numerous research studies have arisen, particularly in mathematical physics and experimental mathematics, that require extremely high numeric precision. Such precision greatly magnifies computer run times, so software packages to support high-precision computing must be designed for thread-based parallel processing. This paper describes a new arbitrary precision software package (``MPFUN2020'') that features several significant improvements over an earlier package. It comes in two versions: a self-contained all-Fortran version, and a version based on the MPFR package, which is even faster. Both versions feature: (a) a completely thread-safe design, so user codes can be converted for parallel execution at the application level; (b) a full-featured high-level Fortran interface, so that most applications can be converted to multiprecision with relatively minor changes to source code; (c) full support for both real and complex datatypes; (d) a wide variety of transcendental functions and special functions; (e) run-time checking and other facilities to overcome problems with converting double precision constants and data; (f) a medium precision datatype, which improves performance and reduces memory cost on large variable precision applications; and (g) interoperability --- with a simple restriction, application codes written for one version can be run with the other without change.

rawabstract:
Numerous research studies have arisen, particularly in mathematical physics and experimental mathematics, that require extremely high numeric precision. Such precision greatly magnifies computer run times, so software packages to support high-precision computing must be designed for thread-based parallel processing. This paper describes a new arbitrary precision software package (``MPFUN2020'') that features several significant improvements over an earlier package. It comes in two versions: a self-contained all-Fortran version, and a version based on the MPFR package, which is even faster. Both versions feature: (a) a completely thread-safe design, so user codes can be converted for parallel execution at the application level; (b) a full-featured high-level Fortran interface, so that most applications can be converted to multiprecision with relatively minor changes to source code; (c) full support for both real and complex datatypes; (d) a wide variety of transcendental functions and special functions; (e) run-time checking and other facilities to overcome problems with converting double precision constants and data; (f) a medium precision datatype, which improves performance and reduces memory cost on large variable precision applications; and (g) interoperability --- with a simple restriction, application codes written for one version can be run with the other without change.

entry:
@Misc{Bailey:2021:PMN,
  author =       "David H. Bailey",
  title =        "\pkg{MPFUN2020}: A new thread-safe arbitrary precision
                 package",
  howpublished = "Web document",
  pages =        "54",
  day =          "18",
  month =        may,
  year =         "2021",
  bibdate =      "Mon Dec 05 07:32:16 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.davidhbailey.com/dhbpapers/mpfun2020.pdf",
  abstract =     "Numerous research studies have arisen, particularly in
                 mathematical physics and experimental mathematics, that
                 require extremely high numeric precision. Such
                 precision greatly magnifies computer run times, so
                 software packages to support high-precision computing
                 must be designed for thread-based parallel
                 processing.

                 This paper describes a new arbitrary precision software
                 package (``MPFUN2020'') that features several
                 significant improvements over an earlier package. It
                 comes in two versions: a self-contained all-Fortran
                 version, and a version based on the MPFR package, which
                 is even faster. Both versions feature: (a) a completely
                 thread-safe design, so user codes can be converted for
                 parallel execution at the application level; (b) a
                 full-featured high-level Fortran interface, so that
                 most applications can be converted to multiprecision
                 with relatively minor changes to source code; (c) full
                 support for both real and complex datatypes; (d) a wide
                 variety of transcendental functions and special
                 functions; (e) run-time checking and other facilities
                 to overcome problems with converting double precision
                 constants and data; (f) a medium precision datatype,
                 which improves performance and reduces memory cost on
                 large variable precision applications; and (g)
                 interoperability --- with a simple restriction,
                 application codes written for one version can be run
                 with the other without change.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2021:GRN
title: Generating Residue Number System Bases
crossref: IEEE:2021:ISC
pages: 86--93
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00027
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawtitle: Generating Residue Number System Bases
author:
Jean-Claude Bajard and Kazuhide Fukushima and Shinsaku Kiyomoto and Thomas Plantard and Arnaud Sipasseuth and Willy Susilo

rawauthor:
Jean-Claude Bajard and Kazuhide Fukushima and Shinsaku Kiyomoto and Thomas Plantard and Arnaud Sipasseuth and Willy Susilo

entry:
@InProceedings{Bajard:2021:GRN,
  author =       "Jean-Claude Bajard and Kazuhide Fukushima and Shinsaku
                 Kiyomoto and Thomas Plantard and Arnaud Sipasseuth and
                 Willy Susilo",
  title =        "Generating Residue Number System Bases",
  crossref =     "IEEE:2021:ISC",
  pages =        "86--93",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00027",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Bertaccini:2021:TFL
editor: IEEE
booktitle: 2021 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2021
DOI: https://doi.org/10.1109/ISCAS51556.2021.9401149
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawbooktitle: {2021 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: {IEEE}
rawtitle: {Tiny-FPU}: Low-Cost Floating-Point Support for Small {RISC-V MCU} Cores
author:
Luca Bertaccini and Matteo Perotti and Stefan Mach and Pasquale Davide Schiavone and Florian Zaruba and Luca Benini

rawauthor:
Luca Bertaccini and Matteo Perotti and Stefan Mach and Pasquale Davide Schiavone and Florian Zaruba and Luca Benini

entry:
@InProceedings{Bertaccini:2021:TFL,
  author =       "Luca Bertaccini and Matteo Perotti and Stefan Mach and
                 Pasquale Davide Schiavone and Florian Zaruba and Luca
                 Benini",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{Tiny-FPU}: Low-Cost Floating-Point Support for Small
                 {RISC-V MCU} Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISCAS51556.2021.9401149",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bigou:2021:ERA
author: Karim Bigou and Mojtaba Bisheh Niasar and Luis Fiolhais and Rogerio Paludo and Hwajeong Seo
title: External Reviewers ARITH 2021
crossref: IEEE:2021:ISC
pages: xiv--xiv
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00009
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Karim Bigou and Mojtaba Bisheh Niasar and Lu{\'\i}s Fiolhais and Rogerio Paludo and Hwajeong Seo
rawtitle: External Reviewers {ARITH 2021}
entry:
@InProceedings{Bigou:2021:ERA,
  author =       "Karim Bigou and Mojtaba Bisheh Niasar and Lu{\'\i}s
                 Fiolhais and Rogerio Paludo and Hwajeong Seo",
  title =        "External Reviewers {ARITH 2021}",
  crossref =     "IEEE:2021:ISC",
  pages =        "xiv--xiv",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00009",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Bisheh-Niasar:2021:HSN
author: Mojtaba Bisheh-Niasar and Reza Azarderakhsh and Mehran Mozaffari-Kermani
title: High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography
crossref: IEEE:2021:ISC
pages: 94--101
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00028
bibdate: Thu Sep 21 10:36:08 2023
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Mojtaba Bisheh-Niasar and Reza Azarderakhsh and Mehran Mozaffari-Kermani
rawtitle: High-Speed {NTT}-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@InProceedings{Bisheh-Niasar:2021:HSN,
  author =       "Mojtaba Bisheh-Niasar and Reza Azarderakhsh and Mehran
                 Mozaffari-Kermani",
  title =        "High-Speed {NTT}-based Polynomial Multiplication
                 Accelerator for Post-Quantum Cryptography",
  crossref =     "IEEE:2021:ISC",
  pages =        "94--101",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00028",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Boldo:2021:ERN
author: Sylvie Boldo and Christoph Quirin Lauter and Jean-Michel Muller
journal: j-IEEE-TRANS-COMPUT
volume: 70
number: 7
pages: 1046--1058
month: jul
monthnumber: 7
year: 2021
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2020.3002702
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jun 10 15:51:57 2021
bibtimestamp: 2021.06.10 15:51:57 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sylvie Boldo and Christoph Quirin Lauter and Jean-Michel Muller
title:
Emulating Round-to-Nearest-Ties-to-Zero ``augmented'' Floating-Point Operations Using Round-to-Nearest-Ties-to-Even Arithmetic

rawtitle:
Emulating Round-to-Nearest-Ties-to-Zero ``augmented'' Floating-Point Operations Using Round-to-Nearest-Ties-to-Even Arithmetic

entry:
@Article{Boldo:2021:ERN,
  author =       "Sylvie Boldo and Christoph Quirin Lauter and
                 Jean-Michel Muller",
  title =        "Emulating Round-to-Nearest-Ties-to-Zero ``augmented''
                 Floating-Point Operations Using
                 Round-to-Nearest-Ties-to-Even Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "70",
  number =       "7",
  pages =        "1046--1058",
  month =        jul,
  year =         "2021",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2020.3002702",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jun 10 15:51:57 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2021:SFT
author: Sylvie Boldo and Guillaume Melquiond
title: Some Formal Tools for Computer Arithmetic: Flocq and Gappa
crossref: IEEE:2021:ISC
pages: 111--114
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00031
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Guillaume Melquiond
rawtitle: Some Formal Tools for Computer Arithmetic: {Flocq} and {Gappa}
entry:
@InProceedings{Boldo:2021:SFT,
  author =       "Sylvie Boldo and Guillaume Melquiond",
  title =        "Some Formal Tools for Computer Arithmetic: {Flocq} and
                 {Gappa}",
  crossref =     "IEEE:2021:ISC",
  pages =        "111--114",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00031",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Borges:2021:AIA
author: Carlos F. Borges
title: Algorithm 1014: an Improved Algorithm for tt hypot(x,y)
journal: j-TOMS
volume: 47
number: 1
pages: 9:1--9:12
month: jan
monthnumber: 1
year: 2021
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3428446
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Thu Jan 7 10:31:04 MST 2021
bibtimestamp: 2021.01.07 10:31:04 MST
URL: https://dl.acm.org/doi/10.1145/3428446
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 9
journalURL: https://dl.acm.org/loi/toms
rawauthor: Carlos F. Borges
rawtitle: {Algorithm 1014}: an Improved Algorithm for {\tt hypot(x,y)}
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/julia.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We develop fast and accurate algorithms for evaluating $ sqrt x^2 + y^2 $ for two floating-point numbers $x$ and $y$. Library functions that perform this computation are generally named tt hypot(x,y). We compare five approaches that we will develop in this article to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will investigate the accuracy of our algorithms by simulation.

rawabstract:
We develop fast and accurate algorithms for evaluating $ \sqrt {x^2 + y^2} $ for two floating-point numbers $x$ and $y$. Library functions that perform this computation are generally named {\tt hypot(x,y)}. We compare five approaches that we will develop in this article to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will investigate the accuracy of our algorithms by simulation.

entry:
@Article{Borges:2021:AIA,
  author =       "Carlos F. Borges",
  title =        "{Algorithm 1014}: an Improved Algorithm for {\tt
                 hypot(x,y)}",
  journal =      j-TOMS,
  volume =       "47",
  number =       "1",
  pages =        "9:1--9:12",
  month =        jan,
  year =         "2021",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3428446",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Thu Jan 7 10:31:04 MST 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/julia.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3428446",
  abstract =     "We develop fast and accurate algorithms for evaluating
                 $ \sqrt {x^2 + y^2} $ for two floating-point numbers
                 $x$ and $y$. Library functions that perform this
                 computation are generally named {\tt hypot(x,y)}. We
                 compare five approaches that we will develop in this
                 article to the current resident library function that
                 is delivered with Julia 1.1 and to the code that has
                 been distributed with the C math library for decades.
                 We will investigate the accuracy of our algorithms by
                 simulation.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Borges:2021:CRN
author: Carlos F. Borges
title: A Correctly Rounded Newton Step for the Reciprocal Square Root
journal: arXiv.org
pages: 1--8
day: 28
month: dec
monthnumber: 12
year: 2021
bibdate: Fri Sep 22 16:08:53 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:08:53 ???
URL: https://arxiv.org/abs/2112.14321
acknowledgement: ack-nhfb
rawauthor: Carlos F. Borges
rawtitle: A Correctly Rounded {Newton} Step for the Reciprocal Square Root
abstract:
The reciprocal square root is an important computation for which many sophisticated algorithms exist (see for example cite Moroz,863046,863031 and the references therein). A common theme is the use of Newton's method to refine the estimates. In this paper we develop a correctly rounded Newton step that can be used to improve the accuracy of a naive calculation (using methods similar to those developed in cite borges) The approach relies on the use of the fused multiply-add (FMA) which is widely available in hardware on a variety of modern computer architectures. We then introduce the notion of em weak rounding and prove that our proposed algorithm meets this standard. We then show how to leverage the exact Newton step to get a Halley's method compensation which requires one additional FMA and one additional multiplication. This method appears to give correctly rounded results experimentally and we show that it can be combined with a square root free method for estimating the reciprocal square root to get a method that is both very fast (in computing environments with a slow square root) and, experimentally, highly accurate.

rawabstract:
The reciprocal square root is an important computation for which many sophisticated algorithms exist (see for example \cite{Moroz,863046,863031} and the references therein). A common theme is the use of Newton's method to refine the estimates. In this paper we develop a correctly rounded Newton step that can be used to improve the accuracy of a naive calculation (using methods similar to those developed in \cite{borges}) The approach relies on the use of the fused multiply-add (FMA) which is widely available in hardware on a variety of modern computer architectures. We then introduce the notion of {\em weak rounding} and prove that our proposed algorithm meets this standard. We then show how to leverage the exact Newton step to get a Halley's method compensation which requires one additional FMA and one additional multiplication. This method appears to give correctly rounded results experimentally and we show that it can be combined with a square root free method for estimating the reciprocal square root to get a method that is both very fast (in computing environments with a slow square root) and, experimentally, highly accurate.

entry:
@Article{Borges:2021:CRN,
  author =       "Carlos F. Borges",
  title =        "A Correctly Rounded {Newton} Step for the Reciprocal
                 Square Root",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--8",
  day =          "28",
  month =        dec,
  year =         "2021",
  bibdate =      "Fri Sep 22 16:08:53 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/2112.14321",
  abstract =     "The reciprocal square root is an important computation
                 for which many sophisticated algorithms exist (see for
                 example \cite{Moroz,863046,863031} and the references
                 therein). A common theme is the use of Newton's method
                 to refine the estimates. In this paper we develop a
                 correctly rounded Newton step that can be used to
                 improve the accuracy of a naive calculation (using
                 methods similar to those developed in \cite{borges})
                 The approach relies on the use of the fused
                 multiply-add (FMA) which is widely available in
                 hardware on a variety of modern computer architectures.
                 We then introduce the notion of {\em weak rounding} and
                 prove that our proposed algorithm meets this standard.
                 We then show how to leverage the exact Newton step to
                 get a Halley's method compensation which requires one
                 additional FMA and one additional multiplication. This
                 method appears to give correctly rounded results
                 experimentally and we show that it can be combined with
                 a square root free method for estimating the reciprocal
                 square root to get a method that is both very fast (in
                 computing environments with a slow square root) and,
                 experimentally, highly accurate.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Borges:2021:FCA
author: Carlos F. Borges
journal: arXiv.org
pages: 1--11
day: 23
month: feb
monthnumber: 2
year: 2021
bibdate: Fri Sep 22 16:05:47 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:05:47 ???
URL: https://arxiv.org/abs/2103.08694
acknowledgement: ack-nhfb
rawauthor: Carlos F. Borges
title:
Fast compensated algorithms for the reciprocal square root, the reciprocal hypotenuse, and Givens rotations

abstract:
The reciprocal square root is an important computation for which many very sophisticated algorithms exist (see for example cite 863046,863031 and the references therein). In this paper we develop a simple differential compensation (much like those developed in cite borges) that can be used to improve the accuracy of a naive calculation. The approach relies on the use of the fused multiply-add (FMA) which is widely available in hardware on a variety of modern computer architectures. We then demonstrate how to combine this approach with a somewhat inaccurate but fast square root free method for estimating the reciprocal square root to get a method that is both fast (in computing environments with a slow square root) and, experimentally, highly accurate. Finally, we show how this same approach can be extended to the reciprocal hypotenuse calculation and, most importantly, to the construction of Givens rotations.

rawabstract:
The reciprocal square root is an important computation for which many very sophisticated algorithms exist (see for example \cite{863046,863031} and the references therein). In this paper we develop a simple differential compensation (much like those developed in \cite{borges}) that can be used to improve the accuracy of a naive calculation. The approach relies on the use of the fused multiply-add (FMA) which is widely available in hardware on a variety of modern computer architectures. We then demonstrate how to combine this approach with a somewhat inaccurate but fast square root free method for estimating the reciprocal square root to get a method that is both fast (in computing environments with a slow square root) and, experimentally, highly accurate. Finally, we show how this same approach can be extended to the reciprocal hypotenuse calculation and, most importantly, to the construction of Givens rotations.

rawtitle:
Fast compensated algorithms for the reciprocal square root, the reciprocal hypotenuse, and {Givens} rotations

entry:
@Article{Borges:2021:FCA,
  author =       "Carlos F. Borges",
  title =        "Fast compensated algorithms for the reciprocal square
                 root, the reciprocal hypotenuse, and {Givens}
                 rotations",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--11",
  day =          "23",
  month =        feb,
  year =         "2021",
  bibdate =      "Fri Sep 22 16:05:47 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/2103.08694",
  abstract =     "The reciprocal square root is an important computation
                 for which many very sophisticated algorithms exist (see
                 for example \cite{863046,863031} and the references
                 therein). In this paper we develop a simple
                 differential compensation (much like those developed in
                 \cite{borges}) that can be used to improve the accuracy
                 of a naive calculation. The approach relies on the use
                 of the fused multiply-add (FMA) which is widely
                 available in hardware on a variety of modern computer
                 architectures. We then demonstrate how to combine this
                 approach with a somewhat inaccurate but fast square
                 root free method for estimating the reciprocal square
                 root to get a method that is both fast (in computing
                 environments with a slow square root) and,
                 experimentally, highly accurate. Finally, we show how
                 this same approach can be extended to the reciprocal
                 hypotenuse calculation and, most importantly, to the
                 construction of Givens rotations.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bos:2021:MPM
author: Joppe W. Bos and Kristin E. Lauter
title: In Memoriam: Peter L. Montgomery (1947--2020)
journal: j-NAMS
volume: 68
number: 4
pages: 538--545
month: apr
monthnumber: 4
year: 2021
CODEN: AMNOAN
DOI: https://doi.org/10.1090/noti2258
ISSN: 0002-9920 (print), 1088-9477 (electronic) OR 00029920 (print), 10889477 (electronic)
ISSNL: 0002-9920 OR 00029920
MRclass: 01A70 (11-03 11Yxx 94A60)
MRnumber: 4228130
bibdate: Sat May 29 18:37:36 2021
bibtimestamp: 2021.05.29 18:37:36 ???
fjournal: Notices of the American Mathematical Society
acknowledgement: ack-nhfb
ajournal: Notices Amer. Math. Soc.
journalURL: http://www.ams.org/notices/
rawauthor: Joppe W. Bos and Kristin E. Lauter
rawtitle: In Memoriam: {Peter L. Montgomery} (1947--2020)
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/nams2020.bib

entry:
@Article{Bos:2021:MPM,
  author =       "Joppe W. Bos and Kristin E. Lauter",
  title =        "In Memoriam: {Peter L. Montgomery} (1947--2020)",
  journal =      j-NAMS,
  volume =       "68",
  number =       "4",
  pages =        "538--545",
  month =        apr,
  year =         "2021",
  CODEN =        "AMNOAN",
  DOI =          "https://doi.org/10.1090/noti2258",
  ISSN =         "0002-9920 (print), 1088-9477 (electronic)",
  ISSN-L =       "0002-9920",
  MRclass =      "01A70 (11-03 11Yxx 94A60)",
  MRnumber =     "4228130",
  bibdate =      "Sat May 29 18:37:36 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/nams2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Notices Amer. Math. Soc.",
  fjournal =     "Notices of the American Mathematical Society",
  journal-URL =  "http://www.ams.org/notices/",
}


bibtype: inproceedings
filename: fparith.bib
label: Bottcher:2021:ROT
author: Andreas Bottcher and Martin Kumm and Florent de Dinechin
title: Resource Optimal Truncated Multipliers for FPGAs
crossref: IEEE:2021:ISC
pages: 102--109
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00029
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Andreas B{\"o}ttcher and Martin Kumm and Florent de Dinechin
rawtitle: Resource Optimal Truncated Multipliers for {FPGAs}
entry:
@InProceedings{Bottcher:2021:ROT,
  author =       "Andreas B{\"o}ttcher and Martin Kumm and Florent de
                 Dinechin",
  title =        "Resource Optimal Truncated Multipliers for {FPGAs}",
  crossref =     "IEEE:2021:ISC",
  pages =        "102--109",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00029",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Brun:2021:SEBa
title: A Study of the Effects and Benefits of Custom-Precision Mathematical Libraries for HPC Codes
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 9
number: 3
pages: 1467--1478
month: jul
monthnumber: 7
year: 2021
DOI: https://doi.org/10.1109/TETC.2021.3070422
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
note: See cite Brun:2021:SEBb.
fjournal: IEEE Transactions on Emerging Topics in Computing
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawnote: See \cite{Brun:2021:SEBb}.
rawtitle: A Study of the Effects and Benefits of Custom-Precision Mathematical Libraries for {HPC} Codes
author:
Emeric Brun and David Defour and Pablo de Oliveira Castro and Matei Istoan and Davide Mancusi and Eric Petit and Alan Vaquet

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib

rawauthor:
Emeric Brun and David Defour and Pablo {de Oliveira Castro} and Matei I{\c{s}}toan and Davide Mancusi and Eric Petit and Alan Vaquet

entry:
@Article{Brun:2021:SEBa,
  author =       "Emeric Brun and David Defour and Pablo {de Oliveira
                 Castro} and Matei I{\c{s}}toan and Davide Mancusi and
                 Eric Petit and Alan Vaquet",
  title =        "A Study of the Effects and Benefits of
                 Custom-Precision Mathematical Libraries for {HPC}
                 Codes",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "9",
  number =       "3",
  pages =        "1467--1478",
  month =        jul # "\slash " # sep,
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TETC.2021.3070422",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  note =         "See \cite{Brun:2021:SEBb}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Brun:2021:SEBb
title: A Study of the Effects and Benefits of Custom-Precision Mathematical Libraries for HPC Codes
crossref: IEEE:2021:ISC
pages: 62--62
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00022
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
note: See cite Brun:2021:SEBa.
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawnote: See \cite{Brun:2021:SEBa}.
rawtitle: A Study of the Effects and Benefits of Custom-Precision Mathematical Libraries for {HPC} Codes
author:
Emeric Brun and David Defour and Pablo De Oliveira Castro and Matei Istoan and Davide Mancusi and Eric Petit and Alan Vaquet

remark:
Published in IEEE Transactions on Emerging Topics in Computing, Volume: 9, Issue: 3, July--September 2021, and orally presented at ARITH 2021.

rawauthor:
Emeric Brun and David Defour and Pablo {De Oliveira Castro} and Matei Istoan and Davide Mancusi and Eric Petit and Alan Vaquet

entry:
@InProceedings{Brun:2021:SEBb,
  author =       "Emeric Brun and David Defour and Pablo {De Oliveira
                 Castro} and Matei Istoan and Davide Mancusi and Eric
                 Petit and Alan Vaquet",
  title =        "A Study of the Effects and Benefits of
                 Custom-Precision Mathematical Libraries for {HPC}
                 Codes",
  crossref =     "IEEE:2021:ISC",
  pages =        "62--62",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00022",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Brun:2021:SEBa}.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
  remark =       "Published in IEEE Transactions on Emerging Topics in
                 Computing, Volume: 9, Issue: 3, July--September 2021,
                 and orally presented at ARITH 2021.",
}


bibtype: inproceedings
filename: fparith.bib
label: Brunie:2021:MAE
author: Nicolas Brunie
title: Manifest for an Approximation Exchange Format
crossref: IEEE:2021:ISC
pages: 63--68
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00023
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Nicolas Brunie
rawtitle: Manifest for an Approximation Exchange Format
abstract:
We introduce AXF, Approximation eXchange Format, a file format dedicated to the description of basic constructs for function approximation, such as numerical description of piecewise polynomial approximations. AXF is designed as a numerical intermediate representation between approximation generation and approximation implementation tools.

rawabstract:
We introduce AXF, Approximation eXchange Format, a file format dedicated to the description of basic constructs for function approximation, such as numerical description of piecewise polynomial approximations. AXF is designed as a numerical intermediate representation between approximation generation and approximation implementation tools.

entry:
@InProceedings{Brunie:2021:MAE,
  author =       "Nicolas Brunie",
  title =        "Manifest for an Approximation Exchange Format",
  crossref =     "IEEE:2021:ISC",
  pages =        "63--68",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00023",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We introduce AXF, Approximation eXchange Format, a
                 file format dedicated to the description of basic
                 constructs for function approximation, such as
                 numerical description of piecewise polynomial
                 approximations. AXF is designed as a numerical
                 intermediate representation between approximation
                 generation and approximation implementation tools.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2021:QIL
author: Lin Chen and Kang He and Hao Jiang and Roberto Barrio and Jie Liu and Tiejun Li
title: Quantization improvements for $ L U $ Decomposition to Solve Linear Equations
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1075--1082
year: 2021
DOI: https://doi.org/10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00149
bibdate: Wed Oct 1 06:40:18 2025
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2025.10.01 06:40:18 ???
acknowledgement: ack-nhfb
rawauthor: Lin Chen and Kang He and Hao Jiang and Roberto Barrio and Jie Liu and Tiejun Li
rawtitle: Quantization improvements for {$ L U $} Decomposition to Solve Linear Equations
booktitle:
2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom)

keywords:
Benchmark testing; Deep learning; GMRES-IR; Gold; LU Factorization; Matrix Multiplication; Mixed-precision; Quantization; Quantization (signal)

rawbooktitle:
{2021 IEEE Intl Conf on Parallel \& Distributed Processing with Applications, Big Data \& Cloud Computing, Sustainable Computing \& Communications, Social Computing \& Networking (ISPA/BDCloud/SocialCom/SustainCom)}

entry:
@InProceedings{Chen:2021:QIL,
  author =       "Lin Chen and Kang He and Hao Jiang and Roberto Barrio
                 and Jie Liu and Tiejun Li",
  booktitle =    "{2021 IEEE Intl Conf on Parallel \& Distributed
                 Processing with Applications, Big Data \& Cloud
                 Computing, Sustainable Computing \& Communications,
                 Social Computing \& Networking
                 (ISPA/BDCloud/SocialCom/SustainCom)}",
  title =        "Quantization improvements for {$ L U $} Decomposition
                 to Solve Linear Equations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1075--1082",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00149",
  bibdate =      "Wed Oct 1 06:40:18 2025",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Benchmark testing; Deep learning; GMRES-IR; Gold; LU
                 Factorization; Matrix Multiplication; Mixed-precision;
                 Quantization; Quantization (signal)",
}


bibtype: article
filename: fparith.bib
label: Ciocirlan:2021:AEPa
title: The Accuracy and Efficiency of Posit Arithmetic
journal: arXiv.org
pages: 1075--1082
day: 16
month: sep
monthnumber: 9
year: 2021
bibdate: Sat Dec 16 15:13:00 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:13:00 ???
acknowledgement: ack-nhfb
rawtitle: The Accuracy and Efficiency of Posit Arithmetic
author:
Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya Ramapantulu and Nicolae Tapus and Yong Meng Teo

abstract:
Motivated by the increasing interest in the posit numeric format, in this paper we evaluate the accuracy and efficiency of posit arithmetic in contrast to the traditional IEEE 754 32-bit floating-point (FP32) arithmetic. We first design and implement a Posit Arithmetic Unit (PAU), called POSAR, with flexible bit-sized arithmetic suitable for applications that can trade accuracy for savings in chip area. Next, we analyze the accuracy and efficiency of POSAR with a series of benchmarks including mathematical computations, ML kernels, NAS Parallel Benchmarks (NPB), and Cifar-10 CNN. This analysis is done on our implementation of POSAR integrated into a RISC-V Rocket Chip core in comparison with the IEEE 754-based Floating Point Unit (FPU) of Rocket Chip. Our analysis shows that POSAR can outperform the FPU, but the results are not spectacular. For NPB, 32-bit posit achieves better accuracy than FP32 and improves the execution by up to 2%. However, POSAR with 32-bit posit needs 30% more FPGA resources compared to the FPU. For classic ML algorithms, we find that 8-bit posits are not suitable to replace FP32 because they exhibit low accuracy leading to wrong results. Instead, 16-bit posit offers the best option in terms of accuracy and efficiency. For example, 16-bit posit achieves the same Top-1 accuracy as FP32 on a Cifar-10 CNN with a speedup of 18%.

rawabstract:
Motivated by the increasing interest in the posit numeric format, in this paper we evaluate the accuracy and efficiency of posit arithmetic in contrast to the traditional IEEE 754 32-bit floating-point (FP32) arithmetic. We first design and implement a Posit Arithmetic Unit (PAU), called POSAR, with flexible bit-sized arithmetic suitable for applications that can trade accuracy for savings in chip area. Next, we analyze the accuracy and efficiency of POSAR with a series of benchmarks including mathematical computations, ML kernels, NAS Parallel Benchmarks (NPB), and Cifar-10 CNN. This analysis is done on our implementation of POSAR integrated into a RISC-V Rocket Chip core in comparison with the IEEE 754-based Floating Point Unit (FPU) of Rocket Chip. Our analysis shows that POSAR can outperform the FPU, but the results are not spectacular. For NPB, 32-bit posit achieves better accuracy than FP32 and improves the execution by up to 2\%. However, POSAR with 32-bit posit needs 30\% more FPGA resources compared to the FPU. For classic ML algorithms, we find that 8-bit posits are not suitable to replace FP32 because they exhibit low accuracy leading to wrong results. Instead, 16-bit posit offers the best option in terms of accuracy and efficiency. For example, 16-bit posit achieves the same Top-1 accuracy as FP32 on a Cifar-10 CNN with a speedup of 18\%.

rawauthor:
Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya Ramapantulu and Nicolae Tapus and Yong Meng Teo

entry:
@Article{Ciocirlan:2021:AEPa,
  author =       "Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya
                 Ramapantulu and Nicolae Tapus and Yong Meng Teo",
  title =        "The Accuracy and Efficiency of Posit Arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  day =          "16",
  month =        sep,
  year =         "2021",
  bibdate =      "Sat Dec 16 15:13:00 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Motivated by the increasing interest in the posit
                 numeric format, in this paper we evaluate the accuracy
                 and efficiency of posit arithmetic in contrast to the
                 traditional IEEE 754 32-bit floating-point (FP32)
                 arithmetic. We first design and implement a Posit
                 Arithmetic Unit (PAU), called POSAR, with flexible
                 bit-sized arithmetic suitable for applications that can
                 trade accuracy for savings in chip area. Next, we
                 analyze the accuracy and efficiency of POSAR with a
                 series of benchmarks including mathematical
                 computations, ML kernels, NAS Parallel Benchmarks
                 (NPB), and Cifar-10 CNN. This analysis is done on our
                 implementation of POSAR integrated into a RISC-V Rocket
                 Chip core in comparison with the IEEE 754-based
                 Floating Point Unit (FPU) of Rocket Chip. Our analysis
                 shows that POSAR can outperform the FPU, but the
                 results are not spectacular. For NPB, 32-bit posit
                 achieves better accuracy than FP32 and improves the
                 execution by up to 2\%. However, POSAR with 32-bit
                 posit needs 30\% more FPGA resources compared to the
                 FPU. For classic ML algorithms, we find that 8-bit
                 posits are not suitable to replace FP32 because they
                 exhibit low accuracy leading to wrong results. Instead,
                 16-bit posit offers the best option in terms of
                 accuracy and efficiency. For example, 16-bit posit
                 achieves the same Top-1 accuracy as FP32 on a Cifar-10
                 CNN with a speedup of 18\%.",
  acknowledgement = ack-nhfb,
  archiveprefix = "arXiv",
  eprint =       "2109.08225",
  primaryclass = "cs.AR",
}


bibtype: inproceedings
filename: fparith.bib
label: Ciocirlan:2021:AEPb
editor: IEEE
booktitle: 2021 IEEE 39th International Conference on Computer Design (ICCD)
title: The Accuracy and Efficiency of Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 83--87
year: 2021
DOI: https://doi.org/10.1109/ICCD53106.2021.00024
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2021 IEEE 39th International Conference on Computer Design (ICCD)}
raweditor: {IEEE}
rawtitle: The Accuracy and Efficiency of Posit Arithmetic
author:
Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya Ramapantulu and Nicolae Tapus and Yong Meng Teo

keywords:
accuracy; Benchmark testing; Computational efficiency; Conferences; efficiency; floating-point; IEEE 754; Kernel; Machine learning; posit arithmetic; Resource management; RISC-V; Rockets

rawauthor:
Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya Ramapantulu and Nicolae {\c{T}}{\u{a}}pu{\c{s}} and Yong Meng Teo

entry:
@InProceedings{Ciocirlan:2021:AEPb,
  author =       "Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya
                 Ramapantulu and Nicolae {\c{T}}{\u{a}}pu{\c{s}} and
                 Yong Meng Teo",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 39th International Conference on Computer
                 Design (ICCD)}",
  title =        "The Accuracy and Efficiency of Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "83--87",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCD53106.2021.00024",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accuracy; Benchmark testing; Computational efficiency;
                 Conferences; efficiency; floating-point; IEEE 754;
                 Kernel; Machine learning; posit arithmetic; Resource
                 management; RISC-V; Rockets",
}


bibtype: article
filename: fparith.bib
label: Cococcioni:2021:VPO
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
journal: Neural Computing and Applications
volume: 33
number: 16
pages: 10575--10585
month: feb
monthnumber: 2
year: 2021
DOI: https://doi.org/10.1007/s00521-021-05814-0
ISSN: 1433-3058 OR 14333058
ISSNL: 0941-0643 OR 09410643
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
title:
Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

rawtitle:
Vectorizing posit operations on {RISC-V} for faster deep neural networks: experiments and comparison with {ARM SVE}

entry:
@Article{Cococcioni:2021:VPO,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  title =        "Vectorizing posit operations on {RISC-V} for faster
                 deep neural networks: experiments and comparison with
                 {ARM SVE}",
  journal =      "Neural Computing and Applications",
  volume =       "33",
  number =       "16",
  pages =        "10575--10585",
  month =        feb,
  year =         "2021",
  DOI =          "https://doi.org/10.1007/s00521-021-05814-0",
  ISSN =         "1433-3058",
  ISSN-L =       "0941-0643",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Coladon:2021:MFR
author: Titouan Coladon and Philippe Elbaz-Vincent and Cyril Hugounenq
crossref: IEEE:2021:ISC
pages: 78--85
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00026
bibdate: Thu Sep 21 10:36:08 2023
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Titouan Coladon and Philippe Elbaz-Vincent and Cyril Hugounenq
title:
MPHELL: a fast and robust library with unified and versatile arithmetics for elliptic curves cryptography

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
{MPHELL}: a fast and robust library with unified and versatile arithmetics for elliptic curves cryptography

entry:
@InProceedings{Coladon:2021:MFR,
  author =       "Titouan Coladon and Philippe Elbaz-Vincent and Cyril
                 Hugounenq",
  title =        "{MPHELL}: a fast and robust library with unified and
                 versatile arithmetics for elliptic curves
                 cryptography",
  crossref =     "IEEE:2021:ISC",
  pages =        "78--85",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00026",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Connolly:2021:SRP
author: Michael P. Connolly and Nicholas J. Higham and Theo Mary
title: Stochastic Rounding and Its Probabilistic Backward Error Analysis
journal: j-SIAM-J-SCI-COMP
volume: 43
number: 1
pages: A566--A585
year: 2021
CODEN: SJOCE3
DOI: https://doi.org/10.1137/20M1334796
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Fri Mar 12 11:40:06 MST 2021
bibtimestamp: 2021.03.12 11:40:06 MST
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2021
rawauthor: Michael P. Connolly and Nicholas J. Higham and Theo Mary
rawtitle: Stochastic Rounding and Its Probabilistic Backward Error Analysis
bibsource:
http://epubs.siam.org/toc/sjoce3/43/1; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{Connolly:2021:SRP,
  author =       "Michael P. Connolly and Nicholas J. Higham and Theo
                 Mary",
  title =        "Stochastic Rounding and Its Probabilistic Backward
                 Error Analysis",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "43",
  number =       "1",
  pages =        "A566--A585",
  month =        "????",
  year =         "2021",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/20M1334796",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Fri Mar 12 11:40:06 MST 2021",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/43/1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  onlinedate =   "January 2021",
}


bibtype: article
filename: fparith.bib
label: Czachor:2021:NNM
author: Marek Czachor
journal: j-FOUND-SCI
volume: 26
number: 1
pages: 75--95
month: mar
monthnumber: 3
year: 2021
CODEN: FOSCFI
DOI: https://doi.org/10.1007/s10699-020-09687-9
ISSN: 1233-1821 (print), 1572-8471 (electronic) OR 12331821 (print), 15728471 (electronic)
ISSNL: 1233-1821 OR 12331821
bibdate: Mon Apr 19 10:16:53 MDT 2021
bibtimestamp: 2021.04.19 10:16:53 MDT
URL: https://link.springer.com/article/10.1007/s10699-020-09687-9
fjournal: Foundations of Science
acknowledgement: ack-nhfb
ajournal: Found. Sci.
journalURL: http://link.springer.com/journal/10699
rawauthor: Marek Czachor
title:
Non-Newtonian Mathematics Instead of Non-Newtonian Physics: Dark Matter and Dark Energy from a Mismatch of Arithmetics

bibsource:
https://www.math.utah.edu/pub/tex/bib/foundsci.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Non-{Newtonian} Mathematics Instead of Non-{Newtonian} Physics: Dark Matter and Dark Energy from a Mismatch of Arithmetics

entry:
@Article{Czachor:2021:NNM,
  author =       "Marek Czachor",
  title =        "Non-{Newtonian} Mathematics Instead of Non-{Newtonian}
                 Physics: Dark Matter and Dark Energy from a Mismatch of
                 Arithmetics",
  journal =      j-FOUND-SCI,
  volume =       "26",
  number =       "1",
  pages =        "75--95",
  month =        mar,
  year =         "2021",
  CODEN =        "FOSCFI",
  DOI =          "https://doi.org/10.1007/s10699-020-09687-9",
  ISSN =         "1233-1821 (print), 1572-8471 (electronic)",
  ISSN-L =       "1233-1821",
  bibdate =      "Mon Apr 19 10:16:53 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/foundsci.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10699-020-09687-9",
  acknowledgement = ack-nhfb,
  ajournal =     "Found. Sci.",
  fjournal =     "Foundations of Science",
  journal-URL =  "http://link.springer.com/journal/10699",
  online-date =  "Published: 28 July 2020 Pages: 75 - 95",
}


bibtype: misc
filename: fparith.bib
label: Darcy:2021:FPA
author: Joseph D. Darcy
title: Floating-Point Arithmetic: What Every Java Programmer Should Know!
pages: 75--95
year: 2021
bibdate: Tue Feb 27 11:53:09 2024
bibtimestamp: 2024.02.27 11:53:09 ???
URL: https://youtu.be/ajaHQ9S4uTA
acknowledgement: ack-nhfb
howpublished: Web site 29m37s video.
rawauthor: Joseph D. Darcy
rawtitle: Floating-Point Arithmetic: What Every {Java} Programmer Should Know!
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/java2020.bib

entry:
@Misc{Darcy:2021:FPA,
  author =       "Joseph D. Darcy",
  title =        "Floating-Point Arithmetic: What Every {Java}
                 Programmer Should Know!",
  howpublished = "Web site 29m37s video.",
  year =         "2021",
  bibdate =      "Tue Feb 27 11:53:09 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/java2020.bib",
  URL =          "https://youtu.be/ajaHQ9S4uTA",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2021:TAC
author: Florent de Dinechin and Silviu-Ioan Filip and Martin Kumm and Anastasia Volkova
title: Towards Arithmetic-Centered Filter Design
crossref: IEEE:2021:ISC
pages: 115--118
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00032
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Silviu-Ioan Filip and Martin Kumm and Anastasia Volkova
rawtitle: Towards Arithmetic-Centered Filter Design
entry:
@InProceedings{deDinechin:2021:TAC,
  author =       "Florent de Dinechin and Silviu-Ioan Filip and Martin
                 Kumm and Anastasia Volkova",
  title =        "Towards Arithmetic-Centered Filter Design",
  crossref =     "IEEE:2021:ISC",
  pages =        "115--118",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00032",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: inproceedings
filename: fparith.bib
label: Defour:2021:SCB
author: David Defour and Pablo de Oliveira Castro and Matei Istoan and Eric Petit
title: Shadow computation with BFloat16 to estimate the numerical accuracy of summations
crossref: IEEE:2021:ISC
pages: 33--36
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00017
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: David Defour and Pablo de Oliveira Castro and Matei I{\c{s}}toan and Eric Petit
rawtitle: Shadow computation with {BFloat16} to estimate the numerical accuracy of summations
entry:
@InProceedings{Defour:2021:SCB,
  author =       "David Defour and Pablo de Oliveira Castro and Matei
                 I{\c{s}}toan and Eric Petit",
  title =        "Shadow computation with {BFloat16} to estimate the
                 numerical accuracy of summations",
  crossref =     "IEEE:2021:ISC",
  pages =        "33--36",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00017",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: delaFraga:2021:DEU
author: Luis Gerardo de la Fraga
title: Differential Evolution under Fixed Point Arithmetic and FP16 Numbers
journal: j-MATH-COMPUT-APPL
volume: 26
number: 1
pages: 13--??
month: mar
monthnumber: 3
year: 2021
DOI: https://doi.org/10.3390/mca26010013
ISSN: 2297-8747 OR 22978747
ISSNL: 2297-8747 OR 22978747
bibdate: Sun Feb 18 06:28:40 MST 2024
bibtimestamp: 2024.02.18 06:28:40 MST
URL: https://www.mdpi.com/2297-8747/26/1/13
fjournal: Mathematical and Computational Applications
acknowledgement: ack-nhfb
journalURL: https://www.mdpi.com/journal/mca
rawauthor: Luis Gerardo de la Fraga
rawtitle: Differential Evolution under Fixed Point Arithmetic and {FP16} Numbers
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/math-comput-appl.bib

entry:
@Article{delaFraga:2021:DEU,
  author =       "Luis Gerardo de la Fraga",
  title =        "Differential Evolution under Fixed Point Arithmetic
                 and {FP16} Numbers",
  journal =      j-MATH-COMPUT-APPL,
  volume =       "26",
  number =       "1",
  pages =        "13--??",
  month =        mar,
  year =         "2021",
  CODEN =        "????",
  DOI =          "https://doi.org/10.3390/mca26010013",
  ISSN =         "2297-8747",
  ISSN-L =       "2297-8747",
  bibdate =      "Sun Feb 18 06:28:40 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/math-comput-appl.bib",
  URL =          "https://www.mdpi.com/2297-8747/26/1/13",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematical and Computational Applications",
  journal-URL =  "https://www.mdpi.com/journal/mca",
}


bibtype: inproceedings
filename: fparith.bib
label: Demeure:2021:TET
author: Nestor Demeure and Cedric Chevalier and Christophe Denis and Pierre Dossantos-Uzarralde
title: Tagged error: tracing numerical error through computations
crossref: IEEE:2021:ISC
pages: 9--16
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00014
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Nestor Demeure and C{\'e}dric Chevalier and Christophe Denis and Pierre Dossantos-Uzarralde
rawtitle: Tagged error: tracing numerical error through computations
entry:
@InProceedings{Demeure:2021:TET,
  author =       "Nestor Demeure and C{\'e}dric Chevalier and Christophe
                 Denis and Pierre Dossantos-Uzarralde",
  title =        "Tagged error: tracing numerical error through
                 computations",
  crossref =     "IEEE:2021:ISC",
  pages =        "9--16",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00014",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Demmel:2021:NIS
author: James Demmel and Jason Riedy
title: A New IEEE 754 Standard for Floating-Point Arithmetic in an Ever-Changing World
journal: j-SIAM-NEWS
volume: 54
number: 6
pages: ??--??
month: jul
monthnumber: 7
year: 2021
ISSN: 0036-1437 OR 00361437
bibdate: Tue Nov 16 08:21:39 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.11.16 08:21:39 ???
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: http://www.siam.org/news/
rawauthor: James Demmel and Jason Riedy
rawtitle: A New {IEEE 754} Standard for Floating-Point Arithmetic in an Ever-Changing World
URL:
https://sinews.siam.org/Details-Page/a-new-ieee-754-standard-for-floating-point-arithmetic-in-an-ever-changing-world

entry:
@Article{Demmel:2021:NIS,
  author =       "James Demmel and Jason Riedy",
  title =        "A New {IEEE 754} Standard for Floating-Point
                 Arithmetic in an Ever-Changing World",
  journal =      j-SIAM-NEWS,
  volume =       "54",
  number =       "6",
  pages =        "??--??",
  month =        jul # "\slash " # aug,
  year =         "2021",
  ISSN =         "0036-1437",
  bibdate =      "Tue Nov 16 08:21:39 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/a-new-ieee-754-standard-for-floating-point-arithmetic-in-an-ever-changing-world",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "http://www.siam.org/news/",
}


bibtype: article
filename: fparith.bib
label: Dimitrakopoulos:2021:SPAa
author: Giorgos Dimitrakopoulos and Kleanthis Papachatzopoulos and Vassilis Paliouras
title: Sum Propagate Adders
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 9
number: 3
pages: 1479--1488
month: jul
monthnumber: 7
year: 2021
DOI: https://doi.org/10.1109/TETC.2021.3068729
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
note: See cite Dimitrakopoulos:2021:SPAb.
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Giorgos Dimitrakopoulos and Kleanthis Papachatzopoulos and Vassilis Paliouras
rawnote: See \cite{Dimitrakopoulos:2021:SPAb}.
rawtitle: Sum Propagate Adders
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib

entry:
@Article{Dimitrakopoulos:2021:SPAa,
  author =       "Giorgos Dimitrakopoulos and Kleanthis Papachatzopoulos
                 and Vassilis Paliouras",
  title =        "Sum Propagate Adders",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "9",
  number =       "3",
  pages =        "1479--1488",
  month =        jul # "\slash " # sep,
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TETC.2021.3068729",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  note =         "See \cite{Dimitrakopoulos:2021:SPAb}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimitrakopoulos:2021:SPAb
author: Giorgos Dimitrakopoulos and Kleanthis Papachatzopoulos and Vassilis Paliouras
title: Sum Propagate Adders
crossref: IEEE:2021:ISC
pages: 110--110
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00030
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.21 10:36:08 ???
note: See cite Dimitrakopoulos:2021:SPAa.
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Giorgos Dimitrakopoulos and Kleanthis Papachatzopoulos and Vassilis Paliouras
rawnote: See \cite{Dimitrakopoulos:2021:SPAa}.
rawtitle: Sum Propagate Adders
remark:
Published in IEEE Transactions on Emerging Topics in Computing, Volume: 9, Issue: 3, July--September 2021, and orally presented at ARITH 2021.

entry:
@InProceedings{Dimitrakopoulos:2021:SPAb,
  author =       "Giorgos Dimitrakopoulos and Kleanthis Papachatzopoulos
                 and Vassilis Paliouras",
  title =        "Sum Propagate Adders",
  crossref =     "IEEE:2021:ISC",
  pages =        "110--110",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00030",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Dimitrakopoulos:2021:SPAa}.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
  remark =       "Published in IEEE Transactions on Emerging Topics in
                 Computing, Volume: 9, Issue: 3, July--September 2021,
                 and orally presented at ARITH 2021.",
}


bibtype: misc
filename: fparith.bib
label: Druck:2021:NSB
author: Philip Druck
title: A Novel Set of Base-Prime Floating Point Numbers
pages: 110--110
day: 16
month: feb
monthnumber: 2
year: 2021
DOI: https://doi.org/10.36227/techrxiv.13960829.v1
bibdate: Fri Sep 29 14:28:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 14:28:55 ???
acknowledgement: ack-nhfb
howpublished: TechRxiv preprint.
rawauthor: Philip Druck
rawtitle: A Novel Set of Base-Prime Floating Point Numbers
abstract:
A novel set is presented that generalizes the usual base representations of floating point real numbers. It uses base-prime numbers instead of the usual base 2 (binary), base 3 (for the Cantor set), base 10 (decimal), base 16 (hexadecimal) and the like. This base-prime set, denoted DS, is essentially an experimental finding, identified in unrelated patented research on nonuniform signal data sampling [1] and self-stabilizing computer arithmetic [2].

rawabstract:
A novel set is presented that generalizes the usual base representations of floating point real numbers. It uses base-prime numbers instead of the usual base 2 (binary), base 3 (for the Cantor set), base 10 (decimal), base 16 (hexadecimal) and the like. This base-prime set, denoted DS, is essentially an experimental finding, identified in unrelated patented research on nonuniform signal data sampling [1] and self-stabilizing computer arithmetic [2].

entry:
@Misc{Druck:2021:NSB,
  author =       "Philip Druck",
  title =        "A Novel Set of Base-Prime Floating Point Numbers",
  howpublished = "TechRxiv preprint.",
  day =          "16",
  month =        feb,
  year =         "2021",
  DOI =          "https://doi.org/10.36227/techrxiv.13960829.v1",
  bibdate =      "Fri Sep 29 14:28:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A novel set is presented that generalizes the usual
                 base representations of floating point real numbers. It
                 uses base-prime numbers instead of the usual base 2
                 (binary), base 3 (for the Cantor set), base 10
                 (decimal), base 16 (hexadecimal) and the like. This
                 base-prime set, denoted DS, is essentially an
                 experimental finding, identified in unrelated patented
                 research on nonuniform signal data sampling [1] and
                 self-stabilizing computer arithmetic [2].",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Eliahu:2021:MME
author: Adi Eliahu and Ronny Ronen and Pierre-Emmanuel Gaillardon and Shahar Kvatinsky
journal: j-JETC
volume: 17
number: 2
pages: 24:1--24:27
month: apr
monthnumber: 4
year: 2021
DOI: https://doi.org/10.1145/3432815
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Fri Apr 30 06:39:29 MDT 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jetc.bib
bibtimestamp: 2021.04.30 06:39:29 MDT
URL: https://dl.acm.org/doi/10.1145/3432815
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
acknowledgement: ack-nhfb
articleno: 24
journalURL: https://dl.acm.org/loi/jetc
rawauthor: Adi Eliahu and Ronny Ronen and Pierre-Emmanuel Gaillardon and Shahar Kvatinsky
title:
multiPULPly: a Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures

abstract:
Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by $ 1.5 times $ to $ 4.5 times $.

rawabstract:
Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by $ 1.5 \times $ to $ 4.5 \times $.

rawtitle:
{multiPULPly}: a Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures

entry:
@Article{Eliahu:2021:MME,
  author =       "Adi Eliahu and Ronny Ronen and Pierre-Emmanuel
                 Gaillardon and Shahar Kvatinsky",
  title =        "{multiPULPly}: a Multiplication Engine for
                 Accelerating Neural Networks on Ultra-low-power
                 Architectures",
  journal =      j-JETC,
  volume =       "17",
  number =       "2",
  pages =        "24:1--24:27",
  month =        apr,
  year =         "2021",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3432815",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Apr 30 06:39:29 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3432815",
  abstract =     "Computationally intensive neural network applications
                 often need to run on resource-limited low-power
                 devices. Numerous hardware accelerators have been
                 developed to speed up the performance of neural network
                 applications and reduce power consumption; however,
                 most focus on data centers and full-fledged systems.
                 Acceleration in ultra-low-power systems has been only
                 partially addressed. In this article, we present
                 multiPULPly, an accelerator that integrates memristive
                 technologies within standard low-power CMOS technology,
                 to accelerate multiplication in neural network
                 inference on ultra-low-power systems. This accelerator
                 was designated for PULP, an open-source microcontroller
                 system that uses low-power RISC-V processors.
                 Memristors were integrated into the accelerator to
                 enable power consumption only when the memory is
                 active, to continue the task with no context-restoring
                 overhead, and to enable highly parallel analog
                 multiplication. To reduce the energy consumption, we
                 propose novel dataflows that handle common
                 multiplication scenarios and are tailored for our
                 architecture. The accelerator was tested on FPGA and
                 achieved a peak energy efficiency of 19.5 TOPS/W,
                 outperforming state-of-the-art accelerators by $ 1.5
                 \times $ to $ 4.5 \times $.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "https://dl.acm.org/loi/jetc",
}


bibtype: inproceedings
filename: fparith.bib
label: Elkhatib:2021:ARV
author: Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
title: Accelerated RISC-V for SIKE
crossref: IEEE:2021:ISC
pages: 131--138
year: 2021
DOI: https://doi.org/10.1109/ARITH51176.2021.00035
bibdate: Thu Sep 21 10:36:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.09.21 10:36:08 ???
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
rawauthor: Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
rawtitle: Accelerated {RISC-V} for {SIKE}
entry:
@InProceedings{Elkhatib:2021:ARV,
  author =       "Rami Elkhatib and Reza Azarderakhsh and Mehran
                 Mozaffari-Kermani",
  title =        "Accelerated {RISC-V} for {SIKE}",
  crossref =     "IEEE:2021:ISC",
  pages =        "131--138",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00035",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH 2021; ARITH-28",
}


bibtype: article
filename: fparith.bib
label: Fasi:2021:ASRa
author: Massimiliano Fasi and Mantas Mikaitis
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 9
number: 3
pages: 1451--1466
month: jul
monthnumber: 7
year: 2021
DOI: https://doi.org/10.1109/TETC.2021.3069165
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
note: See cite Fasi:2021:ASRb.
fjournal: IEEE Transactions on Emerging Topics in Computing
keywords: ARITH 2021; ARITH-28
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Massimiliano Fasi and Mantas Mikaitis
rawnote: See \cite{Fasi:2021:ASRb}.
title:
Algorithms for Stochastically Rounded Elementary Arithmetic Operations in IEEE 754 Floating-Point Arithmetic

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib

rawtitle:
Algorithms for Stochastically Rounded Elementary Arithmetic Operations in {IEEE 754} Floating-Point Arithmetic

entry:
@Article{Fasi:2021:ASRa,
  author =       "Massimiliano Fasi and Mantas Mikaitis",
  title =        "Algorithms for Stochastically Rounded Elementary
                 Arithmetic Operations in {IEEE 754} Floating-Point
                 Arithmetic",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "9",
  number =       "3",
  pages =        "1451--1466",
  month =        jul # "\slash " # sep,
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TETC.2021.3069165",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  note =         "See \cite{Fasi:2021:ASRb}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
  keywords =     "ARITH 2021; ARITH-28",
}


