Last update: Sun Mar 31 02:13:37 MDT 2019
@Article{Bousias:2006:ILP,
author = "Kostas Bousias and Nabil Hasasneh and Chris Jesshope",
title = "Instruction Level Parallelism through Microthreading
--- a Scalable Approach to Chip Multiprocessors",
journal = j-COMP-J,
volume = "49",
number = "2",
pages = "211--233",
month = mar,
year = "2006",
CODEN = "CMPJA6",
DOI = "https://doi.org/10.1093/comjnl/bxh157",
ISSN = "0010-4620 (print), 1460-2067 (electronic)",
ISSN-L = "0010-4620",
bibdate = "Mon Feb 27 15:50:47 MST 2006",
bibsource = "http://comjnl.oxfordjournals.org/content/vol49/issue2/index.dtl;
http://www.math.utah.edu/pub/tex/bib/compj2000.bib",
URL = "http://comjnl.oxfordjournals.org/cgi/content/abstract/49/2/211;
http://comjnl.oxfordjournals.org/cgi/content/full/49/2/211;
http://comjnl.oxfordjournals.org/cgi/reprint/49/2/211",
acknowledgement = ack-nhfb,
fjournal = "The Computer Journal",
journal-URL = "http://comjnl.oxfordjournals.org/",
}