Last update: Sun Mar 31 02:13:37 MDT 2019
@Article{Lee:2007:HSL,
author = "Jaesung Lee and Hyuk-Jae Lee and Chanho Lee",
title = "A High-Speed Link Layer Architecture for Low Latency
and Memory Cost Reduction",
journal = j-COMP-J,
volume = "50",
number = "5",
pages = "616--628",
month = sep,
year = "2007",
CODEN = "CMPJA6",
DOI = "https://doi.org/10.1093/comjnl/bxm032",
ISSN = "0010-4620 (print), 1460-2067 (electronic)",
ISSN-L = "0010-4620",
bibdate = "Wed Apr 28 14:33:33 MDT 2010",
bibsource = "http://comjnl.oxfordjournals.org/content/vol50/issue5/index.dtl;
http://www.math.utah.edu/pub/tex/bib/compj2000.bib",
URL = "http://comjnl.oxfordjournals.org/cgi/content/abstract/50/5/616;
http://comjnl.oxfordjournals.org/cgi/content/full/50/5/616;
http://comjnl.oxfordjournals.org/cgi/reprint/50/5/616",
acknowledgement = ack-nhfb,
fjournal = "The Computer Journal",
journal-URL = "http://comjnl.oxfordjournals.org/",
}