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BibTeX entry
@InProceedings{Nakazawa:1992:PVP,
author = "K. Nakazawa and H. Nakamura and H. Imori and S.
Kawabe",
title = "Pseudo vector processor based on register-windowed
superscalar pipeline",
crossref = "IEEE:1992:PSM",
pages = "642--651",
year = "1992",
bibdate = "Wed Apr 15 15:37:20 MDT 1998",
acknowledgement = ack-nhfb,
classification = "C5220P (Parallel architecture); C5440
(Multiprocessor systems and techniques)",
corpsource = "Inst. of Inf. Sci. and Electron., Tsukuba Univ.,
Japan",
keywords = "cache prefetching; hypothetical extended model;
Livermore Loop Kernels; memory access latency;
performance evaluation; pipeline processing; pseudo
vector processor; register preloading; register
windows; register-windowed superscalar pipeline;
vector processor systems",
sponsororg = "IEEE; ACM",
treatment = "P Practical",
}
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