Entry Zetterlund:1992:MPP from dectechj.bib

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BibTeX entry

@Article{Zetterlund:1992:MPP,
  author =       "B. Zetterlund and J. A. Farrell and T. F. Fox",
  title =        "Microprocessor Performance and Process Complexity in
                 {CMOS} Technologies",
  journal =      j-DEC-TECH-J,
  volume =       "4",
  number =       "2",
  pages =        "12--24",
  month =        "Spring",
  year =         "1992",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  abstract =     "Digitals CMOS technology is characterized by a scaling
                 methodology that doubles the gate density and improves
                 the gate speed by approximately 30 percent with each
                 new generation. Decreasing feature size from one
                 generation of CMOS technology to the next is
                 fundamental to improving the performance of VLSI chips.
                 Each of Digital's successive CMOS generations has added
                 new technology features to improve performance further.
                 Digital's latest, qualified CMOS technology
                 incorporates features such as low voltage operation,
                 low-resistance topside substrate contacts,
                 low-resistance transistor gate material, local
                 interconnects in SRAMs, three levels of metal
                 interconnect, and fuses for redundancy.",
  acknowledgement = ack-nhfb,
  classcodes =   "B2570D (CMOS integrated circuits); B1265F
                 (Microprocessors and microcomputers); C5130
                 (Microprocessor chips)",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips)",
  keywords =     "circuit technology; CMOS integrated circuits; CMOS
                 technology; digital computers; gate density; Gate
                 density; integrated; local interconnects in SRAMs;
                 Local interconnects in SRAMs; Low voltage operation;
                 low voltage operation; low-; low-resistance;
                 Low-resistance topside substrate contacts;
                 Low-resistance transistor gate material; metal
                 interconnect; Metal interconnect; microprocessor chips;
                 Process complexity; process complexity; resistance
                 topside substrate contacts; scaling methodology;
                 Scaling methodology; transistor gate material; VLSI;
                 VLSI chips",
  thesaurus =    "CMOS integrated circuits; Digital computers;
                 Integrated circuit technology; Microprocessor chips;
                 VLSI",
  treatment =    "P Practical",
}

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