Entry Garver:1992:CBP from dectechj.bib

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BibTeX entry

@Article{Garver:1992:CBP,
  author =       "Marion M. Garver and Joseph M. Bulger and Thomas E.
                 Clark and J. H. Dubash and L. M. Ross and D. J. Welch",
  title =        "{CMOS-4} Back-end Process Development for a {VLSI}
                 0.75 $ \mu $ m Triple-level Interconnection
                 Technology",
  journal =      j-DEC-TECH-J,
  volume =       "4",
  number =       "2",
  pages =        "51--72",
  month =        "Spring",
  year =         "1992",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib;
                 UnCover library database",
  abstract =     "Digital's CMOS-4 on-chip interconnect technology,
                 developed for and used in production of the NVAX and
                 the Alpha 21064 microprocessor chips, is a three-level
                 aluminum alloy metallization process with planarized
                 TEOS-based silicon dioxide dielectrics, tungsten-filled
                 contacts and vias, and a minimum feature size of 0.75
                 mu m. The process development effort was a twofold
                 approach based on the maximum use of existing
                 manufacturing capability and the introduction of
                 required new process features. for photolithography,
                 plasma etch, and PVD metallization, the 1.0- mu m
                 manufacturing equipment set and processes were modified
                 and reoptimized for the submicron regime. In addition,
                 two new process features, a blanket CVD tungsten
                 process and a TEOS-based oxide planarization process,
                 were developed and implemented in manufacturing to meet
                 the CMOS-4 technology requirements.",
  acknowledgement = ack-nhfb,
  classcodes =   "B2570D (CMOS integrated circuits); B2550E (Surface
                 treatment)B2550F (Metallisation); B2550G (Lithography);
                 B0520F (Vapour deposition)",
  classification = "B0520F (Vapour deposition); B2550E (Surface
                 treatment ); B2550F (Metallisation); B2550G
                 (Lithography); B2570D (CMOS integrated circuits)",
  keywords =     "aluminium alloys; Aluminum alloy; aluminum alloy;
                 chemical vapour deposition; CMOS; CMOS-4; CVD tungsten
                 process; development; integrated circuit manufacture;
                 integrated circuit technology; integrated circuits;
                 metallisation; metallization; metallization process;
                 Metallization process; on-chip interconnect technology;
                 On-chip interconnect technology; oxide planarization;
                 Oxide planarization process; photolithography;
                 Photolithography; photolithography; plasma etch; Plasma
                 etch; process; Process development; PVD; PVD
                 metallization; sputter etching; tungsten;
                 tungsten-filled contacts; Tungsten-filled contacts;
                 VLSI",
  thesaurus =    "Aluminium alloys; Chemical vapour deposition; CMOS
                 integrated circuits; Integrated circuit manufacture;
                 Integrated circuit technology; Metallisation;
                 Photolithography; Sputter etching; Tungsten; VLSI",
  treatment =    "P Practical",
}

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