Entry Clement:1992:ERV from dectechj.bib

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BibTeX entry

@Article{Clement:1992:ERV,
  author =       "J. Joseph Clement and Eugenia M. Atakov and James R.
                 Lloyd",
  title =        "Electromigration reliability of {VLSI} interconnect",
  journal =      j-DEC-TECH-J,
  volume =       "4",
  number =       "2",
  pages =        "114--125",
  month =        "Spring",
  year =         "1992",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib;
                 UnCover library database",
  abstract =     "Increased speed, reduced line widths, larger chip
                 size, and additional levels of interconnect are all
                 factors that contribute significantly to the improved
                 performance and functionality of VLSI circuits. At the
                 same time, these factors place growing demands on
                 interconnect reliability. Therefore, careful
                 characterization of the interconnect reliability is
                 important in achieving VLSI performance and reliability
                 goals. A scaling model was developed and used to
                 examine factors essential to assuring electromigration
                 reliability in Digital's CMOS-4 technology and in the
                 Alpha 21064 microprocessor which uses this
                 technology.",
  acknowledgement = ack-nhfb,
  classcodes =   "B2570D (CMOS integrated circuits)",
  classification = "B2570D (CMOS integrated circuits)",
  keywords =     "Alpha 21064; Alpha 21064 microprocessor; CMOS
                 integrated circuits; CMOS-4; Digital; electromigration
                 reliability; Electromigration reliability;
                 microprocessor; reliability; Reliability; reliability;
                 VLSI; VLSI interconnect; VLSI performance",
  thesaurus =    "CMOS integrated circuits; Reliability; VLSI",
  treatment =    "P Practical",
}

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