Entry Collica:1992:YEM from dectechj.bib
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BibTeX entry
@Article{Collica:1992:YEM,
author = "Randall S. Collica and X. Joseph Dietrich and Rudolf
{Lambracht Jr.} and D. G. Lau",
title = "A yield enhancement methodology for custom {VLSI}
manufacturing",
journal = j-DEC-TECH-J,
volume = "4",
number = "2",
pages = "83--99",
month = "Spring",
year = "1992",
CODEN = "DTJOEL",
ISSN = "0898-901X",
bibdate = "Thu Mar 20 18:15:43 MST 1997",
bibsource = "http://www.math.utah.edu/pub/tex/bib/dectechj.bib;
UnCover library database",
abstract = "Integrated circuit yield enhancement is a complex
issue due to the many steps involved in the
manufacturing process and the number of variables
governing the overall yield. The task is further
compounded by industry technology goals for continually
improving performance achieved by decreasing minimum
feature size, increasing chip area, and incorporating
more on-chip functionality from generation to
generation. In the final analysis, the cost of
producing chips is directly related to the yield, hence
the necessity for a comprehensive yield improvement
strategy.",
acknowledgement = ack-nhfb,
classcodes = "B2220C (General fabrication techniques)",
classification = "B2220C (General fabrication techniques)",
keywords = "integrated circuit manufacture; Manufacturing process;
manufacturing process; VLSI; VLSI manufacturing; yield
enhancement; Yield enhancement",
thesaurus = "Integrated circuit manufacture; VLSI",
treatment = "P Practical",
}
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