Entry Bowhill:1995:CIS from dectechj.bib

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BibTeX entry

@Article{Bowhill:1995:CIS,
  author =       "William J. Bowhill and Shane L. Bell and Bradley J.
                 Benschneider and Andrew J. Black and Sharon M. Britton
                 and Ruben W. Castelino and Dale R. Donchin and John H.
                 Edmondson and Harry R. {Fair, III} and Paul E.
                 Gronowski and Anil K. Jain and Patricia L. Kroesen and
                 Marc E. Lamere and Bruce J. Loughlin and Shekhar Mehta
                 and Robert O. Mueller and Ronald P. Preston and
                 Sribalan Santhanam and Timothy A. Shedd and Michael J.
                 Smith and Stephen C. Thierauf",
  title =        "Circuit Implementation of a {300-MHz} 64-bit
                 Second-generation {CMOS Alpha CPU}",
  journal =      j-DEC-TECH-J,
  volume =       "7",
  number =       "1",
  pages =        "100--118",
  month =        "Winter",
  year =         "1995",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  URL =          "ftp://ftp.digital.com/pub/Digital/info/DTJ/v7n1/Circuit_Implementation_of_a_30_01jul1995DTJH08P8.ps;
                 http://www.digital.com:80/info/DTJH08/DTJH08SC.TXT",
  abstract =     "A 300-MHz, custom 64-bit VLSI, second generation Alpha
                 CPU chip has been developed. The chip was designed in a
                 0.5-$ \mu $ m CMOS technology using four levels of
                 metal. The die size is 16.5 mm by 18.1 mm, contains 9.3
                 million transistors, operates at 3.3 V, and supports
                 3.3-V\slash 5.0-V interfaces. Power dissipation is 50W.
                 It contains an 8-KB instruction cache; an 8-KB data
                 cache; and a 96-KB unified second-level cache. The chip
                 can issue four instructions per cycle and delivers
                 1,200 mips/600 MFLOPS (peak). Several noteworthy
                 circuit and implementation techniques were used to
                 attain the target operating frequency. This paper
                 focuses on the circuit implementation of the Alpha
                 21164 CPU. Some of the significant circuit design
                 challenges encountered during the project are
                 discussed. The paper begins with an introductory
                 overview of the chip microarchitecture. It continues
                 with a description of the floorplan and the physical
                 layout of the chip. The next section discusses the
                 clock distribution and latch design. This is followed
                 by an overview of the circuit design strategy and some
                 specific circuit design examples. The paper concludes
                 with information about design (physical and electrical)
                 verification and CAD tools.",
  acknowledgement = ack-nhfb,
  classcodes =   "B1265F (Microprocessors and microcomputers); B1130
                 (General circuit analysis and synthesis methods); C5130
                 (Microprocessor chips); C7410D (Electronic engineering
                 computing)",
  classification = "B1130 (General circuit analysis and synthesis
                 methods); B1265F (Microprocessors and microcomputers);
                 C5130 (Microprocessor chips); C7410D (Electronic
                 engineering computing)",
  keywords =     "1200 MIPS; 300 MHz; 600; 600 MFLOPS; 64 Bit; 64 bit;
                 Alpha 21164 CPU; Chip microarchitecture; chip
                 microarchitecture; circuit design; Circuit design;
                 Clock distribution; clock distribution; CMOS Alpha CPU;
                 Floorplan; floorplan; integrated circuit layout; Latch
                 design; latch design; layout; MFLOPS; microprocessor
                 chips; physical; Physical layout; second-generation;
                 Second-generation; VLSI",
  numericalindex = "Frequency 3.0E+08 Hz; Computer speed 6.0E+08 FLOPS;
                 Computer execution rate 1.2E+09 IPS; Word length
                 6.4E+01 bit",
  thesaurus =    "Integrated circuit layout; Microprocessor chips",
  treatment =    "P Practical; R Product Review",
}

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