Entry Godiwala:1995:SPM from dectechj.bib

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BibTeX entry

@Article{Godiwala:1995:SPM,
  author =       "Nitin D. Godiwala and Barry A. Maskas",
  title =        "The Second-generation Processor Module for
                 {AlphaServer 2100 Systems}",
  journal =      j-DEC-TECH-J,
  volume =       "7",
  number =       "1",
  pages =        "77--88",
  month =        "Winter",
  year =         "1995",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  URL =          "ftp://ftp.digital.com/pub/Digital/info/DTJ/v7n1/The_Secondgeneration_Processo_01jul1995DTJH06P8.ps;
                 http://www.digital.com:80/info/DTJH06/DTJH06SC.TXT",
  abstract =     "The second-generation KN470 processor module for
                 AlphaServer 2100 systems performs significantly better
                 than the first-generation KN460 module and was designed
                 to be swap-compatible as an upgrade. The KN470
                 processor module derives its performance improvements
                 from the enhanced architecture of Digital's new Alpha
                 21164 microprocessor, the synchronous design of the
                 third-level cache and system interface, the
                 implementation of a duplicate tag of the third-level
                 cache, and the implementation of a write-invalidate
                 cache coherence protocol for the multiprocessor system
                 bus. Additional design features such as read-miss
                 pipelining, system bus grant parking, hidden coherence
                 transactions to the duplicate tag, and Alpha 21164
                 microprocessor write transactions to the system bus
                 back-off and replay were combined to produce a higher
                 performance processor module. The scope of the project
                 required implementing functionality in system
                 components such as the memory, the backplane, the
                 system bus arbiter, and the I/O bridge, which shipped
                 one year ahead of the KN470 module.",
  acknowledgement = ack-nhfb,
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5630 (Networking equipment);
                 C5440 (Multiprocessing systems)",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5440 (Multiprocessing
                 systems); C5630 (Networking equipment)",
  keywords =     "Alpha 21164 microprocessor; AlphaServer 2100;
                 Backplane; backplane; cache; Cache coherence protocol;
                 coherence protocol; DEC computers; KN470; KN470
                 processor module; memory; Memory; microprocessor chips;
                 Multiprocessor system bus; multiprocessor system bus;
                 network servers; processor module; read-miss
                 pipelining; Read-miss pipelining; second-generation
                 processor module; Second-generation processor module;
                 System bus arbiter; system bus arbiter; system
                 interface; System interface; third-level; Third-level
                 cache",
  thesaurus =    "DEC computers; Microprocessor chips; Network servers",
  treatment =    "P Practical; R Product Review",
}

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