Entry Sites:1992:AAA from dectechj.bib

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BibTeX entry

@Article{Sites:1992:AAA,
  author =       "Richard L. Sites",
  title =        "Alpha {AXP} architecture",
  journal =      j-DEC-TECH-J,
  volume =       "4",
  number =       "4",
  pages =        "19--34",
  month =        "Fall",
  year =         "1992",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  URL =          "ftp://ftp.digital.com/pub/Digital/info/DTJ/v4n4/Alpha_AXP_Architecture_01apr1993DTJ801P8.ps;
                 http://www.digital.com:80/info/DTJ801/DTJ801SC.TXT",
  abstract =     "The Alpha AXP 64-bit computer architecture is designed
                 for high performance and longevity. Because of the
                 focus on multiple instruction issue, the architecture
                 does not contain facilities such as branch delay slots,
                 byte writes, and precise arithmetic exceptions. Because
                 of the focus on multiple processors, the architecture
                 does contain a careful shared-memory model,
                 atomic-update primitive instructions, and relaxed
                 read/write ordering. The first implementation of the
                 Alpha AXP architecture is the world's fastest
                 single-chip microprocessor. The DECchip 21064 runs
                 multiple operating systems and runs native-compiled
                 programs that were translated from the VAX and MIPS
                 architectures.\par

                 {\em Thus in all these cases the Romans did what all
                 wise princes ought to do; namely, not only to look to
                 all present troubles, but also to those in the future,
                 against which they provided with the utmost prudence.
                 -- Niccolo Machiavelli, The Prince}",
  acknowledgement = ack-nhfb,
  classcodes =   "C5220P (Parallel architecture); C5130 (Microprocessor
                 chips); C5440 (Multiprocessor systems and techniques)",
  classification = "C5130 (Microprocessor chips); C5220P (Parallel
                 architecture); C5440 (Multiprocessor systems and
                 techniques)",
  keywords =     "21064; 64; 64 Bit; Alpha AXP 64-bit computer
                 architecture; Atomic-update primitive instructions;
                 atomic-update primitive instructions; bit; computing;
                 DEC computers; DECchip; DECchip 21064; high
                 performance; High performance; memory model;
                 microprocessor chips; MIPS architectures; multiple
                 instruction issue; Multiple instruction issue; multiple
                 processors; Multiple processors; native-compiled
                 programs; Native-compiled programs; read/write
                 ordering; reduced instruction set; relaxed; Relaxed
                 read/write ordering; shared memory systems; shared-;
                 Shared-memory model; Single-chip microprocessor;
                 single-chip microprocessor; VAX",
  numericalindex = "Word length 6.4E+01 bit",
  thesaurus =    "DEC computers; Microprocessor chips; Reduced
                 instruction set computing; Shared memory systems",
  treatment =    "P Practical; R Product Review",
}

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