Entry Durdan:1990:OVM from dectechj.bib

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BibTeX entry

@Article{Durdan:1990:OVM,
  author =       "W. Hugh Durdan and William J. Bowhill and John F.
                 Brown and William V. Herrick and Richard C. Marcello
                 and Sridhar Samudrala and G. Michael Uhler and Nicholas
                 Wade",
  title =        "An overview of the {VAX 6000 Model 400} chip set",
  journal =      j-DEC-TECH-J,
  volume =       "2",
  number =       "2",
  pages =        "36--51",
  month =        "Spring",
  year =         "1990",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  abstract =     "The VAX 6000 Model 400 processor is a CMOS
                 implementation of Digital's VAX architecture, offering
                 an average of seven times the performance of the
                 VAX-11/780 processor at a cycle time of 28 ns. The
                 processor comprises five custom chips implemented in
                 Digital's proprietary CMOS-1 and CMOS-2 semiconductor
                 processes. The chip set design incorporates the best
                 features of the previous VAX 8700 and VLSI VAX designs
                 and in addition implements new performance features.
                 Among these are a larger translation buffer and primary
                 cache, a de-multiplexed 27-bit address and 64-bit data
                 bus, and a tightly coupled 128 KB backup cache. The
                 five chips, which are designed for multiprocessing
                 environments, are the REX520 CPU, the floating point
                 accelerator, the VC vector and cache controller chip,
                 the RSSC system support chip, and the CLK clock chip.",
  acknowledgement = ack-nhfb,
  classcodes =   "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5440 (Multiprocessor systems and techniques)",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5440 (Multiprocessor systems and techniques)",
  keywords =     "64-Bit data bus; 64-bit data bus; accelerator;
                 architecture; Cache controller chip; cache controller
                 chip; CLK clock chip; CMOS implementation; CMOS
                 integrated circuits; CMOS-1; CMOS-2; floating point;
                 Floating point accelerator; microprocessor chips;
                 Multiprocessing environments; multiprocessing
                 environments; parallel; Performance features;
                 performance features; Primary cache; primary cache;
                 processing; REX520 CPU; RSSC system; RSSC system
                 support chip; support chip; Translation buffer;
                 translation buffer; VAX; VAX 6000 Model 400 processor;
                 VAX architecture; VC vector",
  thesaurus =    "CMOS integrated circuits; Microprocessor chips;
                 Parallel processing",
  treatment =    "P Practical",
}

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