Entry Murray:1990:VII from dectechj.bib

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BibTeX entry

@Article{Murray:1990:VII,
  author =       "J. E. Murray and R. C. Hetherington and R. M. Salett",
  title =        "{VAX} instructions that illustrate the architectural
                 features of the {VAX 9000 CPU}",
  journal =      j-DEC-TECH-J,
  volume =       "2",
  number =       "4",
  pages =        "25--42",
  month =        "Fall",
  year =         "1990",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  abstract =     "The VAX 9000 system is Digital's largest and most
                 powerful VAX system. As such, it offers many unique
                 features that required the use of advanced technology
                 and innovative architecture in the design of the
                 system. Overall, the VAX 9000 micro architecture
                 produces a high level of system performance and the
                 lowest cycle time of any VAX processor, i.e. less than
                 five cycles per instruction. Three sections of the VAX
                 9000 CPU-the instruction fetch and decode unit (I-box),
                 the execution unit (E-box), and the data cache and main
                 memory interface unit (M-box)-are illustrated in this
                 paper through descriptions of a small sample of VAX
                 instructions. These instructions are discussed in
                 relation to their flow through the pipeline, how their
                 architectural features combine to work on a single
                 macro instruction, and how various stages of the
                 pipeline interact.",
  acknowledgement = ack-nhfb,
  affiliation =  "Digital Equipment Corp., Maynard, MA, USA",
  classcodes =   "C5420 (Mainframes and minicomputers); C5220 (Computer
                 architecture)",
  classification = "C5220 (Computer architecture); C5420 (Mainframes and
                 minicomputers)",
  corpsource =   "Digital Equipment Corp., Maynard, MA, USA",
  keywords =     "9000 CPU; architectural features; Architectural
                 features; computer architecture; data cache; Data
                 cache; DEC computers; Decode unit; decode unit;
                 Execution unit; execution unit; Instruction fetch;
                 instruction fetch; instruction sets; main memory
                 interface unit; Main memory interface unit; mainframes;
                 Micro architecture; micro architecture; System
                 performance; system performance; VAX; VAX 9000 CPU; VAX
                 instructions",
  thesaurus =    "Computer architecture; DEC computers; Instruction
                 sets; Mainframes",
  treatment =    "P Practical",
}

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