Entry Edmondson:1995:IOA from dectechj.bib

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BibTeX entry

@Article{Edmondson:1995:IOA,
  author =       "John H. Edmondson and Paul I. Rubinfeld and Peter J.
                 Bannon and Bradley J. Benschneider and Debra Bernstein
                 and Ruben W. Castelino and Elizabeth M. Cooper and
                 Daniel E. Dever and Dale R. Donchin Timothy C. Fischer
                 and Anil K. Jain and Shekhar Mehta and Jeanne E. Meyer
                 and Ronald P. Preston and Vidya Rajagopalan and
                 Chandrasekhara Somanathan and Scott A. Taylor and
                 Gilbert M. Wolrich",
  title =        "Internal Organization of the {Alpha} 21164, a
                 300-{MHz} 64-bit Quad-issue {CMOS RISC}
                 Microprocessor",
  journal =      j-DEC-TECH-J,
  volume =       "7",
  number =       "1",
  pages =        "119--135",
  month =        "Winter",
  year =         "1995",
  CODEN =        "DTJOEL",
  ISSN =         "0898-901X",
  bibdate =      "Thu Mar 20 18:15:43 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
  URL =          "ftp://ftp.digital.com/pub/Digital/info/DTJ/v7n1/Internal_Organization_of_the_A_01jul1995DTJH09P8.ps;
                 http://www.digital.com:80/info/DTJH09/DTJH09SC.TXT",
  abstract =     "A new CMOS microprocessor, the Alpha 21164, reaches
                 1,200 mips\slash 600 MFLOPS (peak performance). This
                 new implementation of the Alpha architecture achieves
                 SPECint92\slash SPECfp92 performance of 345\slash 505
                 (estimated). At these performance levels, the Alpha
                 21164 has delivered the highest performance of any
                 commercially available microprocessor in the world as
                 of January 1995. It contains a quad-issue, superscalar
                 instruction unit; two 64-bit integer execution
                 pipelines; two 64-bit floating-point execution
                 pipelines; and a high-performance memory subsystem with
                 multiprocessor-coherent write-back caches.",
  acknowledgement = ack-nhfb,
  classcodes =   "C5130 (Microprocessor chips); C5220 (Computer
                 architecture)",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture)",
  keywords =     "1200; 1200 MIPS; 300 MHz; 600 MFLOPS; 64 Bit; 64 bit;
                 Alpha 21164; Alpha architecture; computer architecture;
                 DEC computers; floating-; Floating-point execution
                 pipelines; instruction unit; integer execution
                 pipelines; Integer execution pipelines; internal
                 organization; Internal organization; microprocessor;
                 microprocessor chips; MIPS; point execution pipelines;
                 quad-issue; Quad-issue; quad-issue CMOS RISC;
                 Quad-issue CMOS RISC microprocessor; reduced
                 instruction set computing; superscalar; Superscalar
                 instruction unit",
  numericalindex = "Frequency 3.0E+08 Hz; Word length 6.4E+01 bit;
                 Computer speed 6.0E+08 FLOPS; Computer execution rate
                 1.2E+09 IPS",
  thesaurus =    "Computer architecture; DEC computers; Microprocessor
                 chips; Reduced instruction set computing",
  treatment =    "P Practical; R Product Review",
}

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