Entry Edmondson:1995:IOA from dectechj.bib
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BibTeX entry
@Article{Edmondson:1995:IOA,
author = "John H. Edmondson and Paul I. Rubinfeld and Peter J.
Bannon and Bradley J. Benschneider and Debra Bernstein
and Ruben W. Castelino and Elizabeth M. Cooper and
Daniel E. Dever and Dale R. Donchin Timothy C. Fischer
and Anil K. Jain and Shekhar Mehta and Jeanne E. Meyer
and Ronald P. Preston and Vidya Rajagopalan and
Chandrasekhara Somanathan and Scott A. Taylor and
Gilbert M. Wolrich",
title = "Internal Organization of the {Alpha} 21164, a
300-{MHz} 64-bit Quad-issue {CMOS RISC}
Microprocessor",
journal = j-DEC-TECH-J,
volume = "7",
number = "1",
pages = "119--135",
month = "Winter",
year = "1995",
CODEN = "DTJOEL",
ISSN = "0898-901X",
bibdate = "Thu Mar 20 18:15:43 MST 1997",
bibsource = "http://www.math.utah.edu/pub/tex/bib/dectechj.bib",
URL = "ftp://ftp.digital.com/pub/Digital/info/DTJ/v7n1/Internal_Organization_of_the_A_01jul1995DTJH09P8.ps;
http://www.digital.com:80/info/DTJH09/DTJH09SC.TXT",
abstract = "A new CMOS microprocessor, the Alpha 21164, reaches
1,200 mips\slash 600 MFLOPS (peak performance). This
new implementation of the Alpha architecture achieves
SPECint92\slash SPECfp92 performance of 345\slash 505
(estimated). At these performance levels, the Alpha
21164 has delivered the highest performance of any
commercially available microprocessor in the world as
of January 1995. It contains a quad-issue, superscalar
instruction unit; two 64-bit integer execution
pipelines; two 64-bit floating-point execution
pipelines; and a high-performance memory subsystem with
multiprocessor-coherent write-back caches.",
acknowledgement = ack-nhfb,
classcodes = "C5130 (Microprocessor chips); C5220 (Computer
architecture)",
classification = "C5130 (Microprocessor chips); C5220 (Computer
architecture)",
keywords = "1200; 1200 MIPS; 300 MHz; 600 MFLOPS; 64 Bit; 64 bit;
Alpha 21164; Alpha architecture; computer architecture;
DEC computers; floating-; Floating-point execution
pipelines; instruction unit; integer execution
pipelines; Integer execution pipelines; internal
organization; Internal organization; microprocessor;
microprocessor chips; MIPS; point execution pipelines;
quad-issue; Quad-issue; quad-issue CMOS RISC;
Quad-issue CMOS RISC microprocessor; reduced
instruction set computing; superscalar; Superscalar
instruction unit",
numericalindex = "Frequency 3.0E+08 Hz; Word length 6.4E+01 bit;
Computer speed 6.0E+08 FLOPS; Computer execution rate
1.2E+09 IPS",
thesaurus = "Computer architecture; DEC computers; Microprocessor
chips; Reduced instruction set computing",
treatment = "P Practical; R Product Review",
}
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2(2)89,
2(4)25,
4(4)35,
4(4)51,
4(4)66,
4(4)100,
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6(2)49,
6(3)29,
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4(3)60,
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7(1)66,
7(1)89,
7(3)39,
8(1)5,
8(2)96
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2(4)13,
2(4)25,
4(4)35
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1(1)43,
1(2)24,
1(7)109,
1(9)29,
2(2)36,
2(3)16,
3(1)79,
5(1)1,
5(1)34,
6(1)54,
7(4)89
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4(4)35,
6(1)66
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4(3)24,
7(1)100
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7(1)136
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4(4)35
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2(2)89,
2(4)13,
3(2)85,
4(2)114,
4(3)11,
4(4)19,
4(4)35,
4(4)51,
4(4)66,
4(4)111,
4(4)137,
6(1)23
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2(2)89,
2(4)13,
4(3)11,
4(4)51,
4(4)66,
4(4)111,
4(4)137,
9(1)49
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1(9)29,
2(1)8,
2(2)27,
2(2)36,
2(2)64,
2(2)84,
2(2)89,
2(3)9,
2(3)24,
2(3)34,
2(4)13,
2(4)25,
2(4)130,
3(1)18,
3(2)19,
3(2)42,
3(2)76,
3(2)85,
3(3)7,
4(2)51,
4(3)11,
4(3)73,
4(3)92,
4(4)19,
4(4)35,
4(4)51,
4(4)66,
4(4)111,
4(4)137,
4(4)181,
5(1)1,
5(1)34,
5(2)100,
5(2)z,
5(3)8,
5(3)21,
5(3)32,
5(3)43,
5(3)63,
5(3)80,
5(3)97,
5(4)69,
6(2)49,
6(3)44,
7(1)43,
7(2)56,
7(3)39,
7(3)66,
7(4)20,
7(4)34,
7(4)101,
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2(2)84,
3(2)85,
3(4)61,
4(3)92,
4(4)66,
6(3)8,
6(3)20,
6(4)5,
7(1)89,
7(4)20,
7(4)34,
7(4)89,
8(3)23
- superscalar,
6(1)66,
7(1)136,
10(1)58
- two,
1(9)78,
2(3)64,
3(1)18,
3(1)33,
3(1)45,
3(2)53,
4(1)47,
4(1)56,
4(2)51,
4(2)73,
4(3)11,
4(3)60,
4(3)73,
4(4)35,
4(4)51,
4(4)66,
4(4)137,
4(4)153,
4(4)193,
5(1)107,
5(4)59,
6(2)62,
6(3)8,
7(2)5,
7(3)84,
7(4)34,
8(1)19,
8(2)96,
8(3)23
- unit,
2(1)38,
2(2)11,
2(2)27,
2(4)25,
2(4)80,
2(4)90,
2(4)102,
4(4)35,
4(4)51
- Wolrich, Gilbert M.,
1(7)109
- world,
4(4)19,
5(3)8,
5(3)21,
5(3)43,
7(3)66,
8(3)66
- write-back,
6(4)5,
8(2)5,
8(2)46